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net: microchip: sparx5: initialize PSFP
authorDaniel Machon <daniel.machon@microchip.com>
Thu, 2 Feb 2023 10:43:54 +0000 (11:43 +0100)
committerDavid S. Miller <davem@davemloft.net>
Mon, 6 Feb 2023 08:26:26 +0000 (08:26 +0000)
Initialize the SDLB's, stream gates and stream filters.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Simon Horman <simon.horman@corigine.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/microchip/sparx5/sparx5_main.h
drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c
drivers/net/ethernet/microchip/sparx5/sparx5_qos.c

index cffed89..72e7928 100644 (file)
@@ -456,6 +456,7 @@ int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx);
 
 void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst,
                            u32 frame_size, u32 idx);
+
 /* sparx5_police.c */
 enum {
        /* More policer types will be added later */
@@ -530,6 +531,8 @@ u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx);
 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid);
 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid);
 
+void sparx5_psfp_init(struct sparx5 *sparx5);
+
 /* sparx5_qos.c */
 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time,
                          const ktime_t org_base_time, ktime_t *new_base_time);
index b70601a..8dee1ab 100644 (file)
@@ -312,3 +312,21 @@ int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id)
 
        return sparx5_sdlb_conf_set(sparx5, &fm);
 }
+
+void sparx5_psfp_init(struct sparx5 *sparx5)
+{
+       const struct sparx5_sdlb_group *group;
+       int i;
+
+       for (i = 0; i < SPX5_SDLB_GROUP_CNT; i++) {
+               group = &sdlb_groups[i];
+               sparx5_sdlb_group_init(sparx5, group->max_rate,
+                                      group->min_burst, group->frame_size, i);
+       }
+
+       spx5_wr(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(1),
+               sparx5, ANA_AC_SG_CYCLETIME_UPDATE_PERIOD);
+
+       spx5_rmw(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(1),
+                ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, sparx5, ANA_L2_FWD_CFG);
+}
index ebfdbbf..5f34feb 100644 (file)
@@ -450,6 +450,8 @@ int sparx5_qos_init(struct sparx5 *sparx5)
        if (ret < 0)
                return ret;
 
+       sparx5_psfp_init(sparx5);
+
        return 0;
 }