drm/amdgpu: skip psp suspend for IMU enabled ASICs mode2 reset

The psp suspend & resume should be skipped to avoid destroy
the TMR and reload FWs again for IMU enabled APU ASICs.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index cbecc25..0366571 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3037,6 +3037,18 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
                    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
                        continue;
 
+               /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
+                * These are in TMR, hence are expected to be reused by PSP-TOS to reload
+                * from this location and RLC Autoload automatically also gets loaded
+                * from here based on PMFW -> PSP message during re-init sequence.
+                * Therefore, the psp suspend & resume should be skipped to avoid destroy
+                * the TMR and reload FWs again for IMU enabled APU ASICs.
+                */
+               if (amdgpu_in_reset(adev) &&
+                   (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
+                   adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
+                       continue;
+
                /* XXX handle errors */
                r = adev->ip_blocks[i].version->funcs->suspend(adev);
                /* XXX handle errors */