#endif
}
+static void rv64_veyron_v1_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
+ set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
+ env->priv_ver = PRIV_VERSION_1_12_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.mmu = true;
+ cpu->cfg.ext_icbom = true;
+ cpu->cfg.cbom_blocksize = 64;
+ cpu->cfg.cboz_blocksize = 64;
+ cpu->cfg.ext_icboz = true;
+ cpu->cfg.ext_smaia = true;
+ cpu->cfg.ext_ssaia = true;
+ cpu->cfg.ext_sscofpmf = true;
+ cpu->cfg.ext_sstc = true;
+ cpu->cfg.ext_svinval = true;
+ cpu->cfg.ext_svnapot = true;
+ cpu->cfg.ext_svpbmt = true;
+ cpu->cfg.ext_smstateen = true;
+ cpu->cfg.ext_zba = true;
+ cpu->cfg.ext_zbb = true;
+ cpu->cfg.ext_zbc = true;
+ cpu->cfg.ext_zbs = true;
+ cpu->cfg.ext_XVentanaCondOps = true;
+
+ cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
+ cpu->cfg.marchid = VEYRON_V1_MARCHID;
+ cpu->cfg.mimpid = VEYRON_V1_MIMPID;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV48);
+#endif
+}
+
static void rv128_base_cpu_init(Object *obj)
{
if (qemu_tcg_mttcg_enabled()) {
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};