struct device *dev;
struct regmap *regmap;
struct clk *clk;
- bool clk_enabled;
+ bool enabled;
u32 max_arr;
const void *triggers;
const void *valids;
return -EBUSY;
mutex_lock(&priv->lock);
- if (!priv->clk_enabled) {
- priv->clk_enabled = true;
+ if (!priv->enabled) {
+ priv->enabled = true;
clk_enable(priv->clk);
}
/* Make sure that registers are updated */
regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
- if (priv->clk_enabled) {
- priv->clk_enabled = false;
+ if (priv->enabled) {
+ priv->enabled = false;
clk_disable(priv->clk);
}
mutex_unlock(&priv->lock);
if (!strncmp(master_mode_table[i], buf,
strlen(master_mode_table[i]))) {
mutex_lock(&priv->lock);
- if (!priv->clk_enabled) {
+ if (!priv->enabled) {
/* Clock should be enabled first */
- priv->clk_enabled = true;
+ priv->enabled = true;
clk_enable(priv->clk);
}
regmap_update_bits(priv->regmap, TIM_CR2, mask,
case IIO_CHAN_INFO_ENABLE:
mutex_lock(&priv->lock);
if (val) {
- if (!priv->clk_enabled) {
- priv->clk_enabled = true;
+ if (!priv->enabled) {
+ priv->enabled = true;
clk_enable(priv->clk);
}
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
} else {
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
0);
- if (priv->clk_enabled) {
- priv->clk_enabled = false;
+ if (priv->enabled) {
+ priv->enabled = false;
clk_disable(priv->clk);
}
}
* enable counter clock, so it can use it. Keeps it in sync with CEN.
*/
mutex_lock(&priv->lock);
- if (sms == 6 && !priv->clk_enabled) {
+ if (sms == 6 && !priv->enabled) {
clk_enable(priv->clk);
- priv->clk_enabled = true;
+ priv->enabled = true;
}
mutex_unlock(&priv->lock);
if (!(val & TIM_CCER_CCXE))
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
- if (priv->clk_enabled)
+ if (priv->enabled)
clk_disable(priv->clk);
return 0;