#include "r600_state.h"
#include "radeon_reg.h"
-#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
+#define R600_VAP_PVS_UPLOAD_ADDRESS 0x2200
# define RADEON_ONE_REG_WR (1 << 15)
/** # of dwords reserved for additional instructions that may need to be written
*/
#define SPACE_FOR_FLUSHING 4
-static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
+static unsigned packet0_count(r600ContextPtr r600, uint32_t *pkt)
{
- if (r300->radeon.radeonScreen->kernel_mm) {
+ if (r600->radeon.radeonScreen->kernel_mm) {
return ((((*pkt) >> 16) & 0x3FFF) + 1);
} else {
drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ BATCH_LOCALS(&r600->radeon);
drm_r300_cmd_header_t cmd;
uint32_t addr, ndw, i;
- if (!r300->radeon.radeonScreen->kernel_mm) {
+ if (!r600->radeon.radeonScreen->kernel_mm) {
uint32_t dwords;
dwords = (*atom->check) (ctx, atom);
BEGIN_BATCH_NO_AUTOSTATE(dwords);
ndw = cmd.vpu.count * 4;
if (ndw) {
- if (r300->vap_flush_needed) {
+ if (r600->vap_flush_needed) {
BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
/* flush processing vertices */
- OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
- OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
+ OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0);
+ OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
- OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
- OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- r300->vap_flush_needed = GL_FALSE;
+ OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0xffffff);
+ OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
+ r600->vap_flush_needed = GL_FALSE;
} else {
BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
}
- OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
- OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
+ OUT_BATCH_REGVAL(R600_VAP_PVS_UPLOAD_ADDRESS, addr);
+ OUT_BATCH(CP_PACKET0(R600_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
for (i = 0; i < ndw; i++) {
OUT_BATCH(atom->cmd[i+1]);
}
- OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+ OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
END_BATCH();
}
}
void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ BATCH_LOCALS(&r600->radeon);
drm_r300_cmd_header_t cmd;
uint32_t addr, ndw, i, sz;
int type, clamp, stride;
- if (!r300->radeon.radeonScreen->kernel_mm) {
+ if (!r600->radeon.radeonScreen->kernel_mm) {
uint32_t dwords;
dwords = (*atom->check) (ctx, atom);
BEGIN_BATCH_NO_AUTOSTATE(dwords);
static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
- int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ BATCH_LOCALS(&r600->radeon);
+ int numtmus = packet0_count(r600, r600->hw.tex.offset.cmd);
int notexture = 0;
if (numtmus) {
int i;
for(i = 0; i < numtmus; ++i) {
- radeonTexObj *t = r300->hw.textures[i];
+ radeonTexObj *t = r600->hw.textures[i];
if (!t)
notexture = 1;
}
- if (r300->radeon.radeonScreen->kernel_mm && notexture) {
+ if (r600->radeon.radeonScreen->kernel_mm && notexture) {
return;
}
BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
for(i = 0; i < numtmus; ++i) {
- radeonTexObj *t = r300->hw.textures[i];
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+ radeonTexObj *t = r600->hw.textures[i];
+ OUT_BATCH_REGSEQ(R600_TX_OFFSET_0 + (i * 4), 1);
if (t && !t->image_override) {
OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else if (!t) {
- OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
+ OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]);
} else { /* override cases */
if (t->bo) {
OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- } else if (!r300->radeon.radeonScreen->kernel_mm) {
+ } else if (!r600->radeon.radeonScreen->kernel_mm) {
OUT_BATCH(t->override_offset);
}
else
- OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
+ OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]);
}
}
END_BATCH();
static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ BATCH_LOCALS(&r600->radeon);
struct radeon_renderbuffer *rrb;
uint32_t cbpitch;
- uint32_t offset = r300->radeon.state.color.draw_offset;
+ uint32_t offset = r600->radeon.state.color.draw_offset;
- rrb = radeon_get_colorbuffer(&r300->radeon);
+ rrb = radeon_get_colorbuffer(&r600->radeon);
if (!rrb || !rrb->bo) {
fprintf(stderr, "no rrb\n");
return;
cbpitch = (rrb->pitch / rrb->cpp);
if (rrb->cpp == 4)
- cbpitch |= R300_COLOR_FORMAT_ARGB8888;
+ cbpitch |= R600_COLOR_FORMAT_ARGB8888;
else
- cbpitch |= R300_COLOR_FORMAT_RGB565;
+ cbpitch |= R600_COLOR_FORMAT_RGB565;
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
- cbpitch |= R300_COLOR_TILE_ENABLE;
+ cbpitch |= R600_COLOR_TILE_ENABLE;
BEGIN_BATCH_NO_AUTOSTATE(8);
- OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
+ OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1);
OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
+ OUT_BATCH_REGSEQ(R600_RB3D_COLORPITCH0, 1);
OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
- if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
+ if (r600->radeon.radeonScreen->driScreen->dri2.enabled) {
+ if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
BEGIN_BATCH_NO_AUTOSTATE(3);
- OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
+ OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2);
OUT_BATCH(0);
- OUT_BATCH((rrb->width << R300_SCISSORS_X_SHIFT) |
- (rrb->height << R300_SCISSORS_Y_SHIFT));
+ OUT_BATCH((rrb->width << R600_SCISSORS_X_SHIFT) |
+ (rrb->height << R600_SCISSORS_Y_SHIFT));
END_BATCH();
} else {
BEGIN_BATCH_NO_AUTOSTATE(3);
- OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
- OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
- (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
- OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET) << R300_SCISSORS_X_SHIFT) |
- ((rrb->height + R300_SCISSORS_OFFSET) << R300_SCISSORS_Y_SHIFT));
+ OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2);
+ OUT_BATCH((R600_SCISSORS_OFFSET << R600_SCISSORS_X_SHIFT) |
+ (R600_SCISSORS_OFFSET << R600_SCISSORS_Y_SHIFT));
+ OUT_BATCH(((rrb->width + R600_SCISSORS_OFFSET) << R600_SCISSORS_X_SHIFT) |
+ ((rrb->height + R600_SCISSORS_OFFSET) << R600_SCISSORS_Y_SHIFT));
END_BATCH();
}
}
static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ BATCH_LOCALS(&r600->radeon);
struct radeon_renderbuffer *rrb;
uint32_t zbpitch;
- rrb = radeon_get_depthbuffer(&r300->radeon);
+ rrb = radeon_get_depthbuffer(&r600->radeon);
if (!rrb)
return;
zbpitch = (rrb->pitch / rrb->cpp);
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
- zbpitch |= R300_DEPTHMACROTILE_ENABLE;
+ zbpitch |= R600_DEPTHMACROTILE_ENABLE;
}
if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
- zbpitch |= R300_DEPTHMICROTILE_TILED;
+ zbpitch |= R600_DEPTHMICROTILE_TILED;
}
BEGIN_BATCH_NO_AUTOSTATE(6);
- OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
+ OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
+ OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, zbpitch);
END_BATCH();
}
static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ BATCH_LOCALS(&r600->radeon);
struct radeon_renderbuffer *rrb;
uint32_t format = 0;
- rrb = radeon_get_depthbuffer(&r300->radeon);
+ rrb = radeon_get_depthbuffer(&r600->radeon);
if (!rrb)
format = 0;
else {
if (rrb->cpp == 2)
- format = R300_DEPTHFORMAT_16BIT_INT_Z;
+ format = R600_DEPTHFORMAT_16BIT_INT_Z;
else if (rrb->cpp == 4)
- format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
+ format = R600_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
}
OUT_BATCH(atom->cmd[0]);
static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
int cnt;
if (atom->cmd[0] == CP_PACKET2) {
return 0;
}
- cnt = packet0_count(r300, atom->cmd);
+ cnt = packet0_count(r600, atom->cmd);
return cnt ? cnt + 1 : 0;
}
#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
do { \
- r300->hw.ATOM.cmd_size = (SZ); \
- r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
- r300->hw.ATOM.name = #ATOM; \
- r300->hw.ATOM.idx = (IDX); \
- r300->hw.ATOM.check = check_##CHK; \
- r300->hw.ATOM.dirty = GL_FALSE; \
- r300->radeon.hw.max_state_size += (SZ); \
- insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
+ r600->hw.ATOM.cmd_size = (SZ); \
+ r600->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
+ r600->hw.ATOM.name = #ATOM; \
+ r600->hw.ATOM.idx = (IDX); \
+ r600->hw.ATOM.check = check_##CHK; \
+ r600->hw.ATOM.dirty = GL_FALSE; \
+ r600->radeon.hw.max_state_size += (SZ); \
+ insert_at_tail(&r600->radeon.hw.atomlist, &r600->hw.ATOM); \
} while (0)
/**
* Allocate memory for the command buffer and initialize the state atom
- * list. Note that the initial hardware state is set by r300InitState().
+ * list. Note that the initial hardware state is set by r600InitState().
*/
-void r300InitCmdBuf(r300ContextPtr r300)
+void r600InitCmdBuf(r600ContextPtr r600)
{
int mtu;
int has_tcl = 1;
int is_r500 = 0;
int i;
- if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
+ if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
has_tcl = 0;
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+ if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
is_r500 = 1;
- r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
+ r600->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
- mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
+ mtu = r600->radeon.glCtx->Const.MaxTextureUnits;
if (RADEON_DEBUG & DEBUG_TEXTURE) {
fprintf(stderr, "Using %d maximum texture units..\n", mtu);
}
/* Setup the atom linked list */
- make_empty_list(&r300->radeon.hw.atomlist);
- r300->radeon.hw.atomlist.name = "atom-list";
+ make_empty_list(&r600->radeon.hw.atomlist);
+ r600->radeon.hw.atomlist.name = "atom-list";
/* Initialize state atoms */
- ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
- r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
- ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
- r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
- r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
- r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
+ ALLOC_STATE(vpt, always, R600_VPT_CMDSIZE, 0);
+ r600->hw.vpt.cmd[R600_VPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VPORT_XSCALE, 6);
+ ALLOC_STATE(vap_cntl, always, R600_VAP_CNTL_SIZE, 0);
+ r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_STATE_FLUSH_REG, 1);
+ r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH_1] = 0;
+ r600->hw.vap_cntl.cmd[R600_VAP_CNTL_CMD] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL, 1);
if (is_r500) {
ALLOC_STATE(vap_index_offset, always, 2, 0);
- r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
- r300->hw.vap_index_offset.cmd[1] = 0;
+ r600->hw.vap_index_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
+ r600->hw.vap_index_offset.cmd[1] = 0;
}
ALLOC_STATE(vte, always, 3, 0);
- r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
+ r600->hw.vte.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VTE_CNTL, 2);
ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
- r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
+ r600->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VF_MAX_VTX_INDX, 2);
ALLOC_STATE(vap_cntl_status, always, 2, 0);
- r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
- ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
- r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
- ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
- r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
- ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
- r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
+ r600->hw.vap_cntl_status.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL_STATUS, 1);
+ ALLOC_STATE(vir[0], variable, R600_VIR_CMDSIZE, 0);
+ r600->hw.vir[0].cmd[R600_VIR_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_0, 1);
+ ALLOC_STATE(vir[1], variable, R600_VIR_CMDSIZE, 1);
+ r600->hw.vir[1].cmd[R600_VIR_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_EXT_0, 1);
+ ALLOC_STATE(vic, always, R600_VIC_CMDSIZE, 0);
+ r600->hw.vic.cmd[R600_VIC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VTX_STATE_CNTL, 2);
ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
- r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
+ r600->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
if (has_tcl) {
ALLOC_STATE(vap_clip_cntl, always, 2, 0);
- r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
+ r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1);
ALLOC_STATE(vap_clip, always, 5, 0);
- r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
+ r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4);
ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
- r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
+ r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
}
- ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
- r300->hw.vof.cmd[R300_VOF_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
+ ALLOC_STATE(vof, always, R600_VOF_CMDSIZE, 0);
+ r600->hw.vof.cmd[R600_VOF_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_VAP_OUTPUT_VTX_FMT_0, 2);
if (has_tcl) {
- ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
- r300->hw.pvs.cmd[R300_PVS_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
+ ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0);
+ r600->hw.pvs.cmd[R600_PVS_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3);
}
ALLOC_STATE(gb_enable, always, 2, 0);
- r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
- ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
- r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
- ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
- r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
+ r600->hw.gb_enable.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_ENABLE, 1);
+ ALLOC_STATE(gb_misc, always, R600_GB_MISC_CMDSIZE, 0);
+ r600->hw.gb_misc.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_MSPOS0, 5);
+ ALLOC_STATE(txe, always, R600_TXE_CMDSIZE, 0);
+ r600->hw.txe.cmd[R600_TXE_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_ENABLE, 1);
ALLOC_STATE(ga_point_s0, always, 5, 0);
- r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
+ r600->hw.ga_point_s0.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_S0, 4);
ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
- r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
- ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
- r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
+ r600->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_TRIANGLE_STIPPLE, 1);
+ ALLOC_STATE(ps, always, R600_PS_CMDSIZE, 0);
+ r600->hw.ps.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_SIZE, 1);
ALLOC_STATE(ga_point_minmax, always, 4, 0);
- r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
+ r600->hw.ga_point_minmax.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_MINMAX, 3);
ALLOC_STATE(lcntl, always, 2, 0);
- r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
+ r600->hw.lcntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_CNTL, 1);
ALLOC_STATE(ga_line_stipple, always, 4, 0);
- r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
+ r600->hw.ga_line_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_STIPPLE_VALUE, 3);
ALLOC_STATE(shade, always, 5, 0);
- r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
+ r600->hw.shade.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_ENHANCE, 4);
ALLOC_STATE(polygon_mode, always, 4, 0);
- r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
+ r600->hw.polygon_mode.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POLY_MODE, 3);
ALLOC_STATE(fogp, always, 3, 0);
- r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
+ r600->hw.fogp.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_FOG_SCALE, 2);
ALLOC_STATE(zbias_cntl, always, 2, 0);
- r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
- ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
- r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
+ r600->hw.zbias_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_TEX_WRAP, 1);
+ ALLOC_STATE(zbs, always, R600_ZBS_CMDSIZE, 0);
+ r600->hw.zbs.cmd[R600_ZBS_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_FRONT_SCALE, 4);
ALLOC_STATE(occlusion_cntl, always, 2, 0);
- r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
- ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
- r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
+ r600->hw.occlusion_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_ENABLE, 1);
+ ALLOC_STATE(cul, always, R600_CUL_CMDSIZE, 0);
+ r600->hw.cul.cmd[R600_CUL_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_CULL_MODE, 1);
ALLOC_STATE(su_depth_scale, always, 3, 0);
- r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
- ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
- r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
+ r600->hw.su_depth_scale.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_DEPTH_SCALE, 2);
+ ALLOC_STATE(rc, always, R600_RC_CMDSIZE, 0);
+ r600->hw.rc.cmd[R600_RC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_COUNT, 2);
if (is_r500) {
ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
- r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
+ r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_IP_0, 16);
for (i = 0; i < 8; i++) {
- r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
+ r600->hw.ri.cmd[R600_RI_CMD_0 + i +1] =
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
}
- ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
+ ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0);
+ r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, 1);
} else {
- ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
- r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
- ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
+ ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0);
+ r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8);
+ ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0);
+ r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1);
}
ALLOC_STATE(sc_hyperz, always, 3, 0);
- r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
+ r600->hw.sc_hyperz.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_HYPERZ, 2);
ALLOC_STATE(sc_screendoor, always, 2, 0);
- r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
+ r600->hw.sc_screendoor.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_SCREENDOOR, 1);
ALLOC_STATE(us_out_fmt, always, 6, 0);
- r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
+ r600->hw.us_out_fmt.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_OUT_FMT, 5);
if (is_r500) {
ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
- r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
- r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
- r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
- r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
- r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
+ r600->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CONFIG, 2);
+ r600->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
+ r600->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
+ r600->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r600->radeon.radeonScreen, R500_US_FC_CTRL, 1);
+ r600->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
- r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
- cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
- r300->hw.r500fp.emit = emit_r500fp;
+ r600->hw.r500fp.cmd[R600_FPI_CMD_0] =
+ cmdr500fp(r600->radeon.radeonScreen, 0, 0, 0, 0);
+ r600->hw.r500fp.emit = emit_r500fp;
ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
- r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
- cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
- r300->hw.r500fp_const.emit = emit_r500fp;
+ r600->hw.r500fp_const.cmd[R600_FPI_CMD_0] =
+ cmdr500fp(r600->radeon.radeonScreen, 0, 0, 1, 0);
+ r600->hw.r500fp_const.emit = emit_r500fp;
} else {
- ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
- r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
- r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
-
- ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
- r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
-
- ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
- r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
- ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
- r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
- ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
- r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
- ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
- r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
- ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
- r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
+ ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0);
+ r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3);
+ r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4);
+
+ ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0);
+ r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0);
+
+ ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0);
+ r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1);
+ ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1);
+ r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1);
+ ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2);
+ r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1);
+ ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3);
+ r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1);
+ ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0);
+ r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0);
}
- ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
- r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
- ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
- r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
- ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
- r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
+ ALLOC_STATE(fogs, always, R600_FOGS_CMDSIZE, 0);
+ r600->hw.fogs.cmd[R600_FOGS_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_BLEND, 1);
+ ALLOC_STATE(fogc, always, R600_FOGC_CMDSIZE, 0);
+ r600->hw.fogc.cmd[R600_FOGC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_COLOR_R, 3);
+ ALLOC_STATE(at, always, R600_AT_CMDSIZE, 0);
+ r600->hw.at.cmd[R600_AT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_ALPHA_FUNC, 2);
ALLOC_STATE(fg_depth_src, always, 2, 0);
- r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
+ r600->hw.fg_depth_src.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_DEPTH_SRC, 1);
ALLOC_STATE(rb3d_cctl, always, 2, 0);
- r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
- ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
- r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
- ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
- r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
+ r600->hw.rb3d_cctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CCTL, 1);
+ ALLOC_STATE(bld, always, R600_BLD_CMDSIZE, 0);
+ r600->hw.bld.cmd[R600_BLD_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CBLEND, 2);
+ ALLOC_STATE(cmk, always, R600_CMK_CMDSIZE, 0);
+ r600->hw.cmk.cmd[R600_CMK_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
if (is_r500) {
ALLOC_STATE(blend_color, always, 3, 0);
- r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
+ r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
} else {
ALLOC_STATE(blend_color, always, 2, 0);
- r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
+ r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1);
}
ALLOC_STATE(rop, always, 2, 0);
- r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
- ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
- r300->hw.cb.emit = &emit_cb_offset;
+ r600->hw.rop.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_ROPCNTL, 1);
+ ALLOC_STATE(cb, always, R600_CB_CMDSIZE, 0);
+ r600->hw.cb.emit = &emit_cb_offset;
ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
- r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
+ r600->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_DITHER_CTL, 9);
ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
- r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
+ r600->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_AARESOLVE_CTL, 1);
ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
- r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
- ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
- r300->hw.zs.cmd[R300_ZS_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
+ r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
+ ALLOC_STATE(zs, always, R600_ZS_CMDSIZE, 0);
+ r600->hw.zs.cmd[R600_ZS_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_ZB_CNTL, 3);
ALLOC_STATE(zstencil_format, always, 5, 0);
- r300->hw.zstencil_format.cmd[0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
- r300->hw.zstencil_format.emit = emit_zstencil_format;
+ r600->hw.zstencil_format.cmd[0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_ZB_FORMAT, 4);
+ r600->hw.zstencil_format.emit = emit_zstencil_format;
- ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
- r300->hw.zb.emit = emit_zb_offset;
+ ALLOC_STATE(zb, always, R600_ZB_CMDSIZE, 0);
+ r600->hw.zb.emit = emit_zb_offset;
ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
- r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
+ r600->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_DEPTHCLEARVALUE, 1);
ALLOC_STATE(unk4F30, always, 3, 0);
- r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
+ r600->hw.unk4F30.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, 0x4F30, 2);
ALLOC_STATE(zb_hiz_offset, always, 2, 0);
- r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
+ r600->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_OFFSET, 1);
ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
- r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
+ r600->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_PITCH, 1);
/* VPU only on TCL */
if (has_tcl) {
int i;
- ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
- r300->hw.vpi.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
- r300->hw.vpi.emit = emit_vpu;
+ ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0);
+ r600->hw.vpi.cmd[0] =
+ cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0);
+ r600->hw.vpi.emit = emit_vpu;
if (is_r500) {
- ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
- r300->hw.vpp.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
- r300->hw.vpp.emit = emit_vpu;
+ ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0);
+ r600->hw.vpp.cmd[0] =
+ cmdvpu(r600->radeon.radeonScreen, R500_PVS_CONST_START, 0);
+ r600->hw.vpp.emit = emit_vpu;
- ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
- r300->hw.vps.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
- r300->hw.vps.emit = emit_vpu;
+ ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0);
+ r600->hw.vps.cmd[0] =
+ cmdvpu(r600->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
+ r600->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
- ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
- r300->hw.vpucp[i].cmd[0] =
- cmdvpu(r300->radeon.radeonScreen,
+ ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0);
+ r600->hw.vpucp[i].cmd[0] =
+ cmdvpu(r600->radeon.radeonScreen,
R500_PVS_UCP_START + i, 1);
- r300->hw.vpucp[i].emit = emit_vpu;
+ r600->hw.vpucp[i].emit = emit_vpu;
}
} else {
- ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
- r300->hw.vpp.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
- r300->hw.vpp.emit = emit_vpu;
+ ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0);
+ r600->hw.vpp.cmd[0] =
+ cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0);
+ r600->hw.vpp.emit = emit_vpu;
- ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
- r300->hw.vps.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
- r300->hw.vps.emit = emit_vpu;
+ ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0);
+ r600->hw.vps.cmd[0] =
+ cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1);
+ r600->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
- ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
- r300->hw.vpucp[i].cmd[0] =
- cmdvpu(r300->radeon.radeonScreen,
- R300_PVS_UCP_START + i, 1);
- r300->hw.vpucp[i].emit = emit_vpu;
+ ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0);
+ r600->hw.vpucp[i].cmd[0] =
+ cmdvpu(r600->radeon.radeonScreen,
+ R600_PVS_UCP_START + i, 1);
+ r600->hw.vpucp[i].emit = emit_vpu;
}
}
}
/* Textures */
ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
- r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
+ r600->hw.tex.filter.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 0);
ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
- r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
+ r600->hw.tex.filter_1.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER1_0, 0);
ALLOC_STATE(tex.size, variable, mtu + 1, 0);
- r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
+ r600->hw.tex.size.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_SIZE_0, 0);
ALLOC_STATE(tex.format, variable, mtu + 1, 0);
- r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
+ r600->hw.tex.format.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT_0, 0);
ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
- r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
+ r600->hw.tex.pitch.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT2_0, 0);
ALLOC_STATE(tex.offset, variable, 1, 0);
- r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
- r300->hw.tex.offset.emit = &emit_tex_offsets;
+ r600->hw.tex.offset.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_OFFSET_0, 0);
+ r600->hw.tex.offset.emit = &emit_tex_offsets;
ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
- r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
+ r600->hw.tex.chroma_key.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_CHROMA_KEY_0, 0);
ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
- r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
+ r600->hw.tex.border_color.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_BORDER_COLOR_0, 0);
- r300->radeon.hw.is_dirty = GL_TRUE;
- r300->radeon.hw.all_dirty = GL_TRUE;
+ r600->radeon.hw.is_dirty = GL_TRUE;
+ r600->radeon.hw.all_dirty = GL_TRUE;
- rcommonInitCmdBuf(&r300->radeon);
+ rcommonInitCmdBuf(&r600->radeon);
}
#include "r600_context.h"
-extern void r300InitCmdBuf(r300ContextPtr r300);
+extern void r600InitCmdBuf(r600ContextPtr r600);
void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom);
int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom);
};
-extern struct tnl_pipeline_stage _r300_render_stage;
-extern const struct tnl_pipeline_stage _r300_tcl_stage;
+extern struct tnl_pipeline_stage _r600_render_stage;
+extern const struct tnl_pipeline_stage _r600_tcl_stage;
-static const struct tnl_pipeline_stage *r300_pipeline[] = {
+static const struct tnl_pipeline_stage *r600_pipeline[] = {
/* Try and go straight to t&l
*/
- &_r300_tcl_stage,
+ &_r600_tcl_stage,
/* Catch any t&l fallbacks
*/
/* Else do them here.
*/
- &_r300_render_stage,
+ &_r600_render_stage,
&_tnl_render_stage, /* FALLBACK */
0,
};
-static void r300RunPipeline(GLcontext * ctx)
+static void r600RunPipeline(GLcontext * ctx)
{
_mesa_lock_context_textures(ctx);
_mesa_unlock_context_textures(ctx);
}
-static void r300_get_lock(radeonContextPtr rmesa)
+static void r600_get_lock(radeonContextPtr rmesa)
{
drm_radeon_sarea_t *sarea = rmesa->sarea;
}
}
-static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
+static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
/* please flush pipe do all pending work */
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_SC_SCREENDOOR, 1));
+ R600_SC_SCREENDOOR, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_SC_SCREENDOOR, 1));
+ R600_SC_SCREENDOOR, 1));
radeon_cs_write_dword(cs, 0x00FFFFFF);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_SC_HYPERZ, 1));
+ R600_SC_HYPERZ, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_US_CONFIG, 1));
+ R600_US_CONFIG, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_ZB_CNTL, 1));
+ R600_ZB_CNTL, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_RB3D_DSTCACHE_CTLSTAT, 1));
- radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
+ R600_RB3D_DSTCACHE_CTLSTAT, 1));
+ radeon_cs_write_dword(cs, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_ZB_ZCACHE_CTLSTAT, 1));
- radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
+ R600_ZB_ZCACHE_CTLSTAT, 1));
+ radeon_cs_write_dword(cs, R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
R300_WAIT_3D | R300_WAIT_3D_CLEAN));
}
-static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
+static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon)
{
- r300ContextPtr r300 = (r300ContextPtr)radeon;
+ r600ContextPtr r600 = (r600ContextPtr)radeon;
BATCH_LOCALS(radeon);
- r300->vap_flush_needed = GL_TRUE;
+ r600->vap_flush_needed = GL_TRUE;
cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
+ OUT_BATCH_REGVAL(R600_TX_INVALTAGS, R600_TX_FLUSH);
END_BATCH();
end_3d(radeon);
}
-static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
+static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
if (mode)
- r300->radeon.Fallback |= bit;
+ r600->radeon.Fallback |= bit;
else
- r300->radeon.Fallback &= ~bit;
+ r600->radeon.Fallback &= ~bit;
}
-static void r300_init_vtbl(radeonContextPtr radeon)
+static void r600_init_vtbl(radeonContextPtr radeon)
{
- radeon->vtbl.get_lock = r300_get_lock;
- radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
- radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
- radeon->vtbl.swtcl_flush = r300_swtcl_flush;
- radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
- radeon->vtbl.fallback = r300_fallback;
+ radeon->vtbl.get_lock = r600_get_lock;
+ radeon->vtbl.update_viewport_offset = r600UpdateViewportOffset;
+ radeon->vtbl.emit_cs_header = r600_vtbl_emit_cs_header;
+ radeon->vtbl.swtcl_flush = r600_swtcl_flush;
+ radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms;
+ radeon->vtbl.fallback = r600_fallback;
}
/* Create the device specific rendering context.
*/
-GLboolean r300CreateContext(const __GLcontextModes * glVisual,
+GLboolean r600CreateContext(const __GLcontextModes * glVisual,
__DRIcontextPrivate * driContextPriv,
void *sharedContextPrivate)
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
struct dd_function_table functions;
- r300ContextPtr r300;
+ r600ContextPtr r600;
GLcontext *ctx;
int tcl_mode;
assert(driContextPriv);
assert(screen);
- /* Allocate the R300 context */
- r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
- if (!r300)
+ /* Allocate the R600 context */
+ r600 = (r600ContextPtr) CALLOC(sizeof(*r600));
+ if (!r600)
return GL_FALSE;
if (!(screen->chip_flags & RADEON_CHIPSET_TCL))
hw_tcl_on = future_hw_tcl_on = 0;
- r300_init_vtbl(&r300->radeon);
+ r600_init_vtbl(&r600->radeon);
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
- driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
- screen->driScreen->myNum, "r300");
- r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache,
+ driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache,
+ screen->driScreen->myNum, "r600");
+ r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache,
"def_max_anisotropy");
- /* Init default driver functions then plug in our R300-specific functions
+ /* Init default driver functions then plug in our R600-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions(&functions);
- r300InitIoctlFuncs(&functions);
- r300InitStateFuncs(&functions);
- r300InitTextureFuncs(&functions);
- r300InitShaderFuncs(&functions);
+ r600InitIoctlFuncs(&functions);
+ r600InitStateFuncs(&functions);
+ r600InitTextureFuncs(&functions);
+ r600InitShaderFuncs(&functions);
- if (!radeonInitContext(&r300->radeon, &functions,
+ if (!radeonInitContext(&r600->radeon, &functions,
glVisual, driContextPriv,
sharedContextPrivate)) {
- FREE(r300);
+ FREE(r600);
return GL_FALSE;
}
- /* Init r300 context data */
+ /* Init r600 context data */
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have them both in
* texturable memory at once.
*/
- ctx = r300->radeon.glCtx;
+ ctx = r600->radeon.glCtx;
ctx->Const.MaxTextureImageUnits =
- driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
+ driQueryOptioni(&r600->radeon.optionCache, "texture_image_units");
ctx->Const.MaxTextureCoordUnits =
- driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
+ driQueryOptioni(&r600->radeon.optionCache, "texture_coord_units");
ctx->Const.MaxTextureUnits =
MIN2(ctx->Const.MaxTextureImageUnits,
ctx->Const.MaxTextureCoordUnits);
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
- ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
- ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
+ ctx->Const.MaxPointSize = R600_POINTSIZE_MAX;
+ ctx->Const.MaxPointSizeAA = R600_POINTSIZE_MAX;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
- ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
- ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
+ ctx->Const.MaxLineWidth = R600_LINESIZE_MAX;
+ ctx->Const.MaxLineWidthAA = R600_LINESIZE_MAX;
/* Needs further modifications */
#if 0
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline(ctx);
- _tnl_install_pipeline(ctx, r300_pipeline);
+ _tnl_install_pipeline(ctx, r600_pipeline);
/* Try and keep materials and vertices separate:
*/
ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
driInitExtensions(ctx, card_extensions, GL_TRUE);
- if (r300->radeon.radeonScreen->kernel_mm)
+ if (r600->radeon.radeonScreen->kernel_mm)
driInitExtensions(ctx, mm_extensions, GL_FALSE);
if (driQueryOptionb
- (&r300->radeon.optionCache, "disable_stencil_two_side"))
+ (&r600->radeon.optionCache, "disable_stencil_two_side"))
_mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
- if (r300->radeon.glCtx->Mesa_DXTn
- && !driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc")) {
+ if (r600->radeon.glCtx->Mesa_DXTn
+ && !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) {
_mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
_mesa_enable_extension(ctx, "GL_S3_s3tc");
} else
- if (driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable"))
+ if (driQueryOptionb(&r600->radeon.optionCache, "force_s3tc_enable"))
{
_mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
}
- r300->disable_lowimpact_fallback =
- driQueryOptionb(&r300->radeon.optionCache,
+ r600->disable_lowimpact_fallback =
+ driQueryOptionb(&r600->radeon.optionCache,
"disable_lowimpact_fallback");
- radeon_fbo_init(&r300->radeon);
+ radeon_fbo_init(&r600->radeon);
radeonInitSpanFuncs( ctx );
- r300InitCmdBuf(r300);
- r300InitState(r300);
+ r600InitCmdBuf(r600);
+ r600InitState(r600);
if (!(screen->chip_flags & RADEON_CHIPSET_TCL))
- r300InitSwtcl(ctx);
+ r600InitSwtcl(ctx);
- TNL_CONTEXT(ctx)->Driver.RunPipeline = r300RunPipeline;
+ TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline;
- tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode");
- if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) {
+ tcl_mode = driQueryOptioni(&r600->radeon.optionCache, "tcl_mode");
+ if (driQueryOptionb(&r600->radeon.optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
#if R200_MERGED
- FALLBACK(&r300->radeon, RADEON_FALLBACK_DISABLE, 1);
+ FALLBACK(&r600->radeon, RADEON_FALLBACK_DISABLE, 1);
#endif
}
if (tcl_mode == DRI_CONF_TCL_SW ||
- !(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
- if (r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
- r300->radeon.radeonScreen->chip_flags &=
+ !(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
+ if (r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
+ r600->radeon.radeonScreen->chip_flags &=
~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
- TCL_FALLBACK(r300->radeon.glCtx,
+ TCL_FALLBACK(r600->radeon.glCtx,
RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
}
#include "main/mtypes.h"
#include "main/colormac.h"
-struct r300_context;
-typedef struct r300_context r300ContextRec;
-typedef struct r300_context *r300ContextPtr;
+struct r600_context;
+typedef struct r600_context r600ContextRec;
+typedef struct r600_context *r600ContextPtr;
#include "main/mm.h"
/* The blit width for texture uploads
*/
-#define R300_BLIT_WIDTH_BYTES 1024
-#define R300_MAX_TEXTURE_UNITS 8
+#define R600_BLIT_WIDTH_BYTES 1024
+#define R600_MAX_TEXTURE_UNITS 8
-struct r300_texture_state {
+struct r600_texture_state {
int tc_count; /* number of incoming texture coordinates from VAP */
};
-#define R300_VPT_CMD_0 0
-#define R300_VPT_XSCALE 1
-#define R300_VPT_XOFFSET 2
-#define R300_VPT_YSCALE 3
-#define R300_VPT_YOFFSET 4
-#define R300_VPT_ZSCALE 5
-#define R300_VPT_ZOFFSET 6
-#define R300_VPT_CMDSIZE 7
-
-#define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
-#define R300_VIR_CNTL_0 1
-#define R300_VIR_CNTL_1 2
-#define R300_VIR_CNTL_2 3
-#define R300_VIR_CNTL_3 4
-#define R300_VIR_CNTL_4 5
-#define R300_VIR_CNTL_5 6
-#define R300_VIR_CNTL_6 7
-#define R300_VIR_CNTL_7 8
-#define R300_VIR_CMDSIZE 9
-
-#define R300_VIC_CMD_0 0
-#define R300_VIC_CNTL_0 1
-#define R300_VIC_CNTL_1 2
-#define R300_VIC_CMDSIZE 3
-
-#define R300_VOF_CMD_0 0
-#define R300_VOF_CNTL_0 1
-#define R300_VOF_CNTL_1 2
-#define R300_VOF_CMDSIZE 3
-
-#define R300_PVS_CMD_0 0
-#define R300_PVS_CNTL_1 1
-#define R300_PVS_CNTL_2 2
-#define R300_PVS_CNTL_3 3
-#define R300_PVS_CMDSIZE 4
-
-#define R300_GB_MISC_CMD_0 0
-#define R300_GB_MISC_MSPOS_0 1
-#define R300_GB_MISC_MSPOS_1 2
-#define R300_GB_MISC_TILE_CONFIG 3
-#define R300_GB_MISC_SELECT 4
-#define R300_GB_MISC_AA_CONFIG 5
-#define R300_GB_MISC_CMDSIZE 6
-
-#define R300_TXE_CMD_0 0
-#define R300_TXE_ENABLE 1
-#define R300_TXE_CMDSIZE 2
-
-#define R300_PS_CMD_0 0
-#define R300_PS_POINTSIZE 1
-#define R300_PS_CMDSIZE 2
-
-#define R300_ZBS_CMD_0 0
-#define R300_ZBS_T_FACTOR 1
-#define R300_ZBS_T_CONSTANT 2
-#define R300_ZBS_W_FACTOR 3
-#define R300_ZBS_W_CONSTANT 4
-#define R300_ZBS_CMDSIZE 5
-
-#define R300_CUL_CMD_0 0
-#define R300_CUL_CULL 1
-#define R300_CUL_CMDSIZE 2
-
-#define R300_RC_CMD_0 0
-#define R300_RC_CNTL_0 1
-#define R300_RC_CNTL_1 2
-#define R300_RC_CMDSIZE 3
-
-#define R300_RI_CMD_0 0
-#define R300_RI_INTERP_0 1
-#define R300_RI_INTERP_1 2
-#define R300_RI_INTERP_2 3
-#define R300_RI_INTERP_3 4
-#define R300_RI_INTERP_4 5
-#define R300_RI_INTERP_5 6
-#define R300_RI_INTERP_6 7
-#define R300_RI_INTERP_7 8
-#define R300_RI_CMDSIZE 9
+#define R600_VPT_CMD_0 0
+#define R600_VPT_XSCALE 1
+#define R600_VPT_XOFFSET 2
+#define R600_VPT_YSCALE 3
+#define R600_VPT_YOFFSET 4
+#define R600_VPT_ZSCALE 5
+#define R600_VPT_ZOFFSET 6
+#define R600_VPT_CMDSIZE 7
+
+#define R600_VIR_CMD_0 0 /* vir is variable size (at least 1) */
+#define R600_VIR_CNTL_0 1
+#define R600_VIR_CNTL_1 2
+#define R600_VIR_CNTL_2 3
+#define R600_VIR_CNTL_3 4
+#define R600_VIR_CNTL_4 5
+#define R600_VIR_CNTL_5 6
+#define R600_VIR_CNTL_6 7
+#define R600_VIR_CNTL_7 8
+#define R600_VIR_CMDSIZE 9
+
+#define R600_VIC_CMD_0 0
+#define R600_VIC_CNTL_0 1
+#define R600_VIC_CNTL_1 2
+#define R600_VIC_CMDSIZE 3
+
+#define R600_VOF_CMD_0 0
+#define R600_VOF_CNTL_0 1
+#define R600_VOF_CNTL_1 2
+#define R600_VOF_CMDSIZE 3
+
+#define R600_PVS_CMD_0 0
+#define R600_PVS_CNTL_1 1
+#define R600_PVS_CNTL_2 2
+#define R600_PVS_CNTL_3 3
+#define R600_PVS_CMDSIZE 4
+
+#define R600_GB_MISC_CMD_0 0
+#define R600_GB_MISC_MSPOS_0 1
+#define R600_GB_MISC_MSPOS_1 2
+#define R600_GB_MISC_TILE_CONFIG 3
+#define R600_GB_MISC_SELECT 4
+#define R600_GB_MISC_AA_CONFIG 5
+#define R600_GB_MISC_CMDSIZE 6
+
+#define R600_TXE_CMD_0 0
+#define R600_TXE_ENABLE 1
+#define R600_TXE_CMDSIZE 2
+
+#define R600_PS_CMD_0 0
+#define R600_PS_POINTSIZE 1
+#define R600_PS_CMDSIZE 2
+
+#define R600_ZBS_CMD_0 0
+#define R600_ZBS_T_FACTOR 1
+#define R600_ZBS_T_CONSTANT 2
+#define R600_ZBS_W_FACTOR 3
+#define R600_ZBS_W_CONSTANT 4
+#define R600_ZBS_CMDSIZE 5
+
+#define R600_CUL_CMD_0 0
+#define R600_CUL_CULL 1
+#define R600_CUL_CMDSIZE 2
+
+#define R600_RC_CMD_0 0
+#define R600_RC_CNTL_0 1
+#define R600_RC_CNTL_1 2
+#define R600_RC_CMDSIZE 3
+
+#define R600_RI_CMD_0 0
+#define R600_RI_INTERP_0 1
+#define R600_RI_INTERP_1 2
+#define R600_RI_INTERP_2 3
+#define R600_RI_INTERP_3 4
+#define R600_RI_INTERP_4 5
+#define R600_RI_INTERP_5 6
+#define R600_RI_INTERP_6 7
+#define R600_RI_INTERP_7 8
+#define R600_RI_CMDSIZE 9
#define R500_RI_CMDSIZE 17
-#define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
-#define R300_RR_INST_0 1
-#define R300_RR_INST_1 2
-#define R300_RR_INST_2 3
-#define R300_RR_INST_3 4
-#define R300_RR_INST_4 5
-#define R300_RR_INST_5 6
-#define R300_RR_INST_6 7
-#define R300_RR_INST_7 8
-#define R300_RR_CMDSIZE 9
-
-#define R300_FP_CMD_0 0
-#define R300_FP_CNTL0 1
-#define R300_FP_CNTL1 2
-#define R300_FP_CNTL2 3
-#define R300_FP_CMD_1 4
-#define R300_FP_NODE0 5
-#define R300_FP_NODE1 6
-#define R300_FP_NODE2 7
-#define R300_FP_NODE3 8
-#define R300_FP_CMDSIZE 9
+#define R600_RR_CMD_0 0 /* rr is variable size (at least 1) */
+#define R600_RR_INST_0 1
+#define R600_RR_INST_1 2
+#define R600_RR_INST_2 3
+#define R600_RR_INST_3 4
+#define R600_RR_INST_4 5
+#define R600_RR_INST_5 6
+#define R600_RR_INST_6 7
+#define R600_RR_INST_7 8
+#define R600_RR_CMDSIZE 9
+
+#define R600_FP_CMD_0 0
+#define R600_FP_CNTL0 1
+#define R600_FP_CNTL1 2
+#define R600_FP_CNTL2 3
+#define R600_FP_CMD_1 4
+#define R600_FP_NODE0 5
+#define R600_FP_NODE1 6
+#define R600_FP_NODE2 7
+#define R600_FP_NODE3 8
+#define R600_FP_CMDSIZE 9
#define R500_FP_CMD_0 0
#define R500_FP_CNTL 1
#define R500_FP_FC_CNTL 8
#define R500_FP_CMDSIZE 9
-#define R300_FPT_CMD_0 0
-#define R300_FPT_INSTR_0 1
-#define R300_FPT_CMDSIZE 65
+#define R600_FPT_CMD_0 0
+#define R600_FPT_INSTR_0 1
+#define R600_FPT_CMDSIZE 65
-#define R300_FPI_CMD_0 0
-#define R300_FPI_INSTR_0 1
-#define R300_FPI_CMDSIZE 65
+#define R600_FPI_CMD_0 0
+#define R600_FPI_INSTR_0 1
+#define R600_FPI_CMDSIZE 65
/* R500 has space for 512 instructions - 6 dwords per instruction */
#define R500_FPI_CMDSIZE (512*6+1)
-#define R300_FPP_CMD_0 0
-#define R300_FPP_PARAM_0 1
-#define R300_FPP_CMDSIZE (32*4+1)
+#define R600_FPP_CMD_0 0
+#define R600_FPP_PARAM_0 1
+#define R600_FPP_CMDSIZE (32*4+1)
/* R500 has spcae for 256 constants - 4 dwords per constant */
#define R500_FPP_CMDSIZE (256*4+1)
-#define R300_FOGS_CMD_0 0
-#define R300_FOGS_STATE 1
-#define R300_FOGS_CMDSIZE 2
-
-#define R300_FOGC_CMD_0 0
-#define R300_FOGC_R 1
-#define R300_FOGC_G 2
-#define R300_FOGC_B 3
-#define R300_FOGC_CMDSIZE 4
-
-#define R300_FOGP_CMD_0 0
-#define R300_FOGP_SCALE 1
-#define R300_FOGP_START 2
-#define R300_FOGP_CMDSIZE 3
-
-#define R300_AT_CMD_0 0
-#define R300_AT_ALPHA_TEST 1
-#define R300_AT_UNKNOWN 2
-#define R300_AT_CMDSIZE 3
-
-#define R300_BLD_CMD_0 0
-#define R300_BLD_CBLEND 1
-#define R300_BLD_ABLEND 2
-#define R300_BLD_CMDSIZE 3
-
-#define R300_CMK_CMD_0 0
-#define R300_CMK_COLORMASK 1
-#define R300_CMK_CMDSIZE 2
-
-#define R300_CB_CMD_0 0
-#define R300_CB_OFFSET 1
-#define R300_CB_CMD_1 2
-#define R300_CB_PITCH 3
-#define R300_CB_CMDSIZE 4
-
-#define R300_ZS_CMD_0 0
-#define R300_ZS_CNTL_0 1
-#define R300_ZS_CNTL_1 2
-#define R300_ZS_CNTL_2 3
-#define R300_ZS_CMDSIZE 4
-
-#define R300_ZB_CMD_0 0
-#define R300_ZB_OFFSET 1
-#define R300_ZB_PITCH 2
-#define R300_ZB_CMDSIZE 3
-
-#define R300_VAP_CNTL_FLUSH 0
-#define R300_VAP_CNTL_FLUSH_1 1
-#define R300_VAP_CNTL_CMD 2
-#define R300_VAP_CNTL_INSTR 3
-#define R300_VAP_CNTL_SIZE 4
-
-#define R300_VPI_CMD_0 0
-#define R300_VPI_INSTR_0 1
-#define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
-
-#define R300_VPP_CMD_0 0
-#define R300_VPP_PARAM_0 1
-#define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
-
-#define R300_VPUCP_CMD_0 0
-#define R300_VPUCP_X 1
-#define R300_VPUCP_Y 2
-#define R300_VPUCP_Z 3
-#define R300_VPUCP_W 4
-#define R300_VPUCP_CMDSIZE 5 /* 256 4-component parameters */
-
-#define R300_VPS_CMD_0 0
-#define R300_VPS_ZERO_0 1
-#define R300_VPS_ZERO_1 2
-#define R300_VPS_POINTSIZE 3
-#define R300_VPS_ZERO_3 4
-#define R300_VPS_CMDSIZE 5
+#define R600_FOGS_CMD_0 0
+#define R600_FOGS_STATE 1
+#define R600_FOGS_CMDSIZE 2
+
+#define R600_FOGC_CMD_0 0
+#define R600_FOGC_R 1
+#define R600_FOGC_G 2
+#define R600_FOGC_B 3
+#define R600_FOGC_CMDSIZE 4
+
+#define R600_FOGP_CMD_0 0
+#define R600_FOGP_SCALE 1
+#define R600_FOGP_START 2
+#define R600_FOGP_CMDSIZE 3
+
+#define R600_AT_CMD_0 0
+#define R600_AT_ALPHA_TEST 1
+#define R600_AT_UNKNOWN 2
+#define R600_AT_CMDSIZE 3
+
+#define R600_BLD_CMD_0 0
+#define R600_BLD_CBLEND 1
+#define R600_BLD_ABLEND 2
+#define R600_BLD_CMDSIZE 3
+
+#define R600_CMK_CMD_0 0
+#define R600_CMK_COLORMASK 1
+#define R600_CMK_CMDSIZE 2
+
+#define R600_CB_CMD_0 0
+#define R600_CB_OFFSET 1
+#define R600_CB_CMD_1 2
+#define R600_CB_PITCH 3
+#define R600_CB_CMDSIZE 4
+
+#define R600_ZS_CMD_0 0
+#define R600_ZS_CNTL_0 1
+#define R600_ZS_CNTL_1 2
+#define R600_ZS_CNTL_2 3
+#define R600_ZS_CMDSIZE 4
+
+#define R600_ZB_CMD_0 0
+#define R600_ZB_OFFSET 1
+#define R600_ZB_PITCH 2
+#define R600_ZB_CMDSIZE 3
+
+#define R600_VAP_CNTL_FLUSH 0
+#define R600_VAP_CNTL_FLUSH_1 1
+#define R600_VAP_CNTL_CMD 2
+#define R600_VAP_CNTL_INSTR 3
+#define R600_VAP_CNTL_SIZE 4
+
+#define R600_VPI_CMD_0 0
+#define R600_VPI_INSTR_0 1
+#define R600_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
+
+#define R600_VPP_CMD_0 0
+#define R600_VPP_PARAM_0 1
+#define R600_VPP_CMDSIZE 1025 /* 256 4-component parameters */
+
+#define R600_VPUCP_CMD_0 0
+#define R600_VPUCP_X 1
+#define R600_VPUCP_Y 2
+#define R600_VPUCP_Z 3
+#define R600_VPUCP_W 4
+#define R600_VPUCP_CMDSIZE 5 /* 256 4-component parameters */
+
+#define R600_VPS_CMD_0 0
+#define R600_VPS_ZERO_0 1
+#define R600_VPS_ZERO_1 2
+#define R600_VPS_POINTSIZE 3
+#define R600_VPS_ZERO_3 4
+#define R600_VPS_CMDSIZE 5
/* the layout is common for all fields inside tex */
-#define R300_TEX_CMD_0 0
-#define R300_TEX_VALUE_0 1
+#define R600_TEX_CMD_0 0
+#define R600_TEX_VALUE_0 1
/* We don't really use this, instead specify mtu+1 dynamically
-#define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
+#define R600_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
*/
/**
* Cache for hardware register state.
*/
-struct r300_hw_state {
+struct r600_hw_state {
struct radeon_state_atom vpt; /* viewport (1D98) */
struct radeon_state_atom vap_cntl;
struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
} tex;
struct radeon_state_atom txe; /* tex enable (4104) */
- radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
+ radeonTexObj *textures[R600_MAX_TEXTURE_UNITS];
};
/**
/* Vertex shader state */
/* Perhaps more if we store programs in vmem? */
-/* drm_r300_cmd_header_t->vpu->count is unsigned char */
+/* drm_r600_cmd_header_t->vpu->count is unsigned char */
#define VSF_MAX_FRAGMENT_LENGTH (255*4)
/* Can be tested with colormat currently. */
#define VSF_MAX_FRAGMENT_TEMPS (14)
-#define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
-#define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
+#define STATE_R600_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
+#define STATE_R600_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
-struct r300_vertex_shader_fragment {
+struct r600_vertex_shader_fragment {
int length;
union {
GLuint d[VSF_MAX_FRAGMENT_LENGTH];
} body;
};
-struct r300_vertex_shader_state {
- struct r300_vertex_shader_fragment program;
+struct r600_vertex_shader_state {
+ struct r600_vertex_shader_fragment program;
};
extern int hw_tcl_on;
#define COLOR_IS_RGBA
-#define TAG(x) r300##x
+#define TAG(x) r600##x
#include "tnl_dd/t_dd_vertex.h"
#undef TAG
//#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
-#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
+#define CURRENT_VERTEX_SHADER(ctx) (R600_CONTEXT(ctx)->selected_vp)
/* Should but doesnt work */
-//#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
+//#define CURRENT_VERTEX_SHADER(ctx) (R600_CONTEXT(ctx)->curr_vp)
-/* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
+/* r600_vertex_shader_state and r600_vertex_program should probably be merged together someday.
* Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
*/
-struct r300_vertex_program_key {
+struct r600_vertex_program_key {
GLuint InputsRead;
GLuint OutputsWritten;
GLuint OutputsAdded;
};
-struct r300_vertex_program {
- struct r300_vertex_program *next;
- struct r300_vertex_program_key key;
+struct r600_vertex_program {
+ struct r600_vertex_program *next;
+ struct r600_vertex_program_key key;
int translated;
- struct r300_vertex_shader_fragment program;
+ struct r600_vertex_shader_fragment program;
int pos_end;
int num_temporaries; /* Number of temp vars used by program */
int use_ref_count;
};
-struct r300_vertex_program_cont {
+struct r600_vertex_program_cont {
struct gl_vertex_program mesa_program; /* Must be first */
- struct r300_vertex_shader_fragment params;
- struct r300_vertex_program *progs;
+ struct r600_vertex_shader_fragment params;
+ struct r600_vertex_program *progs;
};
#define PFS_MAX_ALU_INST 64
#define PFS_NUM_TEMP_REGS 32
#define PFS_NUM_CONST_REGS 16
-struct r300_pfs_compile_state;
+struct r600_pfs_compile_state;
/**
* Stores state that influences the compilation of a fragment program.
*/
-struct r300_fragment_program_external_state {
+struct r600_fragment_program_external_state {
struct {
/**
* If the sampler is used as a shadow sampler,
};
-struct r300_fragment_program_node {
+struct r600_fragment_program_node {
int tex_offset; /**< first tex instruction */
int tex_end; /**< last tex instruction, relative to tex_offset */
int alu_offset; /**< first ALU instruction */
};
/**
- * Stores an R300 fragment program in its compiled-to-hardware form.
+ * Stores an R600 fragment program in its compiled-to-hardware form.
*/
-struct r300_fragment_program_code {
+struct r600_fragment_program_code {
struct {
int length; /**< total # of texture instructions used */
GLuint inst[PFS_MAX_TEX_INST];
} inst[PFS_MAX_ALU_INST];
} alu;
- struct r300_fragment_program_node node[4];
+ struct r600_fragment_program_node node[4];
int cur_node;
int first_node_has_tex;
* Store everything about a fragment program that is needed
* to render with that program.
*/
-struct r300_fragment_program {
+struct r600_fragment_program {
struct gl_fragment_program mesa_program;
GLboolean translated;
GLboolean error;
- struct r300_fragment_program_external_state state;
- struct r300_fragment_program_code code;
+ struct r600_fragment_program_external_state state;
+ struct r600_fragment_program_code code;
GLboolean WritesDepth;
GLuint optimization;
GLuint optimization;
};
-#define R300_MAX_AOS_ARRAYS 16
+#define R600_MAX_AOS_ARRAYS 16
#define REG_COORDS 0
#define REG_COLOR0 1
#define REG_TEX0 2
-struct r300_state {
- struct r300_texture_state texture;
+struct r600_state {
+ struct r600_texture_state texture;
int sw_tcl_inputs[VERT_ATTRIB_MAX];
- struct r300_vertex_shader_state vertex_shader;
+ struct r600_vertex_shader_state vertex_shader;
- DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
+ DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R600 was configured for.
They are the same as tnl->render_inputs for fixed pipeline */
};
-#define R300_FALLBACK_NONE 0
-#define R300_FALLBACK_TCL 1
-#define R300_FALLBACK_RAST 2
+#define R600_FALLBACK_NONE 0
+#define R600_FALLBACK_TCL 1
+#define R600_FALLBACK_RAST 2
-/* r300_swtcl.c
+/* r600_swtcl.c
*/
-struct r300_swtcl_info {
+struct r600_swtcl_info {
/*
* Offset of the 4UB color data within a hardware (swtcl) vertex.
*/
/**
- * \brief R300 context structure.
+ * \brief R600 context structure.
*/
-struct r300_context {
+struct r600_context {
struct radeon_context radeon; /* parent class, must be first */
- struct r300_hw_state hw;
+ struct r600_hw_state hw;
- struct r300_state state;
+ struct r600_state state;
struct gl_vertex_program *curr_vp;
- struct r300_vertex_program *selected_vp;
+ struct r600_vertex_program *selected_vp;
/* Vertex buffers
*/
GLboolean disable_lowimpact_fallback;
- struct r300_swtcl_info swtcl;
+ struct r600_swtcl_info swtcl;
GLboolean vap_flush_needed;
};
-#define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
+#define R600_CONTEXT(ctx) ((r600ContextPtr)(ctx->DriverCtx))
-extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
-extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
+extern void r600DestroyContext(__DRIcontextPrivate * driContextPriv);
+extern GLboolean r600CreateContext(const __GLcontextModes * glVisual,
__DRIcontextPrivate * driContextPriv,
void *sharedContextPrivate);
-extern void r300SelectVertexShader(r300ContextPtr r300);
-extern void r300InitShaderFuncs(struct dd_function_table *functions);
-extern int r300VertexProgUpdateParams(GLcontext * ctx,
- struct r300_vertex_program_cont *vp,
+extern void r600SelectVertexShader(r600ContextPtr r600);
+extern void r600InitShaderFuncs(struct dd_function_table *functions);
+extern int r600VertexProgUpdateParams(GLcontext * ctx,
+ struct r600_vertex_program_cont *vp,
float *dst);
#define RADEON_D_CAPTURE 0
#define RADEON_D_PLAYBACK_RAW 2
#define RADEON_D_T 3
-#define r300PackFloat32 radeonPackFloat32
-#define r300PackFloat24 radeonPackFloat24
+#define r600PackFloat32 radeonPackFloat32
+#define r600PackFloat24 radeonPackFloat24
-#endif /* __R300_CONTEXT_H__ */
+#endif /* __R600_CONTEXT_H__ */
#include "r600_ioctl.h"
-#if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \
- SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \
- SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \
- SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \
- SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \
- SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE
+#if SWIZZLE_X != R600_INPUT_ROUTE_SELECT_X || \
+ SWIZZLE_Y != R600_INPUT_ROUTE_SELECT_Y || \
+ SWIZZLE_Z != R600_INPUT_ROUTE_SELECT_Z || \
+ SWIZZLE_W != R600_INPUT_ROUTE_SELECT_W || \
+ SWIZZLE_ZERO != R600_INPUT_ROUTE_SELECT_ZERO || \
+ SWIZZLE_ONE != R600_INPUT_ROUTE_SELECT_ONE
#error Cannot change these!
#endif
#define DEBUG_ALL DEBUG_VERTS
-#define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \
- (attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT)
+#define DW_SIZE(x) ((inputs[tab[(x)]] << R600_DST_VEC_LOC_SHIFT) | \
+ (attribptr[tab[(x)]]->size - 1) << R600_DATA_TYPE_0_SHIFT)
-GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
+GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
int *inputs, GLint * tab, GLuint nr)
{
GLuint i, dw;
for (i = 0; i < nr; i += 2) {
/* make sure input is valid, would lockup the gpu */
assert(inputs[tab[i]] != -1);
- dw = (R300_SIGNED | DW_SIZE(i));
+ dw = (R600_SIGNED | DW_SIZE(i));
if (i + 1 == nr) {
- dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
+ dw |= R600_LAST_VEC << R600_DATA_TYPE_0_SHIFT;
} else {
assert(inputs[tab[i + 1]] != -1);
- dw |= (R300_SIGNED |
- DW_SIZE(i + 1)) << R300_DATA_TYPE_1_SHIFT;
+ dw |= (R600_SIGNED |
+ DW_SIZE(i + 1)) << R600_DATA_TYPE_1_SHIFT;
if (i + 2 == nr) {
- dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
+ dw |= R600_LAST_VEC << R600_DATA_TYPE_1_SHIFT;
}
}
dst[i >> 1] = dw;
return (nr + 1) >> 1;
}
-static GLuint r300VAPInputRoute1Swizzle(int swizzle[4])
+static GLuint r600VAPInputRoute1Swizzle(int swizzle[4])
{
- return (swizzle[0] << R300_SWIZZLE_SELECT_X_SHIFT) |
- (swizzle[1] << R300_SWIZZLE_SELECT_Y_SHIFT) |
- (swizzle[2] << R300_SWIZZLE_SELECT_Z_SHIFT) |
- (swizzle[3] << R300_SWIZZLE_SELECT_W_SHIFT);
+ return (swizzle[0] << R600_SWIZZLE_SELECT_X_SHIFT) |
+ (swizzle[1] << R600_SWIZZLE_SELECT_Y_SHIFT) |
+ (swizzle[2] << R600_SWIZZLE_SELECT_Z_SHIFT) |
+ (swizzle[3] << R600_SWIZZLE_SELECT_W_SHIFT);
}
-GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr)
+GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr)
{
GLuint i, dw;
for (i = 0; i < nr; i += 2) {
- dw = (r300VAPInputRoute1Swizzle(swizzle[i]) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y |
- R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE0_SHIFT;
+ dw = (r600VAPInputRoute1Swizzle(swizzle[i]) |
+ ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y |
+ R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE0_SHIFT;
if (i + 1 < nr) {
- dw |= (r300VAPInputRoute1Swizzle(swizzle[i + 1]) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y |
- R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT;
+ dw |= (r600VAPInputRoute1Swizzle(swizzle[i + 1]) |
+ ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y |
+ R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE1_SHIFT;
}
dst[i >> 1] = dw;
}
return (nr + 1) >> 1;
}
-GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead)
+GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead)
{
/* No idea what this value means. I have seen other values written to
* this register... */
return 0x5555;
}
-GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
+GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLuint i, vic_1 = 0;
if (InputsRead & (1 << VERT_ATTRIB_POS))
- vic_1 |= R300_INPUT_CNTL_POS;
+ vic_1 |= R600_INPUT_CNTL_POS;
if (InputsRead & (1 << VERT_ATTRIB_NORMAL))
- vic_1 |= R300_INPUT_CNTL_NORMAL;
+ vic_1 |= R600_INPUT_CNTL_NORMAL;
if (InputsRead & (1 << VERT_ATTRIB_COLOR0))
- vic_1 |= R300_INPUT_CNTL_COLOR;
+ vic_1 |= R600_INPUT_CNTL_COLOR;
rmesa->state.texture.tc_count = 0;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) {
rmesa->state.texture.tc_count++;
- vic_1 |= R300_INPUT_CNTL_TC0 << i;
+ vic_1 |= R600_INPUT_CNTL_TC0 << i;
}
return vic_1;
}
-GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten)
+GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten)
{
GLuint ret = 0;
if (OutputsWritten & (1 << VERT_RESULT_HPOS))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
+ ret |= R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
if (OutputsWritten & (1 << VERT_RESULT_COL0))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT;
+ ret |= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT;
if (OutputsWritten & (1 << VERT_RESULT_COL1))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT;
+ ret |= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT;
if (OutputsWritten & (1 << VERT_RESULT_BFC0)
|| OutputsWritten & (1 << VERT_RESULT_BFC1))
ret |=
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT |
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT |
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT;
+ R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT |
+ R600_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT |
+ R600_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT;
if (OutputsWritten & (1 << VERT_RESULT_PSIZ))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
+ ret |= R600_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
return ret;
}
-GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten)
+GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten)
{
GLuint i, ret = 0, first_free_texcoord = 0;
/* Emit vertex data to GART memory
* Route inputs to the vertex processor
- * This function should never return R300_FALLBACK_TCL when using software tcl.
+ * This function should never return R600_FALLBACK_TCL when using software tcl.
*/
-int r300EmitArrays(GLcontext * ctx)
+int r600EmitArrays(GLcontext * ctx)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
GLuint nr;
int vir_inputs[VERT_ATTRIB_MAX];
GLint tab[VERT_ATTRIB_MAX];
int swizzle[VERT_ATTRIB_MAX][4];
- struct r300_vertex_program *prog =
- (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
+ struct r600_vertex_program *prog =
+ (struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
if (hw_tcl_on) {
inputs = prog->inputs;
}
}
- if (nr > R300_MAX_AOS_ARRAYS) {
- return R300_FALLBACK_TCL;
+ if (nr > R600_MAX_AOS_ARRAYS) {
+ return R600_FALLBACK_TCL;
}
for (i = 0; i < nr; i++) {
/* Setup INPUT_ROUTE. */
if (rmesa->radeon.radeonScreen->kernel_mm) {
- R300_STATECHANGE(rmesa, vir[0]);
+ R600_STATECHANGE(rmesa, vir[0]);
rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF;
rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF;
rmesa->hw.vir[0].cmd[0] |=
- (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0],
+ (r600VAPInputRoute0(&rmesa->hw.vir[0].cmd[R600_VIR_CNTL_0],
vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16;
- R300_STATECHANGE(rmesa, vir[1]);
+ R600_STATECHANGE(rmesa, vir[1]);
rmesa->hw.vir[1].cmd[0] |=
- (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
+ (r600VAPInputRoute1(&rmesa->hw.vir[1].cmd[R600_VIR_CNTL_0], swizzle,
nr) & 0x3FFF) << 16;
} else {
- R300_STATECHANGE(rmesa, vir[0]);
+ R600_STATECHANGE(rmesa, vir[0]);
((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count =
- r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0],
+ r600VAPInputRoute0(&rmesa->hw.vir[0].cmd[R600_VIR_CNTL_0],
vb->AttribPtr, inputs, tab, nr);
- R300_STATECHANGE(rmesa, vir[1]);
+ R600_STATECHANGE(rmesa, vir[1]);
((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count =
- r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
+ r600VAPInputRoute1(&rmesa->hw.vir[1].cmd[R600_VIR_CNTL_0], swizzle,
nr);
}
/* Setup INPUT_CNTL. */
- R300_STATECHANGE(rmesa, vic);
- rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead);
- rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead);
+ R600_STATECHANGE(rmesa, vic);
+ rmesa->hw.vic.cmd[R600_VIC_CNTL_0] = r600VAPInputCntl0(ctx, InputsRead);
+ rmesa->hw.vic.cmd[R600_VIC_CNTL_1] = r600VAPInputCntl1(ctx, InputsRead);
/* Setup OUTPUT_VTX_FMT. */
- R300_STATECHANGE(rmesa, vof);
- rmesa->hw.vof.cmd[R300_VOF_CNTL_0] =
- r300VAPOutputCntl0(ctx, OutputsWritten);
- rmesa->hw.vof.cmd[R300_VOF_CNTL_1] =
- r300VAPOutputCntl1(ctx, OutputsWritten);
+ R600_STATECHANGE(rmesa, vof);
+ rmesa->hw.vof.cmd[R600_VOF_CNTL_0] =
+ r600VAPOutputCntl0(ctx, OutputsWritten);
+ rmesa->hw.vof.cmd[R600_VOF_CNTL_1] =
+ r600VAPOutputCntl1(ctx, OutputsWritten);
rmesa->radeon.tcl.aos_count = nr;
- return R300_FALLBACK_NONE;
+ return R600_FALLBACK_NONE;
}
-void r300EmitCacheFlush(r300ContextPtr rmesa)
+void r600EmitCacheFlush(r600ContextPtr rmesa)
{
BATCH_LOCALS(&rmesa->radeon);
BEGIN_BATCH_NO_AUTOSTATE(4);
- OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT,
- R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
- R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
- OUT_BATCH_REGVAL(R300_ZB_ZCACHE_CTLSTAT,
- R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
- R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
+ OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT,
+ R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
+ R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
+ OUT_BATCH_REGVAL(R600_ZB_ZCACHE_CTLSTAT,
+ R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
+ R600_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
END_BATCH();
COMMIT_BATCH();
}
* Jerome Glisse <j.glisse@gmail.com>
*/
-/* This files defines functions for accessing R300 hardware.
+/* This files defines functions for accessing R600 hardware.
*/
#ifndef __R600_EMIT_H__
#define __R600_EMIT_H__
}
}
-void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count)
+void static INLINE cp_delay(r600ContextPtr rmesa, unsigned short count)
{
BATCH_LOCALS(&rmesa->radeon);
}
}
-extern int r300EmitArrays(GLcontext * ctx);
+extern int r600EmitArrays(GLcontext * ctx);
-extern int r300PrimitiveType(r300ContextPtr rmesa, int prim);
-extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
+extern int r600PrimitiveType(r600ContextPtr rmesa, int prim);
+extern int r600NumVerts(r600ContextPtr rmesa, int num_verts, int prim);
-extern void r300EmitCacheFlush(r300ContextPtr rmesa);
+extern void r600EmitCacheFlush(r600ContextPtr rmesa);
-extern GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
+extern GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
int *inputs, GLint * tab, GLuint nr);
-extern GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr);
-extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead);
-extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead);
-extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten);
-extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten);
+extern GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr);
+extern GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead);
+extern GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead);
+extern GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten);
+extern GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten);
#endif
struct radeon_transform_context *t,
struct prog_instruction* orig_inst, void* data)
{
- struct r300_fragment_program_compiler *compiler =
- (struct r300_fragment_program_compiler*)data;
+ struct r600_fragment_program_compiler *compiler =
+ (struct r600_fragment_program_compiler*)data;
struct prog_instruction inst = *orig_inst;
struct prog_instruction* tgt;
GLboolean destredirect = GL_FALSE;
*/
if (inst.Opcode != OPCODE_KIL && inst.TexSrcTarget == TEXTURE_RECT_INDEX) {
gl_state_index tokens[STATE_LENGTH] = {
- STATE_INTERNAL, STATE_R300_TEXRECT_FACTOR, 0, 0,
+ STATE_INTERNAL, STATE_R600_TEXRECT_FACTOR, 0, 0,
0
};
}
-static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp)
+static void update_params(r600ContextPtr r600, struct r600_fragment_program *fp)
{
struct gl_fragment_program *mp = &fp->mesa_program;
/* Ask Mesa nicely to fill in ParameterValues for us */
if (mp->Base.Parameters)
- _mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters);
+ _mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters);
}
* \todo if/when r5xx supports the radeon_program architecture, this is a
* likely candidate for code sharing.
*/
-static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler)
+static void insert_WPOS_trailer(struct r600_fragment_program_compiler *compiler)
{
GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead;
return;
static gl_state_index tokens[STATE_LENGTH] = {
- STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0
+ STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0
};
struct prog_instruction *fpi;
GLuint window_index;
* fragment program.
*/
static void build_state(
- r300ContextPtr r300,
- struct r300_fragment_program *fp,
- struct r300_fragment_program_external_state *state)
+ r600ContextPtr r600,
+ struct r600_fragment_program *fp,
+ struct r600_fragment_program_external_state *state)
{
int unit;
for(unit = 0; unit < 16; ++unit) {
if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) {
- struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current;
+ struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current;
state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode);
state->unit[unit].texture_compare_func = build_func(tex->CompareFunc);
}
-void r300TranslateFragmentShader(r300ContextPtr r300,
- struct r300_fragment_program *fp)
+void r600TranslateFragmentShader(r600ContextPtr r600,
+ struct r600_fragment_program *fp)
{
- struct r300_fragment_program_external_state state;
+ struct r600_fragment_program_external_state state;
- build_state(r300, fp, &state);
+ build_state(r600, fp, &state);
if (_mesa_memcmp(&fp->state, &state, sizeof(state))) {
/* TODO: cache compiled programs */
fp->translated = GL_FALSE;
}
if (!fp->translated) {
- struct r300_fragment_program_compiler compiler;
+ struct r600_fragment_program_compiler compiler;
- compiler.r300 = r300;
+ compiler.r600 = r600;
compiler.fp = fp;
compiler.code = &fp->code;
- compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base);
+ compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Fragment Program: Initial program:\n");
{ &radeonTransformTrigSimple, 0 }
};
radeonLocalTransform(
- r300->radeon.glCtx,
+ r600->radeon.glCtx,
compiler.program,
3, transformations);
struct radeon_nqssadce_descr nqssadce = {
.Init = &nqssadce_init,
- .IsNativeSwizzle = &r300FPIsNativeSwizzle,
- .BuildSwizzle = &r300FPBuildSwizzle,
+ .IsNativeSwizzle = &r600FPIsNativeSwizzle,
+ .BuildSwizzle = &r600FPBuildSwizzle,
.RewriteDepthOut = GL_TRUE
};
- radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce);
+ radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: after NqSSA-DCE:\n");
_mesa_print_program(compiler.program);
}
- if (!r300FragmentProgramEmit(&compiler))
+ if (!r600FragmentProgramEmit(&compiler))
fp->error = GL_TRUE;
/* Subtle: Rescue any parameters that have been added during transformations */
fp->mesa_program.Base.Parameters = compiler.program->Parameters;
compiler.program->Parameters = 0;
- _mesa_reference_program(r300->radeon.glCtx, &compiler.program, NULL);
+ _mesa_reference_program(r600->radeon.glCtx, &compiler.program, NULL);
if (!fp->error)
fp->translated = GL_TRUE;
if (fp->error || (RADEON_DEBUG & DEBUG_PIXEL))
- r300FragmentProgramDump(fp, &fp->code);
- r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM);
+ r600FragmentProgramDump(fp, &fp->code);
+ r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM);
}
- update_params(r300, fp);
+ update_params(r600, fp);
}
/* just some random things... */
-void r300FragmentProgramDump(
- struct r300_fragment_program *fp,
- struct r300_fragment_program_code *code)
+void r600FragmentProgramDump(
+ struct r600_fragment_program *fp,
+ struct r600_fragment_program_code *code)
{
int n, i, j;
static int pc = 0;
const char *instr;
switch ((code->tex.
- inst[i] >> R300_TEX_INST_SHIFT) &
+ inst[i] >> R600_TEX_INST_SHIFT) &
15) {
- case R300_TEX_OP_LD:
+ case R600_TEX_OP_LD:
instr = "TEX";
break;
- case R300_TEX_OP_KIL:
+ case R600_TEX_OP_KIL:
instr = "KIL";
break;
- case R300_TEX_OP_TXP:
+ case R600_TEX_OP_TXP:
instr = "TXP";
break;
- case R300_TEX_OP_TXB:
+ case R600_TEX_OP_TXB:
instr = "TXB";
break;
default:
" %s t%i, %c%i, texture[%i] (%08x)\n",
instr,
(code->tex.
- inst[i] >> R300_DST_ADDR_SHIFT) & 31,
+ inst[i] >> R600_DST_ADDR_SHIFT) & 31,
't',
(code->tex.
- inst[i] >> R300_SRC_ADDR_SHIFT) & 31,
+ inst[i] >> R600_SRC_ADDR_SHIFT) & 31,
(code->tex.
- inst[i] & R300_TEX_ID_MASK) >>
- R300_TEX_ID_SHIFT,
+ inst[i] & R600_TEX_ID_MASK) >>
+ R600_TEX_ID_SHIFT,
code->tex.inst[i]);
}
}
dstc[0] = 0;
sprintf(flags, "%s%s%s",
(code->alu.inst[i].
- inst1 & R300_ALU_DSTC_REG_X) ? "x" : "",
+ inst1 & R600_ALU_DSTC_REG_X) ? "x" : "",
(code->alu.inst[i].
- inst1 & R300_ALU_DSTC_REG_Y) ? "y" : "",
+ inst1 & R600_ALU_DSTC_REG_Y) ? "y" : "",
(code->alu.inst[i].
- inst1 & R300_ALU_DSTC_REG_Z) ? "z" : "");
+ inst1 & R600_ALU_DSTC_REG_Z) ? "z" : "");
if (flags[0] != 0) {
sprintf(dstc, "t%i.%s ",
(code->alu.inst[i].
- inst1 >> R300_ALU_DSTC_SHIFT) & 31,
+ inst1 >> R600_ALU_DSTC_SHIFT) & 31,
flags);
}
sprintf(flags, "%s%s%s",
(code->alu.inst[i].
- inst1 & R300_ALU_DSTC_OUTPUT_X) ? "x" : "",
+ inst1 & R600_ALU_DSTC_OUTPUT_X) ? "x" : "",
(code->alu.inst[i].
- inst1 & R300_ALU_DSTC_OUTPUT_Y) ? "y" : "",
+ inst1 & R600_ALU_DSTC_OUTPUT_Y) ? "y" : "",
(code->alu.inst[i].
- inst1 & R300_ALU_DSTC_OUTPUT_Z) ? "z" : "");
+ inst1 & R600_ALU_DSTC_OUTPUT_Z) ? "z" : "");
if (flags[0] != 0) {
sprintf(tmp, "o%i.%s",
(code->alu.inst[i].
- inst1 >> R300_ALU_DSTC_SHIFT) & 31,
+ inst1 >> R600_ALU_DSTC_SHIFT) & 31,
flags);
strcat(dstc, tmp);
}
dsta[0] = 0;
- if (code->alu.inst[i].inst3 & R300_ALU_DSTA_REG) {
+ if (code->alu.inst[i].inst3 & R600_ALU_DSTA_REG) {
sprintf(dsta, "t%i.w ",
(code->alu.inst[i].
- inst3 >> R300_ALU_DSTA_SHIFT) & 31);
+ inst3 >> R600_ALU_DSTA_SHIFT) & 31);
}
- if (code->alu.inst[i].inst3 & R300_ALU_DSTA_OUTPUT) {
+ if (code->alu.inst[i].inst3 & R600_ALU_DSTA_OUTPUT) {
sprintf(tmp, "o%i.w ",
(code->alu.inst[i].
- inst3 >> R300_ALU_DSTA_SHIFT) & 31);
+ inst3 >> R600_ALU_DSTA_SHIFT) & 31);
strcat(dsta, tmp);
}
- if (code->alu.inst[i].inst3 & R300_ALU_DSTA_DEPTH) {
+ if (code->alu.inst[i].inst3 & R600_ALU_DSTA_DEPTH) {
strcat(dsta, "Z");
}
d = regc & 31;
if (d < 12) {
switch (d % 4) {
- case R300_ALU_ARGC_SRC0C_XYZ:
+ case R600_ALU_ARGC_SRC0C_XYZ:
sprintf(buf, "%s.xyz",
srcc[d / 4]);
break;
- case R300_ALU_ARGC_SRC0C_XXX:
+ case R600_ALU_ARGC_SRC0C_XXX:
sprintf(buf, "%s.xxx",
srcc[d / 4]);
break;
- case R300_ALU_ARGC_SRC0C_YYY:
+ case R600_ALU_ARGC_SRC0C_YYY:
sprintf(buf, "%s.yyy",
srcc[d / 4]);
break;
- case R300_ALU_ARGC_SRC0C_ZZZ:
+ case R600_ALU_ARGC_SRC0C_ZZZ:
sprintf(buf, "%s.zzz",
srcc[d / 4]);
break;
#define FP_SELC_MASK_XYZ 7
#define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \
- (((destidx) << R300_ALU_DSTC_SHIFT) | \
+ (((destidx) << R600_ALU_DSTC_SHIFT) | \
(FP_SELC_MASK_##regmask << 23) | \
(FP_SELC_MASK_##outmask << 26) | \
- ((src0) << R300_ALU_SRC0C_SHIFT) | \
- ((src1) << R300_ALU_SRC1C_SHIFT) | \
- ((src2) << R300_ALU_SRC2C_SHIFT))
+ ((src0) << R600_ALU_SRC0C_SHIFT) | \
+ ((src1) << R600_ALU_SRC1C_SHIFT) | \
+ ((src2) << R600_ALU_SRC2C_SHIFT))
#define FP_SELA_MASK_NO 0
#define FP_SELA_MASK_W 1
#define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \
- (((destidx) << R300_ALU_DSTA_SHIFT) | \
+ (((destidx) << R600_ALU_DSTA_SHIFT) | \
(FP_SELA_MASK_##regmask << 23) | \
(FP_SELA_MASK_##outmask << 24) | \
- ((src0) << R300_ALU_SRC0A_SHIFT) | \
- ((src1) << R300_ALU_SRC1A_SHIFT) | \
- ((src2) << R300_ALU_SRC2A_SHIFT))
+ ((src0) << R600_ALU_SRC0A_SHIFT) | \
+ ((src1) << R600_ALU_SRC1A_SHIFT) | \
+ ((src2) << R600_ALU_SRC2A_SHIFT))
/* Produce unshifted argument selectors */
-#define FP_ARGC(source) R300_ALU_ARGC_##source
-#define FP_ARGA(source) R300_ALU_ARGA_##source
+#define FP_ARGC(source) R600_ALU_ARGC_##source
+#define FP_ARGA(source) R600_ALU_ARGA_##source
#define FP_ABS(arg) ((arg) | (1 << 6))
#define FP_NEG(arg) ((arg) ^ (1 << 5))
/* Produce instruction dword */
#define FP_INSTRC(opcode,arg0,arg1,arg2) \
- (R300_ALU_OUTC_##opcode | \
- ((arg0) << R300_ALU_ARG0C_SHIFT) | \
- ((arg1) << R300_ALU_ARG1C_SHIFT) | \
- ((arg2) << R300_ALU_ARG2C_SHIFT))
+ (R600_ALU_OUTC_##opcode | \
+ ((arg0) << R600_ALU_ARG0C_SHIFT) | \
+ ((arg1) << R600_ALU_ARG1C_SHIFT) | \
+ ((arg2) << R600_ALU_ARG2C_SHIFT))
#define FP_INSTRA(opcode,arg0,arg1,arg2) \
- (R300_ALU_OUTA_##opcode | \
- ((arg0) << R300_ALU_ARG0A_SHIFT) | \
- ((arg1) << R300_ALU_ARG1A_SHIFT) | \
- ((arg2) << R300_ALU_ARG2A_SHIFT))
+ (R600_ALU_OUTA_##opcode | \
+ ((arg0) << R600_ALU_ARG0A_SHIFT) | \
+ ((arg1) << R600_ALU_ARG1A_SHIFT) | \
+ ((arg2) << R600_ALU_ARG2A_SHIFT))
#endif
-struct r300_fragment_program;
+struct r600_fragment_program;
-extern void r300TranslateFragmentShader(r300ContextPtr r300,
- struct r300_fragment_program *fp);
+extern void r600TranslateFragmentShader(r600ContextPtr r600,
+ struct r600_fragment_program *fp);
/**
- * Used internally by the r300 fragment program code to store compile-time
+ * Used internally by the r600 fragment program code to store compile-time
* only data.
*/
-struct r300_fragment_program_compiler {
- r300ContextPtr r300;
- struct r300_fragment_program *fp;
- struct r300_fragment_program_code *code;
+struct r600_fragment_program_compiler {
+ r600ContextPtr r600;
+ struct r600_fragment_program *fp;
+ struct r600_fragment_program_code *code;
struct gl_program *program;
};
-extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler);
+extern GLboolean r600FragmentProgramEmit(struct r600_fragment_program_compiler *compiler);
-extern void r300FragmentProgramDump(
- struct r300_fragment_program *fp,
- struct r300_fragment_program_code *code);
+extern void r600FragmentProgramDump(
+ struct r600_fragment_program *fp,
+ struct r600_fragment_program_code *code);
#endif
/**
* \file
*
- * Emit the r300_fragment_program_code that can be understood by the hardware.
+ * Emit the r600_fragment_program_code that can be understood by the hardware.
* Input is a pre-transformed radeon_program.
*
* \author Ben Skeggs <darktama@iinet.net.au>
#define PROG_CODE \
- struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)data; \
- struct r300_fragment_program_code *code = c->code
+ struct r600_fragment_program_compiler *c = (struct r600_fragment_program_compiler*)data; \
+ struct r600_fragment_program_code *code = c->code
#define error(fmt, args...) do { \
fprintf(stderr, "%s::%s(): " fmt "\n", \
/**
* Mark a temporary register as used.
*/
-static void use_temporary(struct r300_fragment_program_code *code, GLuint index)
+static void use_temporary(struct r600_fragment_program_code *code, GLuint index)
{
if (index > code->max_temp_idx)
code->max_temp_idx = index;
static GLuint translate_rgb_opcode(GLuint opcode)
{
switch(opcode) {
- case OPCODE_CMP: return R300_ALU_OUTC_CMP;
- case OPCODE_DP3: return R300_ALU_OUTC_DP3;
- case OPCODE_DP4: return R300_ALU_OUTC_DP4;
- case OPCODE_FRC: return R300_ALU_OUTC_FRC;
+ case OPCODE_CMP: return R600_ALU_OUTC_CMP;
+ case OPCODE_DP3: return R600_ALU_OUTC_DP3;
+ case OPCODE_DP4: return R600_ALU_OUTC_DP4;
+ case OPCODE_FRC: return R600_ALU_OUTC_FRC;
default:
error("translate_rgb_opcode(%i): Unknown opcode", opcode);
/* fall through */
case OPCODE_NOP:
/* fall through */
- case OPCODE_MAD: return R300_ALU_OUTC_MAD;
- case OPCODE_MAX: return R300_ALU_OUTC_MAX;
- case OPCODE_MIN: return R300_ALU_OUTC_MIN;
- case OPCODE_REPL_ALPHA: return R300_ALU_OUTC_REPL_ALPHA;
+ case OPCODE_MAD: return R600_ALU_OUTC_MAD;
+ case OPCODE_MAX: return R600_ALU_OUTC_MAX;
+ case OPCODE_MIN: return R600_ALU_OUTC_MIN;
+ case OPCODE_REPL_ALPHA: return R600_ALU_OUTC_REPL_ALPHA;
}
}
static GLuint translate_alpha_opcode(GLuint opcode)
{
switch(opcode) {
- case OPCODE_CMP: return R300_ALU_OUTA_CMP;
- case OPCODE_DP3: return R300_ALU_OUTA_DP4;
- case OPCODE_DP4: return R300_ALU_OUTA_DP4;
- case OPCODE_EX2: return R300_ALU_OUTA_EX2;
- case OPCODE_FRC: return R300_ALU_OUTA_FRC;
- case OPCODE_LG2: return R300_ALU_OUTA_LG2;
+ case OPCODE_CMP: return R600_ALU_OUTA_CMP;
+ case OPCODE_DP3: return R600_ALU_OUTA_DP4;
+ case OPCODE_DP4: return R600_ALU_OUTA_DP4;
+ case OPCODE_EX2: return R600_ALU_OUTA_EX2;
+ case OPCODE_FRC: return R600_ALU_OUTA_FRC;
+ case OPCODE_LG2: return R600_ALU_OUTA_LG2;
default:
error("translate_rgb_opcode(%i): Unknown opcode", opcode);
/* fall through */
case OPCODE_NOP:
/* fall through */
- case OPCODE_MAD: return R300_ALU_OUTA_MAD;
- case OPCODE_MAX: return R300_ALU_OUTA_MAX;
- case OPCODE_MIN: return R300_ALU_OUTA_MIN;
- case OPCODE_RCP: return R300_ALU_OUTA_RCP;
- case OPCODE_RSQ: return R300_ALU_OUTA_RSQ;
+ case OPCODE_MAD: return R600_ALU_OUTA_MAD;
+ case OPCODE_MAX: return R600_ALU_OUTA_MAX;
+ case OPCODE_MIN: return R600_ALU_OUTA_MIN;
+ case OPCODE_RCP: return R600_ALU_OUTA_RCP;
+ case OPCODE_RSQ: return R600_ALU_OUTA_RSQ;
}
}
use_temporary(code, inst->Alpha.Src[j].Index);
code->alu.inst[ip].inst3 |= src << (6*j);
- GLuint arg = r300FPTranslateRGBSwizzle(inst->RGB.Arg[j].Source, inst->RGB.Arg[j].Swizzle);
+ GLuint arg = r600FPTranslateRGBSwizzle(inst->RGB.Arg[j].Source, inst->RGB.Arg[j].Swizzle);
arg |= inst->RGB.Arg[j].Abs << 6;
arg |= inst->RGB.Arg[j].Negate << 5;
code->alu.inst[ip].inst0 |= arg << (7*j);
- arg = r300FPTranslateAlphaSwizzle(inst->Alpha.Arg[j].Source, inst->Alpha.Arg[j].Swizzle);
+ arg = r600FPTranslateAlphaSwizzle(inst->Alpha.Arg[j].Source, inst->Alpha.Arg[j].Swizzle);
arg |= inst->Alpha.Arg[j].Abs << 6;
arg |= inst->Alpha.Arg[j].Negate << 5;
code->alu.inst[ip].inst2 |= arg << (7*j);
}
if (inst->RGB.Saturate)
- code->alu.inst[ip].inst0 |= R300_ALU_OUTC_CLAMP;
+ code->alu.inst[ip].inst0 |= R600_ALU_OUTC_CLAMP;
if (inst->Alpha.Saturate)
- code->alu.inst[ip].inst2 |= R300_ALU_OUTA_CLAMP;
+ code->alu.inst[ip].inst2 |= R600_ALU_OUTA_CLAMP;
if (inst->RGB.WriteMask) {
use_temporary(code, inst->RGB.DestIndex);
code->alu.inst[ip].inst1 |=
- (inst->RGB.DestIndex << R300_ALU_DSTC_SHIFT) |
- (inst->RGB.WriteMask << R300_ALU_DSTC_REG_MASK_SHIFT);
+ (inst->RGB.DestIndex << R600_ALU_DSTC_SHIFT) |
+ (inst->RGB.WriteMask << R600_ALU_DSTC_REG_MASK_SHIFT);
}
if (inst->RGB.OutputWriteMask) {
- code->alu.inst[ip].inst1 |= (inst->RGB.OutputWriteMask << R300_ALU_DSTC_OUTPUT_MASK_SHIFT);
- code->node[code->cur_node].flags |= R300_RGBA_OUT;
+ code->alu.inst[ip].inst1 |= (inst->RGB.OutputWriteMask << R600_ALU_DSTC_OUTPUT_MASK_SHIFT);
+ code->node[code->cur_node].flags |= R600_RGBA_OUT;
}
if (inst->Alpha.WriteMask) {
use_temporary(code, inst->Alpha.DestIndex);
code->alu.inst[ip].inst3 |=
- (inst->Alpha.DestIndex << R300_ALU_DSTA_SHIFT) |
- R300_ALU_DSTA_REG;
+ (inst->Alpha.DestIndex << R600_ALU_DSTA_SHIFT) |
+ R600_ALU_DSTA_REG;
}
if (inst->Alpha.OutputWriteMask) {
- code->alu.inst[ip].inst3 |= R300_ALU_DSTA_OUTPUT;
- code->node[code->cur_node].flags |= R300_RGBA_OUT;
+ code->alu.inst[ip].inst3 |= R600_ALU_DSTA_OUTPUT;
+ code->node[code->cur_node].flags |= R600_RGBA_OUT;
}
if (inst->Alpha.DepthWriteMask) {
- code->alu.inst[ip].inst3 |= R300_ALU_DSTA_DEPTH;
- code->node[code->cur_node].flags |= R300_W_OUT;
+ code->alu.inst[ip].inst3 |= R600_ALU_DSTA_DEPTH;
+ code->node[code->cur_node].flags |= R600_W_OUT;
c->fp->WritesDepth = GL_TRUE;
}
/**
* Finish the current node without advancing to the next one.
*/
-static GLboolean finish_node(struct r300_fragment_program_compiler *c)
+static GLboolean finish_node(struct r600_fragment_program_compiler *c)
{
- struct r300_fragment_program_code *code = c->code;
- struct r300_fragment_program_node *node = &code->node[code->cur_node];
+ struct r600_fragment_program_code *code = c->code;
+ struct r600_fragment_program_node *node = &code->node[code->cur_node];
if (node->alu_end < 0) {
/* Generate a single NOP for this node */
if (!finish_node(c))
return GL_FALSE;
- struct r300_fragment_program_node *node = &code->node[++code->cur_node];
+ struct r600_fragment_program_node *node = &code->node[++code->cur_node];
node->alu_offset = code->alu.length;
node->alu_end = -1;
node->tex_offset = code->tex.length;
GLuint opcode;
switch(inst->Opcode) {
- case OPCODE_KIL: opcode = R300_TEX_OP_KIL; break;
- case OPCODE_TEX: opcode = R300_TEX_OP_LD; break;
- case OPCODE_TXB: opcode = R300_TEX_OP_TXB; break;
- case OPCODE_TXP: opcode = R300_TEX_OP_TXP; break;
+ case OPCODE_KIL: opcode = R600_TEX_OP_KIL; break;
+ case OPCODE_TEX: opcode = R600_TEX_OP_LD; break;
+ case OPCODE_TXB: opcode = R600_TEX_OP_TXB; break;
+ case OPCODE_TXP: opcode = R600_TEX_OP_TXP; break;
default:
error("Unknown texture opcode %i", inst->Opcode);
return GL_FALSE;
code->node[code->cur_node].tex_end++;
code->tex.inst[code->tex.length++] =
- (inst->SrcReg[0].Index << R300_SRC_ADDR_SHIFT) |
- (dest << R300_DST_ADDR_SHIFT) |
- (unit << R300_TEX_ID_SHIFT) |
- (opcode << R300_TEX_INST_SHIFT);
+ (inst->SrcReg[0].Index << R600_SRC_ADDR_SHIFT) |
+ (dest << R600_DST_ADDR_SHIFT) |
+ (unit << R600_TEX_ID_SHIFT) |
+ (opcode << R600_TEX_INST_SHIFT);
return GL_TRUE;
}
* Final compilation step: Turn the intermediate radeon_program into
* machine-readable instructions.
*/
-GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler)
+GLboolean r600FragmentProgramEmit(struct r600_fragment_program_compiler *compiler)
{
- struct r300_fragment_program_code *code = compiler->code;
+ struct r600_fragment_program_code *code = compiler->code;
- _mesa_bzero(code, sizeof(struct r300_fragment_program_code));
+ _mesa_bzero(code, sizeof(struct r600_fragment_program_code));
code->node[0].alu_end = -1;
code->node[0].tex_end = -1;
- if (!radeonPairProgram(compiler->r300->radeon.glCtx, compiler->program, &pair_handler, compiler))
+ if (!radeonPairProgram(compiler->r600->radeon.glCtx, compiler->program, &pair_handler, compiler))
return GL_FALSE;
if (!finish_node(compiler))
/**
* @file
- * Utilities to deal with the somewhat odd restriction on R300 fragment
+ * Utilities to deal with the somewhat odd restriction on R600 fragment
* program swizzles.
*/
};
static const struct swizzle_data native_swizzles[] = {
- {MAKE_SWZ3(X, Y, Z), R300_ALU_ARGC_SRC0C_XYZ, 4},
- {MAKE_SWZ3(X, X, X), R300_ALU_ARGC_SRC0C_XXX, 4},
- {MAKE_SWZ3(Y, Y, Y), R300_ALU_ARGC_SRC0C_YYY, 4},
- {MAKE_SWZ3(Z, Z, Z), R300_ALU_ARGC_SRC0C_ZZZ, 4},
- {MAKE_SWZ3(W, W, W), R300_ALU_ARGC_SRC0A, 1},
- {MAKE_SWZ3(Y, Z, X), R300_ALU_ARGC_SRC0C_YZX, 1},
- {MAKE_SWZ3(Z, X, Y), R300_ALU_ARGC_SRC0C_ZXY, 1},
- {MAKE_SWZ3(W, Z, Y), R300_ALU_ARGC_SRC0CA_WZY, 1},
- {MAKE_SWZ3(ONE, ONE, ONE), R300_ALU_ARGC_ONE, 0},
- {MAKE_SWZ3(ZERO, ZERO, ZERO), R300_ALU_ARGC_ZERO, 0}
+ {MAKE_SWZ3(X, Y, Z), R600_ALU_ARGC_SRC0C_XYZ, 4},
+ {MAKE_SWZ3(X, X, X), R600_ALU_ARGC_SRC0C_XXX, 4},
+ {MAKE_SWZ3(Y, Y, Y), R600_ALU_ARGC_SRC0C_YYY, 4},
+ {MAKE_SWZ3(Z, Z, Z), R600_ALU_ARGC_SRC0C_ZZZ, 4},
+ {MAKE_SWZ3(W, W, W), R600_ALU_ARGC_SRC0A, 1},
+ {MAKE_SWZ3(Y, Z, X), R600_ALU_ARGC_SRC0C_YZX, 1},
+ {MAKE_SWZ3(Z, X, Y), R600_ALU_ARGC_SRC0C_ZXY, 1},
+ {MAKE_SWZ3(W, Z, Y), R600_ALU_ARGC_SRC0CA_WZY, 1},
+ {MAKE_SWZ3(ONE, ONE, ONE), R600_ALU_ARGC_ONE, 0},
+ {MAKE_SWZ3(ZERO, ZERO, ZERO), R600_ALU_ARGC_ZERO, 0}
};
static const int num_native_swizzles = sizeof(native_swizzles)/sizeof(native_swizzles[0]);
* Check whether the given instruction supports the swizzle and negate
* combinations in the given source register.
*/
-GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg)
+GLboolean r600FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg)
{
if (reg.Abs)
reg.NegateBase = 0;
/**
* Generate MOV dst, src using only native swizzles.
*/
-void r300FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src)
+void r600FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src)
{
if (src.Abs)
src.NegateBase = 0;
* Translate an RGB (XYZ) swizzle into the hardware code for the given
* instruction source.
*/
-GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle)
+GLuint r600FPTranslateRGBSwizzle(GLuint src, GLuint swizzle)
{
const struct swizzle_data* sd = lookup_native_swizzle(swizzle);
* Translate an Alpha (W) swizzle into the hardware code for the given
* instruction source.
*/
-GLuint r300FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle)
+GLuint r600FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle)
{
if (swizzle < 3)
return swizzle + 3*src;
switch(swizzle) {
- case SWIZZLE_W: return R300_ALU_ARGA_SRC0A + src;
- case SWIZZLE_ONE: return R300_ALU_ARGA_ONE;
- case SWIZZLE_ZERO: return R300_ALU_ARGA_ZERO;
- default: return R300_ALU_ARGA_ONE;
+ case SWIZZLE_W: return R600_ALU_ARGA_SRC0A + src;
+ case SWIZZLE_ONE: return R600_ALU_ARGA_ONE;
+ case SWIZZLE_ZERO: return R600_ALU_ARGA_ZERO;
+ default: return R600_ALU_ARGA_ONE;
}
}
struct nqssadce_state;
-GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg);
-void r300FPBuildSwizzle(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src);
+GLboolean r600FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg);
+void r600FPBuildSwizzle(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src);
-GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle);
-GLuint r300FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle);
+GLuint r600FPTranslateRGBSwizzle(GLuint src, GLuint swizzle);
+GLuint r600FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle);
-#endif /* __R300_FRAGPROG_SWIZZLE_H_ */
+#endif /* __R600_FRAGPROG_SWIZZLE_H_ */
#define CLEARBUFFER_DEPTH 0x2
#define CLEARBUFFER_STENCIL 0x4
-static void r300EmitClearState(GLcontext * ctx);
+static void r600EmitClearState(GLcontext * ctx);
-static void r300UserClear(GLcontext *ctx, GLuint mask)
+static void r600UserClear(GLcontext *ctx, GLuint mask)
{
radeon_clear_tris(ctx, mask);
}
-static void r300ClearBuffer(r300ContextPtr r300, int flags,
+static void r600ClearBuffer(r600ContextPtr r600, int flags,
struct radeon_renderbuffer *rrb,
struct radeon_renderbuffer *rrbd)
{
- BATCH_LOCALS(&r300->radeon);
- GLcontext *ctx = r300->radeon.glCtx;
- __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+ BATCH_LOCALS(&r600->radeon);
+ GLcontext *ctx = r600->radeon.glCtx;
+ __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
GLuint cbpitch = 0;
- r300ContextPtr rmesa = r300;
+ r600ContextPtr rmesa = r600;
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
if (rrb) {
cbpitch = (rrb->pitch / rrb->cpp);
if (rrb->cpp == 4)
- cbpitch |= R300_COLOR_FORMAT_ARGB8888;
+ cbpitch |= R600_COLOR_FORMAT_ARGB8888;
else
- cbpitch |= R300_COLOR_FORMAT_RGB565;
+ cbpitch |= R600_COLOR_FORMAT_RGB565;
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
- cbpitch |= R300_COLOR_TILE_ENABLE;
+ cbpitch |= R600_COLOR_TILE_ENABLE;
}
}
/* TODO in bufmgr */
- cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
+ cp_wait(&r600->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
end_3d(&rmesa->radeon);
if (flags & CLEARBUFFER_COLOR) {
assert(rrb != 0);
BEGIN_BATCH_NO_AUTOSTATE(6);
- OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
+ OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1);
OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch);
+ OUT_BATCH_REGVAL(R600_RB3D_COLORPITCH0, cbpitch);
END_BATCH();
}
#if 1
assert(rrbd != 0);
cbpitch = (rrbd->pitch / rrbd->cpp);
if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
- cbpitch |= R300_DEPTHMACROTILE_ENABLE;
+ cbpitch |= R600_DEPTHMACROTILE_ENABLE;
}
if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
- cbpitch |= R300_DEPTHMICROTILE_TILED;
+ cbpitch |= R600_DEPTHMICROTILE_TILED;
}
BEGIN_BATCH_NO_AUTOSTATE(6);
- OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
+ OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch);
+ OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, cbpitch);
END_BATCH();
}
#endif
t2 = 0x0;
if (flags & CLEARBUFFER_DEPTH) {
- t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
+ t1 |= R600_Z_ENABLE | R600_Z_WRITE_ENABLE;
t2 |=
- (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
+ (R600_ZS_ALWAYS << R600_Z_FUNC_SHIFT);
}
if (flags & CLEARBUFFER_STENCIL) {
- t1 |= R300_STENCIL_ENABLE;
+ t1 |= R600_STENCIL_ENABLE;
t2 |=
- (R300_ZS_ALWAYS <<
- R300_S_FRONT_FUNC_SHIFT) |
- (R300_ZS_REPLACE <<
- R300_S_FRONT_SFAIL_OP_SHIFT) |
- (R300_ZS_REPLACE <<
- R300_S_FRONT_ZPASS_OP_SHIFT) |
- (R300_ZS_REPLACE <<
- R300_S_FRONT_ZFAIL_OP_SHIFT);
+ (R600_ZS_ALWAYS <<
+ R600_S_FRONT_FUNC_SHIFT) |
+ (R600_ZS_REPLACE <<
+ R600_S_FRONT_SFAIL_OP_SHIFT) |
+ (R600_ZS_REPLACE <<
+ R600_S_FRONT_ZPASS_OP_SHIFT) |
+ (R600_ZS_REPLACE <<
+ R600_S_FRONT_ZFAIL_OP_SHIFT);
}
- OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
+ OUT_BATCH_REGSEQ(R600_ZB_CNTL, 3);
OUT_BATCH(t1);
OUT_BATCH(t2);
- OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
- R300_STENCILWRITEMASK_SHIFT) |
- (ctx->Stencil.Clear & R300_STENCILREF_MASK));
+ OUT_BATCH(((ctx->Stencil.WriteMask[0] & R600_STENCILREF_MASK) <<
+ R600_STENCILWRITEMASK_SHIFT) |
+ (ctx->Stencil.Clear & R600_STENCILREF_MASK));
END_BATCH();
}
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(9);
- OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
+ OUT_BATCH(cmdpacket3(r600->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
OUT_BATCH_FLOAT32(dPriv->w / 2.0);
OUT_BATCH_FLOAT32(dPriv->h / 2.0);
OUT_BATCH_FLOAT32(ctx->Depth.Clear);
END_BATCH();
} else {
OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
- OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
- (1 << R300_PRIM_NUM_VERTICES_SHIFT));
+ OUT_BATCH(R600_PRIM_TYPE_POINT | R600_PRIM_WALK_RING |
+ (1 << R600_PRIM_NUM_VERTICES_SHIFT));
OUT_BATCH_FLOAT32(dPriv->w / 2.0);
OUT_BATCH_FLOAT32(dPriv->h / 2.0);
OUT_BATCH_FLOAT32(ctx->Depth.Clear);
OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
}
- r300EmitCacheFlush(rmesa);
- cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
+ r600EmitCacheFlush(rmesa);
+ cp_wait(&r600->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
- R300_STATECHANGE(r300, cb);
- R300_STATECHANGE(r300, cmk);
- R300_STATECHANGE(r300, zs);
+ R600_STATECHANGE(r600, cb);
+ R600_STATECHANGE(r600, cmk);
+ R600_STATECHANGE(r600, zs);
}
-static void r300EmitClearState(GLcontext * ctx)
+static void r600EmitClearState(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
- __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ BATCH_LOCALS(&r600->radeon);
+ __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
int i;
int has_tcl = 1;
int is_r500 = 0;
GLuint vap_cntl;
- if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
+ if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
has_tcl = 0;
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+ if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
is_r500 = 1;
/* State atom dirty tracking is a little subtle here.
* BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
*
* On the other hand, implicit state emission clears the state atom
- * dirty bits, so we have to call R300_STATECHANGE later than the
+ * dirty bits, so we have to call R600_STATECHANGE later than the
* first BEGIN_BATCH.
*
* The final trickiness is that, because we change state, we need
* to ensure that any stored swtcl primitives are flushed properly
- * before we start changing state. See the R300_NEWPRIM in r300Clear
+ * before we start changing state. See the R600_NEWPRIM in r600Clear
* for this.
*/
BEGIN_BATCH(31);
- OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1);
+ OUT_BATCH_REGSEQ(R600_VAP_PROG_STREAM_CNTL_0, 1);
if (!has_tcl)
- OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
- ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
+ OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) |
+ ((R600_LAST_VEC | (2 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT)));
else
- OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
- ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
-
- OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
- OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
- << R300_SWIZZLE0_SHIFT) |
- (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
- << R300_SWIZZLE1_SHIFT)));
-
- /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
- OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2);
- OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
- OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
+ OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) |
+ ((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT)));
+
+ OUT_BATCH_REGVAL(R600_FG_FOG_BLEND, 0);
+ OUT_BATCH_REGVAL(R600_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((((R600_SWIZZLE_SELECT_X << R600_SWIZZLE_SELECT_X_SHIFT) |
+ (R600_SWIZZLE_SELECT_Y << R600_SWIZZLE_SELECT_Y_SHIFT) |
+ (R600_SWIZZLE_SELECT_Z << R600_SWIZZLE_SELECT_Z_SHIFT) |
+ (R600_SWIZZLE_SELECT_W << R600_SWIZZLE_SELECT_W_SHIFT) |
+ ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT))
+ << R600_SWIZZLE0_SHIFT) |
+ (((R600_SWIZZLE_SELECT_X << R600_SWIZZLE_SELECT_X_SHIFT) |
+ (R600_SWIZZLE_SELECT_Y << R600_SWIZZLE_SELECT_Y_SHIFT) |
+ (R600_SWIZZLE_SELECT_Z << R600_SWIZZLE_SELECT_Z_SHIFT) |
+ (R600_SWIZZLE_SELECT_W << R600_SWIZZLE_SELECT_W_SHIFT) |
+ ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT))
+ << R600_SWIZZLE1_SHIFT)));
+
+ /* R600_VAP_INPUT_CNTL_0, R600_VAP_INPUT_CNTL_1 */
+ OUT_BATCH_REGSEQ(R600_VAP_VTX_STATE_CNTL, 2);
+ OUT_BATCH((R600_SEL_USER_COLOR_0 << R600_COLOR_0_ASSEMBLY_SHIFT));
+ OUT_BATCH(R600_INPUT_CNTL_POS | R600_INPUT_CNTL_COLOR | R600_INPUT_CNTL_TC0);
/* comes from fglrx startup of clear */
- OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
- OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA |
- R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
- R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
- R300_VPORT_Z_OFFSET_ENA);
+ OUT_BATCH_REGSEQ(R600_SE_VTE_CNTL, 2);
+ OUT_BATCH(R600_VTX_W0_FMT | R600_VPORT_X_SCALE_ENA |
+ R600_VPORT_X_OFFSET_ENA | R600_VPORT_Y_SCALE_ENA |
+ R600_VPORT_Y_OFFSET_ENA | R600_VPORT_Z_SCALE_ENA |
+ R600_VPORT_Z_OFFSET_ENA);
OUT_BATCH(0x8);
- OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
+ OUT_BATCH_REGVAL(R600_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
- OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
- OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
+ OUT_BATCH_REGSEQ(R600_VAP_OUTPUT_VTX_FMT_0, 2);
+ OUT_BATCH(R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
+ R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
OUT_BATCH(0); /* no textures */
- OUT_BATCH_REGVAL(R300_TX_ENABLE, 0);
+ OUT_BATCH_REGVAL(R600_TX_ENABLE, 0);
- OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6);
+ OUT_BATCH_REGSEQ(R600_SE_VPORT_XSCALE, 6);
OUT_BATCH_FLOAT32(1.0);
OUT_BATCH_FLOAT32(dPriv->x);
OUT_BATCH_FLOAT32(1.0);
OUT_BATCH_FLOAT32(1.0);
OUT_BATCH_FLOAT32(0.0);
- OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
+ OUT_BATCH_REGVAL(R600_FG_ALPHA_FUNC, 0);
- OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
+ OUT_BATCH_REGSEQ(R600_RB3D_CBLEND, 2);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
END_BATCH();
- R300_STATECHANGE(r300, vir[0]);
- R300_STATECHANGE(r300, fogs);
- R300_STATECHANGE(r300, vir[1]);
- R300_STATECHANGE(r300, vic);
- R300_STATECHANGE(r300, vte);
- R300_STATECHANGE(r300, vof);
- R300_STATECHANGE(r300, txe);
- R300_STATECHANGE(r300, vpt);
- R300_STATECHANGE(r300, at);
- R300_STATECHANGE(r300, bld);
- R300_STATECHANGE(r300, ps);
+ R600_STATECHANGE(r600, vir[0]);
+ R600_STATECHANGE(r600, fogs);
+ R600_STATECHANGE(r600, vir[1]);
+ R600_STATECHANGE(r600, vic);
+ R600_STATECHANGE(r600, vte);
+ R600_STATECHANGE(r600, vof);
+ R600_STATECHANGE(r600, txe);
+ R600_STATECHANGE(r600, vpt);
+ R600_STATECHANGE(r600, at);
+ R600_STATECHANGE(r600, bld);
+ R600_STATECHANGE(r600, ps);
if (has_tcl) {
- R300_STATECHANGE(r300, vap_clip_cntl);
+ R600_STATECHANGE(r600, vap_clip_cntl);
BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
+ OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE);
END_BATCH();
}
BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH_REGVAL(R300_GA_POINT_SIZE,
- ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
- ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
+ OUT_BATCH_REGVAL(R600_GA_POINT_SIZE,
+ ((dPriv->w * 6) << R600_POINTSIZE_X_SHIFT) |
+ ((dPriv->h * 6) << R600_POINTSIZE_Y_SHIFT));
END_BATCH();
if (!is_r500) {
- R300_STATECHANGE(r300, ri);
- R300_STATECHANGE(r300, rc);
- R300_STATECHANGE(r300, rr);
+ R600_STATECHANGE(r600, ri);
+ R600_STATECHANGE(r600, rc);
+ R600_STATECHANGE(r600, rr);
BEGIN_BATCH(14);
- OUT_BATCH_REGSEQ(R300_RS_IP_0, 8);
+ OUT_BATCH_REGSEQ(R600_RS_IP_0, 8);
for (i = 0; i < 8; ++i)
- OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
+ OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3));
- OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
- OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
+ OUT_BATCH_REGSEQ(R600_RS_COUNT, 2);
+ OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN);
OUT_BATCH(0x0);
- OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
+ OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE);
END_BATCH();
} else {
- R300_STATECHANGE(r300, ri);
- R300_STATECHANGE(r300, rc);
- R300_STATECHANGE(r300, rr);
+ R600_STATECHANGE(r600, ri);
+ R600_STATECHANGE(r600, rc);
+ R600_STATECHANGE(r600, rr);
BEGIN_BATCH(14);
OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
}
- OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
- OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
+ OUT_BATCH_REGSEQ(R600_RS_COUNT, 2);
+ OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN);
OUT_BATCH(0x0);
OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
}
if (!is_r500) {
- R300_STATECHANGE(r300, fp);
- R300_STATECHANGE(r300, fpi[0]);
- R300_STATECHANGE(r300, fpi[1]);
- R300_STATECHANGE(r300, fpi[2]);
- R300_STATECHANGE(r300, fpi[3]);
+ R600_STATECHANGE(r600, fp);
+ R600_STATECHANGE(r600, fpi[0]);
+ R600_STATECHANGE(r600, fpi[1]);
+ R600_STATECHANGE(r600, fpi[2]);
+ R600_STATECHANGE(r600, fpi[3]);
BEGIN_BATCH(17);
- OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
+ OUT_BATCH_REGSEQ(R600_US_CONFIG, 3);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
- OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
+ OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
- OUT_BATCH(R300_RGBA_OUT);
+ OUT_BATCH(R600_RGBA_OUT);
- OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0,
+ OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0,
FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
- OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0,
+ OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0,
FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
- OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0,
+ OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0,
FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
- OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0,
+ OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0,
FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
END_BATCH();
} else {
struct radeon_state_atom r500fp;
uint32_t _cmd[10];
- R300_STATECHANGE(r300, fp);
- R300_STATECHANGE(r300, r500fp);
+ R600_STATECHANGE(r600, fp);
+ R600_STATECHANGE(r600, r500fp);
BEGIN_BATCH(7);
OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
r500fp.check = check_r500fp;
r500fp.cmd = _cmd;
- r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
+ r500fp.cmd[0] = cmdr500fp(r600->radeon.radeonScreen, 0, 1, 0, 0);
r500fp.cmd[1] = R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
}
BEGIN_BATCH(2);
- OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+ OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
END_BATCH();
if (has_tcl) {
- vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT));
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+ vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R600_PVS_NUM_CNTLRS_SHIFT) |
+ (12 << R600_VF_MAX_VTX_NUM_SHIFT));
+ if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
} else {
- vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (5 << R300_VF_MAX_VTX_NUM_SHIFT));
+ vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R600_PVS_NUM_CNTLRS_SHIFT) |
+ (5 << R600_VF_MAX_VTX_NUM_SHIFT));
}
- if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
- vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
- else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
- (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
- (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
- vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
- else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
- (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
- vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
- else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
- (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
- vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
+ if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
+ vap_cntl |= (2 << R600_PVS_NUM_FPUS_SHIFT);
+ else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
+ (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
+ (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
+ vap_cntl |= (5 << R600_PVS_NUM_FPUS_SHIFT);
+ else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
+ (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
+ vap_cntl |= (6 << R600_PVS_NUM_FPUS_SHIFT);
+ else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
+ (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
+ vap_cntl |= (8 << R600_PVS_NUM_FPUS_SHIFT);
else
- vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
+ vap_cntl |= (4 << R600_PVS_NUM_FPUS_SHIFT);
- R300_STATECHANGE(r300, vap_cntl);
+ R600_STATECHANGE(r600, vap_cntl);
BEGIN_BATCH(2);
- OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl);
+ OUT_BATCH_REGVAL(R600_VAP_CNTL, vap_cntl);
END_BATCH();
if (has_tcl) {
struct radeon_state_atom vpu;
uint32_t _cmd[10];
- R300_STATECHANGE(r300, pvs);
- R300_STATECHANGE(r300, vpi);
+ R600_STATECHANGE(r600, pvs);
+ R600_STATECHANGE(r600, vpi);
BEGIN_BATCH(4);
- OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
- OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
- (0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (1 << R300_PVS_LAST_INST_SHIFT));
- OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
- (0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
- OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
+ OUT_BATCH_REGSEQ(R600_VAP_PVS_CODE_CNTL_0, 3);
+ OUT_BATCH((0 << R600_PVS_FIRST_INST_SHIFT) |
+ (0 << R600_PVS_XYZW_VALID_INST_SHIFT) |
+ (1 << R600_PVS_LAST_INST_SHIFT));
+ OUT_BATCH((0 << R600_PVS_CONST_BASE_OFFSET_SHIFT) |
+ (0 << R600_PVS_MAX_CONST_ADDR_SHIFT));
+ OUT_BATCH(1 << R600_PVS_LAST_VTX_SRC_INST_SHIFT);
END_BATCH();
vpu.check = check_vpu;
vpu.cmd = _cmd;
- vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
+ vpu.cmd[0] = cmdvpu(r600->radeon.radeonScreen, 0, 2);
vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
0, 0xf, PVS_DST_REG_OUT);
PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
vpu.cmd[8] = 0x0;
- r300->vap_flush_needed = GL_TRUE;
+ r600->vap_flush_needed = GL_TRUE;
emit_vpu(ctx, &vpu);
}
}
-static void r300KernelClear(GLcontext *ctx, GLuint flags)
+static void r600KernelClear(GLcontext *ctx, GLuint flags)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
struct radeon_framebuffer *rfb = dPriv->driverPrivate;
struct radeon_renderbuffer *rrb;
struct radeon_renderbuffer *rrbd;
int bits = 0;
/* Make sure it fits there. */
- rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
+ rcommonEnsureCmdBufSpace(&r600->radeon, 421 * 3, __FUNCTION__);
if (flags || bits)
- r300EmitClearState(ctx);
+ r600EmitClearState(ctx);
rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
if (rrbd && (flags & BUFFER_BIT_DEPTH))
bits |= CLEARBUFFER_DEPTH;
if (flags & BUFFER_BIT_COLOR0) {
rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
- r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
+ r600ClearBuffer(r600, CLEARBUFFER_COLOR, rrb, NULL);
bits = 0;
}
if (flags & BUFFER_BIT_FRONT_LEFT) {
rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
- r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
+ r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd);
bits = 0;
}
if (flags & BUFFER_BIT_BACK_LEFT) {
rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
- r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
+ r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd);
bits = 0;
}
if (bits)
- r300ClearBuffer(r300, bits, NULL, rrbd);
+ r600ClearBuffer(r600, bits, NULL, rrbd);
COMMIT_BATCH();
}
/**
* Buffer clear
*/
-static void r300Clear(GLcontext * ctx, GLbitfield mask)
+static void r600Clear(GLcontext * ctx, GLbitfield mask)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
GLbitfield swrast_mask = 0, tri_mask = 0;
int i;
struct gl_framebuffer *fb = ctx->DrawBuffer;
if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "r300Clear\n");
+ fprintf(stderr, "r600Clear\n");
- if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
- LOCK_HARDWARE(&r300->radeon);
- UNLOCK_HARDWARE(&r300->radeon);
+ if (!r600->radeon.radeonScreen->driScreen->dri2.enabled) {
+ LOCK_HARDWARE(&r600->radeon);
+ UNLOCK_HARDWARE(&r600->radeon);
if (dPriv->numClipRects == 0)
return;
}
/* Flush swtcl vertices if necessary, because we will change hardware
* state during clear. See also the state-related comment in
- * r300EmitClearState.
+ * r600EmitClearState.
*/
- R300_NEWPRIM(r300);
+ R600_NEWPRIM(r600);
if (colorMask == ~0)
tri_mask |= (mask & BUFFER_BITS_COLOR);
swrast_mask = mask & ~tri_mask;
if (tri_mask) {
- if (r300->radeon.radeonScreen->kernel_mm)
- r300UserClear(ctx, tri_mask);
+ if (r600->radeon.radeonScreen->kernel_mm)
+ r600UserClear(ctx, tri_mask);
else
- r300KernelClear(ctx, tri_mask);
+ r600KernelClear(ctx, tri_mask);
}
if (swrast_mask) {
if (RADEON_DEBUG & DEBUG_FALLBACKS)
}
-void r300InitIoctlFuncs(struct dd_function_table *functions)
+void r600InitIoctlFuncs(struct dd_function_table *functions)
{
- functions->Clear = r300Clear;
+ functions->Clear = r600Clear;
functions->Finish = radeonFinish;
functions->Flush = radeonFlush;
}
#include "r600_context.h"
#include "radeon_drm.h"
-extern void r300InitIoctlFuncs(struct dd_function_table *functions);
+extern void r600InitIoctlFuncs(struct dd_function_table *functions);
#endif /* __R600_IOCTL_H__ */
/* *INDENT-OFF* */
-#ifndef _R300_REG_H
-#define _R300_REG_H
-
-#define R300_MC_INIT_MISC_LAT_TIMER 0x180
-# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0
-# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4
-# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8
-# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12
-# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16
-# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20
-# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24
-# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28
-
-
-#define R300_MC_INIT_GFX_LAT_TIMER 0x154
-# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0
-# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4
-# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8
-# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12
-# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16
-# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20
-# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24
-# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28
+#ifndef _R600_REG_H
+#define _R600_REG_H
+
+#define R600_MC_INIT_MISC_LAT_TIMER 0x180
+# define R600_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0
+# define R600_MC_MISC__MC_VF_INIT_LAT_SHIFT 4
+# define R600_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8
+# define R600_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12
+# define R600_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16
+# define R600_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20
+# define R600_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24
+# define R600_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28
+
+
+#define R600_MC_INIT_GFX_LAT_TIMER 0x154
+# define R600_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0
+# define R600_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4
+# define R600_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8
+# define R600_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12
+# define R600_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16
+# define R600_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20
+# define R600_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24
+# define R600_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28
/*
- * This file contains registers and constants for the R300. They have been
+ * This file contains registers and constants for the R600. They have been
* found mostly by examining command buffers captured using glxtest, as well
* as by extrapolating some known registers and constants from the R200.
* I am fairly certain that they are correct unless stated otherwise
* in comments.
*/
-#define R300_SE_VPORT_XSCALE 0x1D98
-#define R300_SE_VPORT_XOFFSET 0x1D9C
-#define R300_SE_VPORT_YSCALE 0x1DA0
-#define R300_SE_VPORT_YOFFSET 0x1DA4
-#define R300_SE_VPORT_ZSCALE 0x1DA8
-#define R300_SE_VPORT_ZOFFSET 0x1DAC
+#define R600_SE_VPORT_XSCALE 0x1D98
+#define R600_SE_VPORT_XOFFSET 0x1D9C
+#define R600_SE_VPORT_YSCALE 0x1DA0
+#define R600_SE_VPORT_YOFFSET 0x1DA4
+#define R600_SE_VPORT_ZSCALE 0x1DA8
+#define R600_SE_VPORT_ZOFFSET 0x1DAC
-#define R300_VAP_PORT_IDX0 0x2040
+#define R600_VAP_PORT_IDX0 0x2040
/*
* Vertex Array Processing (VAP) Control
*/
-#define R300_VAP_CNTL 0x2080
-# define R300_PVS_NUM_SLOTS_SHIFT 0
-# define R300_PVS_NUM_CNTLRS_SHIFT 4
-# define R300_PVS_NUM_FPUS_SHIFT 8
-# define R300_VF_MAX_VTX_NUM_SHIFT 18
-# define R300_GL_CLIP_SPACE_DEF (0 << 22)
-# define R300_DX_CLIP_SPACE_DEF (1 << 22)
+#define R600_VAP_CNTL 0x2080
+# define R600_PVS_NUM_SLOTS_SHIFT 0
+# define R600_PVS_NUM_CNTLRS_SHIFT 4
+# define R600_PVS_NUM_FPUS_SHIFT 8
+# define R600_VF_MAX_VTX_NUM_SHIFT 18
+# define R600_GL_CLIP_SPACE_DEF (0 << 22)
+# define R600_DX_CLIP_SPACE_DEF (1 << 22)
# define R500_TCL_STATE_OPTIMIZATION (1 << 23)
/* This register is written directly and also starts data section
* in many 3d CP_PACKET3's
*/
-#define R300_VAP_VF_CNTL 0x2084
-# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
-# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
-# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
-# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
-# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
-# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
-# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
-# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
-# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
-# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
-# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
-# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
-
-# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
+#define R600_VAP_VF_CNTL 0x2084
+# define R600_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
+# define R600_VAP_VF_CNTL__PRIM_NONE (0<<0)
+# define R600_VAP_VF_CNTL__PRIM_POINTS (1<<0)
+# define R600_VAP_VF_CNTL__PRIM_LINES (2<<0)
+# define R600_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
+# define R600_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
+# define R600_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
+# define R600_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
+# define R600_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
+# define R600_VAP_VF_CNTL__PRIM_QUADS (13<<0)
+# define R600_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
+# define R600_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
+
+# define R600_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
/* State based - direct writes to registers trigger vertex
generation */
-# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
-# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
-# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
-# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
+# define R600_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
+# define R600_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
+# define R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
+# define R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
/* I don't think I saw these three used.. */
-# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
-# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
-# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
+# define R600_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
+# define R600_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
+# define R600_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
/* index size - when not set the indices are assumed to be 16 bit */
-# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
+# define R600_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
/* number of vertices */
-# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
+# define R600_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
#define R500_VAP_INDEX_OFFSET 0x208c
-#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
-# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
-# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16)
+#define R600_VAP_OUTPUT_VTX_FMT_0 0x2090
+# define R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
+# define R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
+# define R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
+# define R600_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
+# define R600_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
+# define R600_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16)
-#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
+#define R600_VAP_OUTPUT_VTX_FMT_1 0x2094
/* each of the following is 3 bits wide, specifies number
of components */
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
-# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0
-# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1
-# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2
-# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3
-# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4
-
-#define R300_SE_VTE_CNTL 0x20b0
-# define R300_VPORT_X_SCALE_ENA (1 << 0)
-# define R300_VPORT_X_OFFSET_ENA (1 << 1)
-# define R300_VPORT_Y_SCALE_ENA (1 << 2)
-# define R300_VPORT_Y_OFFSET_ENA (1 << 3)
-# define R300_VPORT_Z_SCALE_ENA (1 << 4)
-# define R300_VPORT_Z_OFFSET_ENA (1 << 5)
-# define R300_VTX_XY_FMT (1 << 8)
-# define R300_VTX_Z_FMT (1 << 9)
-# define R300_VTX_W0_FMT (1 << 10)
-# define R300_SERIAL_PROC_ENA (1 << 11)
+# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
+# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
+# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
+# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
+# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
+# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
+# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
+# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
+# define R600_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0
+# define R600_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1
+# define R600_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2
+# define R600_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3
+# define R600_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4
+
+#define R600_SE_VTE_CNTL 0x20b0
+# define R600_VPORT_X_SCALE_ENA (1 << 0)
+# define R600_VPORT_X_OFFSET_ENA (1 << 1)
+# define R600_VPORT_Y_SCALE_ENA (1 << 2)
+# define R600_VPORT_Y_OFFSET_ENA (1 << 3)
+# define R600_VPORT_Z_SCALE_ENA (1 << 4)
+# define R600_VPORT_Z_OFFSET_ENA (1 << 5)
+# define R600_VTX_XY_FMT (1 << 8)
+# define R600_VTX_Z_FMT (1 << 9)
+# define R600_VTX_W0_FMT (1 << 10)
+# define R600_SERIAL_PROC_ENA (1 << 11)
/* BEGIN: Vertex data assembly - lots of uncertainties */
/* gap */
/* Maximum Vertex Indx Clamp */
-#define R300_VAP_VF_MAX_VTX_INDX 0x2134
+#define R600_VAP_VF_MAX_VTX_INDX 0x2134
/* Minimum Vertex Indx Clamp */
-#define R300_VAP_VF_MIN_VTX_INDX 0x2138
+#define R600_VAP_VF_MIN_VTX_INDX 0x2138
/** Vertex assembler/processor control status */
-#define R300_VAP_CNTL_STATUS 0x2140
+#define R600_VAP_CNTL_STATUS 0x2140
/* No swap at all (default) */
-# define R300_VC_NO_SWAP (0 << 0)
+# define R600_VC_NO_SWAP (0 << 0)
/* 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC */
-# define R300_VC_16BIT_SWAP (1 << 0)
+# define R600_VC_16BIT_SWAP (1 << 0)
/* 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA */
-# define R300_VC_32BIT_SWAP (2 << 0)
+# define R600_VC_32BIT_SWAP (2 << 0)
/* Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB */
-# define R300_VC_HALF_DWORD_SWAP (3 << 0)
+# define R600_VC_HALF_DWORD_SWAP (3 << 0)
/* The TCL engine will not be used (as it is logically or even physically removed) */
-# define R300_VAP_TCL_BYPASS (1 << 8)
+# define R600_VAP_TCL_BYPASS (1 << 8)
/* Read only flag if TCL engine is busy. */
-# define R300_VAP_PVS_BUSY (1 << 11)
+# define R600_VAP_PVS_BUSY (1 << 11)
/* TODO: gap for MAX_MPS */
/* Read only flag if the vertex store is busy. */
-# define R300_VAP_VS_BUSY (1 << 24)
+# define R600_VAP_VS_BUSY (1 << 24)
/* Read only flag if the reciprocal engine is busy. */
-# define R300_VAP_RCP_BUSY (1 << 25)
+# define R600_VAP_RCP_BUSY (1 << 25)
/* Read only flag if the viewport transform engine is busy. */
-# define R300_VAP_VTE_BUSY (1 << 26)
+# define R600_VAP_VTE_BUSY (1 << 26)
/* Read only flag if the memory interface unit is busy. */
-# define R300_VAP_MUI_BUSY (1 << 27)
+# define R600_VAP_MUI_BUSY (1 << 27)
/* Read only flag if the vertex cache is busy. */
-# define R300_VAP_VC_BUSY (1 << 28)
+# define R600_VAP_VC_BUSY (1 << 28)
/* Read only flag if the vertex fetcher is busy. */
-# define R300_VAP_VF_BUSY (1 << 29)
+# define R600_VAP_VF_BUSY (1 << 29)
/* Read only flag if the register pipeline is busy. */
-# define R300_VAP_REGPIPE_BUSY (1 << 30)
+# define R600_VAP_REGPIPE_BUSY (1 << 30)
/* Read only flag if the VAP engine is busy. */
-# define R300_VAP_VAP_BUSY (1 << 31)
+# define R600_VAP_VAP_BUSY (1 << 31)
/* gap */
* Always set COMPONENTS_4 in immediate mode.
*/
-#define R300_VAP_PROG_STREAM_CNTL_0 0x2150
-# define R300_DATA_TYPE_0_SHIFT 0
-# define R300_DATA_TYPE_FLOAT_1 0
-# define R300_DATA_TYPE_FLOAT_2 1
-# define R300_DATA_TYPE_FLOAT_3 2
-# define R300_DATA_TYPE_FLOAT_4 3
-# define R300_DATA_TYPE_BYTE 4
-# define R300_DATA_TYPE_D3DCOLOR 5
-# define R300_DATA_TYPE_SHORT_2 6
-# define R300_DATA_TYPE_SHORT_4 7
-# define R300_DATA_TYPE_VECTOR_3_TTT 8
-# define R300_DATA_TYPE_VECTOR_3_EET 9
-# define R300_SKIP_DWORDS_SHIFT 4
-# define R300_DST_VEC_LOC_SHIFT 8
-# define R300_LAST_VEC (1 << 13)
-# define R300_SIGNED (1 << 14)
-# define R300_NORMALIZE (1 << 15)
-# define R300_DATA_TYPE_1_SHIFT 16
-#define R300_VAP_PROG_STREAM_CNTL_1 0x2154
-#define R300_VAP_PROG_STREAM_CNTL_2 0x2158
-#define R300_VAP_PROG_STREAM_CNTL_3 0x215C
-#define R300_VAP_PROG_STREAM_CNTL_4 0x2160
-#define R300_VAP_PROG_STREAM_CNTL_5 0x2164
-#define R300_VAP_PROG_STREAM_CNTL_6 0x2168
-#define R300_VAP_PROG_STREAM_CNTL_7 0x216C
+#define R600_VAP_PROG_STREAM_CNTL_0 0x2150
+# define R600_DATA_TYPE_0_SHIFT 0
+# define R600_DATA_TYPE_FLOAT_1 0
+# define R600_DATA_TYPE_FLOAT_2 1
+# define R600_DATA_TYPE_FLOAT_3 2
+# define R600_DATA_TYPE_FLOAT_4 3
+# define R600_DATA_TYPE_BYTE 4
+# define R600_DATA_TYPE_D3DCOLOR 5
+# define R600_DATA_TYPE_SHORT_2 6
+# define R600_DATA_TYPE_SHORT_4 7
+# define R600_DATA_TYPE_VECTOR_3_TTT 8
+# define R600_DATA_TYPE_VECTOR_3_EET 9
+# define R600_SKIP_DWORDS_SHIFT 4
+# define R600_DST_VEC_LOC_SHIFT 8
+# define R600_LAST_VEC (1 << 13)
+# define R600_SIGNED (1 << 14)
+# define R600_NORMALIZE (1 << 15)
+# define R600_DATA_TYPE_1_SHIFT 16
+#define R600_VAP_PROG_STREAM_CNTL_1 0x2154
+#define R600_VAP_PROG_STREAM_CNTL_2 0x2158
+#define R600_VAP_PROG_STREAM_CNTL_3 0x215C
+#define R600_VAP_PROG_STREAM_CNTL_4 0x2160
+#define R600_VAP_PROG_STREAM_CNTL_5 0x2164
+#define R600_VAP_PROG_STREAM_CNTL_6 0x2168
+#define R600_VAP_PROG_STREAM_CNTL_7 0x216C
/* gap */
/* Notes:
* if vertex program uses only position, fglrx will set normal, too
* - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
*/
-#define R300_VAP_VTX_STATE_CNTL 0x2180
-# define R300_COLOR_0_ASSEMBLY_SHIFT 0
-# define R300_SEL_COLOR 0
-# define R300_SEL_USER_COLOR_0 1
-# define R300_SEL_USER_COLOR_1 2
-# define R300_COLOR_1_ASSEMBLY_SHIFT 2
-# define R300_COLOR_2_ASSEMBLY_SHIFT 4
-# define R300_COLOR_3_ASSEMBLY_SHIFT 6
-# define R300_COLOR_4_ASSEMBLY_SHIFT 8
-# define R300_COLOR_5_ASSEMBLY_SHIFT 10
-# define R300_COLOR_6_ASSEMBLY_SHIFT 12
-# define R300_COLOR_7_ASSEMBLY_SHIFT 14
-# define R300_UPDATE_USER_COLOR_0_ENA (1 << 16)
+#define R600_VAP_VTX_STATE_CNTL 0x2180
+# define R600_COLOR_0_ASSEMBLY_SHIFT 0
+# define R600_SEL_COLOR 0
+# define R600_SEL_USER_COLOR_0 1
+# define R600_SEL_USER_COLOR_1 2
+# define R600_COLOR_1_ASSEMBLY_SHIFT 2
+# define R600_COLOR_2_ASSEMBLY_SHIFT 4
+# define R600_COLOR_3_ASSEMBLY_SHIFT 6
+# define R600_COLOR_4_ASSEMBLY_SHIFT 8
+# define R600_COLOR_5_ASSEMBLY_SHIFT 10
+# define R600_COLOR_6_ASSEMBLY_SHIFT 12
+# define R600_COLOR_7_ASSEMBLY_SHIFT 14
+# define R600_UPDATE_USER_COLOR_0_ENA (1 << 16)
/*
* Each bit in this field applies to the corresponding vector in the VSM
* memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit
* is set, then the corresponding 4-Dword Vector is output into the Vertex Stream.
*/
-#define R300_VAP_VSM_VTX_ASSM 0x2184
-# define R300_INPUT_CNTL_POS 0x00000001
-# define R300_INPUT_CNTL_NORMAL 0x00000002
-# define R300_INPUT_CNTL_COLOR 0x00000004
-# define R300_INPUT_CNTL_TC0 0x00000400
-# define R300_INPUT_CNTL_TC1 0x00000800
-# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
-# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
-# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
-# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
-# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
-# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
+#define R600_VAP_VSM_VTX_ASSM 0x2184
+# define R600_INPUT_CNTL_POS 0x00000001
+# define R600_INPUT_CNTL_NORMAL 0x00000002
+# define R600_INPUT_CNTL_COLOR 0x00000004
+# define R600_INPUT_CNTL_TC0 0x00000400
+# define R600_INPUT_CNTL_TC1 0x00000800
+# define R600_INPUT_CNTL_TC2 0x00001000 /* GUESS */
+# define R600_INPUT_CNTL_TC3 0x00002000 /* GUESS */
+# define R600_INPUT_CNTL_TC4 0x00004000 /* GUESS */
+# define R600_INPUT_CNTL_TC5 0x00008000 /* GUESS */
+# define R600_INPUT_CNTL_TC6 0x00010000 /* GUESS */
+# define R600_INPUT_CNTL_TC7 0x00020000 /* GUESS */
/* Programmable Stream Control Signed Normalize Control */
-#define R300_VAP_PSC_SGN_NORM_CNTL 0x21dc
+#define R600_VAP_PSC_SGN_NORM_CNTL 0x21dc
# define SGN_NORM_ZERO 0
# define SGN_NORM_ZERO_CLAMP_MINUS_ONE 1
# define SGN_NORM_NO_ZERO 2
* mode, the swizzling pattern is e.g. used to set zw components in texture
* coordinates with only tweo components.
*/
-#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
-# define R300_SWIZZLE0_SHIFT 0
-# define R300_SWIZZLE_SELECT_X_SHIFT 0
-# define R300_SWIZZLE_SELECT_Y_SHIFT 3
-# define R300_SWIZZLE_SELECT_Z_SHIFT 6
-# define R300_SWIZZLE_SELECT_W_SHIFT 9
-
-# define R300_SWIZZLE_SELECT_X 0
-# define R300_SWIZZLE_SELECT_Y 1
-# define R300_SWIZZLE_SELECT_Z 2
-# define R300_SWIZZLE_SELECT_W 3
-# define R300_SWIZZLE_SELECT_FP_ZERO 4
-# define R300_SWIZZLE_SELECT_FP_ONE 5
-/* alternate forms for r300_emit.c */
-# define R300_INPUT_ROUTE_SELECT_X 0
-# define R300_INPUT_ROUTE_SELECT_Y 1
-# define R300_INPUT_ROUTE_SELECT_Z 2
-# define R300_INPUT_ROUTE_SELECT_W 3
-# define R300_INPUT_ROUTE_SELECT_ZERO 4
-# define R300_INPUT_ROUTE_SELECT_ONE 5
-
-# define R300_WRITE_ENA_SHIFT 12
-# define R300_WRITE_ENA_X 1
-# define R300_WRITE_ENA_Y 2
-# define R300_WRITE_ENA_Z 4
-# define R300_WRITE_ENA_W 8
-# define R300_SWIZZLE1_SHIFT 16
-#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
-#define R300_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8
-#define R300_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec
-#define R300_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0
-#define R300_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4
-#define R300_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8
-#define R300_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc
+#define R600_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
+# define R600_SWIZZLE0_SHIFT 0
+# define R600_SWIZZLE_SELECT_X_SHIFT 0
+# define R600_SWIZZLE_SELECT_Y_SHIFT 3
+# define R600_SWIZZLE_SELECT_Z_SHIFT 6
+# define R600_SWIZZLE_SELECT_W_SHIFT 9
+
+# define R600_SWIZZLE_SELECT_X 0
+# define R600_SWIZZLE_SELECT_Y 1
+# define R600_SWIZZLE_SELECT_Z 2
+# define R600_SWIZZLE_SELECT_W 3
+# define R600_SWIZZLE_SELECT_FP_ZERO 4
+# define R600_SWIZZLE_SELECT_FP_ONE 5
+/* alternate forms for r600_emit.c */
+# define R600_INPUT_ROUTE_SELECT_X 0
+# define R600_INPUT_ROUTE_SELECT_Y 1
+# define R600_INPUT_ROUTE_SELECT_Z 2
+# define R600_INPUT_ROUTE_SELECT_W 3
+# define R600_INPUT_ROUTE_SELECT_ZERO 4
+# define R600_INPUT_ROUTE_SELECT_ONE 5
+
+# define R600_WRITE_ENA_SHIFT 12
+# define R600_WRITE_ENA_X 1
+# define R600_WRITE_ENA_Y 2
+# define R600_WRITE_ENA_Z 4
+# define R600_WRITE_ENA_W 8
+# define R600_SWIZZLE1_SHIFT 16
+#define R600_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
+#define R600_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8
+#define R600_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec
+#define R600_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0
+#define R600_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4
+#define R600_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8
+#define R600_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc
/* END: Vertex data assembly */
*
* At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
* floating point pointsize. The exact purpose of this state is uncertain,
- * as there is also the R300_RE_POINTSIZE register.
+ * as there is also the R600_RE_POINTSIZE register.
*
* Multiple vertex programs and parameter sets can be loaded at once,
* which could explain the size discrepancy.
*/
-#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
-# define R300_PVS_CODE_START 0
-# define R300_MAX_PVS_CODE_LINES 256
+#define R600_VAP_PVS_VECTOR_INDX_REG 0x2200
+# define R600_PVS_CODE_START 0
+# define R600_MAX_PVS_CODE_LINES 256
# define R500_MAX_PVS_CODE_LINES 1024
-# define R300_PVS_CONST_START 512
+# define R600_PVS_CONST_START 512
# define R500_PVS_CONST_START 1024
-# define R300_MAX_PVS_CONST_VECS 256
+# define R600_MAX_PVS_CONST_VECS 256
# define R500_MAX_PVS_CONST_VECS 1024
-# define R300_PVS_UCP_START 1024
+# define R600_PVS_UCP_START 1024
# define R500_PVS_UCP_START 1536
-# define R300_POINT_VPORT_SCALE_OFFSET 1030
+# define R600_POINT_VPORT_SCALE_OFFSET 1030
# define R500_POINT_VPORT_SCALE_OFFSET 1542
-# define R300_POINT_GEN_TEX_OFFSET 1031
+# define R600_POINT_GEN_TEX_OFFSET 1031
# define R500_POINT_GEN_TEX_OFFSET 1543
/*
- * These are obsolete defines form r300_context.h, but they might give some
+ * These are obsolete defines form r600_context.h, but they might give some
* clues when investigating the addresses further...
*/
#if 0
/* gap */
-#define R300_VAP_PVS_UPLOAD_DATA 0x2208
+#define R600_VAP_PVS_UPLOAD_DATA 0x2208
/* END: Upload vertex program and data */
*
* See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view
*/
-#define R300_VAP_CLIP_CNTL 0x221C
-# define R300_VAP_UCP_ENABLE_0 (1 << 0)
-# define R300_VAP_UCP_ENABLE_1 (1 << 1)
-# define R300_VAP_UCP_ENABLE_2 (1 << 2)
-# define R300_VAP_UCP_ENABLE_3 (1 << 3)
-# define R300_VAP_UCP_ENABLE_4 (1 << 4)
-# define R300_VAP_UCP_ENABLE_5 (1 << 5)
-# define R300_PS_UCP_MODE_DIST_COP (0 << 14)
-# define R300_PS_UCP_MODE_RADIUS_COP (1 << 14)
-# define R300_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14)
-# define R300_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14)
-# define R300_CLIP_DISABLE (1 << 16)
-# define R300_UCP_CULL_ONLY_ENABLE (1 << 17)
-# define R300_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18)
+#define R600_VAP_CLIP_CNTL 0x221C
+# define R600_VAP_UCP_ENABLE_0 (1 << 0)
+# define R600_VAP_UCP_ENABLE_1 (1 << 1)
+# define R600_VAP_UCP_ENABLE_2 (1 << 2)
+# define R600_VAP_UCP_ENABLE_3 (1 << 3)
+# define R600_VAP_UCP_ENABLE_4 (1 << 4)
+# define R600_VAP_UCP_ENABLE_5 (1 << 5)
+# define R600_PS_UCP_MODE_DIST_COP (0 << 14)
+# define R600_PS_UCP_MODE_RADIUS_COP (1 << 14)
+# define R600_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14)
+# define R600_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14)
+# define R600_CLIP_DISABLE (1 << 16)
+# define R600_UCP_CULL_ONLY_ENABLE (1 << 17)
+# define R600_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18)
# define R500_COLOR2_IS_TEXTURE (1 << 20)
# define R500_COLOR3_IS_TEXTURE (1 << 21)
*
* These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
*/
-#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220
-#define R300_VAP_GB_VERT_DISC_ADJ 0x2224
-#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228
-#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c
+#define R600_VAP_GB_VERT_CLIP_ADJ 0x2220
+#define R600_VAP_GB_VERT_DISC_ADJ 0x2224
+#define R600_VAP_GB_HORZ_CLIP_ADJ 0x2228
+#define R600_VAP_GB_HORZ_DISC_ADJ 0x222c
/* gap */
* Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
* avoids bugs caused by still running shaders reading bad data from memory.
*/
-#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
+#define R600_VAP_PVS_STATE_FLUSH_REG 0x2284
/* This register is used to define the number of core clocks to wait for a
* vertex to be received by the VAP input controller (while the primitive
* to the vertex processing path.
*/
#define VAP_PVS_VTX_TIMEOUT_REG 0x2288
-# define R300_2288_R300 0x00750000 /* -- nh */
-# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
+# define R600_2288_R600 0x00750000 /* -- nh */
+# define R600_2288_RV350 0x0000FFFF /* -- Vladimir */
/* gap */
* inside the vertex program, otherwise the GPU locks up.
*
* fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
- * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
+ * R600_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
* position takes place.
*
* Most likely this is used to ignore rest of the program in cases
* is sometimes accepted other instruction that have no relationship with
* position calculations.
*/
-#define R300_VAP_PVS_CODE_CNTL_0 0x22D0
-# define R300_PVS_FIRST_INST_SHIFT 0
-# define R300_PVS_XYZW_VALID_INST_SHIFT 10
-# define R300_PVS_LAST_INST_SHIFT 20
+#define R600_VAP_PVS_CODE_CNTL_0 0x22D0
+# define R600_PVS_FIRST_INST_SHIFT 0
+# define R600_PVS_XYZW_VALID_INST_SHIFT 10
+# define R600_PVS_LAST_INST_SHIFT 20
/* Addresses are relative the the vertex program parameters area. */
-#define R300_VAP_PVS_CONST_CNTL 0x22D4
-# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0
-# define R300_PVS_MAX_CONST_ADDR_SHIFT 16
-#define R300_VAP_PVS_CODE_CNTL_1 0x22D8
-# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
-#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
+#define R600_VAP_PVS_CONST_CNTL 0x22D4
+# define R600_PVS_CONST_BASE_OFFSET_SHIFT 0
+# define R600_PVS_MAX_CONST_ADDR_SHIFT 16
+#define R600_VAP_PVS_CODE_CNTL_1 0x22D8
+# define R600_PVS_LAST_VTX_SRC_INST_SHIFT 0
+#define R600_VAP_PVS_FLOW_CNTL_OPC 0x22DC
/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
* immediate vertices
*/
-#define R300_VAP_VTX_COLOR_R 0x2464
-#define R300_VAP_VTX_COLOR_G 0x2468
-#define R300_VAP_VTX_COLOR_B 0x246C
-#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
-#define R300_VAP_VTX_POS_0_Y_1 0x2494
-#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
-#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
-#define R300_VAP_VTX_POS_0_Y_2 0x24A4
-#define R300_VAP_VTX_POS_0_Z_2 0x24A8
+#define R600_VAP_VTX_COLOR_R 0x2464
+#define R600_VAP_VTX_COLOR_G 0x2468
+#define R600_VAP_VTX_COLOR_B 0x246C
+#define R600_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
+#define R600_VAP_VTX_POS_0_Y_1 0x2494
+#define R600_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
+#define R600_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
+#define R600_VAP_VTX_POS_0_Y_2 0x24A4
+#define R600_VAP_VTX_POS_0_Z_2 0x24A8
/* write 0 to indicate end of packet? */
-#define R300_VAP_VTX_END_OF_PKT 0x24AC
+#define R600_VAP_VTX_END_OF_PKT 0x24AC
/* gap */
-/* These are values from r300_reg/r300_reg.h - they are known to be correct
+/* These are values from r600_reg/r600_reg.h - they are known to be correct
* and are here so we can use one register file instead of several
* - Vladimir
*/
-#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
-# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
-
-#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004
+#define R600_GB_VAP_RASTER_VTX_FMT_0 0x4000
+# define R600_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
+# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
+# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
+# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
+# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
+# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
+# define R600_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
+
+#define R600_GB_VAP_RASTER_VTX_FMT_1 0x4004
/* each of the following is 3 bits wide, specifies number
of components */
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
+# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
+# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
+# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
+# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
+# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
+# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
+# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
+# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
/* UNK30 seems to enables point to quad transformation on textures
* (or something closely related to that).
* shader side
* Specifies top of Raster pipe specific enable controls.
*/
-#define R300_GB_ENABLE 0x4008
-# define R300_GB_POINT_STUFF_DISABLE (0 << 0)
-# define R300_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */
-# define R300_GB_LINE_STUFF_DISABLE (0 << 1)
-# define R300_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */
-# define R300_GB_TRIANGLE_STUFF_DISABLE (0 << 2)
-# define R300_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */
-# define R300_GB_STENCIL_AUTO_DISABLE (0 << 4)
-# define R300_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */
-# define R300_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */
+#define R600_GB_ENABLE 0x4008
+# define R600_GB_POINT_STUFF_DISABLE (0 << 0)
+# define R600_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */
+# define R600_GB_LINE_STUFF_DISABLE (0 << 1)
+# define R600_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */
+# define R600_GB_TRIANGLE_STUFF_DISABLE (0 << 2)
+# define R600_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */
+# define R600_GB_STENCIL_AUTO_DISABLE (0 << 4)
+# define R600_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */
+# define R600_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */
/* each of the following is 2 bits wide */
-#define R300_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */
-#define R300_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */
-#define R300_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */
-# define R300_GB_TEX0_SOURCE_SHIFT 16
-# define R300_GB_TEX1_SOURCE_SHIFT 18
-# define R300_GB_TEX2_SOURCE_SHIFT 20
-# define R300_GB_TEX3_SOURCE_SHIFT 22
-# define R300_GB_TEX4_SOURCE_SHIFT 24
-# define R300_GB_TEX5_SOURCE_SHIFT 26
-# define R300_GB_TEX6_SOURCE_SHIFT 28
-# define R300_GB_TEX7_SOURCE_SHIFT 30
+#define R600_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */
+#define R600_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */
+#define R600_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */
+# define R600_GB_TEX0_SOURCE_SHIFT 16
+# define R600_GB_TEX1_SOURCE_SHIFT 18
+# define R600_GB_TEX2_SOURCE_SHIFT 20
+# define R600_GB_TEX3_SOURCE_SHIFT 22
+# define R600_GB_TEX4_SOURCE_SHIFT 24
+# define R600_GB_TEX5_SOURCE_SHIFT 26
+# define R600_GB_TEX6_SOURCE_SHIFT 28
+# define R600_GB_TEX7_SOURCE_SHIFT 30
/* MSPOS - positions for multisample antialiasing (?) */
-#define R300_GB_MSPOS0 0x4010
+#define R600_GB_MSPOS0 0x4010
/* shifts - each of the fields is 4 bits */
-# define R300_GB_MSPOS0__MS_X0_SHIFT 0
-# define R300_GB_MSPOS0__MS_Y0_SHIFT 4
-# define R300_GB_MSPOS0__MS_X1_SHIFT 8
-# define R300_GB_MSPOS0__MS_Y1_SHIFT 12
-# define R300_GB_MSPOS0__MS_X2_SHIFT 16
-# define R300_GB_MSPOS0__MS_Y2_SHIFT 20
-# define R300_GB_MSPOS0__MSBD0_Y 24
-# define R300_GB_MSPOS0__MSBD0_X 28
-
-#define R300_GB_MSPOS1 0x4014
-# define R300_GB_MSPOS1__MS_X3_SHIFT 0
-# define R300_GB_MSPOS1__MS_Y3_SHIFT 4
-# define R300_GB_MSPOS1__MS_X4_SHIFT 8
-# define R300_GB_MSPOS1__MS_Y4_SHIFT 12
-# define R300_GB_MSPOS1__MS_X5_SHIFT 16
-# define R300_GB_MSPOS1__MS_Y5_SHIFT 20
-# define R300_GB_MSPOS1__MSBD1 24
+# define R600_GB_MSPOS0__MS_X0_SHIFT 0
+# define R600_GB_MSPOS0__MS_Y0_SHIFT 4
+# define R600_GB_MSPOS0__MS_X1_SHIFT 8
+# define R600_GB_MSPOS0__MS_Y1_SHIFT 12
+# define R600_GB_MSPOS0__MS_X2_SHIFT 16
+# define R600_GB_MSPOS0__MS_Y2_SHIFT 20
+# define R600_GB_MSPOS0__MSBD0_Y 24
+# define R600_GB_MSPOS0__MSBD0_X 28
+
+#define R600_GB_MSPOS1 0x4014
+# define R600_GB_MSPOS1__MS_X3_SHIFT 0
+# define R600_GB_MSPOS1__MS_Y3_SHIFT 4
+# define R600_GB_MSPOS1__MS_X4_SHIFT 8
+# define R600_GB_MSPOS1__MS_Y4_SHIFT 12
+# define R600_GB_MSPOS1__MS_X5_SHIFT 16
+# define R600_GB_MSPOS1__MS_Y5_SHIFT 20
+# define R600_GB_MSPOS1__MSBD1 24
/* Specifies the graphics pipeline configuration for rasterization. */
-#define R300_GB_TILE_CONFIG 0x4018
-# define R300_GB_TILE_DISABLE (0 << 0)
-# define R300_GB_TILE_ENABLE (1 << 0)
-# define R300_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */
-# define R300_GB_TILE_PIPE_COUNT_R300 (3 << 1) /* R300 (2 pipes, 1 ctx) */
-# define R300_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */
-# define R300_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */
-# define R300_GB_TILE_SIZE_8 (0 << 4)
-# define R300_GB_TILE_SIZE_16 (1 << 4)
-# define R300_GB_TILE_SIZE_32 (2 << 4)
-# define R300_GB_SUPER_SIZE_1 (0 << 6)
-# define R300_GB_SUPER_SIZE_2 (1 << 6)
-# define R300_GB_SUPER_SIZE_4 (2 << 6)
-# define R300_GB_SUPER_SIZE_8 (3 << 6)
-# define R300_GB_SUPER_SIZE_16 (4 << 6)
-# define R300_GB_SUPER_SIZE_32 (5 << 6)
-# define R300_GB_SUPER_SIZE_64 (6 << 6)
-# define R300_GB_SUPER_SIZE_128 (7 << 6)
-# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */
-# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */
-# define R300_GB_SUPER_TILE_A (0 << 15)
-# define R300_GB_SUPER_TILE_B (1 << 15)
-# define R300_GB_SUBPIXEL_1_12 (0 << 16)
-# define R300_GB_SUBPIXEL_1_16 (1 << 16)
+#define R600_GB_TILE_CONFIG 0x4018
+# define R600_GB_TILE_DISABLE (0 << 0)
+# define R600_GB_TILE_ENABLE (1 << 0)
+# define R600_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */
+# define R600_GB_TILE_PIPE_COUNT_R600 (3 << 1) /* R600 (2 pipes, 1 ctx) */
+# define R600_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */
+# define R600_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */
+# define R600_GB_TILE_SIZE_8 (0 << 4)
+# define R600_GB_TILE_SIZE_16 (1 << 4)
+# define R600_GB_TILE_SIZE_32 (2 << 4)
+# define R600_GB_SUPER_SIZE_1 (0 << 6)
+# define R600_GB_SUPER_SIZE_2 (1 << 6)
+# define R600_GB_SUPER_SIZE_4 (2 << 6)
+# define R600_GB_SUPER_SIZE_8 (3 << 6)
+# define R600_GB_SUPER_SIZE_16 (4 << 6)
+# define R600_GB_SUPER_SIZE_32 (5 << 6)
+# define R600_GB_SUPER_SIZE_64 (6 << 6)
+# define R600_GB_SUPER_SIZE_128 (7 << 6)
+# define R600_GB_SUPER_X_SHIFT 9 /* 3 bits wide */
+# define R600_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */
+# define R600_GB_SUPER_TILE_A (0 << 15)
+# define R600_GB_SUPER_TILE_B (1 << 15)
+# define R600_GB_SUBPIXEL_1_12 (0 << 16)
+# define R600_GB_SUBPIXEL_1_16 (1 << 16)
# define GB_TILE_CONFIG_QUADS_PER_RAS_4 (0 << 17)
# define GB_TILE_CONFIG_QUADS_PER_RAS_8 (1 << 17)
# define GB_TILE_CONFIG_QUADS_PER_RAS_16 (2 << 17)
# define GB_TILE_CONFIG_Z_EXTENDED_S25_1 (1 << 24)
/* Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written */
-#define R300_GB_FIFO_SIZE 0x4024
+#define R600_GB_FIFO_SIZE 0x4024
/* each of the following is 2 bits wide */
-#define R300_GB_FIFO_SIZE_32 0
-#define R300_GB_FIFO_SIZE_64 1
-#define R300_GB_FIFO_SIZE_128 2
-#define R300_GB_FIFO_SIZE_256 3
-# define R300_SC_IFIFO_SIZE_SHIFT 0
-# define R300_SC_TZFIFO_SIZE_SHIFT 2
-# define R300_SC_BFIFO_SIZE_SHIFT 4
-
-# define R300_US_OFIFO_SIZE_SHIFT 12
-# define R300_US_WFIFO_SIZE_SHIFT 14
+#define R600_GB_FIFO_SIZE_32 0
+#define R600_GB_FIFO_SIZE_64 1
+#define R600_GB_FIFO_SIZE_128 2
+#define R600_GB_FIFO_SIZE_256 3
+# define R600_SC_IFIFO_SIZE_SHIFT 0
+# define R600_SC_TZFIFO_SIZE_SHIFT 2
+# define R600_SC_BFIFO_SIZE_SHIFT 4
+
+# define R600_US_OFIFO_SIZE_SHIFT 12
+# define R600_US_WFIFO_SIZE_SHIFT 14
/* the following use the same constants as above, but meaning is
is times 2 (i.e. instead of 32 words it means 64 */
-# define R300_RS_TFIFO_SIZE_SHIFT 6
-# define R300_RS_CFIFO_SIZE_SHIFT 8
-# define R300_US_RAM_SIZE_SHIFT 10
+# define R600_RS_TFIFO_SIZE_SHIFT 6
+# define R600_RS_CFIFO_SIZE_SHIFT 8
+# define R600_US_RAM_SIZE_SHIFT 10
/* watermarks, 3 bits wide */
-# define R300_RS_HIGHWATER_COL_SHIFT 16
-# define R300_RS_HIGHWATER_TEX_SHIFT 19
-# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
-# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24
+# define R600_RS_HIGHWATER_COL_SHIFT 16
+# define R600_RS_HIGHWATER_TEX_SHIFT 19
+# define R600_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
+# define R600_CUBE_FIFO_HIGHWATER_COL_SHIFT 24
#define GB_Z_PEQ_CONFIG 0x4028
# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_4_4 (0 << 0)
# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8 (1 << 0)
/* Specifies various polygon specific selects (fog, depth, perspective). */
-#define R300_GB_SELECT 0x401c
-# define R300_GB_FOG_SELECT_C0A (0 << 0)
-# define R300_GB_FOG_SELECT_C1A (1 << 0)
-# define R300_GB_FOG_SELECT_C2A (2 << 0)
-# define R300_GB_FOG_SELECT_C3A (3 << 0)
-# define R300_GB_FOG_SELECT_1_1_W (4 << 0)
-# define R300_GB_FOG_SELECT_Z (5 << 0)
-# define R300_GB_DEPTH_SELECT_Z (0 << 3)
-# define R300_GB_DEPTH_SELECT_1_1_W (1 << 3)
-# define R300_GB_W_SELECT_1_W (0 << 4)
-# define R300_GB_W_SELECT_1 (1 << 4)
-# define R300_GB_FOG_STUFF_DISABLE (0 << 5)
-# define R300_GB_FOG_STUFF_ENABLE (1 << 5)
-# define R300_GB_FOG_STUFF_TEX_SHIFT 6
-# define R300_GB_FOG_STUFF_TEX_MASK 0x000003c0
-# define R300_GB_FOG_STUFF_COMP_SHIFT 10
-# define R300_GB_FOG_STUFF_COMP_MASK 0x00000c00
+#define R600_GB_SELECT 0x401c
+# define R600_GB_FOG_SELECT_C0A (0 << 0)
+# define R600_GB_FOG_SELECT_C1A (1 << 0)
+# define R600_GB_FOG_SELECT_C2A (2 << 0)
+# define R600_GB_FOG_SELECT_C3A (3 << 0)
+# define R600_GB_FOG_SELECT_1_1_W (4 << 0)
+# define R600_GB_FOG_SELECT_Z (5 << 0)
+# define R600_GB_DEPTH_SELECT_Z (0 << 3)
+# define R600_GB_DEPTH_SELECT_1_1_W (1 << 3)
+# define R600_GB_W_SELECT_1_W (0 << 4)
+# define R600_GB_W_SELECT_1 (1 << 4)
+# define R600_GB_FOG_STUFF_DISABLE (0 << 5)
+# define R600_GB_FOG_STUFF_ENABLE (1 << 5)
+# define R600_GB_FOG_STUFF_TEX_SHIFT 6
+# define R600_GB_FOG_STUFF_TEX_MASK 0x000003c0
+# define R600_GB_FOG_STUFF_COMP_SHIFT 10
+# define R600_GB_FOG_STUFF_COMP_MASK 0x00000c00
/* Specifies the graphics pipeline configuration for antialiasing. */
#define GB_AA_CONFIG 0x4020
/* gap */
/* Zero to flush caches. */
-#define R300_TX_INVALTAGS 0x4100
-#define R300_TX_FLUSH 0x0
+#define R600_TX_INVALTAGS 0x4100
+#define R600_TX_FLUSH 0x0
/* The upper enable bits are guessed, based on fglrx reported limits. */
-#define R300_TX_ENABLE 0x4104
-# define R300_TX_ENABLE_0 (1 << 0)
-# define R300_TX_ENABLE_1 (1 << 1)
-# define R300_TX_ENABLE_2 (1 << 2)
-# define R300_TX_ENABLE_3 (1 << 3)
-# define R300_TX_ENABLE_4 (1 << 4)
-# define R300_TX_ENABLE_5 (1 << 5)
-# define R300_TX_ENABLE_6 (1 << 6)
-# define R300_TX_ENABLE_7 (1 << 7)
-# define R300_TX_ENABLE_8 (1 << 8)
-# define R300_TX_ENABLE_9 (1 << 9)
-# define R300_TX_ENABLE_10 (1 << 10)
-# define R300_TX_ENABLE_11 (1 << 11)
-# define R300_TX_ENABLE_12 (1 << 12)
-# define R300_TX_ENABLE_13 (1 << 13)
-# define R300_TX_ENABLE_14 (1 << 14)
-# define R300_TX_ENABLE_15 (1 << 15)
+#define R600_TX_ENABLE 0x4104
+# define R600_TX_ENABLE_0 (1 << 0)
+# define R600_TX_ENABLE_1 (1 << 1)
+# define R600_TX_ENABLE_2 (1 << 2)
+# define R600_TX_ENABLE_3 (1 << 3)
+# define R600_TX_ENABLE_4 (1 << 4)
+# define R600_TX_ENABLE_5 (1 << 5)
+# define R600_TX_ENABLE_6 (1 << 6)
+# define R600_TX_ENABLE_7 (1 << 7)
+# define R600_TX_ENABLE_8 (1 << 8)
+# define R600_TX_ENABLE_9 (1 << 9)
+# define R600_TX_ENABLE_10 (1 << 10)
+# define R600_TX_ENABLE_11 (1 << 11)
+# define R600_TX_ENABLE_12 (1 << 12)
+# define R600_TX_ENABLE_13 (1 << 13)
+# define R600_TX_ENABLE_14 (1 << 14)
+# define R600_TX_ENABLE_15 (1 << 15)
#define R500_TX_FILTER_4 0x4110
# define R500_TX_WEIGHT_1_SHIFT (0)
# define R500_TX_DIRECTION_VERITCAL (1<<27)
/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
-#define R300_GA_POINT_S0 0x4200
+#define R600_GA_POINT_S0 0x4200
/* T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
-#define R300_GA_POINT_T0 0x4204
+#define R600_GA_POINT_T0 0x4204
/* S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */
-#define R300_GA_POINT_S1 0x4208
+#define R600_GA_POINT_S1 0x4208
/* T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */
-#define R300_GA_POINT_T1 0x420c
+#define R600_GA_POINT_T1 0x420c
/* Specifies amount to shift integer position of vertex (screen space) before
* converting to float for triangle stipple.
*/
-#define R300_GA_TRIANGLE_STIPPLE 0x4214
-# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0
-# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f
-# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16
-# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000
+#define R600_GA_TRIANGLE_STIPPLE 0x4214
+# define R600_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0
+# define R600_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f
+# define R600_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16
+# define R600_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000
/* The pointsize is given in multiples of 6. The pointsize can be enormous:
* Clear() renders a single point that fills the entire framebuffer.
* 1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in
* 8b precision).
*/
-#define R300_GA_POINT_SIZE 0x421C
-# define R300_POINTSIZE_Y_SHIFT 0
-# define R300_POINTSIZE_Y_MASK 0x0000ffff
-# define R300_POINTSIZE_X_SHIFT 16
-# define R300_POINTSIZE_X_MASK 0xffff0000
-# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
+#define R600_GA_POINT_SIZE 0x421C
+# define R600_POINTSIZE_Y_SHIFT 0
+# define R600_POINTSIZE_Y_MASK 0x0000ffff
+# define R600_POINTSIZE_X_SHIFT 16
+# define R600_POINTSIZE_X_MASK 0xffff0000
+# define R600_POINTSIZE_MAX (R600_POINTSIZE_Y_MASK / 6)
/* Blue fill color */
#define R500_GA_FILL_R 0x4220
/* Specifies maximum and minimum point & sprite sizes for per vertex size
* specification. The lower part (15:0) is MIN and (31:16) is max.
*/
-#define R300_GA_POINT_MINMAX 0x4230
-# define R300_GA_POINT_MINMAX_MIN_SHIFT 0
-# define R300_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0)
-# define R300_GA_POINT_MINMAX_MAX_SHIFT 16
-# define R300_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16)
+#define R600_GA_POINT_MINMAX 0x4230
+# define R600_GA_POINT_MINMAX_MIN_SHIFT 0
+# define R600_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0)
+# define R600_GA_POINT_MINMAX_MAX_SHIFT 16
+# define R600_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16)
/* 1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b
* subprecision); (16.0) fixed format.
* VE: vertical or horizontal
* HO & VE: no classification
*/
-#define R300_GA_LINE_CNTL 0x4234
-# define R300_GA_LINE_CNTL_WIDTH_SHIFT 0
-# define R300_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff
-# define R300_GA_LINE_CNTL_END_TYPE_HOR (0 << 16)
-# define R300_GA_LINE_CNTL_END_TYPE_VER (1 << 16)
-# define R300_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */
-# define R300_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */
+#define R600_GA_LINE_CNTL 0x4234
+# define R600_GA_LINE_CNTL_WIDTH_SHIFT 0
+# define R600_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff
+# define R600_GA_LINE_CNTL_END_TYPE_HOR (0 << 16)
+# define R600_GA_LINE_CNTL_END_TYPE_VER (1 << 16)
+# define R600_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */
+# define R600_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */
# define R500_GA_LINE_CNTL_SORT_NO (0 << 18)
# define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18)
/** TODO: looks wrong */
-# define R300_LINESIZE_MAX (R300_GA_LINE_CNTL_WIDTH_MASK / 6)
+# define R600_LINESIZE_MAX (R600_GA_LINE_CNTL_WIDTH_MASK / 6)
/** TODO: looks wrong */
-# define R300_LINE_CNT_HO (1 << 16)
+# define R600_LINE_CNT_HO (1 << 16)
/** TODO: looks wrong */
-# define R300_LINE_CNT_VE (1 << 17)
+# define R600_LINE_CNT_VE (1 << 17)
/* Line Stipple configuration information. */
-#define R300_GA_LINE_STIPPLE_CONFIG 0x4238
-# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0)
-# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0)
-# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0)
-# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2
-# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc
+#define R600_GA_LINE_STIPPLE_CONFIG 0x4238
+# define R600_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0)
+# define R600_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0)
+# define R600_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0)
+# define R600_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2
+# define R600_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc
/* Used to load US instructions and constants */
#define R500_GA_US_VECTOR_INDEX 0x4250
# define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26)
/* Current value of stipple accumulator. */
-#define R300_GA_LINE_STIPPLE_VALUE 0x4260
+#define R600_GA_LINE_STIPPLE_VALUE 0x4260
/* S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) */
-#define R300_GA_LINE_S0 0x4264
+#define R600_GA_LINE_S0 0x4264
/* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */
-#define R300_GA_LINE_S1 0x4268
+#define R600_GA_LINE_S1 0x4268
/* GA Input fifo high water marks */
#define R500_GA_FIFO_CNTL 0x4270
# define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6
/* GA enhance/tweaks */
-#define R300_GA_ENHANCE 0x4274
-# define R300_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0)
-# define R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */
-# define R300_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1)
-# define R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */
+#define R600_GA_ENHANCE 0x4274
+# define R600_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0)
+# define R600_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */
+# define R600_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1)
+# define R600_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */
# define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */
# define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */
# define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3)
# define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */
-#define R300_GA_COLOR_CONTROL 0x4278
-# define R300_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0)
-# define R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0)
-# define R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0)
-# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2)
-# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2)
-# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2)
-# define R300_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4)
-# define R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4)
-# define R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4)
-# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6)
-# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6)
-# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6)
-# define R300_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8)
-# define R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8)
-# define R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8)
-# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10)
-# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10)
-# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10)
-# define R300_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12)
-# define R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12)
-# define R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12)
-# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14)
-# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14)
-# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14)
-# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16)
-# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16)
-# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16)
-# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16)
+#define R600_GA_COLOR_CONTROL 0x4278
+# define R600_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0)
+# define R600_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0)
+# define R600_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0)
+# define R600_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2)
+# define R600_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2)
+# define R600_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2)
+# define R600_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4)
+# define R600_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4)
+# define R600_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4)
+# define R600_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6)
+# define R600_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6)
+# define R600_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6)
+# define R600_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8)
+# define R600_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8)
+# define R600_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8)
+# define R600_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10)
+# define R600_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10)
+# define R600_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10)
+# define R600_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12)
+# define R600_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12)
+# define R600_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12)
+# define R600_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14)
+# define R600_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14)
+# define R600_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14)
+# define R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16)
+# define R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16)
+# define R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16)
+# define R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16)
/** TODO: might be candidate for removal */
-# define R300_RE_SHADE_MODEL_SMOOTH ( \
- R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST )
+# define R600_RE_SHADE_MODEL_SMOOTH ( \
+ R600_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R600_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \
+ R600_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R600_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
+ R600_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R600_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \
+ R600_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R600_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \
+ R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST )
/** TODO: might be candidate for removal, the GOURAUD stuff also looks buggy to me */
-# define R300_RE_SHADE_MODEL_FLAT ( \
- R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \
- R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \
- R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST )
+# define R600_RE_SHADE_MODEL_FLAT ( \
+ R600_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R600_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \
+ R600_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R600_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
+ R600_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R600_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \
+ R600_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R600_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \
+ R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST )
/* Specifies red & green components of fill color -- S312 format -- Backwards comp. */
-#define R300_GA_SOLID_RG 0x427c
+#define R600_GA_SOLID_RG 0x427c
# define GA_SOLID_RG_COLOR_GREEN_SHIFT 0
# define GA_SOLID_RG_COLOR_GREEN_MASK 0x0000ffff
# define GA_SOLID_RG_COLOR_RED_SHIFT 16
# define GA_SOLID_RG_COLOR_RED_MASK 0xffff0000
/* Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. */
-#define R300_GA_SOLID_BA 0x4280
+#define R600_GA_SOLID_BA 0x4280
# define GA_SOLID_BA_COLOR_ALPHA_SHIFT 0
# define GA_SOLID_BA_COLOR_ALPHA_MASK 0x0000ffff
# define GA_SOLID_BA_COLOR_BLUE_SHIFT 16
/* Polygon Mode
* Dangerous
*/
-#define R300_GA_POLY_MODE 0x4288
-# define R300_GA_POLY_MODE_DISABLE (0 << 0)
-# define R300_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */
+#define R600_GA_POLY_MODE 0x4288
+# define R600_GA_POLY_MODE_DISABLE (0 << 0)
+# define R600_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */
/* reserved */
-# define R300_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4)
-# define R300_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4)
-# define R300_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4)
+# define R600_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4)
+# define R600_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4)
+# define R600_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4)
/* reserved */
-# define R300_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7)
-# define R300_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7)
-# define R300_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7)
+# define R600_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7)
+# define R600_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7)
+# define R600_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7)
/* reserved */
/* Specifies the rouding mode for geometry & color SPFP to FP conversions. */
-#define R300_GA_ROUND_MODE 0x428c
-# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0)
-# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0)
-# define R300_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2)
-# define R300_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2)
-# define R300_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4)
-# define R300_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4)
-# define R300_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5)
-# define R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5)
+#define R600_GA_ROUND_MODE 0x428c
+# define R600_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0)
+# define R600_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0)
+# define R600_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2)
+# define R600_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2)
+# define R600_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4)
+# define R600_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4)
+# define R600_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5)
+# define R600_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5)
# define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6
# define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0
* Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b
* subprecision).
*/
-#define R300_GA_OFFSET 0x4290
-# define R300_GA_OFFSET_X_OFFSET_SHIFT 0
-# define R300_GA_OFFSET_X_OFFSET_MASK 0x0000ffff
-# define R300_GA_OFFSET_Y_OFFSET_SHIFT 16
-# define R300_GA_OFFSET_Y_OFFSET_MASK 0xffff0000
+#define R600_GA_OFFSET 0x4290
+# define R600_GA_OFFSET_X_OFFSET_SHIFT 0
+# define R600_GA_OFFSET_X_OFFSET_MASK 0x0000ffff
+# define R600_GA_OFFSET_Y_OFFSET_SHIFT 16
+# define R600_GA_OFFSET_Y_OFFSET_MASK 0xffff0000
/* Specifies the scale to apply to fog. */
-#define R300_GA_FOG_SCALE 0x4294
+#define R600_GA_FOG_SCALE 0x4294
/* Specifies the offset to apply to fog. */
-#define R300_GA_FOG_OFFSET 0x4298
+#define R600_GA_FOG_OFFSET 0x4298
/* Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert. */
-#define R300_GA_SOFT_RESET 0x429c
+#define R600_GA_SOFT_RESET 0x429c
/* Not sure why there are duplicate of factor and constant values.
* My best guess so far is that there are seperate zbiases for test and write.
* Some of the tests indicate that fgl has a fallback implementation of zbias
* via pixel shaders.
*/
-#define R300_SU_TEX_WRAP 0x42A0
-#define R300_SU_POLY_OFFSET_FRONT_SCALE 0x42A4
-#define R300_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8
-#define R300_SU_POLY_OFFSET_BACK_SCALE 0x42AC
-#define R300_SU_POLY_OFFSET_BACK_OFFSET 0x42B0
+#define R600_SU_TEX_WRAP 0x42A0
+#define R600_SU_POLY_OFFSET_FRONT_SCALE 0x42A4
+#define R600_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8
+#define R600_SU_POLY_OFFSET_BACK_SCALE 0x42AC
+#define R600_SU_POLY_OFFSET_BACK_OFFSET 0x42B0
/* This register needs to be set to (1<<1) for RV350 to correctly
- * perform depth test (see --vb-triangles in r300_demo)
+ * perform depth test (see --vb-triangles in r600_demo)
* Don't know about other chips. - Vladimir
* This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
* My guess is that there are two bits for each zbias primitive
* One to enable depth test and one for depth write.
* Yet this doesnt explain why depth writes work ...
*/
-#define R300_SU_POLY_OFFSET_ENABLE 0x42B4
-# define R300_FRONT_ENABLE (1 << 0)
-# define R300_BACK_ENABLE (1 << 1)
-# define R300_PARA_ENABLE (1 << 2)
+#define R600_SU_POLY_OFFSET_ENABLE 0x42B4
+# define R600_FRONT_ENABLE (1 << 0)
+# define R600_BACK_ENABLE (1 << 1)
+# define R600_PARA_ENABLE (1 << 2)
-#define R300_SU_CULL_MODE 0x42B8
-# define R300_CULL_FRONT (1 << 0)
-# define R300_CULL_BACK (1 << 1)
-# define R300_FRONT_FACE_CCW (0 << 2)
-# define R300_FRONT_FACE_CW (1 << 2)
+#define R600_SU_CULL_MODE 0x42B8
+# define R600_CULL_FRONT (1 << 0)
+# define R600_CULL_BACK (1 << 1)
+# define R600_FRONT_FACE_CCW (0 << 2)
+# define R600_FRONT_FACE_CW (1 << 2)
/* SU Depth Scale value */
-#define R300_SU_DEPTH_SCALE 0x42c0
+#define R600_SU_DEPTH_SCALE 0x42c0
/* SU Depth Offset value */
-#define R300_SU_DEPTH_OFFSET 0x42c4
+#define R600_SU_DEPTH_OFFSET 0x42c4
/* BEGIN: Rasterization / Interpolators - many guesses */
* TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
* on the vertex program, *not* the fragment program)
*/
-#define R300_RS_COUNT 0x4300
-# define R300_IT_COUNT_SHIFT 0
-# define R300_IT_COUNT_MASK 0x0000007f
-# define R300_IC_COUNT_SHIFT 7
-# define R300_IC_COUNT_MASK 0x00000780
-# define R300_W_ADDR_SHIFT 12
-# define R300_W_ADDR_MASK 0x0003f000
-# define R300_HIRES_DIS (0 << 18)
-# define R300_HIRES_EN (1 << 18)
-
-#define R300_RS_INST_COUNT 0x4304
-# define R300_RS_INST_COUNT_SHIFT 0
-# define R300_RS_INST_COUNT_MASK 0x0000000f
-# define R300_RS_TX_OFFSET_SHIFT 5
-# define R300_RS_TX_OFFSET_MASK 0x000000e0
+#define R600_RS_COUNT 0x4300
+# define R600_IT_COUNT_SHIFT 0
+# define R600_IT_COUNT_MASK 0x0000007f
+# define R600_IC_COUNT_SHIFT 7
+# define R600_IC_COUNT_MASK 0x00000780
+# define R600_W_ADDR_SHIFT 12
+# define R600_W_ADDR_MASK 0x0003f000
+# define R600_HIRES_DIS (0 << 18)
+# define R600_HIRES_EN (1 << 18)
+
+#define R600_RS_INST_COUNT 0x4304
+# define R600_RS_INST_COUNT_SHIFT 0
+# define R600_RS_INST_COUNT_MASK 0x0000000f
+# define R600_RS_TX_OFFSET_SHIFT 5
+# define R600_RS_TX_OFFSET_MASK 0x000000e0
/* gap */
* Note: The _UNKNOWN constants are always set in their respective
* register. I don't know if this is necessary.
*/
-#define R300_RS_IP_0 0x4310
-#define R300_RS_IP_1 0x4314
-#define R300_RS_IP_2 0x4318
-#define R300_RS_IP_3 0x431C
-# define R300_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */
-# define R300_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */
-# define R300_RS_TEX_PTR(x) ((x) << 0)
-# define R300_RS_COL_PTR(x) ((x) << 6)
-# define R300_RS_COL_FMT(x) ((x) << 9)
-# define R300_RS_COL_FMT_RGBA 0
-# define R300_RS_COL_FMT_RGB0 1
-# define R300_RS_COL_FMT_RGB1 2
-# define R300_RS_COL_FMT_000A 4
-# define R300_RS_COL_FMT_0000 5
-# define R300_RS_COL_FMT_0001 6
-# define R300_RS_COL_FMT_111A 8
-# define R300_RS_COL_FMT_1110 9
-# define R300_RS_COL_FMT_1111 10
-# define R300_RS_SEL_S(x) ((x) << 13)
-# define R300_RS_SEL_T(x) ((x) << 16)
-# define R300_RS_SEL_R(x) ((x) << 19)
-# define R300_RS_SEL_Q(x) ((x) << 22)
-# define R300_RS_SEL_C0 0
-# define R300_RS_SEL_C1 1
-# define R300_RS_SEL_C2 2
-# define R300_RS_SEL_C3 3
-# define R300_RS_SEL_K0 4
-# define R300_RS_SEL_K1 5
+#define R600_RS_IP_0 0x4310
+#define R600_RS_IP_1 0x4314
+#define R600_RS_IP_2 0x4318
+#define R600_RS_IP_3 0x431C
+# define R600_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */
+# define R600_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */
+# define R600_RS_TEX_PTR(x) ((x) << 0)
+# define R600_RS_COL_PTR(x) ((x) << 6)
+# define R600_RS_COL_FMT(x) ((x) << 9)
+# define R600_RS_COL_FMT_RGBA 0
+# define R600_RS_COL_FMT_RGB0 1
+# define R600_RS_COL_FMT_RGB1 2
+# define R600_RS_COL_FMT_000A 4
+# define R600_RS_COL_FMT_0000 5
+# define R600_RS_COL_FMT_0001 6
+# define R600_RS_COL_FMT_111A 8
+# define R600_RS_COL_FMT_1110 9
+# define R600_RS_COL_FMT_1111 10
+# define R600_RS_SEL_S(x) ((x) << 13)
+# define R600_RS_SEL_T(x) ((x) << 16)
+# define R600_RS_SEL_R(x) ((x) << 19)
+# define R600_RS_SEL_Q(x) ((x) << 22)
+# define R600_RS_SEL_C0 0
+# define R600_RS_SEL_C1 1
+# define R600_RS_SEL_C2 2
+# define R600_RS_SEL_C3 3
+# define R600_RS_SEL_K0 4
+# define R600_RS_SEL_K1 5
/* */
/* These DWORDs control how vertex data is routed into fragment program
* registers, after interpolators.
*/
-#define R300_RS_INST_0 0x4330
-#define R300_RS_INST_1 0x4334
-#define R300_RS_INST_2 0x4338
-#define R300_RS_INST_3 0x433C /* GUESS */
-#define R300_RS_INST_4 0x4340 /* GUESS */
-#define R300_RS_INST_5 0x4344 /* GUESS */
-#define R300_RS_INST_6 0x4348 /* GUESS */
-#define R300_RS_INST_7 0x434C /* GUESS */
-# define R300_RS_INST_TEX_ID(x) ((x) << 0)
-# define R300_RS_INST_TEX_CN_WRITE (1 << 3)
-# define R300_RS_INST_TEX_ADDR_SHIFT 6
-# define R300_RS_INST_TEX_ADDR(x) ((x) << R300_RS_INST_TEX_ADDR_SHIFT)
-# define R300_RS_INST_COL_ID(x) ((x) << 11)
-# define R300_RS_INST_COL_CN_WRITE (1 << 14)
-# define R300_RS_INST_COL_ADDR_SHIFT 17
-# define R300_RS_INST_COL_ADDR(x) ((x) << R300_RS_INST_COL_ADDR_SHIFT)
-# define R300_RS_INST_TEX_ADJ (1 << 22)
-# define R300_RS_COL_BIAS_UNUSED_SHIFT 23
+#define R600_RS_INST_0 0x4330
+#define R600_RS_INST_1 0x4334
+#define R600_RS_INST_2 0x4338
+#define R600_RS_INST_3 0x433C /* GUESS */
+#define R600_RS_INST_4 0x4340 /* GUESS */
+#define R600_RS_INST_5 0x4344 /* GUESS */
+#define R600_RS_INST_6 0x4348 /* GUESS */
+#define R600_RS_INST_7 0x434C /* GUESS */
+# define R600_RS_INST_TEX_ID(x) ((x) << 0)
+# define R600_RS_INST_TEX_CN_WRITE (1 << 3)
+# define R600_RS_INST_TEX_ADDR_SHIFT 6
+# define R600_RS_INST_TEX_ADDR(x) ((x) << R600_RS_INST_TEX_ADDR_SHIFT)
+# define R600_RS_INST_COL_ID(x) ((x) << 11)
+# define R600_RS_INST_COL_CN_WRITE (1 << 14)
+# define R600_RS_INST_COL_ADDR_SHIFT 17
+# define R600_RS_INST_COL_ADDR(x) ((x) << R600_RS_INST_COL_ADDR_SHIFT)
+# define R600_RS_INST_TEX_ADJ (1 << 22)
+# define R600_RS_COL_BIAS_UNUSED_SHIFT 23
/* END: Rasterization / Interpolators - many guesses */
/* Hierarchical Z Enable */
-#define R300_SC_HYPERZ 0x43a4
-# define R300_SC_HYPERZ_DISABLE (0 << 0)
-# define R300_SC_HYPERZ_ENABLE (1 << 0)
-# define R300_SC_HYPERZ_MIN (0 << 1)
-# define R300_SC_HYPERZ_MAX (1 << 1)
-# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
-# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
-# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
-# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
-# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
-# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
-# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
-# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
-# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
-# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
-# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
-# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
-
-#define R300_SC_EDGERULE 0x43a8
+#define R600_SC_HYPERZ 0x43a4
+# define R600_SC_HYPERZ_DISABLE (0 << 0)
+# define R600_SC_HYPERZ_ENABLE (1 << 0)
+# define R600_SC_HYPERZ_MIN (0 << 1)
+# define R600_SC_HYPERZ_MAX (1 << 1)
+# define R600_SC_HYPERZ_ADJ_256 (0 << 2)
+# define R600_SC_HYPERZ_ADJ_128 (1 << 2)
+# define R600_SC_HYPERZ_ADJ_64 (2 << 2)
+# define R600_SC_HYPERZ_ADJ_32 (3 << 2)
+# define R600_SC_HYPERZ_ADJ_16 (4 << 2)
+# define R600_SC_HYPERZ_ADJ_8 (5 << 2)
+# define R600_SC_HYPERZ_ADJ_4 (6 << 2)
+# define R600_SC_HYPERZ_ADJ_2 (7 << 2)
+# define R600_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
+# define R600_SC_HYPERZ_HZ_Z0MIN (1 << 5)
+# define R600_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
+# define R600_SC_HYPERZ_HZ_Z0MAX (1 << 6)
+
+#define R600_SC_EDGERULE 0x43a8
/* BEGIN: Scissors and cliprects */
* For some reason, the top-left corner of the framebuffer is at (1440, 1440)
* for the purpose of clipping and scissors.
*/
-#define R300_SC_CLIPRECT_TL_0 0x43B0
-#define R300_SC_CLIPRECT_BR_0 0x43B4
-#define R300_SC_CLIPRECT_TL_1 0x43B8
-#define R300_SC_CLIPRECT_BR_1 0x43BC
-#define R300_SC_CLIPRECT_TL_2 0x43C0
-#define R300_SC_CLIPRECT_BR_2 0x43C4
-#define R300_SC_CLIPRECT_TL_3 0x43C8
-#define R300_SC_CLIPRECT_BR_3 0x43CC
-# define R300_CLIPRECT_OFFSET 1440
-# define R300_CLIPRECT_MASK 0x1FFF
-# define R300_CLIPRECT_X_SHIFT 0
-# define R300_CLIPRECT_X_MASK (0x1FFF << 0)
-# define R300_CLIPRECT_Y_SHIFT 13
-# define R300_CLIPRECT_Y_MASK (0x1FFF << 13)
-#define R300_SC_CLIP_RULE 0x43D0
-# define R300_CLIP_OUT (1 << 0)
-# define R300_CLIP_0 (1 << 1)
-# define R300_CLIP_1 (1 << 2)
-# define R300_CLIP_10 (1 << 3)
-# define R300_CLIP_2 (1 << 4)
-# define R300_CLIP_20 (1 << 5)
-# define R300_CLIP_21 (1 << 6)
-# define R300_CLIP_210 (1 << 7)
-# define R300_CLIP_3 (1 << 8)
-# define R300_CLIP_30 (1 << 9)
-# define R300_CLIP_31 (1 << 10)
-# define R300_CLIP_310 (1 << 11)
-# define R300_CLIP_32 (1 << 12)
-# define R300_CLIP_320 (1 << 13)
-# define R300_CLIP_321 (1 << 14)
-# define R300_CLIP_3210 (1 << 15)
+#define R600_SC_CLIPRECT_TL_0 0x43B0
+#define R600_SC_CLIPRECT_BR_0 0x43B4
+#define R600_SC_CLIPRECT_TL_1 0x43B8
+#define R600_SC_CLIPRECT_BR_1 0x43BC
+#define R600_SC_CLIPRECT_TL_2 0x43C0
+#define R600_SC_CLIPRECT_BR_2 0x43C4
+#define R600_SC_CLIPRECT_TL_3 0x43C8
+#define R600_SC_CLIPRECT_BR_3 0x43CC
+# define R600_CLIPRECT_OFFSET 1440
+# define R600_CLIPRECT_MASK 0x1FFF
+# define R600_CLIPRECT_X_SHIFT 0
+# define R600_CLIPRECT_X_MASK (0x1FFF << 0)
+# define R600_CLIPRECT_Y_SHIFT 13
+# define R600_CLIPRECT_Y_MASK (0x1FFF << 13)
+#define R600_SC_CLIP_RULE 0x43D0
+# define R600_CLIP_OUT (1 << 0)
+# define R600_CLIP_0 (1 << 1)
+# define R600_CLIP_1 (1 << 2)
+# define R600_CLIP_10 (1 << 3)
+# define R600_CLIP_2 (1 << 4)
+# define R600_CLIP_20 (1 << 5)
+# define R600_CLIP_21 (1 << 6)
+# define R600_CLIP_210 (1 << 7)
+# define R600_CLIP_3 (1 << 8)
+# define R600_CLIP_30 (1 << 9)
+# define R600_CLIP_31 (1 << 10)
+# define R600_CLIP_310 (1 << 11)
+# define R600_CLIP_32 (1 << 12)
+# define R600_CLIP_320 (1 << 13)
+# define R600_CLIP_321 (1 << 14)
+# define R600_CLIP_3210 (1 << 15)
/* gap */
-#define R300_SC_SCISSORS_TL 0x43E0
-#define R300_SC_SCISSORS_BR 0x43E4
-# define R300_SCISSORS_OFFSET 1440
-# define R300_SCISSORS_X_SHIFT 0
-# define R300_SCISSORS_X_MASK (0x1FFF << 0)
-# define R300_SCISSORS_Y_SHIFT 13
-# define R300_SCISSORS_Y_MASK (0x1FFF << 13)
+#define R600_SC_SCISSORS_TL 0x43E0
+#define R600_SC_SCISSORS_BR 0x43E4
+# define R600_SCISSORS_OFFSET 1440
+# define R600_SCISSORS_X_SHIFT 0
+# define R600_SCISSORS_X_MASK (0x1FFF << 0)
+# define R600_SCISSORS_Y_SHIFT 13
+# define R600_SCISSORS_Y_MASK (0x1FFF << 13)
/* Screen door sample mask */
-#define R300_SC_SCREENDOOR 0x43e8
+#define R600_SC_SCREENDOOR 0x43e8
/* END: Scissors and cliprects */
* unit. This means that e.g. the offset for texture image unit N is found in
* register TX_OFFSET_0 + (4*N)
*/
-#define R300_TX_FILTER0_0 0x4400
-#define R300_TX_FILTER0_1 0x4404
-#define R300_TX_FILTER0_2 0x4408
-#define R300_TX_FILTER0_3 0x440c
-#define R300_TX_FILTER0_4 0x4410
-#define R300_TX_FILTER0_5 0x4414
-#define R300_TX_FILTER0_6 0x4418
-#define R300_TX_FILTER0_7 0x441c
-#define R300_TX_FILTER0_8 0x4420
-#define R300_TX_FILTER0_9 0x4424
-#define R300_TX_FILTER0_10 0x4428
-#define R300_TX_FILTER0_11 0x442c
-#define R300_TX_FILTER0_12 0x4430
-#define R300_TX_FILTER0_13 0x4434
-#define R300_TX_FILTER0_14 0x4438
-#define R300_TX_FILTER0_15 0x443c
-# define R300_TX_REPEAT 0
-# define R300_TX_MIRRORED 1
-# define R300_TX_CLAMP_TO_EDGE 2
-# define R300_TX_MIRROR_ONCE_TO_EDGE 3
-# define R300_TX_CLAMP 4
-# define R300_TX_MIRROR_ONCE 5
-# define R300_TX_CLAMP_TO_BORDER 6
-# define R300_TX_MIRROR_ONCE_TO_BORDER 7
-# define R300_TX_WRAP_S_SHIFT 0
-# define R300_TX_WRAP_S_MASK (7 << 0)
-# define R300_TX_WRAP_T_SHIFT 3
-# define R300_TX_WRAP_T_MASK (7 << 3)
-# define R300_TX_WRAP_R_SHIFT 6
-# define R300_TX_WRAP_R_MASK (7 << 6)
-# define R300_TX_MAG_FILTER_4 (0 << 9)
-# define R300_TX_MAG_FILTER_NEAREST (1 << 9)
-# define R300_TX_MAG_FILTER_LINEAR (2 << 9)
-# define R300_TX_MAG_FILTER_ANISO (3 << 9)
-# define R300_TX_MAG_FILTER_MASK (3 << 9)
-# define R300_TX_MIN_FILTER_NEAREST (1 << 11)
-# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
-# define R300_TX_MIN_FILTER_ANISO (3 << 11)
-# define R300_TX_MIN_FILTER_MASK (3 << 11)
-# define R300_TX_MIN_FILTER_MIP_NONE (0 << 13)
-# define R300_TX_MIN_FILTER_MIP_NEAREST (1 << 13)
-# define R300_TX_MIN_FILTER_MIP_LINEAR (2 << 13)
-# define R300_TX_MIN_FILTER_MIP_MASK (3 << 13)
-# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)
-# define R300_TX_MAX_ANISO_2_TO_1 (1 << 21)
-# define R300_TX_MAX_ANISO_4_TO_1 (2 << 21)
-# define R300_TX_MAX_ANISO_8_TO_1 (3 << 21)
-# define R300_TX_MAX_ANISO_16_TO_1 (4 << 21)
-# define R300_TX_MAX_ANISO_MASK (7 << 21)
-
-#define R300_TX_FILTER1_0 0x4440
-# define R300_CHROMA_KEY_MODE_DISABLE 0
-# define R300_CHROMA_KEY_FORCE 1
-# define R300_CHROMA_KEY_BLEND 2
-# define R300_MC_ROUND_NORMAL (0<<2)
-# define R300_MC_ROUND_MPEG4 (1<<2)
-# define R300_LOD_BIAS_SHIFT 3
-# define R300_LOD_BIAS_MASK 0x1ff8
-# define R300_EDGE_ANISO_EDGE_DIAG (0<<13)
-# define R300_EDGE_ANISO_EDGE_ONLY (1<<13)
-# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14)
-# define R300_MC_COORD_TRUNCATE_MPEG (1<<14)
-# define R300_TX_TRI_PERF_0_8 (0<<15)
-# define R300_TX_TRI_PERF_1_8 (1<<15)
-# define R300_TX_TRI_PERF_1_4 (2<<15)
-# define R300_TX_TRI_PERF_3_8 (3<<15)
-# define R300_ANISO_THRESHOLD_MASK (7<<17)
+#define R600_TX_FILTER0_0 0x4400
+#define R600_TX_FILTER0_1 0x4404
+#define R600_TX_FILTER0_2 0x4408
+#define R600_TX_FILTER0_3 0x440c
+#define R600_TX_FILTER0_4 0x4410
+#define R600_TX_FILTER0_5 0x4414
+#define R600_TX_FILTER0_6 0x4418
+#define R600_TX_FILTER0_7 0x441c
+#define R600_TX_FILTER0_8 0x4420
+#define R600_TX_FILTER0_9 0x4424
+#define R600_TX_FILTER0_10 0x4428
+#define R600_TX_FILTER0_11 0x442c
+#define R600_TX_FILTER0_12 0x4430
+#define R600_TX_FILTER0_13 0x4434
+#define R600_TX_FILTER0_14 0x4438
+#define R600_TX_FILTER0_15 0x443c
+# define R600_TX_REPEAT 0
+# define R600_TX_MIRRORED 1
+# define R600_TX_CLAMP_TO_EDGE 2
+# define R600_TX_MIRROR_ONCE_TO_EDGE 3
+# define R600_TX_CLAMP 4
+# define R600_TX_MIRROR_ONCE 5
+# define R600_TX_CLAMP_TO_BORDER 6
+# define R600_TX_MIRROR_ONCE_TO_BORDER 7
+# define R600_TX_WRAP_S_SHIFT 0
+# define R600_TX_WRAP_S_MASK (7 << 0)
+# define R600_TX_WRAP_T_SHIFT 3
+# define R600_TX_WRAP_T_MASK (7 << 3)
+# define R600_TX_WRAP_R_SHIFT 6
+# define R600_TX_WRAP_R_MASK (7 << 6)
+# define R600_TX_MAG_FILTER_4 (0 << 9)
+# define R600_TX_MAG_FILTER_NEAREST (1 << 9)
+# define R600_TX_MAG_FILTER_LINEAR (2 << 9)
+# define R600_TX_MAG_FILTER_ANISO (3 << 9)
+# define R600_TX_MAG_FILTER_MASK (3 << 9)
+# define R600_TX_MIN_FILTER_NEAREST (1 << 11)
+# define R600_TX_MIN_FILTER_LINEAR (2 << 11)
+# define R600_TX_MIN_FILTER_ANISO (3 << 11)
+# define R600_TX_MIN_FILTER_MASK (3 << 11)
+# define R600_TX_MIN_FILTER_MIP_NONE (0 << 13)
+# define R600_TX_MIN_FILTER_MIP_NEAREST (1 << 13)
+# define R600_TX_MIN_FILTER_MIP_LINEAR (2 << 13)
+# define R600_TX_MIN_FILTER_MIP_MASK (3 << 13)
+# define R600_TX_MAX_ANISO_1_TO_1 (0 << 21)
+# define R600_TX_MAX_ANISO_2_TO_1 (1 << 21)
+# define R600_TX_MAX_ANISO_4_TO_1 (2 << 21)
+# define R600_TX_MAX_ANISO_8_TO_1 (3 << 21)
+# define R600_TX_MAX_ANISO_16_TO_1 (4 << 21)
+# define R600_TX_MAX_ANISO_MASK (7 << 21)
+
+#define R600_TX_FILTER1_0 0x4440
+# define R600_CHROMA_KEY_MODE_DISABLE 0
+# define R600_CHROMA_KEY_FORCE 1
+# define R600_CHROMA_KEY_BLEND 2
+# define R600_MC_ROUND_NORMAL (0<<2)
+# define R600_MC_ROUND_MPEG4 (1<<2)
+# define R600_LOD_BIAS_SHIFT 3
+# define R600_LOD_BIAS_MASK 0x1ff8
+# define R600_EDGE_ANISO_EDGE_DIAG (0<<13)
+# define R600_EDGE_ANISO_EDGE_ONLY (1<<13)
+# define R600_MC_COORD_TRUNCATE_DISABLE (0<<14)
+# define R600_MC_COORD_TRUNCATE_MPEG (1<<14)
+# define R600_TX_TRI_PERF_0_8 (0<<15)
+# define R600_TX_TRI_PERF_1_8 (1<<15)
+# define R600_TX_TRI_PERF_1_4 (2<<15)
+# define R600_TX_TRI_PERF_3_8 (3<<15)
+# define R600_ANISO_THRESHOLD_MASK (7<<17)
# define R500_MACRO_SWITCH (1<<22)
# define R500_BORDER_FIX (1<<31)
-#define R300_TX_SIZE_0 0x4480
-# define R300_TX_WIDTHMASK_SHIFT 0
-# define R300_TX_WIDTHMASK_MASK (2047 << 0)
-# define R300_TX_HEIGHTMASK_SHIFT 11
-# define R300_TX_HEIGHTMASK_MASK (2047 << 11)
-# define R300_TX_DEPTHMASK_SHIFT 22
-# define R300_TX_DEPTHMASK_MASK (0xf << 22)
-# define R300_TX_MAX_MIP_LEVEL_SHIFT 26
-# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26)
-# define R300_TX_SIZE_PROJECTED (1<<30)
-# define R300_TX_SIZE_TXPITCH_EN (1<<31)
-#define R300_TX_FORMAT_0 0x44C0
+#define R600_TX_SIZE_0 0x4480
+# define R600_TX_WIDTHMASK_SHIFT 0
+# define R600_TX_WIDTHMASK_MASK (2047 << 0)
+# define R600_TX_HEIGHTMASK_SHIFT 11
+# define R600_TX_HEIGHTMASK_MASK (2047 << 11)
+# define R600_TX_DEPTHMASK_SHIFT 22
+# define R600_TX_DEPTHMASK_MASK (0xf << 22)
+# define R600_TX_MAX_MIP_LEVEL_SHIFT 26
+# define R600_TX_MAX_MIP_LEVEL_MASK (0xf << 26)
+# define R600_TX_SIZE_PROJECTED (1<<30)
+# define R600_TX_SIZE_TXPITCH_EN (1<<31)
+#define R600_TX_FORMAT_0 0x44C0
/* The interpretation of the format word by Wladimir van der Laan */
/* The X, Y, Z and W refer to the layout of the components.
They are given meanings as R, G, B and Alpha by the swizzle
specification */
-# define R300_TX_FORMAT_X8 0x0
+# define R600_TX_FORMAT_X8 0x0
# define R500_TX_FORMAT_X1 0x0 // bit set in format 2
-# define R300_TX_FORMAT_X16 0x1
+# define R600_TX_FORMAT_X16 0x1
# define R500_TX_FORMAT_X1_REV 0x0 // bit set in format 2
-# define R300_TX_FORMAT_Y4X4 0x2
-# define R300_TX_FORMAT_Y8X8 0x3
-# define R300_TX_FORMAT_Y16X16 0x4
-# define R300_TX_FORMAT_Z3Y3X2 0x5
-# define R300_TX_FORMAT_Z5Y6X5 0x6
-# define R300_TX_FORMAT_Z6Y5X5 0x7
-# define R300_TX_FORMAT_Z11Y11X10 0x8
-# define R300_TX_FORMAT_Z10Y11X11 0x9
-# define R300_TX_FORMAT_W4Z4Y4X4 0xA
-# define R300_TX_FORMAT_W1Z5Y5X5 0xB
-# define R300_TX_FORMAT_W8Z8Y8X8 0xC
-# define R300_TX_FORMAT_W2Z10Y10X10 0xD
-# define R300_TX_FORMAT_W16Z16Y16X16 0xE
-# define R300_TX_FORMAT_DXT1 0xF
-# define R300_TX_FORMAT_DXT3 0x10
-# define R300_TX_FORMAT_DXT5 0x11
-# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
-# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
-# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
-# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
+# define R600_TX_FORMAT_Y4X4 0x2
+# define R600_TX_FORMAT_Y8X8 0x3
+# define R600_TX_FORMAT_Y16X16 0x4
+# define R600_TX_FORMAT_Z3Y3X2 0x5
+# define R600_TX_FORMAT_Z5Y6X5 0x6
+# define R600_TX_FORMAT_Z6Y5X5 0x7
+# define R600_TX_FORMAT_Z11Y11X10 0x8
+# define R600_TX_FORMAT_Z10Y11X11 0x9
+# define R600_TX_FORMAT_W4Z4Y4X4 0xA
+# define R600_TX_FORMAT_W1Z5Y5X5 0xB
+# define R600_TX_FORMAT_W8Z8Y8X8 0xC
+# define R600_TX_FORMAT_W2Z10Y10X10 0xD
+# define R600_TX_FORMAT_W16Z16Y16X16 0xE
+# define R600_TX_FORMAT_DXT1 0xF
+# define R600_TX_FORMAT_DXT3 0x10
+# define R600_TX_FORMAT_DXT5 0x11
+# define R600_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
+# define R600_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
+# define R600_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
+# define R600_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
/* These two values are wrong, but they're the only values that
- * produce any even vaguely correct results. Can r300 only do 16-bit
+ * produce any even vaguely correct results. Can r600 only do 16-bit
* depth textures?
*/
-# define R300_TX_FORMAT_X24_Y8 0x1e
-# define R300_TX_FORMAT_X32 0x1e
+# define R600_TX_FORMAT_X24_Y8 0x1e
+# define R600_TX_FORMAT_X32 0x1e
/* 0x16 - some 16 bit green format.. ?? */
-# define R300_TX_FORMAT_3D (1 << 25)
-# define R300_TX_FORMAT_CUBIC_MAP (2 << 25)
+# define R600_TX_FORMAT_3D (1 << 25)
+# define R600_TX_FORMAT_CUBIC_MAP (2 << 25)
/* gap */
/* Floating point formats */
/* Note - hardware supports both 16 and 32 bit floating point */
-# define R300_TX_FORMAT_FL_I16 0x18
-# define R300_TX_FORMAT_FL_I16A16 0x19
-# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
-# define R300_TX_FORMAT_FL_I32 0x1B
-# define R300_TX_FORMAT_FL_I32A32 0x1C
-# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
+# define R600_TX_FORMAT_FL_I16 0x18
+# define R600_TX_FORMAT_FL_I16A16 0x19
+# define R600_TX_FORMAT_FL_R16G16B16A16 0x1A
+# define R600_TX_FORMAT_FL_I32 0x1B
+# define R600_TX_FORMAT_FL_I32A32 0x1C
+# define R600_TX_FORMAT_FL_R32G32B32A32 0x1D
/* alpha modes, convenience mostly */
/* if you have alpha, pick constant appropriate to the
number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
-# define R300_TX_FORMAT_ALPHA_1CH 0x000
-# define R300_TX_FORMAT_ALPHA_2CH 0x200
-# define R300_TX_FORMAT_ALPHA_4CH 0x600
-# define R300_TX_FORMAT_ALPHA_NONE 0xA00
+# define R600_TX_FORMAT_ALPHA_1CH 0x000
+# define R600_TX_FORMAT_ALPHA_2CH 0x200
+# define R600_TX_FORMAT_ALPHA_4CH 0x600
+# define R600_TX_FORMAT_ALPHA_NONE 0xA00
/* Swizzling */
/* constants */
-# define R300_TX_FORMAT_X 0
-# define R300_TX_FORMAT_Y 1
-# define R300_TX_FORMAT_Z 2
-# define R300_TX_FORMAT_W 3
-# define R300_TX_FORMAT_ZERO 4
-# define R300_TX_FORMAT_ONE 5
+# define R600_TX_FORMAT_X 0
+# define R600_TX_FORMAT_Y 1
+# define R600_TX_FORMAT_Z 2
+# define R600_TX_FORMAT_W 3
+# define R600_TX_FORMAT_ZERO 4
+# define R600_TX_FORMAT_ONE 5
/* 2.0*Z, everything above 1.0 is set to 0.0 */
-# define R300_TX_FORMAT_CUT_Z 6
+# define R600_TX_FORMAT_CUT_Z 6
/* 2.0*W, everything above 1.0 is set to 0.0 */
-# define R300_TX_FORMAT_CUT_W 7
+# define R600_TX_FORMAT_CUT_W 7
-# define R300_TX_FORMAT_B_SHIFT 18
-# define R300_TX_FORMAT_G_SHIFT 15
-# define R300_TX_FORMAT_R_SHIFT 12
-# define R300_TX_FORMAT_A_SHIFT 9
+# define R600_TX_FORMAT_B_SHIFT 18
+# define R600_TX_FORMAT_G_SHIFT 15
+# define R600_TX_FORMAT_R_SHIFT 12
+# define R600_TX_FORMAT_A_SHIFT 9
/* Convenience macro to take care of layout and swizzling */
-# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
- ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
- | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
- | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
- | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
- | (R300_TX_FORMAT_##FMT) \
+# define R600_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
+ ((R600_TX_FORMAT_##B)<<R600_TX_FORMAT_B_SHIFT) \
+ | ((R600_TX_FORMAT_##G)<<R600_TX_FORMAT_G_SHIFT) \
+ | ((R600_TX_FORMAT_##R)<<R600_TX_FORMAT_R_SHIFT) \
+ | ((R600_TX_FORMAT_##A)<<R600_TX_FORMAT_A_SHIFT) \
+ | (R600_TX_FORMAT_##FMT) \
)
- /* These can be ORed with result of R300_EASY_TX_FORMAT()
+ /* These can be ORed with result of R600_EASY_TX_FORMAT()
We don't really know what they do. Take values from a
constant color ? */
-# define R300_TX_FORMAT_CONST_X (1<<5)
-# define R300_TX_FORMAT_CONST_Y (2<<5)
-# define R300_TX_FORMAT_CONST_Z (4<<5)
-# define R300_TX_FORMAT_CONST_W (8<<5)
+# define R600_TX_FORMAT_CONST_X (1<<5)
+# define R600_TX_FORMAT_CONST_Y (2<<5)
+# define R600_TX_FORMAT_CONST_Z (4<<5)
+# define R600_TX_FORMAT_CONST_W (8<<5)
-# define R300_TX_FORMAT_YUV_MODE 0x00800000
+# define R600_TX_FORMAT_YUV_MODE 0x00800000
-#define R300_TX_FORMAT2_0 0x4500 /* obvious missing in gap */
-# define R300_TX_PITCHMASK_SHIFT 0
-# define R300_TX_PITCHMASK_MASK (2047 << 0)
+#define R600_TX_FORMAT2_0 0x4500 /* obvious missing in gap */
+# define R600_TX_PITCHMASK_SHIFT 0
+# define R600_TX_PITCHMASK_MASK (2047 << 0)
# define R500_TXFORMAT_MSB (1 << 14)
# define R500_TXWIDTH_BIT11 (1 << 15)
# define R500_TXHEIGHT_BIT11 (1 << 16)
# define R500_SEL_FILTER4_TC2 (2 << 18)
# define R500_SEL_FILTER4_TC3 (3 << 18)
-#define R300_TX_OFFSET_0 0x4540
-#define R300_TX_OFFSET_1 0x4544
-#define R300_TX_OFFSET_2 0x4548
-#define R300_TX_OFFSET_3 0x454C
-#define R300_TX_OFFSET_4 0x4550
-#define R300_TX_OFFSET_5 0x4554
-#define R300_TX_OFFSET_6 0x4558
-#define R300_TX_OFFSET_7 0x455C
+#define R600_TX_OFFSET_0 0x4540
+#define R600_TX_OFFSET_1 0x4544
+#define R600_TX_OFFSET_2 0x4548
+#define R600_TX_OFFSET_3 0x454C
+#define R600_TX_OFFSET_4 0x4550
+#define R600_TX_OFFSET_5 0x4554
+#define R600_TX_OFFSET_6 0x4558
+#define R600_TX_OFFSET_7 0x455C
/* BEGIN: Guess from R200 */
-# define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
-# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
-# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
-# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
-# define R300_TXO_MACRO_TILE (1 << 2)
-# define R300_TXO_MICRO_TILE_LINEAR (0 << 3)
-# define R300_TXO_MICRO_TILE (1 << 3)
-# define R300_TXO_MICRO_TILE_SQUARE (2 << 3)
-# define R300_TXO_OFFSET_MASK 0xffffffe0
-# define R300_TXO_OFFSET_SHIFT 5
+# define R600_TXO_ENDIAN_NO_SWAP (0 << 0)
+# define R600_TXO_ENDIAN_BYTE_SWAP (1 << 0)
+# define R600_TXO_ENDIAN_WORD_SWAP (2 << 0)
+# define R600_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
+# define R600_TXO_MACRO_TILE (1 << 2)
+# define R600_TXO_MICRO_TILE_LINEAR (0 << 3)
+# define R600_TXO_MICRO_TILE (1 << 3)
+# define R600_TXO_MICRO_TILE_SQUARE (2 << 3)
+# define R600_TXO_OFFSET_MASK 0xffffffe0
+# define R600_TXO_OFFSET_SHIFT 5
/* END: Guess from R200 */
/* 32 bit chroma key */
-#define R300_TX_CHROMA_KEY_0 0x4580
-#define R300_TX_CHROMA_KEY_1 0x4584
-#define R300_TX_CHROMA_KEY_2 0x4588
-#define R300_TX_CHROMA_KEY_3 0x458c
-#define R300_TX_CHROMA_KEY_4 0x4590
-#define R300_TX_CHROMA_KEY_5 0x4594
-#define R300_TX_CHROMA_KEY_6 0x4598
-#define R300_TX_CHROMA_KEY_7 0x459c
-#define R300_TX_CHROMA_KEY_8 0x45a0
-#define R300_TX_CHROMA_KEY_9 0x45a4
-#define R300_TX_CHROMA_KEY_10 0x45a8
-#define R300_TX_CHROMA_KEY_11 0x45ac
-#define R300_TX_CHROMA_KEY_12 0x45b0
-#define R300_TX_CHROMA_KEY_13 0x45b4
-#define R300_TX_CHROMA_KEY_14 0x45b8
-#define R300_TX_CHROMA_KEY_15 0x45bc
+#define R600_TX_CHROMA_KEY_0 0x4580
+#define R600_TX_CHROMA_KEY_1 0x4584
+#define R600_TX_CHROMA_KEY_2 0x4588
+#define R600_TX_CHROMA_KEY_3 0x458c
+#define R600_TX_CHROMA_KEY_4 0x4590
+#define R600_TX_CHROMA_KEY_5 0x4594
+#define R600_TX_CHROMA_KEY_6 0x4598
+#define R600_TX_CHROMA_KEY_7 0x459c
+#define R600_TX_CHROMA_KEY_8 0x45a0
+#define R600_TX_CHROMA_KEY_9 0x45a4
+#define R600_TX_CHROMA_KEY_10 0x45a8
+#define R600_TX_CHROMA_KEY_11 0x45ac
+#define R600_TX_CHROMA_KEY_12 0x45b0
+#define R600_TX_CHROMA_KEY_13 0x45b4
+#define R600_TX_CHROMA_KEY_14 0x45b8
+#define R600_TX_CHROMA_KEY_15 0x45bc
/* ff00ff00 == { 0, 1.0, 0, 1.0 } */
/* Border Color */
-#define R300_TX_BORDER_COLOR_0 0x45c0
-#define R300_TX_BORDER_COLOR_1 0x45c4
-#define R300_TX_BORDER_COLOR_2 0x45c8
-#define R300_TX_BORDER_COLOR_3 0x45cc
-#define R300_TX_BORDER_COLOR_4 0x45d0
-#define R300_TX_BORDER_COLOR_5 0x45d4
-#define R300_TX_BORDER_COLOR_6 0x45d8
-#define R300_TX_BORDER_COLOR_7 0x45dc
-#define R300_TX_BORDER_COLOR_8 0x45e0
-#define R300_TX_BORDER_COLOR_9 0x45e4
-#define R300_TX_BORDER_COLOR_10 0x45e8
-#define R300_TX_BORDER_COLOR_11 0x45ec
-#define R300_TX_BORDER_COLOR_12 0x45f0
-#define R300_TX_BORDER_COLOR_13 0x45f4
-#define R300_TX_BORDER_COLOR_14 0x45f8
-#define R300_TX_BORDER_COLOR_15 0x45fc
+#define R600_TX_BORDER_COLOR_0 0x45c0
+#define R600_TX_BORDER_COLOR_1 0x45c4
+#define R600_TX_BORDER_COLOR_2 0x45c8
+#define R600_TX_BORDER_COLOR_3 0x45cc
+#define R600_TX_BORDER_COLOR_4 0x45d0
+#define R600_TX_BORDER_COLOR_5 0x45d4
+#define R600_TX_BORDER_COLOR_6 0x45d8
+#define R600_TX_BORDER_COLOR_7 0x45dc
+#define R600_TX_BORDER_COLOR_8 0x45e0
+#define R600_TX_BORDER_COLOR_9 0x45e4
+#define R600_TX_BORDER_COLOR_10 0x45e8
+#define R600_TX_BORDER_COLOR_11 0x45ec
+#define R600_TX_BORDER_COLOR_12 0x45f0
+#define R600_TX_BORDER_COLOR_13 0x45f4
+#define R600_TX_BORDER_COLOR_14 0x45f8
+#define R600_TX_BORDER_COLOR_15 0x45fc
/* END: Texture specification */
* offsets into the respective instruction streams, while *_END points to the
* last instruction relative to this offset.
*/
-#define R300_US_CONFIG 0x4600
-# define R300_PFS_CNTL_LAST_NODES_SHIFT 0
-# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
-# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
-#define R300_US_PIXSIZE 0x4604
+#define R600_US_CONFIG 0x4600
+# define R600_PFS_CNTL_LAST_NODES_SHIFT 0
+# define R600_PFS_CNTL_LAST_NODES_MASK (3 << 0)
+# define R600_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
+#define R600_US_PIXSIZE 0x4604
/* There is an unshifted value here which has so far always been equal to the
* index of the highest used temporary register.
*/
-#define R300_US_CODE_OFFSET 0x4608
-# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
-# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
-# define R300_PFS_CNTL_ALU_END_SHIFT 6
-# define R300_PFS_CNTL_ALU_END_MASK (63 << 6)
-# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 13
-# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 13)
-# define R300_PFS_CNTL_TEX_END_SHIFT 18
-# define R300_PFS_CNTL_TEX_END_MASK (31 << 18)
+#define R600_US_CODE_OFFSET 0x4608
+# define R600_PFS_CNTL_ALU_OFFSET_SHIFT 0
+# define R600_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
+# define R600_PFS_CNTL_ALU_END_SHIFT 6
+# define R600_PFS_CNTL_ALU_END_MASK (63 << 6)
+# define R600_PFS_CNTL_TEX_OFFSET_SHIFT 13
+# define R600_PFS_CNTL_TEX_OFFSET_MASK (31 << 13)
+# define R600_PFS_CNTL_TEX_END_SHIFT 18
+# define R600_PFS_CNTL_TEX_END_MASK (31 << 18)
/* gap */
*
* Offsets are relative to the master offset from PFS_CNTL_2.
*/
-#define R300_US_CODE_ADDR_0 0x4610
-#define R300_US_CODE_ADDR_1 0x4614
-#define R300_US_CODE_ADDR_2 0x4618
-#define R300_US_CODE_ADDR_3 0x461C
-# define R300_ALU_START_SHIFT 0
-# define R300_ALU_START_MASK (63 << 0)
-# define R300_ALU_SIZE_SHIFT 6
-# define R300_ALU_SIZE_MASK (63 << 6)
-# define R300_TEX_START_SHIFT 12
-# define R300_TEX_START_MASK (31 << 12)
-# define R300_TEX_SIZE_SHIFT 17
-# define R300_TEX_SIZE_MASK (31 << 17)
-# define R300_RGBA_OUT (1 << 22)
-# define R300_W_OUT (1 << 23)
+#define R600_US_CODE_ADDR_0 0x4610
+#define R600_US_CODE_ADDR_1 0x4614
+#define R600_US_CODE_ADDR_2 0x4618
+#define R600_US_CODE_ADDR_3 0x461C
+# define R600_ALU_START_SHIFT 0
+# define R600_ALU_START_MASK (63 << 0)
+# define R600_ALU_SIZE_SHIFT 6
+# define R600_ALU_SIZE_MASK (63 << 6)
+# define R600_TEX_START_SHIFT 12
+# define R600_TEX_START_MASK (31 << 12)
+# define R600_TEX_SIZE_SHIFT 17
+# define R600_TEX_SIZE_MASK (31 << 17)
+# define R600_RGBA_OUT (1 << 22)
+# define R600_W_OUT (1 << 23)
/* TEX
* As far as I can tell, texture instructions cannot write into output
* registers directly. A subsequent ALU instruction is always necessary,
* even if it's just MAD o0, r0, 1, 0
*/
-#define R300_US_TEX_INST_0 0x4620
-# define R300_SRC_ADDR_SHIFT 0
-# define R300_SRC_ADDR_MASK (31 << 0)
-# define R300_DST_ADDR_SHIFT 6
-# define R300_DST_ADDR_MASK (31 << 6)
-# define R300_TEX_ID_SHIFT 11
-# define R300_TEX_ID_MASK (15 << 11)
-# define R300_TEX_INST_SHIFT 15
-# define R300_TEX_OP_NOP 0
-# define R300_TEX_OP_LD 1
-# define R300_TEX_OP_KIL 2
-# define R300_TEX_OP_TXP 3
-# define R300_TEX_OP_TXB 4
-# define R300_TEX_INST_MASK (7 << 15)
+#define R600_US_TEX_INST_0 0x4620
+# define R600_SRC_ADDR_SHIFT 0
+# define R600_SRC_ADDR_MASK (31 << 0)
+# define R600_DST_ADDR_SHIFT 6
+# define R600_DST_ADDR_MASK (31 << 6)
+# define R600_TEX_ID_SHIFT 11
+# define R600_TEX_ID_MASK (15 << 11)
+# define R600_TEX_INST_SHIFT 15
+# define R600_TEX_OP_NOP 0
+# define R600_TEX_OP_LD 1
+# define R600_TEX_OP_KIL 2
+# define R600_TEX_OP_TXP 3
+# define R600_TEX_OP_TXB 4
+# define R600_TEX_INST_MASK (7 << 15)
/* Output format from the unfied shader */
-#define R300_US_OUT_FMT 0x46A4
-# define R300_US_OUT_FMT_C4_8 (0 << 0)
-# define R300_US_OUT_FMT_C4_10 (1 << 0)
-# define R300_US_OUT_FMT_C4_10_GAMMA (2 << 0)
-# define R300_US_OUT_FMT_C_16 (3 << 0)
-# define R300_US_OUT_FMT_C2_16 (4 << 0)
-# define R300_US_OUT_FMT_C4_16 (5 << 0)
-# define R300_US_OUT_FMT_C_16_MPEG (6 << 0)
-# define R300_US_OUT_FMT_C2_16_MPEG (7 << 0)
-# define R300_US_OUT_FMT_C2_4 (8 << 0)
-# define R300_US_OUT_FMT_C_3_3_2 (9 << 0)
-# define R300_US_OUT_FMT_C_6_5_6 (10 << 0)
-# define R300_US_OUT_FMT_C_11_11_10 (11 << 0)
-# define R300_US_OUT_FMT_C_10_11_11 (12 << 0)
-# define R300_US_OUT_FMT_C_2_10_10_10 (13 << 0)
+#define R600_US_OUT_FMT 0x46A4
+# define R600_US_OUT_FMT_C4_8 (0 << 0)
+# define R600_US_OUT_FMT_C4_10 (1 << 0)
+# define R600_US_OUT_FMT_C4_10_GAMMA (2 << 0)
+# define R600_US_OUT_FMT_C_16 (3 << 0)
+# define R600_US_OUT_FMT_C2_16 (4 << 0)
+# define R600_US_OUT_FMT_C4_16 (5 << 0)
+# define R600_US_OUT_FMT_C_16_MPEG (6 << 0)
+# define R600_US_OUT_FMT_C2_16_MPEG (7 << 0)
+# define R600_US_OUT_FMT_C2_4 (8 << 0)
+# define R600_US_OUT_FMT_C_3_3_2 (9 << 0)
+# define R600_US_OUT_FMT_C_6_5_6 (10 << 0)
+# define R600_US_OUT_FMT_C_11_11_10 (11 << 0)
+# define R600_US_OUT_FMT_C_10_11_11 (12 << 0)
+# define R600_US_OUT_FMT_C_2_10_10_10 (13 << 0)
/* reserved */
-# define R300_US_OUT_FMT_UNUSED (15 << 0)
-# define R300_US_OUT_FMT_C_16_FP (16 << 0)
-# define R300_US_OUT_FMT_C2_16_FP (17 << 0)
-# define R300_US_OUT_FMT_C4_16_FP (18 << 0)
-# define R300_US_OUT_FMT_C_32_FP (19 << 0)
-# define R300_US_OUT_FMT_C2_32_FP (20 << 0)
-# define R300_US_OUT_FMT_C4_32_FP (20 << 0)
+# define R600_US_OUT_FMT_UNUSED (15 << 0)
+# define R600_US_OUT_FMT_C_16_FP (16 << 0)
+# define R600_US_OUT_FMT_C2_16_FP (17 << 0)
+# define R600_US_OUT_FMT_C4_16_FP (18 << 0)
+# define R600_US_OUT_FMT_C_32_FP (19 << 0)
+# define R600_US_OUT_FMT_C2_32_FP (20 << 0)
+# define R600_US_OUT_FMT_C4_32_FP (20 << 0)
/* ALU
* The ALU instructions register blocks are enumerated according to the order
* - Set FPI0/FPI2_SPECIAL_LRP
* Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
*/
-#define R300_US_ALU_RGB_ADDR_0 0x46C0
-# define R300_ALU_SRC0C_SHIFT 0
-# define R300_ALU_SRC0C_MASK (31 << 0)
-# define R300_ALU_SRC0C_CONST (1 << 5)
-# define R300_ALU_SRC1C_SHIFT 6
-# define R300_ALU_SRC1C_MASK (31 << 6)
-# define R300_ALU_SRC1C_CONST (1 << 11)
-# define R300_ALU_SRC2C_SHIFT 12
-# define R300_ALU_SRC2C_MASK (31 << 12)
-# define R300_ALU_SRC2C_CONST (1 << 17)
-# define R300_ALU_SRC_MASK 0x0003ffff
-# define R300_ALU_DSTC_SHIFT 18
-# define R300_ALU_DSTC_MASK (31 << 18)
-# define R300_ALU_DSTC_REG_MASK_SHIFT 23
-# define R300_ALU_DSTC_REG_X (1 << 23)
-# define R300_ALU_DSTC_REG_Y (1 << 24)
-# define R300_ALU_DSTC_REG_Z (1 << 25)
-# define R300_ALU_DSTC_OUTPUT_MASK_SHIFT 26
-# define R300_ALU_DSTC_OUTPUT_X (1 << 26)
-# define R300_ALU_DSTC_OUTPUT_Y (1 << 27)
-# define R300_ALU_DSTC_OUTPUT_Z (1 << 28)
-
-#define R300_US_ALU_ALPHA_ADDR_0 0x47C0
-# define R300_ALU_SRC0A_SHIFT 0
-# define R300_ALU_SRC0A_MASK (31 << 0)
-# define R300_ALU_SRC0A_CONST (1 << 5)
-# define R300_ALU_SRC1A_SHIFT 6
-# define R300_ALU_SRC1A_MASK (31 << 6)
-# define R300_ALU_SRC1A_CONST (1 << 11)
-# define R300_ALU_SRC2A_SHIFT 12
-# define R300_ALU_SRC2A_MASK (31 << 12)
-# define R300_ALU_SRC2A_CONST (1 << 17)
-# define R300_ALU_SRC_MASK 0x0003ffff
-# define R300_ALU_DSTA_SHIFT 18
-# define R300_ALU_DSTA_MASK (31 << 18)
-# define R300_ALU_DSTA_REG (1 << 23)
-# define R300_ALU_DSTA_OUTPUT (1 << 24)
-# define R300_ALU_DSTA_DEPTH (1 << 27)
-
-#define R300_US_ALU_RGB_INST_0 0x48C0
-# define R300_ALU_ARGC_SRC0C_XYZ 0
-# define R300_ALU_ARGC_SRC0C_XXX 1
-# define R300_ALU_ARGC_SRC0C_YYY 2
-# define R300_ALU_ARGC_SRC0C_ZZZ 3
-# define R300_ALU_ARGC_SRC1C_XYZ 4
-# define R300_ALU_ARGC_SRC1C_XXX 5
-# define R300_ALU_ARGC_SRC1C_YYY 6
-# define R300_ALU_ARGC_SRC1C_ZZZ 7
-# define R300_ALU_ARGC_SRC2C_XYZ 8
-# define R300_ALU_ARGC_SRC2C_XXX 9
-# define R300_ALU_ARGC_SRC2C_YYY 10
-# define R300_ALU_ARGC_SRC2C_ZZZ 11
-# define R300_ALU_ARGC_SRC0A 12
-# define R300_ALU_ARGC_SRC1A 13
-# define R300_ALU_ARGC_SRC2A 14
-# define R300_ALU_ARGC_SRCP_XYZ 15
-# define R300_ALU_ARGC_SRCP_XXX 16
-# define R300_ALU_ARGC_SRCP_YYY 17
-# define R300_ALU_ARGC_SRCP_ZZZ 18
-# define R300_ALU_ARGC_SRCP_WWW 19
-# define R300_ALU_ARGC_ZERO 20
-# define R300_ALU_ARGC_ONE 21
-# define R300_ALU_ARGC_HALF 22
-# define R300_ALU_ARGC_SRC0C_YZX 23
-# define R300_ALU_ARGC_SRC1C_YZX 24
-# define R300_ALU_ARGC_SRC2C_YZX 25
-# define R300_ALU_ARGC_SRC0C_ZXY 26
-# define R300_ALU_ARGC_SRC1C_ZXY 27
-# define R300_ALU_ARGC_SRC2C_ZXY 28
-# define R300_ALU_ARGC_SRC0CA_WZY 29
-# define R300_ALU_ARGC_SRC1CA_WZY 30
-# define R300_ALU_ARGC_SRC2CA_WZY 31
-
-# define R300_ALU_ARG0C_SHIFT 0
-# define R300_ALU_ARG0C_MASK (31 << 0)
-# define R300_ALU_ARG0C_NOP (0 << 5)
-# define R300_ALU_ARG0C_NEG (1 << 5)
-# define R300_ALU_ARG0C_ABS (2 << 5)
-# define R300_ALU_ARG0C_NAB (3 << 5)
-# define R300_ALU_ARG1C_SHIFT 7
-# define R300_ALU_ARG1C_MASK (31 << 7)
-# define R300_ALU_ARG1C_NOP (0 << 12)
-# define R300_ALU_ARG1C_NEG (1 << 12)
-# define R300_ALU_ARG1C_ABS (2 << 12)
-# define R300_ALU_ARG1C_NAB (3 << 12)
-# define R300_ALU_ARG2C_SHIFT 14
-# define R300_ALU_ARG2C_MASK (31 << 14)
-# define R300_ALU_ARG2C_NOP (0 << 19)
-# define R300_ALU_ARG2C_NEG (1 << 19)
-# define R300_ALU_ARG2C_ABS (2 << 19)
-# define R300_ALU_ARG2C_NAB (3 << 19)
-# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21)
-# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21)
-# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21)
-# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21)
-
-# define R300_ALU_OUTC_MAD (0 << 23)
-# define R300_ALU_OUTC_DP3 (1 << 23)
-# define R300_ALU_OUTC_DP4 (2 << 23)
-# define R300_ALU_OUTC_D2A (3 << 23)
-# define R300_ALU_OUTC_MIN (4 << 23)
-# define R300_ALU_OUTC_MAX (5 << 23)
-# define R300_ALU_OUTC_CMPH (7 << 23)
-# define R300_ALU_OUTC_CMP (8 << 23)
-# define R300_ALU_OUTC_FRC (9 << 23)
-# define R300_ALU_OUTC_REPL_ALPHA (10 << 23)
-
-# define R300_ALU_OUTC_MOD_NOP (0 << 27)
-# define R300_ALU_OUTC_MOD_MUL2 (1 << 27)
-# define R300_ALU_OUTC_MOD_MUL4 (2 << 27)
-# define R300_ALU_OUTC_MOD_MUL8 (3 << 27)
-# define R300_ALU_OUTC_MOD_DIV2 (4 << 27)
-# define R300_ALU_OUTC_MOD_DIV4 (5 << 27)
-# define R300_ALU_OUTC_MOD_DIV8 (6 << 27)
-
-# define R300_ALU_OUTC_CLAMP (1 << 30)
-# define R300_ALU_INSERT_NOP (1 << 31)
-
-#define R300_US_ALU_ALPHA_INST_0 0x49C0
-# define R300_ALU_ARGA_SRC0C_X 0
-# define R300_ALU_ARGA_SRC0C_Y 1
-# define R300_ALU_ARGA_SRC0C_Z 2
-# define R300_ALU_ARGA_SRC1C_X 3
-# define R300_ALU_ARGA_SRC1C_Y 4
-# define R300_ALU_ARGA_SRC1C_Z 5
-# define R300_ALU_ARGA_SRC2C_X 6
-# define R300_ALU_ARGA_SRC2C_Y 7
-# define R300_ALU_ARGA_SRC2C_Z 8
-# define R300_ALU_ARGA_SRC0A 9
-# define R300_ALU_ARGA_SRC1A 10
-# define R300_ALU_ARGA_SRC2A 11
-# define R300_ALU_ARGA_SRCP_X 12
-# define R300_ALU_ARGA_SRCP_Y 13
-# define R300_ALU_ARGA_SRCP_Z 14
-# define R300_ALU_ARGA_SRCP_W 15
-
-# define R300_ALU_ARGA_ZERO 16
-# define R300_ALU_ARGA_ONE 17
-# define R300_ALU_ARGA_HALF 18
-# define R300_ALU_ARG0A_SHIFT 0
-# define R300_ALU_ARG0A_MASK (31 << 0)
-# define R300_ALU_ARG0A_NOP (0 << 5)
-# define R300_ALU_ARG0A_NEG (1 << 5)
-# define R300_ALU_ARG0A_ABS (2 << 5)
-# define R300_ALU_ARG0A_NAB (3 << 5)
-# define R300_ALU_ARG1A_SHIFT 7
-# define R300_ALU_ARG1A_MASK (31 << 7)
-# define R300_ALU_ARG1A_NOP (0 << 12)
-# define R300_ALU_ARG1A_NEG (1 << 12)
-# define R300_ALU_ARG1A_ABS (2 << 12)
-# define R300_ALU_ARG1A_NAB (3 << 12)
-# define R300_ALU_ARG2A_SHIFT 14
-# define R300_ALU_ARG2A_MASK (31 << 14)
-# define R300_ALU_ARG2A_NOP (0 << 19)
-# define R300_ALU_ARG2A_NEG (1 << 19)
-# define R300_ALU_ARG2A_ABS (2 << 19)
-# define R300_ALU_ARG2A_NAB (3 << 19)
-# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21)
-# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21)
-# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21)
-# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21)
-
-# define R300_ALU_OUTA_MAD (0 << 23)
-# define R300_ALU_OUTA_DP4 (1 << 23)
-# define R300_ALU_OUTA_MIN (2 << 23)
-# define R300_ALU_OUTA_MAX (3 << 23)
-# define R300_ALU_OUTA_CND (5 << 23)
-# define R300_ALU_OUTA_CMP (6 << 23)
-# define R300_ALU_OUTA_FRC (7 << 23)
-# define R300_ALU_OUTA_EX2 (8 << 23)
-# define R300_ALU_OUTA_LG2 (9 << 23)
-# define R300_ALU_OUTA_RCP (10 << 23)
-# define R300_ALU_OUTA_RSQ (11 << 23)
-
-# define R300_ALU_OUTA_MOD_NOP (0 << 27)
-# define R300_ALU_OUTA_MOD_MUL2 (1 << 27)
-# define R300_ALU_OUTA_MOD_MUL4 (2 << 27)
-# define R300_ALU_OUTA_MOD_MUL8 (3 << 27)
-# define R300_ALU_OUTA_MOD_DIV2 (4 << 27)
-# define R300_ALU_OUTA_MOD_DIV4 (5 << 27)
-# define R300_ALU_OUTA_MOD_DIV8 (6 << 27)
-
-# define R300_ALU_OUTA_CLAMP (1 << 30)
+#define R600_US_ALU_RGB_ADDR_0 0x46C0
+# define R600_ALU_SRC0C_SHIFT 0
+# define R600_ALU_SRC0C_MASK (31 << 0)
+# define R600_ALU_SRC0C_CONST (1 << 5)
+# define R600_ALU_SRC1C_SHIFT 6
+# define R600_ALU_SRC1C_MASK (31 << 6)
+# define R600_ALU_SRC1C_CONST (1 << 11)
+# define R600_ALU_SRC2C_SHIFT 12
+# define R600_ALU_SRC2C_MASK (31 << 12)
+# define R600_ALU_SRC2C_CONST (1 << 17)
+# define R600_ALU_SRC_MASK 0x0003ffff
+# define R600_ALU_DSTC_SHIFT 18
+# define R600_ALU_DSTC_MASK (31 << 18)
+# define R600_ALU_DSTC_REG_MASK_SHIFT 23
+# define R600_ALU_DSTC_REG_X (1 << 23)
+# define R600_ALU_DSTC_REG_Y (1 << 24)
+# define R600_ALU_DSTC_REG_Z (1 << 25)
+# define R600_ALU_DSTC_OUTPUT_MASK_SHIFT 26
+# define R600_ALU_DSTC_OUTPUT_X (1 << 26)
+# define R600_ALU_DSTC_OUTPUT_Y (1 << 27)
+# define R600_ALU_DSTC_OUTPUT_Z (1 << 28)
+
+#define R600_US_ALU_ALPHA_ADDR_0 0x47C0
+# define R600_ALU_SRC0A_SHIFT 0
+# define R600_ALU_SRC0A_MASK (31 << 0)
+# define R600_ALU_SRC0A_CONST (1 << 5)
+# define R600_ALU_SRC1A_SHIFT 6
+# define R600_ALU_SRC1A_MASK (31 << 6)
+# define R600_ALU_SRC1A_CONST (1 << 11)
+# define R600_ALU_SRC2A_SHIFT 12
+# define R600_ALU_SRC2A_MASK (31 << 12)
+# define R600_ALU_SRC2A_CONST (1 << 17)
+# define R600_ALU_SRC_MASK 0x0003ffff
+# define R600_ALU_DSTA_SHIFT 18
+# define R600_ALU_DSTA_MASK (31 << 18)
+# define R600_ALU_DSTA_REG (1 << 23)
+# define R600_ALU_DSTA_OUTPUT (1 << 24)
+# define R600_ALU_DSTA_DEPTH (1 << 27)
+
+#define R600_US_ALU_RGB_INST_0 0x48C0
+# define R600_ALU_ARGC_SRC0C_XYZ 0
+# define R600_ALU_ARGC_SRC0C_XXX 1
+# define R600_ALU_ARGC_SRC0C_YYY 2
+# define R600_ALU_ARGC_SRC0C_ZZZ 3
+# define R600_ALU_ARGC_SRC1C_XYZ 4
+# define R600_ALU_ARGC_SRC1C_XXX 5
+# define R600_ALU_ARGC_SRC1C_YYY 6
+# define R600_ALU_ARGC_SRC1C_ZZZ 7
+# define R600_ALU_ARGC_SRC2C_XYZ 8
+# define R600_ALU_ARGC_SRC2C_XXX 9
+# define R600_ALU_ARGC_SRC2C_YYY 10
+# define R600_ALU_ARGC_SRC2C_ZZZ 11
+# define R600_ALU_ARGC_SRC0A 12
+# define R600_ALU_ARGC_SRC1A 13
+# define R600_ALU_ARGC_SRC2A 14
+# define R600_ALU_ARGC_SRCP_XYZ 15
+# define R600_ALU_ARGC_SRCP_XXX 16
+# define R600_ALU_ARGC_SRCP_YYY 17
+# define R600_ALU_ARGC_SRCP_ZZZ 18
+# define R600_ALU_ARGC_SRCP_WWW 19
+# define R600_ALU_ARGC_ZERO 20
+# define R600_ALU_ARGC_ONE 21
+# define R600_ALU_ARGC_HALF 22
+# define R600_ALU_ARGC_SRC0C_YZX 23
+# define R600_ALU_ARGC_SRC1C_YZX 24
+# define R600_ALU_ARGC_SRC2C_YZX 25
+# define R600_ALU_ARGC_SRC0C_ZXY 26
+# define R600_ALU_ARGC_SRC1C_ZXY 27
+# define R600_ALU_ARGC_SRC2C_ZXY 28
+# define R600_ALU_ARGC_SRC0CA_WZY 29
+# define R600_ALU_ARGC_SRC1CA_WZY 30
+# define R600_ALU_ARGC_SRC2CA_WZY 31
+
+# define R600_ALU_ARG0C_SHIFT 0
+# define R600_ALU_ARG0C_MASK (31 << 0)
+# define R600_ALU_ARG0C_NOP (0 << 5)
+# define R600_ALU_ARG0C_NEG (1 << 5)
+# define R600_ALU_ARG0C_ABS (2 << 5)
+# define R600_ALU_ARG0C_NAB (3 << 5)
+# define R600_ALU_ARG1C_SHIFT 7
+# define R600_ALU_ARG1C_MASK (31 << 7)
+# define R600_ALU_ARG1C_NOP (0 << 12)
+# define R600_ALU_ARG1C_NEG (1 << 12)
+# define R600_ALU_ARG1C_ABS (2 << 12)
+# define R600_ALU_ARG1C_NAB (3 << 12)
+# define R600_ALU_ARG2C_SHIFT 14
+# define R600_ALU_ARG2C_MASK (31 << 14)
+# define R600_ALU_ARG2C_NOP (0 << 19)
+# define R600_ALU_ARG2C_NEG (1 << 19)
+# define R600_ALU_ARG2C_ABS (2 << 19)
+# define R600_ALU_ARG2C_NAB (3 << 19)
+# define R600_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21)
+# define R600_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21)
+# define R600_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21)
+# define R600_ALU_SRCP_1_MINUS_SRC0 (3 << 21)
+
+# define R600_ALU_OUTC_MAD (0 << 23)
+# define R600_ALU_OUTC_DP3 (1 << 23)
+# define R600_ALU_OUTC_DP4 (2 << 23)
+# define R600_ALU_OUTC_D2A (3 << 23)
+# define R600_ALU_OUTC_MIN (4 << 23)
+# define R600_ALU_OUTC_MAX (5 << 23)
+# define R600_ALU_OUTC_CMPH (7 << 23)
+# define R600_ALU_OUTC_CMP (8 << 23)
+# define R600_ALU_OUTC_FRC (9 << 23)
+# define R600_ALU_OUTC_REPL_ALPHA (10 << 23)
+
+# define R600_ALU_OUTC_MOD_NOP (0 << 27)
+# define R600_ALU_OUTC_MOD_MUL2 (1 << 27)
+# define R600_ALU_OUTC_MOD_MUL4 (2 << 27)
+# define R600_ALU_OUTC_MOD_MUL8 (3 << 27)
+# define R600_ALU_OUTC_MOD_DIV2 (4 << 27)
+# define R600_ALU_OUTC_MOD_DIV4 (5 << 27)
+# define R600_ALU_OUTC_MOD_DIV8 (6 << 27)
+
+# define R600_ALU_OUTC_CLAMP (1 << 30)
+# define R600_ALU_INSERT_NOP (1 << 31)
+
+#define R600_US_ALU_ALPHA_INST_0 0x49C0
+# define R600_ALU_ARGA_SRC0C_X 0
+# define R600_ALU_ARGA_SRC0C_Y 1
+# define R600_ALU_ARGA_SRC0C_Z 2
+# define R600_ALU_ARGA_SRC1C_X 3
+# define R600_ALU_ARGA_SRC1C_Y 4
+# define R600_ALU_ARGA_SRC1C_Z 5
+# define R600_ALU_ARGA_SRC2C_X 6
+# define R600_ALU_ARGA_SRC2C_Y 7
+# define R600_ALU_ARGA_SRC2C_Z 8
+# define R600_ALU_ARGA_SRC0A 9
+# define R600_ALU_ARGA_SRC1A 10
+# define R600_ALU_ARGA_SRC2A 11
+# define R600_ALU_ARGA_SRCP_X 12
+# define R600_ALU_ARGA_SRCP_Y 13
+# define R600_ALU_ARGA_SRCP_Z 14
+# define R600_ALU_ARGA_SRCP_W 15
+
+# define R600_ALU_ARGA_ZERO 16
+# define R600_ALU_ARGA_ONE 17
+# define R600_ALU_ARGA_HALF 18
+# define R600_ALU_ARG0A_SHIFT 0
+# define R600_ALU_ARG0A_MASK (31 << 0)
+# define R600_ALU_ARG0A_NOP (0 << 5)
+# define R600_ALU_ARG0A_NEG (1 << 5)
+# define R600_ALU_ARG0A_ABS (2 << 5)
+# define R600_ALU_ARG0A_NAB (3 << 5)
+# define R600_ALU_ARG1A_SHIFT 7
+# define R600_ALU_ARG1A_MASK (31 << 7)
+# define R600_ALU_ARG1A_NOP (0 << 12)
+# define R600_ALU_ARG1A_NEG (1 << 12)
+# define R600_ALU_ARG1A_ABS (2 << 12)
+# define R600_ALU_ARG1A_NAB (3 << 12)
+# define R600_ALU_ARG2A_SHIFT 14
+# define R600_ALU_ARG2A_MASK (31 << 14)
+# define R600_ALU_ARG2A_NOP (0 << 19)
+# define R600_ALU_ARG2A_NEG (1 << 19)
+# define R600_ALU_ARG2A_ABS (2 << 19)
+# define R600_ALU_ARG2A_NAB (3 << 19)
+# define R600_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21)
+# define R600_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21)
+# define R600_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21)
+# define R600_ALU_SRCP_1_MINUS_SRC0 (3 << 21)
+
+# define R600_ALU_OUTA_MAD (0 << 23)
+# define R600_ALU_OUTA_DP4 (1 << 23)
+# define R600_ALU_OUTA_MIN (2 << 23)
+# define R600_ALU_OUTA_MAX (3 << 23)
+# define R600_ALU_OUTA_CND (5 << 23)
+# define R600_ALU_OUTA_CMP (6 << 23)
+# define R600_ALU_OUTA_FRC (7 << 23)
+# define R600_ALU_OUTA_EX2 (8 << 23)
+# define R600_ALU_OUTA_LG2 (9 << 23)
+# define R600_ALU_OUTA_RCP (10 << 23)
+# define R600_ALU_OUTA_RSQ (11 << 23)
+
+# define R600_ALU_OUTA_MOD_NOP (0 << 27)
+# define R600_ALU_OUTA_MOD_MUL2 (1 << 27)
+# define R600_ALU_OUTA_MOD_MUL4 (2 << 27)
+# define R600_ALU_OUTA_MOD_MUL8 (3 << 27)
+# define R600_ALU_OUTA_MOD_DIV2 (4 << 27)
+# define R600_ALU_OUTA_MOD_DIV4 (5 << 27)
+# define R600_ALU_OUTA_MOD_DIV8 (6 << 27)
+
+# define R600_ALU_OUTA_CLAMP (1 << 30)
/* END: Fragment program instruction set */
/* Fog: Fog Blending Enable */
-#define R300_FG_FOG_BLEND 0x4bc0
-# define R300_FG_FOG_BLEND_DISABLE (0 << 0)
-# define R300_FG_FOG_BLEND_ENABLE (1 << 0)
-# define R300_FG_FOG_BLEND_FN_LINEAR (0 << 1)
-# define R300_FG_FOG_BLEND_FN_EXP (1 << 1)
-# define R300_FG_FOG_BLEND_FN_EXP2 (2 << 1)
-# define R300_FG_FOG_BLEND_FN_CONSTANT (3 << 1)
-# define R300_FG_FOG_BLEND_FN_MASK (3 << 1)
+#define R600_FG_FOG_BLEND 0x4bc0
+# define R600_FG_FOG_BLEND_DISABLE (0 << 0)
+# define R600_FG_FOG_BLEND_ENABLE (1 << 0)
+# define R600_FG_FOG_BLEND_FN_LINEAR (0 << 1)
+# define R600_FG_FOG_BLEND_FN_EXP (1 << 1)
+# define R600_FG_FOG_BLEND_FN_EXP2 (2 << 1)
+# define R600_FG_FOG_BLEND_FN_CONSTANT (3 << 1)
+# define R600_FG_FOG_BLEND_FN_MASK (3 << 1)
/* Fog: Red Component of Fog Color */
-#define R300_FG_FOG_COLOR_R 0x4bc8
+#define R600_FG_FOG_COLOR_R 0x4bc8
/* Fog: Green Component of Fog Color */
-#define R300_FG_FOG_COLOR_G 0x4bcc
+#define R600_FG_FOG_COLOR_G 0x4bcc
/* Fog: Blue Component of Fog Color */
-#define R300_FG_FOG_COLOR_B 0x4bd0
-# define R300_FG_FOG_COLOR_MASK 0x000003ff
+#define R600_FG_FOG_COLOR_B 0x4bd0
+# define R600_FG_FOG_COLOR_MASK 0x000003ff
/* Fog: Constant Factor for Fog Blending */
-#define R300_FG_FOG_FACTOR 0x4bc4
+#define R600_FG_FOG_FACTOR 0x4bc4
# define FG_FOG_FACTOR_MASK 0x000003ff
/* Fog: Alpha function */
-#define R300_FG_ALPHA_FUNC 0x4bd4
-# define R300_FG_ALPHA_FUNC_VAL_MASK 0x000000ff
-# define R300_FG_ALPHA_FUNC_NEVER (0 << 8)
-# define R300_FG_ALPHA_FUNC_LESS (1 << 8)
-# define R300_FG_ALPHA_FUNC_EQUAL (2 << 8)
-# define R300_FG_ALPHA_FUNC_LE (3 << 8)
-# define R300_FG_ALPHA_FUNC_GREATER (4 << 8)
-# define R300_FG_ALPHA_FUNC_NOTEQUAL (5 << 8)
-# define R300_FG_ALPHA_FUNC_GE (6 << 8)
-# define R300_FG_ALPHA_FUNC_ALWAYS (7 << 8)
-# define R300_ALPHA_TEST_OP_MASK (7 << 8)
-# define R300_FG_ALPHA_FUNC_DISABLE (0 << 11)
-# define R300_FG_ALPHA_FUNC_ENABLE (1 << 11)
+#define R600_FG_ALPHA_FUNC 0x4bd4
+# define R600_FG_ALPHA_FUNC_VAL_MASK 0x000000ff
+# define R600_FG_ALPHA_FUNC_NEVER (0 << 8)
+# define R600_FG_ALPHA_FUNC_LESS (1 << 8)
+# define R600_FG_ALPHA_FUNC_EQUAL (2 << 8)
+# define R600_FG_ALPHA_FUNC_LE (3 << 8)
+# define R600_FG_ALPHA_FUNC_GREATER (4 << 8)
+# define R600_FG_ALPHA_FUNC_NOTEQUAL (5 << 8)
+# define R600_FG_ALPHA_FUNC_GE (6 << 8)
+# define R600_FG_ALPHA_FUNC_ALWAYS (7 << 8)
+# define R600_ALPHA_TEST_OP_MASK (7 << 8)
+# define R600_FG_ALPHA_FUNC_DISABLE (0 << 11)
+# define R600_FG_ALPHA_FUNC_ENABLE (1 << 11)
# define R500_FG_ALPHA_FUNC_10BIT (0 << 12)
# define R500_FG_ALPHA_FUNC_8BIT (1 << 12)
-# define R300_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16)
-# define R300_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16)
-# define R300_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17)
-# define R300_FG_ALPHA_FUNC_CFG_3_OF_6 (1 << 17)
+# define R600_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16)
+# define R600_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16)
+# define R600_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17)
+# define R600_FG_ALPHA_FUNC_CFG_3_OF_6 (1 << 17)
-# define R300_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20)
-# define R300_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20)
+# define R600_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20)
+# define R600_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20)
# define R500_FG_ALPHA_FUNC_OFFSET_DISABLE (0 << 24)
# define R500_FG_ALPHA_FUNC_OFFSET_ENABLE (1 << 24) /* Not supported in R520 */
/* Fog: Where does the depth come from? */
-#define R300_FG_DEPTH_SRC 0x4bd8
-# define R300_FG_DEPTH_SRC_SCAN (0 << 0)
-# define R300_FG_DEPTH_SRC_SHADER (1 << 0)
+#define R600_FG_DEPTH_SRC 0x4bd8
+# define R600_FG_DEPTH_SRC_SCAN (0 << 0)
+# define R600_FG_DEPTH_SRC_SHADER (1 << 0)
/* Fog: Alpha Compare Value */
#define R500_FG_ALPHA_VALUE 0x4be0
/* gap */
/* Fragment program parameters in 7.16 floating point */
-#define R300_PFS_PARAM_0_X 0x4C00
-#define R300_PFS_PARAM_0_Y 0x4C04
-#define R300_PFS_PARAM_0_Z 0x4C08
-#define R300_PFS_PARAM_0_W 0x4C0C
+#define R600_PFS_PARAM_0_X 0x4C00
+#define R600_PFS_PARAM_0_Y 0x4C04
+#define R600_PFS_PARAM_0_Z 0x4C08
+#define R600_PFS_PARAM_0_W 0x4C0C
/* last consts */
-#define R300_PFS_PARAM_31_X 0x4DF0
-#define R300_PFS_PARAM_31_Y 0x4DF4
-#define R300_PFS_PARAM_31_Z 0x4DF8
-#define R300_PFS_PARAM_31_W 0x4DFC
+#define R600_PFS_PARAM_31_X 0x4DF0
+#define R600_PFS_PARAM_31_Y 0x4DF4
+#define R600_PFS_PARAM_31_Z 0x4DF8
+#define R600_PFS_PARAM_31_W 0x4DFC
/* Unpipelined. */
-#define R300_RB3D_CCTL 0x4e00
-# define R300_RB3D_CCTL_NUM_MULTIWRITES_1_BUFFER (0 << 5)
-# define R300_RB3D_CCTL_NUM_MULTIWRITES_2_BUFFERS (1 << 5)
-# define R300_RB3D_CCTL_NUM_MULTIWRITES_3_BUFFERS (2 << 5)
-# define R300_RB3D_CCTL_NUM_MULTIWRITES_4_BUFFERS (3 << 5)
-# define R300_RB3D_CCTL_CLRCMP_FLIPE_DISABLE (0 << 7)
-# define R300_RB3D_CCTL_CLRCMP_FLIPE_ENABLE (1 << 7)
-# define R300_RB3D_CCTL_AA_COMPRESSION_DISABLE (0 << 9)
-# define R300_RB3D_CCTL_AA_COMPRESSION_ENABLE (1 << 9)
-# define R300_RB3D_CCTL_CMASK_DISABLE (0 << 10)
-# define R300_RB3D_CCTL_CMASK_ENABLE (1 << 10)
+#define R600_RB3D_CCTL 0x4e00
+# define R600_RB3D_CCTL_NUM_MULTIWRITES_1_BUFFER (0 << 5)
+# define R600_RB3D_CCTL_NUM_MULTIWRITES_2_BUFFERS (1 << 5)
+# define R600_RB3D_CCTL_NUM_MULTIWRITES_3_BUFFERS (2 << 5)
+# define R600_RB3D_CCTL_NUM_MULTIWRITES_4_BUFFERS (3 << 5)
+# define R600_RB3D_CCTL_CLRCMP_FLIPE_DISABLE (0 << 7)
+# define R600_RB3D_CCTL_CLRCMP_FLIPE_ENABLE (1 << 7)
+# define R600_RB3D_CCTL_AA_COMPRESSION_DISABLE (0 << 9)
+# define R600_RB3D_CCTL_AA_COMPRESSION_ENABLE (1 << 9)
+# define R600_RB3D_CCTL_CMASK_DISABLE (0 << 10)
+# define R600_RB3D_CCTL_CMASK_ENABLE (1 << 10)
/* reserved */
-# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_DISABLE (0 << 12)
-# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE (1 << 12)
-# define R300_RB3D_CCTL_WRITE_COMPRESSION_ENABLE (0 << 13)
-# define R300_RB3D_CCTL_WRITE_COMPRESSION_DISABLE (1 << 13)
-# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_DISABLE (0 << 14)
-# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE (1 << 14)
+# define R600_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_DISABLE (0 << 12)
+# define R600_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE (1 << 12)
+# define R600_RB3D_CCTL_WRITE_COMPRESSION_ENABLE (0 << 13)
+# define R600_RB3D_CCTL_WRITE_COMPRESSION_DISABLE (1 << 13)
+# define R600_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_DISABLE (0 << 14)
+# define R600_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE (1 << 14)
/* Notes:
* function (both registers are always set up completely in any case)
* - Most blend flags are simply copied from R200 and not tested yet
*/
-#define R300_RB3D_CBLEND 0x4E04
-#define R300_RB3D_ABLEND 0x4E08
+#define R600_RB3D_CBLEND 0x4E04
+#define R600_RB3D_ABLEND 0x4E08
/* the following only appear in CBLEND */
-# define R300_ALPHA_BLEND_ENABLE (1 << 0)
-# define R300_SEPARATE_ALPHA_ENABLE (1 << 1)
-# define R300_READ_ENABLE (1 << 2)
-# define R300_DISCARD_SRC_PIXELS_DIS (0 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0 (1 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_0 (2 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0 (3 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1 (4 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_1 (5 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1 (6 << 3)
+# define R600_ALPHA_BLEND_ENABLE (1 << 0)
+# define R600_SEPARATE_ALPHA_ENABLE (1 << 1)
+# define R600_READ_ENABLE (1 << 2)
+# define R600_DISCARD_SRC_PIXELS_DIS (0 << 3)
+# define R600_DISCARD_SRC_PIXELS_SRC_ALPHA_0 (1 << 3)
+# define R600_DISCARD_SRC_PIXELS_SRC_COLOR_0 (2 << 3)
+# define R600_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0 (3 << 3)
+# define R600_DISCARD_SRC_PIXELS_SRC_ALPHA_1 (4 << 3)
+# define R600_DISCARD_SRC_PIXELS_SRC_COLOR_1 (5 << 3)
+# define R600_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1 (6 << 3)
/* the following are shared between CBLEND and ABLEND */
-# define R300_FCN_MASK (3 << 12)
-# define R300_COMB_FCN_ADD_CLAMP (0 << 12)
-# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
-# define R300_COMB_FCN_SUB_CLAMP (2 << 12)
-# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
-# define R300_COMB_FCN_MIN (4 << 12)
-# define R300_COMB_FCN_MAX (5 << 12)
-# define R300_COMB_FCN_RSUB_CLAMP (6 << 12)
-# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12)
-# define R300_BLEND_GL_ZERO (32)
-# define R300_BLEND_GL_ONE (33)
-# define R300_BLEND_GL_SRC_COLOR (34)
-# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35)
-# define R300_BLEND_GL_DST_COLOR (36)
-# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37)
-# define R300_BLEND_GL_SRC_ALPHA (38)
-# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)
-# define R300_BLEND_GL_DST_ALPHA (40)
-# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41)
-# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42)
-# define R300_BLEND_GL_CONST_COLOR (43)
-# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44)
-# define R300_BLEND_GL_CONST_ALPHA (45)
-# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)
-# define R300_BLEND_MASK (63)
-# define R300_SRC_BLEND_SHIFT (16)
-# define R300_DST_BLEND_SHIFT (24)
+# define R600_FCN_MASK (3 << 12)
+# define R600_COMB_FCN_ADD_CLAMP (0 << 12)
+# define R600_COMB_FCN_ADD_NOCLAMP (1 << 12)
+# define R600_COMB_FCN_SUB_CLAMP (2 << 12)
+# define R600_COMB_FCN_SUB_NOCLAMP (3 << 12)
+# define R600_COMB_FCN_MIN (4 << 12)
+# define R600_COMB_FCN_MAX (5 << 12)
+# define R600_COMB_FCN_RSUB_CLAMP (6 << 12)
+# define R600_COMB_FCN_RSUB_NOCLAMP (7 << 12)
+# define R600_BLEND_GL_ZERO (32)
+# define R600_BLEND_GL_ONE (33)
+# define R600_BLEND_GL_SRC_COLOR (34)
+# define R600_BLEND_GL_ONE_MINUS_SRC_COLOR (35)
+# define R600_BLEND_GL_DST_COLOR (36)
+# define R600_BLEND_GL_ONE_MINUS_DST_COLOR (37)
+# define R600_BLEND_GL_SRC_ALPHA (38)
+# define R600_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)
+# define R600_BLEND_GL_DST_ALPHA (40)
+# define R600_BLEND_GL_ONE_MINUS_DST_ALPHA (41)
+# define R600_BLEND_GL_SRC_ALPHA_SATURATE (42)
+# define R600_BLEND_GL_CONST_COLOR (43)
+# define R600_BLEND_GL_ONE_MINUS_CONST_COLOR (44)
+# define R600_BLEND_GL_CONST_ALPHA (45)
+# define R600_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)
+# define R600_BLEND_MASK (63)
+# define R600_SRC_BLEND_SHIFT (16)
+# define R600_DST_BLEND_SHIFT (24)
/* Constant color used by the blender. Pipelined through the blender.
* Note: For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__BLUE,
* RB3D_CONSTANT_COLOR_GB__GREEN, etc. instead.
*/
-#define R300_RB3D_BLEND_COLOR 0x4E10
+#define R600_RB3D_BLEND_COLOR 0x4E10
/* 3D Color Channel Mask. If all the channels used in the current color format
#define RB3D_CLRCMP_MSK 0x4e24
/* Color Buffer Address Offset of multibuffer 0. Unpipelined. */
-#define R300_RB3D_COLOROFFSET0 0x4E28
-# define R300_COLOROFFSET_MASK 0xFFFFFFE0
+#define R600_RB3D_COLOROFFSET0 0x4E28
+# define R600_COLOROFFSET_MASK 0xFFFFFFE0
/* Color Buffer Address Offset of multibuffer 1. Unpipelined. */
-#define R300_RB3D_COLOROFFSET1 0x4E2C
+#define R600_RB3D_COLOROFFSET1 0x4E2C
/* Color Buffer Address Offset of multibuffer 2. Unpipelined. */
-#define R300_RB3D_COLOROFFSET2 0x4E30
+#define R600_RB3D_COLOROFFSET2 0x4E30
/* Color Buffer Address Offset of multibuffer 3. Unpipelined. */
-#define R300_RB3D_COLOROFFSET3 0x4E34
+#define R600_RB3D_COLOROFFSET3 0x4E34
/* Color buffer format and tiling control for all the multibuffers and the
* pitch of multibuffer 0 to 3. Unpipelined. The cache must be empty before any
* Bit 17: 4x2 tiles
* Bit 18: Extremely weird tile like, but some pixels duplicated?
*/
-#define R300_RB3D_COLORPITCH0 0x4E38
-# define R300_COLORPITCH_MASK 0x00003FFE
-# define R300_COLOR_TILE_DISABLE (0 << 16)
-# define R300_COLOR_TILE_ENABLE (1 << 16)
-# define R300_COLOR_MICROTILE_DISABLE (0 << 17)
-# define R300_COLOR_MICROTILE_ENABLE (1 << 17)
-# define R300_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */
-# define R300_COLOR_ENDIAN_NO_SWAP (0 << 19)
-# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 19)
-# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 19)
-# define R300_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19)
+#define R600_RB3D_COLORPITCH0 0x4E38
+# define R600_COLORPITCH_MASK 0x00003FFE
+# define R600_COLOR_TILE_DISABLE (0 << 16)
+# define R600_COLOR_TILE_ENABLE (1 << 16)
+# define R600_COLOR_MICROTILE_DISABLE (0 << 17)
+# define R600_COLOR_MICROTILE_ENABLE (1 << 17)
+# define R600_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */
+# define R600_COLOR_ENDIAN_NO_SWAP (0 << 19)
+# define R600_COLOR_ENDIAN_WORD_SWAP (1 << 19)
+# define R600_COLOR_ENDIAN_DWORD_SWAP (2 << 19)
+# define R600_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19)
# define R500_COLOR_FORMAT_ARGB10101010 (0 << 21)
# define R500_COLOR_FORMAT_UV1010 (1 << 21)
# define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */
-# define R300_COLOR_FORMAT_ARGB1555 (3 << 21)
-# define R300_COLOR_FORMAT_RGB565 (4 << 21)
+# define R600_COLOR_FORMAT_ARGB1555 (3 << 21)
+# define R600_COLOR_FORMAT_RGB565 (4 << 21)
# define R500_COLOR_FORMAT_ARGB2101010 (5 << 21)
-# define R300_COLOR_FORMAT_ARGB8888 (6 << 21)
-# define R300_COLOR_FORMAT_ARGB32323232 (7 << 21)
+# define R600_COLOR_FORMAT_ARGB8888 (6 << 21)
+# define R600_COLOR_FORMAT_ARGB32323232 (7 << 21)
/* reserved */
-# define R300_COLOR_FORMAT_I8 (9 << 21)
-# define R300_COLOR_FORMAT_ARGB16161616 (10 << 21)
-# define R300_COLOR_FORMAT_VYUY (11 << 21)
-# define R300_COLOR_FORMAT_YVYU (12 << 21)
-# define R300_COLOR_FORMAT_UV88 (13 << 21)
+# define R600_COLOR_FORMAT_I8 (9 << 21)
+# define R600_COLOR_FORMAT_ARGB16161616 (10 << 21)
+# define R600_COLOR_FORMAT_VYUY (11 << 21)
+# define R600_COLOR_FORMAT_YVYU (12 << 21)
+# define R600_COLOR_FORMAT_UV88 (13 << 21)
# define R500_COLOR_FORMAT_I10 (14 << 21)
-# define R300_COLOR_FORMAT_ARGB4444 (15 << 21)
-#define R300_RB3D_COLORPITCH1 0x4E3C
-#define R300_RB3D_COLORPITCH2 0x4E40
-#define R300_RB3D_COLORPITCH3 0x4E44
+# define R600_COLOR_FORMAT_ARGB4444 (15 << 21)
+#define R600_RB3D_COLORPITCH1 0x4E3C
+#define R600_RB3D_COLORPITCH2 0x4E40
+#define R600_RB3D_COLORPITCH3 0x4E44
/* gap */
*
* Set to 0A before 3D operations, set to 02 afterwards.
*/
-#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT (0 << 0)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT_1 (1 << 0)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D (2 << 0)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D_1 (3 << 0)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT (0 << 2)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT_1 (1 << 2)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS (2 << 2)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS_1 (3 << 2)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_NO_SIGNAL (0 << 4)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL (1 << 4)
-
-#define R300_RB3D_DITHER_CTL 0x4E50
-# define R300_RB3D_DITHER_CTL_DITHER_MODE_TRUNCATE (0 << 0)
-# define R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND (1 << 0)
-# define R300_RB3D_DITHER_CTL_DITHER_MODE_LUT (2 << 0)
+#define R600_RB3D_DSTCACHE_CTLSTAT 0x4e4c
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT (0 << 0)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT_1 (1 << 0)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D (2 << 0)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D_1 (3 << 0)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT (0 << 2)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT_1 (1 << 2)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS (2 << 2)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS_1 (3 << 2)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_NO_SIGNAL (0 << 4)
+# define R600_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL (1 << 4)
+
+#define R600_RB3D_DITHER_CTL 0x4E50
+# define R600_RB3D_DITHER_CTL_DITHER_MODE_TRUNCATE (0 << 0)
+# define R600_RB3D_DITHER_CTL_DITHER_MODE_ROUND (1 << 0)
+# define R600_RB3D_DITHER_CTL_DITHER_MODE_LUT (2 << 0)
/* reserved */
-# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_TRUNCATE (0 << 2)
-# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_ROUND (1 << 2)
-# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT (2 << 2)
+# define R600_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_TRUNCATE (0 << 2)
+# define R600_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_ROUND (1 << 2)
+# define R600_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT (2 << 2)
/* reserved */
/* Resolve buffer destination address. The cache must be empty before changing
* this register if the cb is in resolve mode. Unpipelined
*/
-#define R300_RB3D_AARESOLVE_OFFSET 0x4e80
-# define R300_RB3D_AARESOLVE_OFFSET_SHIFT 5
-# define R300_RB3D_AARESOLVE_OFFSET_MASK 0xffffffe0 /* At least according to the calculations of Christoph Brill */
+#define R600_RB3D_AARESOLVE_OFFSET 0x4e80
+# define R600_RB3D_AARESOLVE_OFFSET_SHIFT 5
+# define R600_RB3D_AARESOLVE_OFFSET_MASK 0xffffffe0 /* At least according to the calculations of Christoph Brill */
/* Resolve Buffer Pitch and Tiling Control. The cache must be empty before
* changing this register if the cb is in resolve mode. Unpipelined
*/
-#define R300_RB3D_AARESOLVE_PITCH 0x4e84
-# define R300_RB3D_AARESOLVE_PITCH_SHIFT 1
-# define R300_RB3D_AARESOLVE_PITCH_MASK 0x00003ffe /* At least according to the calculations of Christoph Brill */
+#define R600_RB3D_AARESOLVE_PITCH 0x4e84
+# define R600_RB3D_AARESOLVE_PITCH_SHIFT 1
+# define R600_RB3D_AARESOLVE_PITCH_MASK 0x00003ffe /* At least according to the calculations of Christoph Brill */
/* Resolve Buffer Control. Unpipelined */
-#define R300_RB3D_AARESOLVE_CTL 0x4e88
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_NORMAL (0 << 0)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE (1 << 0)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_10 (0 << 1)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_22 (1 << 1)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2)
+#define R600_RB3D_AARESOLVE_CTL 0x4e88
+# define R600_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_NORMAL (0 << 0)
+# define R600_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE (1 << 0)
+# define R600_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_10 (0 << 1)
+# define R600_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_22 (1 << 1)
+# define R600_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2)
+# define R600_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2)
/* Discard src pixels less than or equal to threshold. */
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000
/* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */
-#define R300_RB3D_ROPCNTL 0x4e18
-# define R300_RB3D_ROPCNTL_ROP_ENABLE 0x00000004
-# define R300_RB3D_ROPCNTL_ROP_MASK (15 << 8)
-# define R300_RB3D_ROPCNTL_ROP_SHIFT 8
+#define R600_RB3D_ROPCNTL 0x4e18
+# define R600_RB3D_ROPCNTL_ROP_ENABLE 0x00000004
+# define R600_RB3D_ROPCNTL_ROP_MASK (15 << 8)
+# define R600_RB3D_ROPCNTL_ROP_SHIFT 8
/* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */
-#define R300_RB3D_CLRCMP_FLIPE 0x4e1c
+#define R600_RB3D_CLRCMP_FLIPE 0x4e1c
/* Sets the fifo sizes */
#define R500_RB3D_FIFO_SIZE 0x4ef4
* for this.
* Bit (1<<8) is the "test" bit. so plain write is 6 - vd
*/
-#define R300_ZB_CNTL 0x4F00
-# define R300_STENCIL_ENABLE (1 << 0)
-# define R300_Z_ENABLE (1 << 1)
-# define R300_Z_WRITE_ENABLE (1 << 2)
-# define R300_Z_SIGNED_COMPARE (1 << 3)
-# define R300_STENCIL_FRONT_BACK (1 << 4)
-
-#define R300_ZB_ZSTENCILCNTL 0x4f04
+#define R600_ZB_CNTL 0x4F00
+# define R600_STENCIL_ENABLE (1 << 0)
+# define R600_Z_ENABLE (1 << 1)
+# define R600_Z_WRITE_ENABLE (1 << 2)
+# define R600_Z_SIGNED_COMPARE (1 << 3)
+# define R600_STENCIL_FRONT_BACK (1 << 4)
+
+#define R600_ZB_ZSTENCILCNTL 0x4f04
/* functions */
-# define R300_ZS_NEVER 0
-# define R300_ZS_LESS 1
-# define R300_ZS_LEQUAL 2
-# define R300_ZS_EQUAL 3
-# define R300_ZS_GEQUAL 4
-# define R300_ZS_GREATER 5
-# define R300_ZS_NOTEQUAL 6
-# define R300_ZS_ALWAYS 7
-# define R300_ZS_MASK 7
+# define R600_ZS_NEVER 0
+# define R600_ZS_LESS 1
+# define R600_ZS_LEQUAL 2
+# define R600_ZS_EQUAL 3
+# define R600_ZS_GEQUAL 4
+# define R600_ZS_GREATER 5
+# define R600_ZS_NOTEQUAL 6
+# define R600_ZS_ALWAYS 7
+# define R600_ZS_MASK 7
/* operations */
-# define R300_ZS_KEEP 0
-# define R300_ZS_ZERO 1
-# define R300_ZS_REPLACE 2
-# define R300_ZS_INCR 3
-# define R300_ZS_DECR 4
-# define R300_ZS_INVERT 5
-# define R300_ZS_INCR_WRAP 6
-# define R300_ZS_DECR_WRAP 7
-# define R300_Z_FUNC_SHIFT 0
+# define R600_ZS_KEEP 0
+# define R600_ZS_ZERO 1
+# define R600_ZS_REPLACE 2
+# define R600_ZS_INCR 3
+# define R600_ZS_DECR 4
+# define R600_ZS_INVERT 5
+# define R600_ZS_INCR_WRAP 6
+# define R600_ZS_DECR_WRAP 7
+# define R600_Z_FUNC_SHIFT 0
/* front and back refer to operations done for front
and back faces, i.e. separate stencil function support */
-# define R300_S_FRONT_FUNC_SHIFT 3
-# define R300_S_FRONT_SFAIL_OP_SHIFT 6
-# define R300_S_FRONT_ZPASS_OP_SHIFT 9
-# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
-# define R300_S_BACK_FUNC_SHIFT 15
-# define R300_S_BACK_SFAIL_OP_SHIFT 18
-# define R300_S_BACK_ZPASS_OP_SHIFT 21
-# define R300_S_BACK_ZFAIL_OP_SHIFT 24
-
-#define R300_ZB_STENCILREFMASK 0x4f08
-# define R300_STENCILREF_SHIFT 0
-# define R300_STENCILREF_MASK 0x000000ff
-# define R300_STENCILMASK_SHIFT 8
-# define R300_STENCILMASK_MASK 0x0000ff00
-# define R300_STENCILWRITEMASK_SHIFT 16
-# define R300_STENCILWRITEMASK_MASK 0x00ff0000
+# define R600_S_FRONT_FUNC_SHIFT 3
+# define R600_S_FRONT_SFAIL_OP_SHIFT 6
+# define R600_S_FRONT_ZPASS_OP_SHIFT 9
+# define R600_S_FRONT_ZFAIL_OP_SHIFT 12
+# define R600_S_BACK_FUNC_SHIFT 15
+# define R600_S_BACK_SFAIL_OP_SHIFT 18
+# define R600_S_BACK_ZPASS_OP_SHIFT 21
+# define R600_S_BACK_ZFAIL_OP_SHIFT 24
+
+#define R600_ZB_STENCILREFMASK 0x4f08
+# define R600_STENCILREF_SHIFT 0
+# define R600_STENCILREF_MASK 0x000000ff
+# define R600_STENCILMASK_SHIFT 8
+# define R600_STENCILMASK_MASK 0x0000ff00
+# define R600_STENCILWRITEMASK_SHIFT 16
+# define R600_STENCILWRITEMASK_MASK 0x00ff0000
/* gap */
-#define R300_ZB_FORMAT 0x4f10
-# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
-# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
-# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
+#define R600_ZB_FORMAT 0x4f10
+# define R600_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
+# define R600_DEPTHFORMAT_16BIT_13E3 (1 << 0)
+# define R600_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
/* reserved up to (15 << 0) */
-# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
-# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
+# define R600_INVERT_13E3_LEADING_ONES (0 << 4)
+# define R600_INVERT_13E3_LEADING_ZEROS (1 << 4)
-#define R300_ZB_ZTOP 0x4F14
-# define R300_ZTOP_DISABLE (0 << 0)
-# define R300_ZTOP_ENABLE (1 << 0)
+#define R600_ZB_ZTOP 0x4F14
+# define R600_ZTOP_DISABLE (0 << 0)
+# define R600_ZTOP_ENABLE (1 << 0)
/* gap */
-#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
-
-#define R300_ZB_BW_CNTL 0x4f1c
-# define R300_HIZ_DISABLE (0 << 0)
-# define R300_HIZ_ENABLE (1 << 0)
-# define R300_HIZ_MIN (0 << 1)
-# define R300_HIZ_MAX (1 << 1)
-# define R300_FAST_FILL_DISABLE (0 << 2)
-# define R300_FAST_FILL_ENABLE (1 << 2)
-# define R300_RD_COMP_DISABLE (0 << 3)
-# define R300_RD_COMP_ENABLE (1 << 3)
-# define R300_WR_COMP_DISABLE (0 << 4)
-# define R300_WR_COMP_ENABLE (1 << 4)
-# define R300_ZB_CB_CLEAR_RMW (0 << 5)
-# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
-# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
-# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
+#define R600_ZB_ZCACHE_CTLSTAT 0x4f18
+# define R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
+# define R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
+# define R600_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
+# define R600_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
+# define R600_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
+# define R600_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
+
+#define R600_ZB_BW_CNTL 0x4f1c
+# define R600_HIZ_DISABLE (0 << 0)
+# define R600_HIZ_ENABLE (1 << 0)
+# define R600_HIZ_MIN (0 << 1)
+# define R600_HIZ_MAX (1 << 1)
+# define R600_FAST_FILL_DISABLE (0 << 2)
+# define R600_FAST_FILL_ENABLE (1 << 2)
+# define R600_RD_COMP_DISABLE (0 << 3)
+# define R600_RD_COMP_ENABLE (1 << 3)
+# define R600_WR_COMP_DISABLE (0 << 4)
+# define R600_WR_COMP_ENABLE (1 << 4)
+# define R600_ZB_CB_CLEAR_RMW (0 << 5)
+# define R600_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
+# define R600_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
+# define R600_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
/* Z Buffer Address Offset.
* Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
*/
-#define R300_ZB_DEPTHOFFSET 0x4f20
+#define R600_ZB_DEPTHOFFSET 0x4f20
/* Z Buffer Pitch and Endian Control */
-#define R300_ZB_DEPTHPITCH 0x4f24
-# define R300_DEPTHPITCH_MASK 0x00003FFC
-# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
-# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
-# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
-# define R300_DEPTHMICROTILE_TILED (1 << 17)
-# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
-# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
-# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
-# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
-# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
+#define R600_ZB_DEPTHPITCH 0x4f24
+# define R600_DEPTHPITCH_MASK 0x00003FFC
+# define R600_DEPTHMACROTILE_DISABLE (0 << 16)
+# define R600_DEPTHMACROTILE_ENABLE (1 << 16)
+# define R600_DEPTHMICROTILE_LINEAR (0 << 17)
+# define R600_DEPTHMICROTILE_TILED (1 << 17)
+# define R600_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
+# define R600_DEPTHENDIAN_NO_SWAP (0 << 18)
+# define R600_DEPTHENDIAN_WORD_SWAP (1 << 18)
+# define R600_DEPTHENDIAN_DWORD_SWAP (2 << 18)
+# define R600_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
/* Z Buffer Clear Value */
-#define R300_ZB_DEPTHCLEARVALUE 0x4f28
+#define R600_ZB_DEPTHCLEARVALUE 0x4f28
/* Hierarchical Z Memory Offset */
-#define R300_ZB_HIZ_OFFSET 0x4f44
+#define R600_ZB_HIZ_OFFSET 0x4f44
/* Hierarchical Z Write Index */
-#define R300_ZB_HIZ_WRINDEX 0x4f48
+#define R600_ZB_HIZ_WRINDEX 0x4f48
/* Hierarchical Z Data */
-#define R300_ZB_HIZ_DWORD 0x4f4c
+#define R600_ZB_HIZ_DWORD 0x4f4c
/* Hierarchical Z Read Index */
-#define R300_ZB_HIZ_RDINDEX 0x4f50
+#define R600_ZB_HIZ_RDINDEX 0x4f50
/* Hierarchical Z Pitch */
-#define R300_ZB_HIZ_PITCH 0x4f54
+#define R600_ZB_HIZ_PITCH 0x4f54
/* Z Buffer Z Pass Counter Data */
-#define R300_ZB_ZPASS_DATA 0x4f58
+#define R600_ZB_ZPASS_DATA 0x4f58
/* Z Buffer Z Pass Counter Address */
-#define R300_ZB_ZPASS_ADDR 0x4f5c
+#define R600_ZB_ZPASS_ADDR 0x4f5c
/* Depth buffer X and Y coordinate offset */
-#define R300_ZB_DEPTHXY_OFFSET 0x4f60
-# define R300_DEPTHX_OFFSET_SHIFT 1
-# define R300_DEPTHX_OFFSET_MASK 0x000007FE
-# define R300_DEPTHY_OFFSET_SHIFT 17
-# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
+#define R600_ZB_DEPTHXY_OFFSET 0x4f60
+# define R600_DEPTHX_OFFSET_SHIFT 1
+# define R600_DEPTHX_OFFSET_MASK 0x000007FE
+# define R600_DEPTHY_OFFSET_SHIFT 17
+# define R600_DEPTHY_OFFSET_MASK 0x07FE0000
/* Sets the fifo sizes */
#define R500_ZB_FIFO_SIZE 0x4fd0
# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
/* Stencil Reference Value and Mask for backfacing quads */
-/* R300_ZB_STENCILREFMASK handles front face */
+/* R600_ZB_STENCILREFMASK handles front face */
#define R500_ZB_STENCILREFMASK_BF 0x4fd4
# define R500_STENCILREF_SHIFT 0
# define R500_STENCILREF_MASK 0x000000ff
/* BEGIN: Packet 3 commands */
/* A primitive emission dword. */
-#define R300_PRIM_TYPE_NONE (0 << 0)
-#define R300_PRIM_TYPE_POINT (1 << 0)
-#define R300_PRIM_TYPE_LINE (2 << 0)
-#define R300_PRIM_TYPE_LINE_STRIP (3 << 0)
-#define R300_PRIM_TYPE_TRI_LIST (4 << 0)
-#define R300_PRIM_TYPE_TRI_FAN (5 << 0)
-#define R300_PRIM_TYPE_TRI_STRIP (6 << 0)
-#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0)
-#define R300_PRIM_TYPE_RECT_LIST (8 << 0)
-#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
-#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
+#define R600_PRIM_TYPE_NONE (0 << 0)
+#define R600_PRIM_TYPE_POINT (1 << 0)
+#define R600_PRIM_TYPE_LINE (2 << 0)
+#define R600_PRIM_TYPE_LINE_STRIP (3 << 0)
+#define R600_PRIM_TYPE_TRI_LIST (4 << 0)
+#define R600_PRIM_TYPE_TRI_FAN (5 << 0)
+#define R600_PRIM_TYPE_TRI_STRIP (6 << 0)
+#define R600_PRIM_TYPE_TRI_TYPE2 (7 << 0)
+#define R600_PRIM_TYPE_RECT_LIST (8 << 0)
+#define R600_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
+#define R600_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
/* GUESS (based on r200) */
-#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0)
-#define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
-#define R300_PRIM_TYPE_QUADS (13 << 0)
-#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
-#define R300_PRIM_TYPE_POLYGON (15 << 0)
-#define R300_PRIM_TYPE_MASK 0xF
-#define R300_PRIM_WALK_IND (1 << 4)
-#define R300_PRIM_WALK_LIST (2 << 4)
-#define R300_PRIM_WALK_RING (3 << 4)
-#define R300_PRIM_WALK_MASK (3 << 4)
+#define R600_PRIM_TYPE_POINT_SPRITES (11 << 0)
+#define R600_PRIM_TYPE_LINE_LOOP (12 << 0)
+#define R600_PRIM_TYPE_QUADS (13 << 0)
+#define R600_PRIM_TYPE_QUAD_STRIP (14 << 0)
+#define R600_PRIM_TYPE_POLYGON (15 << 0)
+#define R600_PRIM_TYPE_MASK 0xF
+#define R600_PRIM_WALK_IND (1 << 4)
+#define R600_PRIM_WALK_LIST (2 << 4)
+#define R600_PRIM_WALK_RING (3 << 4)
+#define R600_PRIM_WALK_MASK (3 << 4)
/* GUESS (based on r200) */
-#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)
-#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)
-#define R300_PRIM_NUM_VERTICES_SHIFT 16
-#define R300_PRIM_NUM_VERTICES_MASK 0xffff
+#define R600_PRIM_COLOR_ORDER_BGRA (0 << 6)
+#define R600_PRIM_COLOR_ORDER_RGBA (1 << 6)
+#define R600_PRIM_NUM_VERTICES_SHIFT 16
+#define R600_PRIM_NUM_VERTICES_MASK 0xffff
# define R500_TEX_SEM_ACQUIRE (1 << 25)
# define R500_TEX_IGNORE_UNCOVERED (1 << 26)
# define R500_TEX_UNSCALED (1 << 27)
-#define R300_US_W_FMT 0x46b4
-# define R300_W_FMT_W0 (0 << 0)
-# define R300_W_FMT_W24 (1 << 0)
-# define R300_W_FMT_W24FP (2 << 0)
-# define R300_W_SRC_US (0 << 2)
-# define R300_W_SRC_RAS (1 << 2)
+#define R600_US_W_FMT 0x46b4
+# define R600_W_FMT_W0 (0 << 0)
+# define R600_W_FMT_W24 (1 << 0)
+# define R600_W_FMT_W24FP (2 << 0)
+# define R600_W_SRC_US (0 << 2)
+# define R600_W_SRC_RAS (1 << 2)
/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
* 0. VAP_VTX_FMT: The first parameter is not written to hardware
* 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
*/
-#define R300_PACKET3_3D_DRAW_VBUF 0x00002800
+#define R600_PACKET3_3D_DRAW_VBUF 0x00002800
/* Draw a primitive from immediate vertices in this packet
* Up to 16382 dwords:
* 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
* 2 to end: Up to 16380 dwords of vertex data.
*/
-#define R300_PACKET3_3D_DRAW_IMMD 0x00002900
+#define R600_PACKET3_3D_DRAW_IMMD 0x00002900
/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR and
* immediate vertices in this packet
* 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
* 2 to end: Up to 16380 dwords of vertex data.
*/
-#define R300_PACKET3_3D_DRAW_INDX 0x00002A00
+#define R600_PACKET3_3D_DRAW_INDX 0x00002A00
/* Specify the full set of vertex arrays as (address, stride).
* Note that if the total number of arrays is odd, the third dword of
* the last block is omitted.
*/
-#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00
+#define R600_PACKET3_3D_LOAD_VBPNTR 0x00002F00
-#define R300_PACKET3_INDX_BUFFER 0x00003300
-# define R300_INDX_BUFFER_DST_SHIFT 0
-# define R300_INDX_BUFFER_SKIP_SHIFT 16
-# define R300_INDX_BUFFER_ONE_REG_WR (1<<31)
+#define R600_PACKET3_INDX_BUFFER 0x00003300
+# define R600_INDX_BUFFER_DST_SHIFT 0
+# define R600_INDX_BUFFER_SKIP_SHIFT 16
+# define R600_INDX_BUFFER_ONE_REG_WR (1<<31)
-/* Same as R300_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */
-#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400
-/* Same as R300_PACKET3_3D_DRAW_IMMD but without VAP_VTX_FMT */
-#define R300_PACKET3_3D_DRAW_IMMD_2 0x00003500
-/* Same as R300_PACKET3_3D_DRAW_INDX but without VAP_VTX_FMT */
-#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600
+/* Same as R600_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */
+#define R600_PACKET3_3D_DRAW_VBUF_2 0x00003400
+/* Same as R600_PACKET3_3D_DRAW_IMMD but without VAP_VTX_FMT */
+#define R600_PACKET3_3D_DRAW_IMMD_2 0x00003500
+/* Same as R600_PACKET3_3D_DRAW_INDX but without VAP_VTX_FMT */
+#define R600_PACKET3_3D_DRAW_INDX_2 0x00003600
/* Clears a portion of hierachical Z RAM
* 3 dword parameters
* 1. COUNT: 13:0 (max is 0x3FFF)
* 2. CLEAR_VALUE: Value to write into HIZ RAM.
*/
-#define R300_PACKET3_3D_CLEAR_HIZ 0x00003700
+#define R600_PACKET3_3D_CLEAR_HIZ 0x00003700
/* Draws a set of primitives using vertex buffers pointed by the state data.
* At least 2 Parameters:
* 0. VAP_VF_CNTL: The first parameter is a standard primitive emission dword.
* 2 to end: Data or indices (see other 3D_DRAW_* packets for details)
*/
-#define R300_PACKET3_3D_DRAW_128 0x00003900
+#define R600_PACKET3_3D_DRAW_128 0x00003900
/* END: Packet 3 commands */
/* Color formats for 2d packets
*/
-#define R300_CP_COLOR_FORMAT_CI8 2
-#define R300_CP_COLOR_FORMAT_ARGB1555 3
-#define R300_CP_COLOR_FORMAT_RGB565 4
-#define R300_CP_COLOR_FORMAT_ARGB8888 6
-#define R300_CP_COLOR_FORMAT_RGB332 7
-#define R300_CP_COLOR_FORMAT_RGB8 9
-#define R300_CP_COLOR_FORMAT_ARGB4444 15
+#define R600_CP_COLOR_FORMAT_CI8 2
+#define R600_CP_COLOR_FORMAT_ARGB1555 3
+#define R600_CP_COLOR_FORMAT_RGB565 4
+#define R600_CP_COLOR_FORMAT_ARGB8888 6
+#define R600_CP_COLOR_FORMAT_RGB332 7
+#define R600_CP_COLOR_FORMAT_RGB8 9
+#define R600_CP_COLOR_FORMAT_ARGB4444 15
/*
* CP type-3 packets
*/
-#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
+#define R600_CP_CMD_BITBLT_MULTI 0xC0009B00
-#endif /* _R300_REG_H */
+#endif /* _R600_REG_H */
/* *INDENT-ON* */
/**
* \file
*
- * \brief R300 Render (Vertex Buffer Implementation)
+ * \brief R600 Render (Vertex Buffer Implementation)
*
* The immediate implementation has been removed from CVS in favor of the vertex
* buffer implementation.
extern int future_hw_tcl_on;
/**
- * \brief Convert a OpenGL primitive type into a R300 primitive type.
+ * \brief Convert a OpenGL primitive type into a R600 primitive type.
*/
-int r300PrimitiveType(r300ContextPtr rmesa, int prim)
+int r600PrimitiveType(r600ContextPtr rmesa, int prim)
{
switch (prim & PRIM_MODE_MASK) {
case GL_POINTS:
- return R300_VAP_VF_CNTL__PRIM_POINTS;
+ return R600_VAP_VF_CNTL__PRIM_POINTS;
break;
case GL_LINES:
- return R300_VAP_VF_CNTL__PRIM_LINES;
+ return R600_VAP_VF_CNTL__PRIM_LINES;
break;
case GL_LINE_STRIP:
- return R300_VAP_VF_CNTL__PRIM_LINE_STRIP;
+ return R600_VAP_VF_CNTL__PRIM_LINE_STRIP;
break;
case GL_LINE_LOOP:
- return R300_VAP_VF_CNTL__PRIM_LINE_LOOP;
+ return R600_VAP_VF_CNTL__PRIM_LINE_LOOP;
break;
case GL_TRIANGLES:
- return R300_VAP_VF_CNTL__PRIM_TRIANGLES;
+ return R600_VAP_VF_CNTL__PRIM_TRIANGLES;
break;
case GL_TRIANGLE_STRIP:
- return R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
+ return R600_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
break;
case GL_TRIANGLE_FAN:
- return R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
+ return R600_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
break;
case GL_QUADS:
- return R300_VAP_VF_CNTL__PRIM_QUADS;
+ return R600_VAP_VF_CNTL__PRIM_QUADS;
break;
case GL_QUAD_STRIP:
- return R300_VAP_VF_CNTL__PRIM_QUAD_STRIP;
+ return R600_VAP_VF_CNTL__PRIM_QUAD_STRIP;
break;
case GL_POLYGON:
- return R300_VAP_VF_CNTL__PRIM_POLYGON;
+ return R600_VAP_VF_CNTL__PRIM_POLYGON;
break;
default:
assert(0);
}
}
-int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim)
+int r600NumVerts(r600ContextPtr rmesa, int num_verts, int prim)
{
int verts_off = 0;
return num_verts - verts_off;
}
-static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts)
+static void r600EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
void *out;
radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo,
radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
}
-static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
+static void r600FireEB(r600ContextPtr rmesa, int vertex_count, int type)
{
BATCH_LOCALS(&rmesa->radeon);
if (vertex_count > 0) {
BEGIN_BATCH(10);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0);
- OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
+ OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_INDX_2, 0);
+ OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_INDICES |
((vertex_count + 0) << 16) |
type |
- R300_VAP_VF_CNTL__INDEX_SIZE_32bit);
+ R600_VAP_VF_CNTL__INDEX_SIZE_32bit);
if (!rmesa->radeon.radeonScreen->kernel_mm) {
- OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
- OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
- (R300_VAP_PORT_IDX0 >> 2));
+ OUT_BATCH_PACKET3(R600_PACKET3_INDX_BUFFER, 2);
+ OUT_BATCH(R600_INDX_BUFFER_ONE_REG_WR | (0 << R600_INDX_BUFFER_SKIP_SHIFT) |
+ (R600_VAP_PORT_IDX0 >> 2));
OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
rmesa->radeon.tcl.elt_dma_bo,
rmesa->radeon.tcl.elt_dma_offset,
RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH(vertex_count);
} else {
- OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
- OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
- (R300_VAP_PORT_IDX0 >> 2));
+ OUT_BATCH_PACKET3(R600_PACKET3_INDX_BUFFER, 2);
+ OUT_BATCH(R600_INDX_BUFFER_ONE_REG_WR | (0 << R600_INDX_BUFFER_SKIP_SHIFT) |
+ (R600_VAP_PORT_IDX0 >> 2));
OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
OUT_BATCH(vertex_count);
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
}
}
-static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
+static void r600EmitAOS(r600ContextPtr rmesa, GLuint nr, GLuint offset)
{
BATCH_LOCALS(&rmesa->radeon);
uint32_t voffset;
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH(sz+2+(nr * 2));
- OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
+ OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH(nr);
for (i = 0; i + 1 < nr; i += 2) {
} else {
BEGIN_BATCH(sz+2+(nr * 2));
- OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
+ OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH(nr);
for (i = 0; i + 1 < nr; i += 2) {
}
-static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type)
+static void r600FireAOS(r600ContextPtr rmesa, int vertex_count, int type)
{
BATCH_LOCALS(&rmesa->radeon);
BEGIN_BATCH(3);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
- OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type);
+ OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0);
+ OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type);
END_BATCH();
}
-static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx,
+static void r600RunRenderPrimitive(r600ContextPtr rmesa, GLcontext * ctx,
int start, int end, int prim)
{
int type, num_verts;
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
- type = r300PrimitiveType(rmesa, prim);
- num_verts = r300NumVerts(rmesa, end - start, prim);
+ type = r600PrimitiveType(rmesa, prim);
+ num_verts = r600NumVerts(rmesa, end - start, prim);
if (type < 0 || num_verts <= 0)
return;
* allocating the index array might actually evict the vertex
* arrays. *sigh*
*/
- r300EmitElts(ctx, vb->Elts, num_verts);
- r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
- r300FireEB(rmesa, num_verts, type);
+ r600EmitElts(ctx, vb->Elts, num_verts);
+ r600EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
+ r600FireEB(rmesa, num_verts, type);
} else {
- r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
- r300FireAOS(rmesa, num_verts, type);
+ r600EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
+ r600FireAOS(rmesa, num_verts, type);
}
COMMIT_BATCH();
}
-static GLboolean r300RunRender(GLcontext * ctx,
+static GLboolean r600RunRender(GLcontext * ctx,
struct tnl_pipeline_stage *stage)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
int i;
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
if (RADEON_DEBUG & DEBUG_PRIMS)
fprintf(stderr, "%s\n", __FUNCTION__);
- r300UpdateShaders(rmesa);
- if (r300EmitArrays(ctx))
+ r600UpdateShaders(rmesa);
+ if (r600EmitArrays(ctx))
return GL_TRUE;
- r300UpdateShaderStates(rmesa);
+ r600UpdateShaderStates(rmesa);
- r300EmitCacheFlush(rmesa);
+ r600EmitCacheFlush(rmesa);
radeonEmitState(&rmesa->radeon);
for (i = 0; i < vb->PrimitiveCount; i++) {
GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
GLuint start = vb->Primitive[i].start;
GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
- r300RunRenderPrimitive(rmesa, ctx, start, end, prim);
+ r600RunRenderPrimitive(rmesa, ctx, start, end, prim);
}
- r300EmitCacheFlush(rmesa);
+ r600EmitCacheFlush(rmesa);
radeonReleaseArrays(ctx, ~0);
if (1 || RADEON_DEBUG & DEBUG_FALLBACKS) \
WARN_ONCE("Software fallback:%s\n", \
#expr); \
- return R300_FALLBACK_RAST; \
+ return R600_FALLBACK_RAST; \
} \
} while(0)
-static int r300Fallback(GLcontext * ctx)
+static int r600Fallback(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
const unsigned back = ctx->Stencil._BackFace;
- FALLBACK_IF(r300->radeon.Fallback);
+ FALLBACK_IF(r600->radeon.Fallback);
/* Do we need to use new-style shaders?
* Also is there a better way to do this? */
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
+ if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
struct r500_fragment_program *fp = (struct r500_fragment_program *)
(char *)ctx->FragmentProgram._Current;
if (fp) {
if (!fp->translated) {
- r500TranslateFragmentShader(r300, fp);
+ r500TranslateFragmentShader(r600, fp);
FALLBACK_IF(!fp->translated);
}
}
} else {
- struct r300_fragment_program *fp = (struct r300_fragment_program *)
+ struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
if (fp) {
if (!fp->translated) {
- r300TranslateFragmentShader(r300, fp);
+ r600TranslateFragmentShader(r600, fp);
FALLBACK_IF(!fp->translated);
}
}
if (ctx->Extensions.NV_point_sprite || ctx->Extensions.ARB_point_sprite)
FALLBACK_IF(ctx->Point.PointSprite);
- if (!r300->disable_lowimpact_fallback) {
+ if (!r600->disable_lowimpact_fallback) {
FALLBACK_IF(ctx->Polygon.StippleFlag);
FALLBACK_IF(ctx->Multisample._Enabled);
FALLBACK_IF(ctx->Line.StippleFlag);
FALLBACK_IF(ctx->Point.SmoothFlag);
}
- return R300_FALLBACK_NONE;
+ return R600_FALLBACK_NONE;
}
-static GLboolean r300RunNonTCLRender(GLcontext * ctx,
+static GLboolean r600RunNonTCLRender(GLcontext * ctx,
struct tnl_pipeline_stage *stage)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
if (RADEON_DEBUG & DEBUG_PRIMS)
fprintf(stderr, "%s\n", __FUNCTION__);
- if (r300Fallback(ctx) >= R300_FALLBACK_RAST)
+ if (r600Fallback(ctx) >= R600_FALLBACK_RAST)
return GL_TRUE;
if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
return GL_TRUE;
- if (!r300ValidateBuffers(ctx))
+ if (!r600ValidateBuffers(ctx))
return GL_TRUE;
- return r300RunRender(ctx, stage);
+ return r600RunRender(ctx, stage);
}
-static GLboolean r300RunTCLRender(GLcontext * ctx,
+static GLboolean r600RunTCLRender(GLcontext * ctx,
struct tnl_pipeline_stage *stage)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct r300_vertex_program *vp;
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
+ struct r600_vertex_program *vp;
hw_tcl_on = future_hw_tcl_on;
if (hw_tcl_on == GL_FALSE)
return GL_TRUE;
- if (r300Fallback(ctx) >= R300_FALLBACK_TCL) {
+ if (r600Fallback(ctx) >= R600_FALLBACK_TCL) {
hw_tcl_on = GL_FALSE;
return GL_TRUE;
}
- if (!r300ValidateBuffers(ctx))
+ if (!r600ValidateBuffers(ctx))
return GL_TRUE;
- r300UpdateShaders(rmesa);
+ r600UpdateShaders(rmesa);
- vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
+ vp = (struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
if (vp->native == GL_FALSE) {
hw_tcl_on = GL_FALSE;
return GL_TRUE;
}
- return r300RunRender(ctx, stage);
+ return r600RunRender(ctx, stage);
}
-const struct tnl_pipeline_stage _r300_render_stage = {
- "r300 Hardware Rasterization",
+const struct tnl_pipeline_stage _r600_render_stage = {
+ "r600 Hardware Rasterization",
NULL,
NULL,
NULL,
NULL,
- r300RunNonTCLRender
+ r600RunNonTCLRender
};
-const struct tnl_pipeline_stage _r300_tcl_stage = {
- "r300 Hardware Transform, Clipping and Lighting",
+const struct tnl_pipeline_stage _r600_tcl_stage = {
+ "r600 Hardware Transform, Clipping and Lighting",
NULL,
NULL,
NULL,
NULL,
- r300RunTCLRender
+ r600RunTCLRender
};
#include "r600_context.h"
#include "r600_fragprog.h"
-static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target,
+static struct gl_program *r600NewProgram(GLcontext * ctx, GLenum target,
GLuint id)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct r300_vertex_program_cont *vp;
- struct r300_fragment_program *r300_fp;
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
+ struct r600_vertex_program_cont *vp;
+ struct r600_fragment_program *r600_fp;
struct r500_fragment_program *r500_fp;
switch (target) {
case GL_VERTEX_STATE_PROGRAM_NV:
case GL_VERTEX_PROGRAM_ARB:
- vp = CALLOC_STRUCT(r300_vertex_program_cont);
+ vp = CALLOC_STRUCT(r600_vertex_program_cont);
return _mesa_init_vertex_program(ctx, &vp->mesa_program,
target, id);
case GL_FRAGMENT_PROGRAM_ARB:
return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program,
target, id);
} else {
- r300_fp = CALLOC_STRUCT(r300_fragment_program);
- return _mesa_init_fragment_program(ctx, &r300_fp->mesa_program,
+ r600_fp = CALLOC_STRUCT(r600_fragment_program);
+ return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program,
target, id);
}
return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program,
target, id);
} else {
- r300_fp = CALLOC_STRUCT(r300_fragment_program);
- return _mesa_init_fragment_program(ctx, &r300_fp->mesa_program,
+ r600_fp = CALLOC_STRUCT(r600_fragment_program);
+ return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program,
target, id);
}
default:
- _mesa_problem(ctx, "Bad target in r300NewProgram");
+ _mesa_problem(ctx, "Bad target in r600NewProgram");
}
return NULL;
}
-static void r300DeleteProgram(GLcontext * ctx, struct gl_program *prog)
+static void r600DeleteProgram(GLcontext * ctx, struct gl_program *prog)
{
_mesa_delete_program(ctx, prog);
}
static void
-r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
+r600ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct r300_vertex_program_cont *vp = (void *)prog;
- struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)prog;
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
+ struct r600_vertex_program_cont *vp = (void *)prog;
+ struct r600_fragment_program *r600_fp = (struct r600_fragment_program *)prog;
struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)prog;
switch (target) {
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
r500_fp->translated = GL_FALSE;
else
- r300_fp->translated = GL_FALSE;
+ r600_fp->translated = GL_FALSE;
break;
}
}
static GLboolean
-r300IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog)
+r600IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog)
{
return GL_TRUE;
}
-void r300InitShaderFuncs(struct dd_function_table *functions)
+void r600InitShaderFuncs(struct dd_function_table *functions)
{
- functions->NewProgram = r300NewProgram;
- functions->DeleteProgram = r300DeleteProgram;
- functions->ProgramStringNotify = r300ProgramStringNotify;
- functions->IsProgramNative = r300IsProgramNative;
+ functions->NewProgram = r600NewProgram;
+ functions->DeleteProgram = r600DeleteProgram;
+ functions->ProgramStringNotify = r600ProgramStringNotify;
+ functions->IsProgramNative = r600IsProgramNative;
}
extern int future_hw_tcl_on;
extern void _tnl_UpdateFixedFunctionProgram(GLcontext * ctx);
-static void r300BlendColor(GLcontext * ctx, const GLfloat cf[4])
+static void r600BlendColor(GLcontext * ctx, const GLfloat cf[4])
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
- R300_STATECHANGE(rmesa, blend_color);
+ R600_STATECHANGE(rmesa, blend_color);
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
GLuint r = IROUND(cf[0]*1023.0f);
{
switch (factor) {
case GL_ZERO:
- return R300_BLEND_GL_ZERO;
+ return R600_BLEND_GL_ZERO;
break;
case GL_ONE:
- return R300_BLEND_GL_ONE;
+ return R600_BLEND_GL_ONE;
break;
case GL_DST_COLOR:
- return R300_BLEND_GL_DST_COLOR;
+ return R600_BLEND_GL_DST_COLOR;
break;
case GL_ONE_MINUS_DST_COLOR:
- return R300_BLEND_GL_ONE_MINUS_DST_COLOR;
+ return R600_BLEND_GL_ONE_MINUS_DST_COLOR;
break;
case GL_SRC_COLOR:
- return R300_BLEND_GL_SRC_COLOR;
+ return R600_BLEND_GL_SRC_COLOR;
break;
case GL_ONE_MINUS_SRC_COLOR:
- return R300_BLEND_GL_ONE_MINUS_SRC_COLOR;
+ return R600_BLEND_GL_ONE_MINUS_SRC_COLOR;
break;
case GL_SRC_ALPHA:
- return R300_BLEND_GL_SRC_ALPHA;
+ return R600_BLEND_GL_SRC_ALPHA;
break;
case GL_ONE_MINUS_SRC_ALPHA:
- return R300_BLEND_GL_ONE_MINUS_SRC_ALPHA;
+ return R600_BLEND_GL_ONE_MINUS_SRC_ALPHA;
break;
case GL_DST_ALPHA:
- return R300_BLEND_GL_DST_ALPHA;
+ return R600_BLEND_GL_DST_ALPHA;
break;
case GL_ONE_MINUS_DST_ALPHA:
- return R300_BLEND_GL_ONE_MINUS_DST_ALPHA;
+ return R600_BLEND_GL_ONE_MINUS_DST_ALPHA;
break;
case GL_SRC_ALPHA_SATURATE:
- return (is_src) ? R300_BLEND_GL_SRC_ALPHA_SATURATE :
- R300_BLEND_GL_ZERO;
+ return (is_src) ? R600_BLEND_GL_SRC_ALPHA_SATURATE :
+ R600_BLEND_GL_ZERO;
break;
case GL_CONSTANT_COLOR:
- return R300_BLEND_GL_CONST_COLOR;
+ return R600_BLEND_GL_CONST_COLOR;
break;
case GL_ONE_MINUS_CONSTANT_COLOR:
- return R300_BLEND_GL_ONE_MINUS_CONST_COLOR;
+ return R600_BLEND_GL_ONE_MINUS_CONST_COLOR;
break;
case GL_CONSTANT_ALPHA:
- return R300_BLEND_GL_CONST_ALPHA;
+ return R600_BLEND_GL_CONST_ALPHA;
break;
case GL_ONE_MINUS_CONSTANT_ALPHA:
- return R300_BLEND_GL_ONE_MINUS_CONST_ALPHA;
+ return R600_BLEND_GL_ONE_MINUS_CONST_ALPHA;
break;
default:
fprintf(stderr, "unknown blend factor %x\n", factor);
- return (is_src) ? R300_BLEND_GL_ONE : R300_BLEND_GL_ZERO;
+ return (is_src) ? R600_BLEND_GL_ONE : R600_BLEND_GL_ZERO;
break;
}
}
*/
/* helper function */
-static void r300SetBlendCntl(r300ContextPtr r300, int func, int eqn,
+static void r600SetBlendCntl(r600ContextPtr r600, int func, int eqn,
int cbits, int funcA, int eqnA)
{
GLuint new_ablend, new_cblend;
*/
#if 0
if (new_ablend == new_cblend) {
- new_cblend |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
+ new_cblend |= R600_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
}
#endif
new_cblend |= cbits;
- if ((new_ablend != r300->hw.bld.cmd[R300_BLD_ABLEND]) ||
- (new_cblend != r300->hw.bld.cmd[R300_BLD_CBLEND])) {
- R300_STATECHANGE(r300, bld);
- r300->hw.bld.cmd[R300_BLD_ABLEND] = new_ablend;
- r300->hw.bld.cmd[R300_BLD_CBLEND] = new_cblend;
+ if ((new_ablend != r600->hw.bld.cmd[R600_BLD_ABLEND]) ||
+ (new_cblend != r600->hw.bld.cmd[R600_BLD_CBLEND])) {
+ R600_STATECHANGE(r600, bld);
+ r600->hw.bld.cmd[R600_BLD_ABLEND] = new_ablend;
+ r600->hw.bld.cmd[R600_BLD_CBLEND] = new_cblend;
}
}
-static void r300SetBlendState(GLcontext * ctx)
+static void r600SetBlendState(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT);
- int eqn = R300_COMB_FCN_ADD_CLAMP;
- int funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT);
- int eqnA = R300_COMB_FCN_ADD_CLAMP;
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ int func = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) |
+ (R600_BLEND_GL_ZERO << R600_DST_BLEND_SHIFT);
+ int eqn = R600_COMB_FCN_ADD_CLAMP;
+ int funcA = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) |
+ (R600_BLEND_GL_ZERO << R600_DST_BLEND_SHIFT);
+ int eqnA = R600_COMB_FCN_ADD_CLAMP;
if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
- r300SetBlendCntl(r300, func, eqn, 0, func, eqn);
+ r600SetBlendCntl(r600, func, eqn, 0, func, eqn);
return;
}
func =
(blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE) <<
- R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstRGB,
+ R600_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstRGB,
GL_FALSE) <<
- R300_DST_BLEND_SHIFT);
+ R600_DST_BLEND_SHIFT);
switch (ctx->Color.BlendEquationRGB) {
case GL_FUNC_ADD:
- eqn = R300_COMB_FCN_ADD_CLAMP;
+ eqn = R600_COMB_FCN_ADD_CLAMP;
break;
case GL_FUNC_SUBTRACT:
- eqn = R300_COMB_FCN_SUB_CLAMP;
+ eqn = R600_COMB_FCN_SUB_CLAMP;
break;
case GL_FUNC_REVERSE_SUBTRACT:
- eqn = R300_COMB_FCN_RSUB_CLAMP;
+ eqn = R600_COMB_FCN_RSUB_CLAMP;
break;
case GL_MIN:
- eqn = R300_COMB_FCN_MIN;
- func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
+ eqn = R600_COMB_FCN_MIN;
+ func = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) |
+ (R600_BLEND_GL_ONE << R600_DST_BLEND_SHIFT);
break;
case GL_MAX:
- eqn = R300_COMB_FCN_MAX;
- func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
+ eqn = R600_COMB_FCN_MAX;
+ func = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) |
+ (R600_BLEND_GL_ONE << R600_DST_BLEND_SHIFT);
break;
default:
funcA =
(blend_factor(ctx->Color.BlendSrcA, GL_TRUE) <<
- R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstA,
+ R600_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstA,
GL_FALSE) <<
- R300_DST_BLEND_SHIFT);
+ R600_DST_BLEND_SHIFT);
switch (ctx->Color.BlendEquationA) {
case GL_FUNC_ADD:
- eqnA = R300_COMB_FCN_ADD_CLAMP;
+ eqnA = R600_COMB_FCN_ADD_CLAMP;
break;
case GL_FUNC_SUBTRACT:
- eqnA = R300_COMB_FCN_SUB_CLAMP;
+ eqnA = R600_COMB_FCN_SUB_CLAMP;
break;
case GL_FUNC_REVERSE_SUBTRACT:
- eqnA = R300_COMB_FCN_RSUB_CLAMP;
+ eqnA = R600_COMB_FCN_RSUB_CLAMP;
break;
case GL_MIN:
- eqnA = R300_COMB_FCN_MIN;
- funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
+ eqnA = R600_COMB_FCN_MIN;
+ funcA = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) |
+ (R600_BLEND_GL_ONE << R600_DST_BLEND_SHIFT);
break;
case GL_MAX:
- eqnA = R300_COMB_FCN_MAX;
- funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
+ eqnA = R600_COMB_FCN_MAX;
+ funcA = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) |
+ (R600_BLEND_GL_ONE << R600_DST_BLEND_SHIFT);
break;
default:
return;
}
- r300SetBlendCntl(r300,
+ r600SetBlendCntl(r600,
func, eqn,
- (R300_SEPARATE_ALPHA_ENABLE |
- R300_READ_ENABLE |
- R300_ALPHA_BLEND_ENABLE), funcA, eqnA);
+ (R600_SEPARATE_ALPHA_ENABLE |
+ R600_READ_ENABLE |
+ R600_ALPHA_BLEND_ENABLE), funcA, eqnA);
}
-static void r300BlendEquationSeparate(GLcontext * ctx,
+static void r600BlendEquationSeparate(GLcontext * ctx,
GLenum modeRGB, GLenum modeA)
{
- r300SetBlendState(ctx);
+ r600SetBlendState(ctx);
}
-static void r300BlendFuncSeparate(GLcontext * ctx,
+static void r600BlendFuncSeparate(GLcontext * ctx,
GLenum sfactorRGB, GLenum dfactorRGB,
GLenum sfactorA, GLenum dfactorA)
{
- r300SetBlendState(ctx);
+ r600SetBlendState(ctx);
}
/**
{
GLuint bits = logicop - GL_CLEAR;
bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
- return bits << R300_RB3D_ROPCNTL_ROP_SHIFT;
+ return bits << R600_RB3D_ROPCNTL_ROP_SHIFT;
}
/**
- * Used internally to update the r300->hw hardware state to match the
+ * Used internally to update the r600->hw hardware state to match the
* current OpenGL state.
*/
-static void r300SetLogicOpState(GLcontext *ctx)
+static void r600SetLogicOpState(GLcontext *ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- R300_STATECHANGE(r300, rop);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ R600_STATECHANGE(r600, rop);
if (RGBA_LOGICOP_ENABLED(ctx)) {
- r300->hw.rop.cmd[1] = R300_RB3D_ROPCNTL_ROP_ENABLE |
+ r600->hw.rop.cmd[1] = R600_RB3D_ROPCNTL_ROP_ENABLE |
translate_logicop(ctx->Color.LogicOp);
} else {
- r300->hw.rop.cmd[1] = 0;
+ r600->hw.rop.cmd[1] = 0;
}
}
* Called by Mesa when an application program changes the LogicOp state
* via glLogicOp.
*/
-static void r300LogicOpcode(GLcontext *ctx, GLenum logicop)
+static void r600LogicOpcode(GLcontext *ctx, GLenum logicop)
{
if (RGBA_LOGICOP_ENABLED(ctx))
- r300SetLogicOpState(ctx);
+ r600SetLogicOpState(ctx);
}
-static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
+static void r600ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLint p;
GLint *ip;
p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
ip = (GLint *)ctx->Transform._ClipUserPlane[p];
- R300_STATECHANGE( rmesa, vpucp[p] );
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
+ R600_STATECHANGE( rmesa, vpucp[p] );
+ rmesa->hw.vpucp[p].cmd[R600_VPUCP_X] = ip[0];
+ rmesa->hw.vpucp[p].cmd[R600_VPUCP_Y] = ip[1];
+ rmesa->hw.vpucp[p].cmd[R600_VPUCP_Z] = ip[2];
+ rmesa->hw.vpucp[p].cmd[R600_VPUCP_W] = ip[3];
}
-static void r300SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
+static void r600SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
GLuint p;
/* no VAP UCP on non-TCL chipsets */
- if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
+ if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
return;
p = cap - GL_CLIP_PLANE0;
- R300_STATECHANGE(r300, vap_clip_cntl);
+ R600_STATECHANGE(r600, vap_clip_cntl);
if (state) {
- r300->hw.vap_clip_cntl.cmd[1] |= (R300_VAP_UCP_ENABLE_0 << p);
- r300ClipPlane(ctx, cap, NULL);
+ r600->hw.vap_clip_cntl.cmd[1] |= (R600_VAP_UCP_ENABLE_0 << p);
+ r600ClipPlane(ctx, cap, NULL);
} else {
- r300->hw.vap_clip_cntl.cmd[1] &= ~(R300_VAP_UCP_ENABLE_0 << p);
+ r600->hw.vap_clip_cntl.cmd[1] &= ~(R600_VAP_UCP_ENABLE_0 << p);
}
}
/**
* Update our tracked culling state based on Mesa's state.
*/
-static void r300UpdateCulling(GLcontext * ctx)
+static void r600UpdateCulling(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
uint32_t val = 0;
if (ctx->Polygon.CullFlag) {
switch (ctx->Polygon.CullFaceMode) {
case GL_FRONT:
- val = R300_CULL_FRONT;
+ val = R600_CULL_FRONT;
break;
case GL_BACK:
- val = R300_CULL_BACK;
+ val = R600_CULL_BACK;
break;
case GL_FRONT_AND_BACK:
- val = R300_CULL_FRONT | R300_CULL_BACK;
+ val = R600_CULL_FRONT | R600_CULL_BACK;
break;
default:
break;
switch (ctx->Polygon.FrontFace) {
case GL_CW:
- val |= R300_FRONT_FACE_CW;
+ val |= R600_FRONT_FACE_CW;
break;
case GL_CCW:
- val |= R300_FRONT_FACE_CCW;
+ val |= R600_FRONT_FACE_CCW;
break;
default:
break;
}
- R300_STATECHANGE(r300, cul);
- r300->hw.cul.cmd[R300_CUL_CULL] = val;
+ R600_STATECHANGE(r600, cul);
+ r600->hw.cul.cmd[R600_CUL_CULL] = val;
}
-static void r300SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
+static void r600SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
- R300_STATECHANGE(r300, occlusion_cntl);
+ R600_STATECHANGE(r600, occlusion_cntl);
if (state) {
- r300->hw.occlusion_cntl.cmd[1] |= (3 << 0);
+ r600->hw.occlusion_cntl.cmd[1] |= (3 << 0);
} else {
- r300->hw.occlusion_cntl.cmd[1] &= ~(3 << 0);
+ r600->hw.occlusion_cntl.cmd[1] &= ~(3 << 0);
}
}
static GLboolean current_fragment_program_writes_depth(GLcontext* ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
- if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
- struct r300_fragment_program *fp = (struct r300_fragment_program *)
+ if (r600->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
+ struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
return (fp && fp->WritesDepth);
} else {
}
}
-static void r300SetEarlyZState(GLcontext * ctx)
+static void r600SetEarlyZState(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- GLuint topZ = R300_ZTOP_ENABLE;
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ GLuint topZ = R600_ZTOP_ENABLE;
if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS)
- topZ = R300_ZTOP_DISABLE;
+ topZ = R600_ZTOP_DISABLE;
if (current_fragment_program_writes_depth(ctx))
- topZ = R300_ZTOP_DISABLE;
+ topZ = R600_ZTOP_DISABLE;
- if (topZ != r300->hw.zstencil_format.cmd[2]) {
+ if (topZ != r600->hw.zstencil_format.cmd[2]) {
/* Note: This completely reemits the stencil format.
* I have not tested whether this is strictly necessary,
* or if emitting a write to ZB_ZTOP is enough.
*/
- R300_STATECHANGE(r300, zstencil_format);
- r300->hw.zstencil_format.cmd[2] = topZ;
+ R600_STATECHANGE(r600, zstencil_format);
+ r600->hw.zstencil_format.cmd[2] = topZ;
}
}
-static void r300SetAlphaState(GLcontext * ctx)
+static void r600SetAlphaState(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
GLubyte refByte;
uint32_t pp_misc = 0x0;
GLboolean really_enabled = ctx->Color.AlphaEnabled;
switch (ctx->Color.AlphaFunc) {
case GL_NEVER:
- pp_misc |= R300_FG_ALPHA_FUNC_NEVER;
+ pp_misc |= R600_FG_ALPHA_FUNC_NEVER;
break;
case GL_LESS:
- pp_misc |= R300_FG_ALPHA_FUNC_LESS;
+ pp_misc |= R600_FG_ALPHA_FUNC_LESS;
break;
case GL_EQUAL:
- pp_misc |= R300_FG_ALPHA_FUNC_EQUAL;
+ pp_misc |= R600_FG_ALPHA_FUNC_EQUAL;
break;
case GL_LEQUAL:
- pp_misc |= R300_FG_ALPHA_FUNC_LE;
+ pp_misc |= R600_FG_ALPHA_FUNC_LE;
break;
case GL_GREATER:
- pp_misc |= R300_FG_ALPHA_FUNC_GREATER;
+ pp_misc |= R600_FG_ALPHA_FUNC_GREATER;
break;
case GL_NOTEQUAL:
- pp_misc |= R300_FG_ALPHA_FUNC_NOTEQUAL;
+ pp_misc |= R600_FG_ALPHA_FUNC_NOTEQUAL;
break;
case GL_GEQUAL:
- pp_misc |= R300_FG_ALPHA_FUNC_GE;
+ pp_misc |= R600_FG_ALPHA_FUNC_GE;
break;
case GL_ALWAYS:
/*pp_misc |= FG_ALPHA_FUNC_ALWAYS; */
}
if (really_enabled) {
- pp_misc |= R300_FG_ALPHA_FUNC_ENABLE;
+ pp_misc |= R600_FG_ALPHA_FUNC_ENABLE;
pp_misc |= R500_FG_ALPHA_FUNC_8BIT;
- pp_misc |= (refByte & R300_FG_ALPHA_FUNC_VAL_MASK);
+ pp_misc |= (refByte & R600_FG_ALPHA_FUNC_VAL_MASK);
} else {
pp_misc = 0x0;
}
- R300_STATECHANGE(r300, at);
- r300->hw.at.cmd[R300_AT_ALPHA_TEST] = pp_misc;
- r300->hw.at.cmd[R300_AT_UNKNOWN] = 0;
+ R600_STATECHANGE(r600, at);
+ r600->hw.at.cmd[R600_AT_ALPHA_TEST] = pp_misc;
+ r600->hw.at.cmd[R600_AT_UNKNOWN] = 0;
- r300SetEarlyZState(ctx);
+ r600SetEarlyZState(ctx);
}
-static void r300AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref)
+static void r600AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref)
{
(void)func;
(void)ref;
- r300SetAlphaState(ctx);
+ r600SetAlphaState(ctx);
}
static int translate_func(int func)
{
switch (func) {
case GL_NEVER:
- return R300_ZS_NEVER;
+ return R600_ZS_NEVER;
case GL_LESS:
- return R300_ZS_LESS;
+ return R600_ZS_LESS;
case GL_EQUAL:
- return R300_ZS_EQUAL;
+ return R600_ZS_EQUAL;
case GL_LEQUAL:
- return R300_ZS_LEQUAL;
+ return R600_ZS_LEQUAL;
case GL_GREATER:
- return R300_ZS_GREATER;
+ return R600_ZS_GREATER;
case GL_NOTEQUAL:
- return R300_ZS_NOTEQUAL;
+ return R600_ZS_NOTEQUAL;
case GL_GEQUAL:
- return R300_ZS_GEQUAL;
+ return R600_ZS_GEQUAL;
case GL_ALWAYS:
- return R300_ZS_ALWAYS;
+ return R600_ZS_ALWAYS;
}
return 0;
}
-static void r300SetDepthState(GLcontext * ctx)
+static void r600SetDepthState(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
- R300_STATECHANGE(r300, zs);
- r300->hw.zs.cmd[R300_ZS_CNTL_0] &= R300_STENCIL_ENABLE|R300_STENCIL_FRONT_BACK;
- r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_Z_FUNC_SHIFT);
+ R600_STATECHANGE(r600, zs);
+ r600->hw.zs.cmd[R600_ZS_CNTL_0] &= R600_STENCIL_ENABLE|R600_STENCIL_FRONT_BACK;
+ r600->hw.zs.cmd[R600_ZS_CNTL_1] &= ~(R600_ZS_MASK << R600_Z_FUNC_SHIFT);
if (ctx->Depth.Test) {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_ENABLE;
+ r600->hw.zs.cmd[R600_ZS_CNTL_0] |= R600_Z_ENABLE;
if (ctx->Depth.Mask)
- r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_WRITE_ENABLE;
- r300->hw.zs.cmd[R300_ZS_CNTL_1] |=
- translate_func(ctx->Depth.Func) << R300_Z_FUNC_SHIFT;
+ r600->hw.zs.cmd[R600_ZS_CNTL_0] |= R600_Z_WRITE_ENABLE;
+ r600->hw.zs.cmd[R600_ZS_CNTL_1] |=
+ translate_func(ctx->Depth.Func) << R600_Z_FUNC_SHIFT;
}
- r300SetEarlyZState(ctx);
+ r600SetEarlyZState(ctx);
}
-static void r300SetStencilState(GLcontext * ctx, GLboolean state)
+static void r600SetStencilState(GLcontext * ctx, GLboolean state)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
GLboolean hw_stencil = GL_FALSE;
if (ctx->DrawBuffer) {
struct radeon_renderbuffer *rrbStencil
}
if (hw_stencil) {
- R300_STATECHANGE(r300, zs);
+ R600_STATECHANGE(r600, zs);
if (state) {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
- R300_STENCIL_ENABLE;
+ r600->hw.zs.cmd[R600_ZS_CNTL_0] |=
+ R600_STENCIL_ENABLE;
} else {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] &=
- ~R300_STENCIL_ENABLE;
+ r600->hw.zs.cmd[R600_ZS_CNTL_0] &=
+ ~R600_STENCIL_ENABLE;
}
} else {
#if R200_MERGED
- FALLBACK(&r300->radeon, RADEON_FALLBACK_STENCIL, state);
+ FALLBACK(&r600->radeon, RADEON_FALLBACK_STENCIL, state);
#endif
}
}
-static void r300UpdatePolygonMode(GLcontext * ctx)
+static void r600UpdatePolygonMode(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- uint32_t hw_mode = R300_GA_POLY_MODE_DISABLE;
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
+ uint32_t hw_mode = R600_GA_POLY_MODE_DISABLE;
/* Only do something if a polygon mode is wanted, default is GL_FILL */
if (ctx->Polygon.FrontMode != GL_FILL ||
}
/* Enable polygon mode */
- hw_mode |= R300_GA_POLY_MODE_DUAL;
+ hw_mode |= R600_GA_POLY_MODE_DUAL;
switch (f) {
case GL_LINE:
- hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_LINE;
+ hw_mode |= R600_GA_POLY_MODE_FRONT_PTYPE_LINE;
break;
case GL_POINT:
- hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_POINT;
+ hw_mode |= R600_GA_POLY_MODE_FRONT_PTYPE_POINT;
break;
case GL_FILL:
- hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_TRI;
+ hw_mode |= R600_GA_POLY_MODE_FRONT_PTYPE_TRI;
break;
}
switch (b) {
case GL_LINE:
- hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_LINE;
+ hw_mode |= R600_GA_POLY_MODE_BACK_PTYPE_LINE;
break;
case GL_POINT:
- hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_POINT;
+ hw_mode |= R600_GA_POLY_MODE_BACK_PTYPE_POINT;
break;
case GL_FILL:
- hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_TRI;
+ hw_mode |= R600_GA_POLY_MODE_BACK_PTYPE_TRI;
break;
}
}
- if (r300->hw.polygon_mode.cmd[1] != hw_mode) {
- R300_STATECHANGE(r300, polygon_mode);
- r300->hw.polygon_mode.cmd[1] = hw_mode;
+ if (r600->hw.polygon_mode.cmd[1] != hw_mode) {
+ R600_STATECHANGE(r600, polygon_mode);
+ r600->hw.polygon_mode.cmd[1] = hw_mode;
}
- r300->hw.polygon_mode.cmd[2] = 0x00000001;
- r300->hw.polygon_mode.cmd[3] = 0x00000000;
+ r600->hw.polygon_mode.cmd[2] = 0x00000001;
+ r600->hw.polygon_mode.cmd[3] = 0x00000000;
}
/**
*
* \note Mesa already filters redundant calls to this function.
*/
-static void r300CullFace(GLcontext * ctx, GLenum mode)
+static void r600CullFace(GLcontext * ctx, GLenum mode)
{
(void)mode;
- r300UpdateCulling(ctx);
+ r600UpdateCulling(ctx);
}
/**
*
* \note Mesa already filters redundant calls to this function.
*/
-static void r300FrontFace(GLcontext * ctx, GLenum mode)
+static void r600FrontFace(GLcontext * ctx, GLenum mode)
{
(void)mode;
- r300UpdateCulling(ctx);
- r300UpdatePolygonMode(ctx);
+ r600UpdateCulling(ctx);
+ r600UpdatePolygonMode(ctx);
}
/**
*
* \note Mesa already filters redundant calls to this function.
*/
-static void r300DepthFunc(GLcontext * ctx, GLenum func)
+static void r600DepthFunc(GLcontext * ctx, GLenum func)
{
(void)func;
- r300SetDepthState(ctx);
+ r600SetDepthState(ctx);
}
/**
*
* \note Mesa already filters redundant calls to this function.
*/
-static void r300DepthMask(GLcontext * ctx, GLboolean mask)
+static void r600DepthMask(GLcontext * ctx, GLboolean mask)
{
(void)mask;
- r300SetDepthState(ctx);
+ r600SetDepthState(ctx);
}
/**
* Handle glColorMask()
*/
-static void r300ColorMask(GLcontext * ctx,
+static void r600ColorMask(GLcontext * ctx,
GLboolean r, GLboolean g, GLboolean b, GLboolean a)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
int mask = (r ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
(g ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
(b ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
(a ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0);
- if (mask != r300->hw.cmk.cmd[R300_CMK_COLORMASK]) {
- R300_STATECHANGE(r300, cmk);
- r300->hw.cmk.cmd[R300_CMK_COLORMASK] = mask;
+ if (mask != r600->hw.cmk.cmd[R600_CMK_COLORMASK]) {
+ R600_STATECHANGE(r600, cmk);
+ r600->hw.cmk.cmd[R600_CMK_COLORMASK] = mask;
}
}
/* =============================================================
* Point state
*/
-static void r300PointSize(GLcontext * ctx, GLfloat size)
+static void r600PointSize(GLcontext * ctx, GLfloat size)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
/* same size limits for AA, non-AA points */
size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
- R300_STATECHANGE(r300, ps);
- r300->hw.ps.cmd[R300_PS_POINTSIZE] =
- ((int)(size * 6) << R300_POINTSIZE_X_SHIFT) |
- ((int)(size * 6) << R300_POINTSIZE_Y_SHIFT);
+ R600_STATECHANGE(r600, ps);
+ r600->hw.ps.cmd[R600_PS_POINTSIZE] =
+ ((int)(size * 6) << R600_POINTSIZE_X_SHIFT) |
+ ((int)(size * 6) << R600_POINTSIZE_Y_SHIFT);
}
-static void r300PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param)
+static void r600PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
switch (pname) {
case GL_POINT_SIZE_MIN:
- R300_STATECHANGE(r300, ga_point_minmax);
- r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MIN_MASK;
- r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0);
+ R600_STATECHANGE(r600, ga_point_minmax);
+ r600->hw.ga_point_minmax.cmd[1] &= ~R600_GA_POINT_MINMAX_MIN_MASK;
+ r600->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0);
break;
case GL_POINT_SIZE_MAX:
- R300_STATECHANGE(r300, ga_point_minmax);
- r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MAX_MASK;
- r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0)
- << R300_GA_POINT_MINMAX_MAX_SHIFT;
+ R600_STATECHANGE(r600, ga_point_minmax);
+ r600->hw.ga_point_minmax.cmd[1] &= ~R600_GA_POINT_MINMAX_MAX_MASK;
+ r600->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0)
+ << R600_GA_POINT_MINMAX_MAX_SHIFT;
break;
case GL_POINT_DISTANCE_ATTENUATION:
break;
/* =============================================================
* Line state
*/
-static void r300LineWidth(GLcontext * ctx, GLfloat widthf)
+static void r600LineWidth(GLcontext * ctx, GLfloat widthf)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
widthf = CLAMP(widthf,
ctx->Const.MinPointSize,
ctx->Const.MaxPointSize);
- R300_STATECHANGE(r300, lcntl);
- r300->hw.lcntl.cmd[1] =
- R300_LINE_CNT_HO | R300_LINE_CNT_VE | (int)(widthf * 6.0);
+ R600_STATECHANGE(r600, lcntl);
+ r600->hw.lcntl.cmd[1] =
+ R600_LINE_CNT_HO | R600_LINE_CNT_VE | (int)(widthf * 6.0);
}
-static void r300PolygonMode(GLcontext * ctx, GLenum face, GLenum mode)
+static void r600PolygonMode(GLcontext * ctx, GLenum face, GLenum mode)
{
(void)face;
(void)mode;
- r300UpdatePolygonMode(ctx);
+ r600UpdatePolygonMode(ctx);
}
/* =============================================================
{
switch (op) {
case GL_KEEP:
- return R300_ZS_KEEP;
+ return R600_ZS_KEEP;
case GL_ZERO:
- return R300_ZS_ZERO;
+ return R600_ZS_ZERO;
case GL_REPLACE:
- return R300_ZS_REPLACE;
+ return R600_ZS_REPLACE;
case GL_INCR:
- return R300_ZS_INCR;
+ return R600_ZS_INCR;
case GL_DECR:
- return R300_ZS_DECR;
+ return R600_ZS_DECR;
case GL_INCR_WRAP_EXT:
- return R300_ZS_INCR_WRAP;
+ return R600_ZS_INCR_WRAP;
case GL_DECR_WRAP_EXT:
- return R300_ZS_DECR_WRAP;
+ return R600_ZS_DECR_WRAP;
case GL_INVERT:
- return R300_ZS_INVERT;
+ return R600_ZS_INVERT;
default:
WARN_ONCE("Do not know how to translate stencil op");
- return R300_ZS_KEEP;
+ return R600_ZS_KEEP;
}
return 0;
}
-static void r300ShadeModel(GLcontext * ctx, GLenum mode)
+static void r600ShadeModel(GLcontext * ctx, GLenum mode)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
- R300_STATECHANGE(rmesa, shade);
+ R600_STATECHANGE(rmesa, shade);
rmesa->hw.shade.cmd[1] = 0x00000002;
switch (mode) {
case GL_FLAT:
- rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_FLAT;
+ rmesa->hw.shade.cmd[2] = R600_RE_SHADE_MODEL_FLAT;
break;
case GL_SMOOTH:
- rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_SMOOTH;
+ rmesa->hw.shade.cmd[2] = R600_RE_SHADE_MODEL_SMOOTH;
break;
default:
return;
rmesa->hw.shade.cmd[4] = 0x00000000;
}
-static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face,
+static void r600StencilFuncSeparate(GLcontext * ctx, GLenum face,
GLenum func, GLint ref, GLuint mask)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLuint refmask =
- ((ctx->Stencil.Ref[0] & 0xff) << R300_STENCILREF_SHIFT)
- | ((ctx->Stencil.ValueMask[0] & 0xff) << R300_STENCILMASK_SHIFT);
+ ((ctx->Stencil.Ref[0] & 0xff) << R600_STENCILREF_SHIFT)
+ | ((ctx->Stencil.ValueMask[0] & 0xff) << R600_STENCILMASK_SHIFT);
const unsigned back = ctx->Stencil._BackFace;
GLuint flag;
- R300_STATECHANGE(rmesa, zs);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_STENCIL_FRONT_BACK;
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= ~((R300_ZS_MASK <<
- R300_S_FRONT_FUNC_SHIFT)
- | (R300_ZS_MASK <<
- R300_S_BACK_FUNC_SHIFT));
+ R600_STATECHANGE(rmesa, zs);
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_0] |= R600_STENCIL_FRONT_BACK;
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_1] &= ~((R600_ZS_MASK <<
+ R600_S_FRONT_FUNC_SHIFT)
+ | (R600_ZS_MASK <<
+ R600_S_BACK_FUNC_SHIFT));
- rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
- ~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) |
- (R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT));
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_2] &=
+ ~((R600_STENCILREF_MASK << R600_STENCILREF_SHIFT) |
+ (R600_STENCILREF_MASK << R600_STENCILMASK_SHIFT));
flag = translate_func(ctx->Stencil.Function[0]);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
- (flag << R300_S_FRONT_FUNC_SHIFT);
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_1] |=
+ (flag << R600_S_FRONT_FUNC_SHIFT);
flag = translate_func(ctx->Stencil.Function[back]);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
- (flag << R300_S_BACK_FUNC_SHIFT);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= refmask;
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_1] |=
+ (flag << R600_S_BACK_FUNC_SHIFT);
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_2] |= refmask;
}
-static void r300StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask)
+static void r600StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
- R300_STATECHANGE(rmesa, zs);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
- ~(R300_STENCILREF_MASK <<
- R300_STENCILWRITEMASK_SHIFT);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |=
+ R600_STATECHANGE(rmesa, zs);
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_2] &=
+ ~(R600_STENCILREF_MASK <<
+ R600_STENCILWRITEMASK_SHIFT);
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_2] |=
(ctx->Stencil.
- WriteMask[0] & R300_STENCILREF_MASK) <<
- R300_STENCILWRITEMASK_SHIFT;
+ WriteMask[0] & R600_STENCILREF_MASK) <<
+ R600_STENCILWRITEMASK_SHIFT;
}
-static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
+static void r600StencilOpSeparate(GLcontext * ctx, GLenum face,
GLenum fail, GLenum zfail, GLenum zpass)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
const unsigned back = ctx->Stencil._BackFace;
- R300_STATECHANGE(rmesa, zs);
+ R600_STATECHANGE(rmesa, zs);
/* It is easier to mask what's left.. */
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &=
- (R300_ZS_MASK << R300_Z_FUNC_SHIFT) |
- (R300_ZS_MASK << R300_S_FRONT_FUNC_SHIFT) |
- (R300_ZS_MASK << R300_S_BACK_FUNC_SHIFT);
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_1] &=
+ (R600_ZS_MASK << R600_Z_FUNC_SHIFT) |
+ (R600_ZS_MASK << R600_S_FRONT_FUNC_SHIFT) |
+ (R600_ZS_MASK << R600_S_BACK_FUNC_SHIFT);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_1] |=
(translate_stencil_op(ctx->Stencil.FailFunc[0]) <<
- R300_S_FRONT_SFAIL_OP_SHIFT)
+ R600_S_FRONT_SFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZFailFunc[0]) <<
- R300_S_FRONT_ZFAIL_OP_SHIFT)
+ R600_S_FRONT_ZFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZPassFunc[0]) <<
- R300_S_FRONT_ZPASS_OP_SHIFT);
+ R600_S_FRONT_ZPASS_OP_SHIFT);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
+ rmesa->hw.zs.cmd[R600_ZS_CNTL_1] |=
(translate_stencil_op(ctx->Stencil.FailFunc[back]) <<
- R300_S_BACK_SFAIL_OP_SHIFT)
+ R600_S_BACK_SFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZFailFunc[back]) <<
- R300_S_BACK_ZFAIL_OP_SHIFT)
+ R600_S_BACK_ZFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZPassFunc[back]) <<
- R300_S_BACK_ZPASS_OP_SHIFT);
+ R600_S_BACK_ZPASS_OP_SHIFT);
}
/* =============================================================
#define SUBPIXEL_X 0.125
#define SUBPIXEL_Y 0.125
-static void r300UpdateWindow(GLcontext * ctx)
+static void r600UpdateWindow(GLcontext * ctx)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
GLfloat sz = v[MAT_SZ] * depthScale;
GLfloat tz = v[MAT_TZ] * depthScale;
- R300_STATECHANGE(rmesa, vpt);
+ R600_STATECHANGE(rmesa, vpt);
- rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx);
- rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx);
- rmesa->hw.vpt.cmd[R300_VPT_YSCALE] = r300PackFloat32(sy);
- rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty);
- rmesa->hw.vpt.cmd[R300_VPT_ZSCALE] = r300PackFloat32(sz);
- rmesa->hw.vpt.cmd[R300_VPT_ZOFFSET] = r300PackFloat32(tz);
+ rmesa->hw.vpt.cmd[R600_VPT_XSCALE] = r600PackFloat32(sx);
+ rmesa->hw.vpt.cmd[R600_VPT_XOFFSET] = r600PackFloat32(tx);
+ rmesa->hw.vpt.cmd[R600_VPT_YSCALE] = r600PackFloat32(sy);
+ rmesa->hw.vpt.cmd[R600_VPT_YOFFSET] = r600PackFloat32(ty);
+ rmesa->hw.vpt.cmd[R600_VPT_ZSCALE] = r600PackFloat32(sz);
+ rmesa->hw.vpt.cmd[R600_VPT_ZOFFSET] = r600PackFloat32(tz);
}
-static void r300Viewport(GLcontext * ctx, GLint x, GLint y,
+static void r600Viewport(GLcontext * ctx, GLint x, GLint y,
GLsizei width, GLsizei height)
{
/* Don't pipeline viewport changes, conflict with window offset
* setting below. Could apply deltas to rescue pipelined viewport
* values, or keep the originals hanging around.
*/
- r300UpdateWindow(ctx);
+ r600UpdateWindow(ctx);
radeon_viewport(ctx, x, y, width, height);
}
-static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
+static void r600DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
{
- r300UpdateWindow(ctx);
+ r600UpdateWindow(ctx);
}
-void r300UpdateViewportOffset(GLcontext * ctx)
+void r600UpdateViewportOffset(GLcontext * ctx)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = ((radeonContextPtr) rmesa)->dri.drawable;
GLfloat xoffset = (GLfloat) dPriv->x;
GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y;
- if (rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] != r300PackFloat32(tx) ||
- rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] != r300PackFloat32(ty)) {
+ if (rmesa->hw.vpt.cmd[R600_VPT_XOFFSET] != r600PackFloat32(tx) ||
+ rmesa->hw.vpt.cmd[R600_VPT_YOFFSET] != r600PackFloat32(ty)) {
/* Note: this should also modify whatever data the context reset
* code uses...
*/
- R300_STATECHANGE(rmesa, vpt);
- rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx);
- rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty);
+ R600_STATECHANGE(rmesa, vpt);
+ rmesa->hw.vpt.cmd[R600_VPT_XOFFSET] = r600PackFloat32(tx);
+ rmesa->hw.vpt.cmd[R600_VPT_YOFFSET] = r600PackFloat32(ty);
}
}
static void
-r300FetchStateParameter(GLcontext * ctx,
+r600FetchStateParameter(GLcontext * ctx,
const gl_state_index state[STATE_LENGTH],
GLfloat * value)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
switch (state[0]) {
case STATE_INTERNAL:
switch (state[1]) {
- case STATE_R300_WINDOW_DIMENSION:
- value[0] = r300->radeon.dri.drawable->w * 0.5f; /* width*0.5 */
- value[1] = r300->radeon.dri.drawable->h * 0.5f; /* height*0.5 */
+ case STATE_R600_WINDOW_DIMENSION:
+ value[0] = r600->radeon.dri.drawable->w * 0.5f; /* width*0.5 */
+ value[1] = r600->radeon.dri.drawable->h * 0.5f; /* height*0.5 */
value[2] = 0.5F; /* for moving range [-1 1] -> [0 1] */
value[3] = 1.0F; /* not used */
break;
- case STATE_R300_TEXRECT_FACTOR:{
+ case STATE_R600_TEXRECT_FACTOR:{
struct gl_texture_object *t =
ctx->Texture.Unit[state[2]].CurrentTex[TEXTURE_RECT_INDEX];
}
/**
- * Update R300's own internal state parameters.
- * For now just STATE_R300_WINDOW_DIMENSION
+ * Update R600's own internal state parameters.
+ * For now just STATE_R600_WINDOW_DIMENSION
*/
-void r300UpdateStateParameters(GLcontext * ctx, GLuint new_state)
+void r600UpdateStateParameters(GLcontext * ctx, GLuint new_state)
{
- struct r300_fragment_program *fp;
+ struct r600_fragment_program *fp;
struct gl_program_parameter_list *paramList;
GLuint i;
if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
return;
- fp = (struct r300_fragment_program *)ctx->FragmentProgram._Current;
+ fp = (struct r600_fragment_program *)ctx->FragmentProgram._Current;
if (!fp)
return;
for (i = 0; i < paramList->NumParameters; i++) {
if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR) {
- r300FetchStateParameter(ctx,
+ r600FetchStateParameter(ctx,
paramList->Parameters[i].
StateIndexes,
paramList->ParameterValues[i]);
/* =============================================================
* Polygon state
*/
-static void r300PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units)
+static void r600PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLfloat constant = units;
switch (ctx->Visual.depthBits) {
/* fprintf(stderr, "%s f:%f u:%f\n", __FUNCTION__, factor, constant); */
- R300_STATECHANGE(rmesa, zbs);
- rmesa->hw.zbs.cmd[R300_ZBS_T_FACTOR] = r300PackFloat32(factor);
- rmesa->hw.zbs.cmd[R300_ZBS_T_CONSTANT] = r300PackFloat32(constant);
- rmesa->hw.zbs.cmd[R300_ZBS_W_FACTOR] = r300PackFloat32(factor);
- rmesa->hw.zbs.cmd[R300_ZBS_W_CONSTANT] = r300PackFloat32(constant);
+ R600_STATECHANGE(rmesa, zbs);
+ rmesa->hw.zbs.cmd[R600_ZBS_T_FACTOR] = r600PackFloat32(factor);
+ rmesa->hw.zbs.cmd[R600_ZBS_T_CONSTANT] = r600PackFloat32(constant);
+ rmesa->hw.zbs.cmd[R600_ZBS_W_FACTOR] = r600PackFloat32(factor);
+ rmesa->hw.zbs.cmd[R600_ZBS_W_CONSTANT] = r600PackFloat32(constant);
}
/* Routing and texture-related */
-/* r300 doesnt handle GL_CLAMP and GL_MIRROR_CLAMP_EXT correctly when filter is NEAREST.
+/* r600 doesnt handle GL_CLAMP and GL_MIRROR_CLAMP_EXT correctly when filter is NEAREST.
* Since texwrap produces same results for GL_CLAMP and GL_CLAMP_TO_EDGE we use them instead.
* We need to recalculate wrap modes whenever filter mode is changed because someone might do:
* glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);
* glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_CLAMP);
* glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR);
- * Since r300 completely ignores R300_TX_CLAMP when either min or mag is nearest it cant handle
+ * Since r600 completely ignores R600_TX_CLAMP when either min or mag is nearest it cant handle
* combinations where only one of them is nearest.
*/
static unsigned long gen_fixed_filter(unsigned long f)
//return f;
/* We ignore MIRROR bit so we dont have to do everything twice */
- if ((f & ((7 - 1) << R300_TX_WRAP_S_SHIFT)) ==
- (R300_TX_CLAMP << R300_TX_WRAP_S_SHIFT)) {
+ if ((f & ((7 - 1) << R600_TX_WRAP_S_SHIFT)) ==
+ (R600_TX_CLAMP << R600_TX_WRAP_S_SHIFT)) {
needs_fixing |= 1;
}
- if ((f & ((7 - 1) << R300_TX_WRAP_T_SHIFT)) ==
- (R300_TX_CLAMP << R300_TX_WRAP_T_SHIFT)) {
+ if ((f & ((7 - 1) << R600_TX_WRAP_T_SHIFT)) ==
+ (R600_TX_CLAMP << R600_TX_WRAP_T_SHIFT)) {
needs_fixing |= 2;
}
- if ((f & ((7 - 1) << R300_TX_WRAP_R_SHIFT)) ==
- (R300_TX_CLAMP << R300_TX_WRAP_R_SHIFT)) {
+ if ((f & ((7 - 1) << R600_TX_WRAP_R_SHIFT)) ==
+ (R600_TX_CLAMP << R600_TX_WRAP_R_SHIFT)) {
needs_fixing |= 4;
}
if (!needs_fixing)
return f;
- mag = f & R300_TX_MAG_FILTER_MASK;
- min = f & (R300_TX_MIN_FILTER_MASK|R300_TX_MIN_FILTER_MIP_MASK);
+ mag = f & R600_TX_MAG_FILTER_MASK;
+ min = f & (R600_TX_MIN_FILTER_MASK|R600_TX_MIN_FILTER_MIP_MASK);
/* TODO: Check for anisto filters too */
- if ((mag != R300_TX_MAG_FILTER_NEAREST)
- && (min != R300_TX_MIN_FILTER_NEAREST))
+ if ((mag != R600_TX_MAG_FILTER_NEAREST)
+ && (min != R600_TX_MIN_FILTER_NEAREST))
return f;
- /* r300 cant handle these modes hence we force nearest to linear */
- if ((mag == R300_TX_MAG_FILTER_NEAREST)
- && (min != R300_TX_MIN_FILTER_NEAREST)) {
- f &= ~R300_TX_MAG_FILTER_NEAREST;
- f |= R300_TX_MAG_FILTER_LINEAR;
+ /* r600 cant handle these modes hence we force nearest to linear */
+ if ((mag == R600_TX_MAG_FILTER_NEAREST)
+ && (min != R600_TX_MIN_FILTER_NEAREST)) {
+ f &= ~R600_TX_MAG_FILTER_NEAREST;
+ f |= R600_TX_MAG_FILTER_LINEAR;
return f;
}
- if ((min == R300_TX_MIN_FILTER_NEAREST)
- && (mag != R300_TX_MAG_FILTER_NEAREST)) {
- f &= ~R300_TX_MIN_FILTER_NEAREST;
- f |= R300_TX_MIN_FILTER_LINEAR;
+ if ((min == R600_TX_MIN_FILTER_NEAREST)
+ && (mag != R600_TX_MAG_FILTER_NEAREST)) {
+ f &= ~R600_TX_MIN_FILTER_NEAREST;
+ f |= R600_TX_MIN_FILTER_LINEAR;
return f;
}
/* Both are nearest */
if (needs_fixing & 1) {
- f &= ~((7 - 1) << R300_TX_WRAP_S_SHIFT);
- f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT;
+ f &= ~((7 - 1) << R600_TX_WRAP_S_SHIFT);
+ f |= R600_TX_CLAMP_TO_EDGE << R600_TX_WRAP_S_SHIFT;
}
if (needs_fixing & 2) {
- f &= ~((7 - 1) << R300_TX_WRAP_T_SHIFT);
- f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT;
+ f &= ~((7 - 1) << R600_TX_WRAP_T_SHIFT);
+ f |= R600_TX_CLAMP_TO_EDGE << R600_TX_WRAP_T_SHIFT;
}
if (needs_fixing & 4) {
- f &= ~((7 - 1) << R300_TX_WRAP_R_SHIFT);
- f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT;
+ f &= ~((7 - 1) << R600_TX_WRAP_R_SHIFT);
+ f |= R600_TX_CLAMP_TO_EDGE << R600_TX_WRAP_R_SHIFT;
}
return f;
}
-static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
+static void r600SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
int i;
- struct r300_fragment_program *fp = (struct r300_fragment_program *)
+ struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
- struct r300_fragment_program_code *code = &fp->code;
+ struct r600_fragment_program_code *code = &fp->code;
- R300_STATECHANGE(r300, fpt);
+ R600_STATECHANGE(r600, fpt);
for (i = 0; i < code->tex.length; i++) {
int unit;
int opcode;
unsigned long val;
- unit = code->tex.inst[i] >> R300_TEX_ID_SHIFT;
+ unit = code->tex.inst[i] >> R600_TEX_ID_SHIFT;
unit &= 15;
val = code->tex.inst[i];
- val &= ~R300_TEX_ID_MASK;
+ val &= ~R600_TEX_ID_MASK;
opcode =
- (val & R300_TEX_INST_MASK) >> R300_TEX_INST_SHIFT;
- if (opcode == R300_TEX_OP_KIL) {
- r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+ (val & R600_TEX_INST_MASK) >> R600_TEX_INST_SHIFT;
+ if (opcode == R600_TEX_OP_KIL) {
+ r600->hw.fpt.cmd[R600_FPT_INSTR_0 + i] = val;
} else {
if (tmu_mappings[unit] >= 0) {
val |=
tmu_mappings[unit] <<
- R300_TEX_ID_SHIFT;
- r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+ R600_TEX_ID_SHIFT;
+ r600->hw.fpt.cmd[R600_FPT_INSTR_0 + i] = val;
} else {
// We get here when the corresponding texture image is incomplete
// (e.g. incomplete mipmaps etc.)
- r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+ r600->hw.fpt.cmd[R600_FPT_INSTR_0 + i] = val;
}
}
}
- r300->hw.fpt.cmd[R300_FPT_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen,
- R300_US_TEX_INST_0, code->tex.length);
+ r600->hw.fpt.cmd[R600_FPT_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen,
+ R600_US_TEX_INST_0, code->tex.length);
}
static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
b = (1 << 9)-1;
else if (b < -(1 << 9))
b = -(1 << 9);
- return (((GLuint)b) << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
+ return (((GLuint)b) << R600_LOD_BIAS_SHIFT) & R600_LOD_BIAS_MASK;
}
-static void r300SetupTextures(GLcontext * ctx)
+static void r600SetupTextures(GLcontext * ctx)
{
int i, mtu;
struct radeon_tex_obj *t;
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
int hw_tmu = 0;
int last_hw_tmu = -1; /* -1 translates into no setup costs for fields */
- int tmu_mappings[R300_MAX_TEXTURE_UNITS] = { -1, };
- struct r300_fragment_program *fp = (struct r300_fragment_program *)
+ int tmu_mappings[R600_MAX_TEXTURE_UNITS] = { -1, };
+ struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
- R300_STATECHANGE(r300, txe);
- R300_STATECHANGE(r300, tex.filter);
- R300_STATECHANGE(r300, tex.filter_1);
- R300_STATECHANGE(r300, tex.size);
- R300_STATECHANGE(r300, tex.format);
- R300_STATECHANGE(r300, tex.pitch);
- R300_STATECHANGE(r300, tex.offset);
- R300_STATECHANGE(r300, tex.chroma_key);
- R300_STATECHANGE(r300, tex.border_color);
+ R600_STATECHANGE(r600, txe);
+ R600_STATECHANGE(r600, tex.filter);
+ R600_STATECHANGE(r600, tex.filter_1);
+ R600_STATECHANGE(r600, tex.size);
+ R600_STATECHANGE(r600, tex.format);
+ R600_STATECHANGE(r600, tex.pitch);
+ R600_STATECHANGE(r600, tex.offset);
+ R600_STATECHANGE(r600, tex.chroma_key);
+ R600_STATECHANGE(r600, tex.border_color);
- r300->hw.txe.cmd[R300_TXE_ENABLE] = 0x0;
+ r600->hw.txe.cmd[R600_TXE_ENABLE] = 0x0;
- mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
+ mtu = r600->radeon.glCtx->Const.MaxTextureUnits;
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "mtu=%d\n", mtu);
- if (mtu > R300_MAX_TEXTURE_UNITS) {
+ if (mtu > R600_MAX_TEXTURE_UNITS) {
fprintf(stderr,
- "Aiiee ! mtu=%d is greater than R300_MAX_TEXTURE_UNITS=%d\n",
- mtu, R300_MAX_TEXTURE_UNITS);
+ "Aiiee ! mtu=%d is greater than R600_MAX_TEXTURE_UNITS=%d\n",
+ mtu, R600_MAX_TEXTURE_UNITS);
_mesa_exit(-1);
}
fprintf(stderr,
"Activating texture unit %d\n", i);
- r300->hw.txe.cmd[R300_TXE_ENABLE] |= (1 << hw_tmu);
+ r600->hw.txe.cmd[R600_TXE_ENABLE] |= (1 << hw_tmu);
- r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 +
+ r600->hw.tex.filter.cmd[R600_TEX_VALUE_0 +
hw_tmu] =
gen_fixed_filter(t->pp_txfilter) | (hw_tmu << 28);
/* Note: There is a LOD bias per texture unit and a LOD bias
* (The per-texture object LOD bias was introduced in OpenGL 1.4
* and is not present in the EXT_texture_object extension).
*/
- r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] =
+ r600->hw.tex.filter_1.cmd[R600_TEX_VALUE_0 + hw_tmu] =
t->pp_txfilter_1 |
translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.LodBias);
- r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] =
+ r600->hw.tex.size.cmd[R600_TEX_VALUE_0 + hw_tmu] =
t->pp_txsize;
- r300->hw.tex.format.cmd[R300_TEX_VALUE_0 +
+ r600->hw.tex.format.cmd[R600_TEX_VALUE_0 +
hw_tmu] = t->pp_txformat;
- r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0 + hw_tmu] =
+ r600->hw.tex.pitch.cmd[R600_TEX_VALUE_0 + hw_tmu] =
t->pp_txpitch;
- r300->hw.textures[hw_tmu] = t;
+ r600->hw.textures[hw_tmu] = t;
- if (t->tile_bits & R300_TXO_MACRO_TILE) {
+ if (t->tile_bits & R600_TXO_MACRO_TILE) {
WARN_ONCE("macro tiling enabled!\n");
}
- if (t->tile_bits & R300_TXO_MICRO_TILE) {
+ if (t->tile_bits & R600_TXO_MICRO_TILE) {
WARN_ONCE("micro tiling enabled!\n");
}
- r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0 +
+ r600->hw.tex.chroma_key.cmd[R600_TEX_VALUE_0 +
hw_tmu] = 0x0;
- r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0 +
+ r600->hw.tex.border_color.cmd[R600_TEX_VALUE_0 +
hw_tmu] =
t->pp_border_color;
}
}
- r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, last_hw_tmu + 1);
- r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, last_hw_tmu + 1);
- r300->hw.tex.size.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, last_hw_tmu + 1);
- r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, last_hw_tmu + 1);
- r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, last_hw_tmu + 1);
- r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, last_hw_tmu + 1);
- r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, last_hw_tmu + 1);
- r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1);
+ r600->hw.tex.filter.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, last_hw_tmu + 1);
+ r600->hw.tex.filter_1.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER1_0, last_hw_tmu + 1);
+ r600->hw.tex.size.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_SIZE_0, last_hw_tmu + 1);
+ r600->hw.tex.format.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT_0, last_hw_tmu + 1);
+ r600->hw.tex.pitch.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT2_0, last_hw_tmu + 1);
+ r600->hw.tex.offset.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_OFFSET_0, last_hw_tmu + 1);
+ r600->hw.tex.chroma_key.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_CHROMA_KEY_0, last_hw_tmu + 1);
+ r600->hw.tex.border_color.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_BORDER_COLOR_0, last_hw_tmu + 1);
if (!fp) /* should only happenen once, just after context is created */
return;
- if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
+ if (r600->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
if (fp->mesa_program.UsesKill && last_hw_tmu < 0) {
// The KILL operation requires the first texture unit
// to be enabled.
- r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1;
- r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0;
- r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 1);
+ r600->hw.txe.cmd[R600_TXE_ENABLE] |= 1;
+ r600->hw.tex.filter.cmd[R600_TEX_VALUE_0] = 0;
+ r600->hw.tex.filter.cmd[R600_TEX_CMD_0] =
+ cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 1);
}
- r300SetupFragmentShaderTextures(ctx, tmu_mappings);
+ r600SetupFragmentShaderTextures(ctx, tmu_mappings);
} else
r500SetupFragmentShaderTextures(ctx, tmu_mappings);
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n",
- r300->hw.txe.cmd[R300_TXE_ENABLE], last_hw_tmu);
+ r600->hw.txe.cmd[R600_TXE_ENABLE], last_hw_tmu);
}
-union r300_outputs_written {
+union r600_outputs_written {
GLuint vp_outputs; /* hw_tcl_on */
DECLARE_RENDERINPUTS(index_bitset); /* !hw_tcl_on */
};
-#define R300_OUTPUTS_WRITTEN_TEST(ow, vp_result, tnl_attrib) \
+#define R600_OUTPUTS_WRITTEN_TEST(ow, vp_result, tnl_attrib) \
((hw_tcl_on) ? (ow).vp_outputs & (1 << (vp_result)) : \
RENDERINPUTS_TEST( (ow.index_bitset), (tnl_attrib) ))
-static void r300SetupRSUnit(GLcontext * ctx)
+static void r600SetupRSUnit(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
- union r300_outputs_written OutputsWritten;
+ union r600_outputs_written OutputsWritten;
GLuint InputsRead;
int fp_reg, high_rr;
int col_ip, tex_ip;
if (hw_tcl_on)
OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
else
- RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
+ RENDERINPUTS_COPY(OutputsWritten.index_bitset, r600->state.render_inputs_bitset);
if (ctx->FragmentProgram._Current)
InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
return; /* This should only ever happen once.. */
}
- R300_STATECHANGE(r300, ri);
- R300_STATECHANGE(r300, rc);
- R300_STATECHANGE(r300, rr);
+ R600_STATECHANGE(r600, ri);
+ R600_STATECHANGE(r600, rc);
+ R600_STATECHANGE(r600, rr);
fp_reg = col_ip = tex_ip = col_fmt = 0;
- r300->hw.rc.cmd[1] = 0;
- r300->hw.rc.cmd[2] = 0;
- for (i=0; i<R300_RR_CMDSIZE-1; ++i)
- r300->hw.rr.cmd[R300_RR_INST_0 + i] = 0;
+ r600->hw.rc.cmd[1] = 0;
+ r600->hw.rc.cmd[2] = 0;
+ for (i=0; i<R600_RR_CMDSIZE-1; ++i)
+ r600->hw.rr.cmd[R600_RR_INST_0 + i] = 0;
- for (i=0; i<R300_RI_CMDSIZE-1; ++i)
- r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0;
+ for (i=0; i<R600_RI_CMDSIZE-1; ++i)
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + i] = 0;
if (InputsRead & FRAG_BIT_COL0) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
+ if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size;
if (count == 4)
- col_fmt = R300_RS_COL_FMT_RGBA;
+ col_fmt = R600_RS_COL_FMT_RGBA;
else if (count == 3)
- col_fmt = R300_RS_COL_FMT_RGB1;
+ col_fmt = R600_RS_COL_FMT_RGB1;
else
- col_fmt = R300_RS_COL_FMT_0001;
+ col_fmt = R600_RS_COL_FMT_0001;
- r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(col_fmt);
- r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg);
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R600_RS_COL_PTR(col_ip) | R600_RS_COL_FMT(col_fmt);
+ r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R600_RS_INST_COL_ID(col_ip) | R600_RS_INST_COL_CN_WRITE | R600_RS_INST_COL_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_COL0;
++col_ip;
++fp_reg;
}
if (InputsRead & FRAG_BIT_COL1) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
+ if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size;
if (count == 4)
- col_fmt = R300_RS_COL_FMT_RGBA;
+ col_fmt = R600_RS_COL_FMT_RGBA;
else if (count == 3)
- col_fmt = R300_RS_COL_FMT_RGB1;
+ col_fmt = R600_RS_COL_FMT_RGB1;
else
- col_fmt = R300_RS_COL_FMT_0001;
+ col_fmt = R600_RS_COL_FMT_0001;
- r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(col_fmt);
- r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg);
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R600_RS_COL_PTR(col_ip) | R600_RS_COL_FMT(col_fmt);
+ r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R600_RS_INST_COL_ID(col_ip) | R600_RS_INST_COL_CN_WRITE | R600_RS_INST_COL_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_COL1;
++col_ip;
++fp_reg;
if (! ( InputsRead & FRAG_BIT_TEX(i) ) )
continue;
- if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
+ if (!R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
continue;
}
count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size;
switch(count) {
- case 4: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3); break;
- case 3: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(R300_RS_SEL_K1); break;
+ case 4: swiz = R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3); break;
+ case 3: swiz = R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(R600_RS_SEL_K1); break;
default:
case 1:
- case 2: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1); break;
+ case 2: swiz = R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(R600_RS_SEL_K0) | R600_RS_SEL_Q(R600_RS_SEL_K1); break;
};
- r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= swiz | R300_RS_TEX_PTR(rs_tex_count);
- r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg);
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= swiz | R600_RS_TEX_PTR(rs_tex_count);
+ r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R600_RS_INST_TEX_ID(tex_ip) | R600_RS_INST_TEX_CN_WRITE | R600_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~(FRAG_BIT_TEX0 << i);
rs_tex_count += count;
++tex_ip;
}
if (InputsRead & FRAG_BIT_FOGC) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count);
- r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg);
+ if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) {
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3) | R600_RS_TEX_PTR(rs_tex_count);
+ r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R600_RS_INST_TEX_ID(tex_ip) | R600_RS_INST_TEX_CN_WRITE | R600_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_FOGC;
rs_tex_count += 4;
++tex_ip;
}
if (InputsRead & FRAG_BIT_WPOS) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count);
- r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg);
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3) | R600_RS_TEX_PTR(rs_tex_count);
+ r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R600_RS_INST_TEX_ID(tex_ip) | R600_RS_INST_TEX_CN_WRITE | R600_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_WPOS;
rs_tex_count += 4;
++tex_ip;
/* Setup default color if no color or tex was set */
if (rs_tex_count == 0 && col_ip == 0) {
- r300->hw.rr.cmd[R300_RR_INST_0] = R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(0) | R300_RS_COL_FMT(R300_RS_COL_FMT_0001);
+ r600->hw.rr.cmd[R600_RR_INST_0] = R600_RS_INST_COL_ID(0) | R600_RS_INST_COL_CN_WRITE | R600_RS_INST_COL_ADDR(0) | R600_RS_COL_FMT(R600_RS_COL_FMT_0001);
++col_ip;
}
high_rr = (col_ip > tex_ip) ? col_ip : tex_ip;
- r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN;
- r300->hw.rc.cmd[2] |= high_rr - 1;
+ r600->hw.rc.cmd[1] |= (rs_tex_count << R600_IT_COUNT_SHIFT) | (col_ip << R600_IC_COUNT_SHIFT) | R600_HIRES_EN;
+ r600->hw.rc.cmd[2] |= high_rr - 1;
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr);
+ r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, high_rr);
if (InputsRead)
WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
static void r500SetupRSUnit(GLcontext * ctx)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
- union r300_outputs_written OutputsWritten;
+ union r600_outputs_written OutputsWritten;
GLuint InputsRead;
int fp_reg, high_rr;
int col_ip, tex_ip;
if (hw_tcl_on)
OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
else
- RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
+ RENDERINPUTS_COPY(OutputsWritten.index_bitset, r600->state.render_inputs_bitset);
if (ctx->FragmentProgram._Current)
InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
return; /* This should only ever happen once.. */
}
- R300_STATECHANGE(r300, ri);
- R300_STATECHANGE(r300, rc);
- R300_STATECHANGE(r300, rr);
+ R600_STATECHANGE(r600, ri);
+ R600_STATECHANGE(r600, rc);
+ R600_STATECHANGE(r600, rr);
fp_reg = col_ip = tex_ip = col_fmt = 0;
- r300->hw.rc.cmd[1] = 0;
- r300->hw.rc.cmd[2] = 0;
- for (i=0; i<R300_RR_CMDSIZE-1; ++i)
- r300->hw.rr.cmd[R300_RR_INST_0 + i] = 0;
+ r600->hw.rc.cmd[1] = 0;
+ r600->hw.rc.cmd[2] = 0;
+ for (i=0; i<R600_RR_CMDSIZE-1; ++i)
+ r600->hw.rr.cmd[R600_RR_INST_0 + i] = 0;
for (i=0; i<R500_RI_CMDSIZE-1; ++i)
- r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0;
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + i] = 0;
if (InputsRead & FRAG_BIT_COL0) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
+ if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size;
if (count == 4)
- col_fmt = R300_RS_COL_FMT_RGBA;
+ col_fmt = R600_RS_COL_FMT_RGBA;
else if (count == 3)
- col_fmt = R300_RS_COL_FMT_RGB1;
+ col_fmt = R600_RS_COL_FMT_RGB1;
else
- col_fmt = R300_RS_COL_FMT_0001;
+ col_fmt = R600_RS_COL_FMT_0001;
- r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt);
- r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt);
+ r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_COL0;
++col_ip;
++fp_reg;
}
if (InputsRead & FRAG_BIT_COL1) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
+ if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size;
if (count == 4)
- col_fmt = R300_RS_COL_FMT_RGBA;
+ col_fmt = R600_RS_COL_FMT_RGBA;
else if (count == 3)
- col_fmt = R300_RS_COL_FMT_RGB1;
+ col_fmt = R600_RS_COL_FMT_RGB1;
else
- col_fmt = R300_RS_COL_FMT_0001;
+ col_fmt = R600_RS_COL_FMT_0001;
- r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt);
- r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt);
+ r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_COL1;
++col_ip;
++fp_reg;
if (! ( InputsRead & FRAG_BIT_TEX(i) ) )
continue;
- if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
+ if (!R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
continue;
}
swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
}
- r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= swiz;
- r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= swiz;
+ r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~(FRAG_BIT_TEX0 << i);
rs_tex_count += count;
++tex_ip;
}
if (InputsRead & FRAG_BIT_FOGC) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) {
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) |
((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) |
((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT);
- r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
+ r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_FOGC;
rs_tex_count += 4;
++tex_ip;
}
if (InputsRead & FRAG_BIT_WPOS) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) |
((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) |
((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT);
- r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
+ r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_WPOS;
rs_tex_count += 4;
++tex_ip;
/* Setup default color if no color or tex was set */
if (rs_tex_count == 0 && col_ip == 0) {
- r300->hw.rr.cmd[R300_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R300_RS_COL_FMT_0001);
+ r600->hw.rr.cmd[R600_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R600_RS_COL_FMT_0001);
++col_ip;
}
high_rr = (col_ip > tex_ip) ? col_ip : tex_ip;
- r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN;
- r300->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1);
+ r600->hw.rc.cmd[1] |= (rs_tex_count << R600_IT_COUNT_SHIFT) | (col_ip << R600_IC_COUNT_SHIFT) | R600_HIRES_EN;
+ r600->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr);
+ r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, high_rr);
if (InputsRead)
WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
if(_nc>_p->vpu.count)_p->vpu.count=_nc;\
}while(0)
-static INLINE void r300SetupVertexProgramFragment(r300ContextPtr r300, int dest, struct r300_vertex_shader_fragment *vsf)
+static INLINE void r600SetupVertexProgramFragment(r600ContextPtr r600, int dest, struct r600_vertex_shader_fragment *vsf)
{
int i;
switch ((dest >> 8) & 0xf) {
case 0:
- R300_STATECHANGE(r300, vpi);
+ R600_STATECHANGE(r600, vpi);
for (i = 0; i < vsf->length; i++)
- r300->hw.vpi.cmd[R300_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
- bump_vpu_count(r300->hw.vpi.cmd, vsf->length + 4 * (dest & 0xff));
+ r600->hw.vpi.cmd[R600_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
+ bump_vpu_count(r600->hw.vpi.cmd, vsf->length + 4 * (dest & 0xff));
break;
case 2:
- R300_STATECHANGE(r300, vpp);
+ R600_STATECHANGE(r600, vpp);
for (i = 0; i < vsf->length; i++)
- r300->hw.vpp.cmd[R300_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
- bump_vpu_count(r300->hw.vpp.cmd, vsf->length + 4 * (dest & 0xff));
+ r600->hw.vpp.cmd[R600_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
+ bump_vpu_count(r600->hw.vpp.cmd, vsf->length + 4 * (dest & 0xff));
break;
case 4:
- R300_STATECHANGE(r300, vps);
+ R600_STATECHANGE(r600, vps);
for (i = 0; i < vsf->length; i++)
- r300->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
- bump_vpu_count(r300->hw.vps.cmd, vsf->length + 4 * (dest & 0xff));
+ r600->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]);
+ bump_vpu_count(r600->hw.vps.cmd, vsf->length + 4 * (dest & 0xff));
break;
default:
fprintf(stderr, "%s:%s don't know how to handle dest %04x\n", __FILE__, __FUNCTION__, dest);
#define MIN3(a, b, c) ((a) < (b) ? MIN2(a, c) : MIN2(b, c))
-static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count,
+static void r600VapCntl(r600ContextPtr rmesa, GLuint input_count,
GLuint output_count, GLuint temp_count)
{
int vtx_mem_size;
pvs_num_slots = MIN3(10, vtx_mem_size/input_count, vtx_mem_size/output_count);
pvs_num_cntrls = MIN2(6, vtx_mem_size/temp_count);
- R300_STATECHANGE(rmesa, vap_cntl);
+ R600_STATECHANGE(rmesa, vap_cntl);
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] =
- (pvs_num_slots << R300_PVS_NUM_SLOTS_SHIFT) |
- (pvs_num_cntrls << R300_PVS_NUM_CNTLRS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT);
+ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] =
+ (pvs_num_slots << R600_PVS_NUM_SLOTS_SHIFT) |
+ (pvs_num_cntrls << R600_PVS_NUM_CNTLRS_SHIFT) |
+ (12 << R600_VF_MAX_VTX_NUM_SHIFT);
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION;
+ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION;
} else
/* not sure about non-tcl */
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (5 << R300_VF_MAX_VTX_NUM_SHIFT));
+ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R600_PVS_NUM_CNTLRS_SHIFT) |
+ (5 << R600_VF_MAX_VTX_NUM_SHIFT));
if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (2 << R300_PVS_NUM_FPUS_SHIFT);
+ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (2 << R600_PVS_NUM_FPUS_SHIFT);
else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
(rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
(rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (5 << R300_PVS_NUM_FPUS_SHIFT);
+ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (5 << R600_PVS_NUM_FPUS_SHIFT);
else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
(rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (6 << R300_PVS_NUM_FPUS_SHIFT);
+ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (6 << R600_PVS_NUM_FPUS_SHIFT);
else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
(rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (8 << R300_PVS_NUM_FPUS_SHIFT);
+ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (8 << R600_PVS_NUM_FPUS_SHIFT);
else
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (4 << R300_PVS_NUM_FPUS_SHIFT);
+ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (4 << R600_PVS_NUM_FPUS_SHIFT);
}
-static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
+static void r600SetupDefaultVertexProgram(r600ContextPtr rmesa)
{
- struct r300_vertex_shader_state *prog = &(rmesa->state.vertex_shader);
+ struct r600_vertex_shader_state *prog = &(rmesa->state.vertex_shader);
GLuint o_reg = 0;
GLuint i_reg = 0;
int i;
prog->program.length = program_end;
- r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START,
+ r600SetupVertexProgramFragment(rmesa, R600_PVS_CODE_START,
&(prog->program));
inst_count = (prog->program.length / 4) - 1;
- r300VapCntl(rmesa, i_reg, o_reg, 0);
+ r600VapCntl(rmesa, i_reg, o_reg, 0);
- R300_STATECHANGE(rmesa, pvs);
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] =
- (0 << R300_PVS_FIRST_INST_SHIFT) |
- (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (inst_count << R300_PVS_LAST_INST_SHIFT);
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] =
- (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
- (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT);
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] =
- (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
+ R600_STATECHANGE(rmesa, pvs);
+ rmesa->hw.pvs.cmd[R600_PVS_CNTL_1] =
+ (0 << R600_PVS_FIRST_INST_SHIFT) |
+ (inst_count << R600_PVS_XYZW_VALID_INST_SHIFT) |
+ (inst_count << R600_PVS_LAST_INST_SHIFT);
+ rmesa->hw.pvs.cmd[R600_PVS_CNTL_2] =
+ (0 << R600_PVS_CONST_BASE_OFFSET_SHIFT) |
+ (param_count << R600_PVS_MAX_CONST_ADDR_SHIFT);
+ rmesa->hw.pvs.cmd[R600_PVS_CNTL_3] =
+ (inst_count << R600_PVS_LAST_VTX_SRC_INST_SHIFT);
}
static int bit_count (int x)
return (x >> 8) + (x & 0x00ff);
}
-static void r300SetupRealVertexProgram(r300ContextPtr rmesa)
+static void r600SetupRealVertexProgram(r600ContextPtr rmesa)
{
GLcontext *ctx = rmesa->radeon.glCtx;
- struct r300_vertex_program *prog = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
+ struct r600_vertex_program *prog = (struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
int inst_count = 0;
int param_count = 0;
- /* FIXME: r300SetupVertexProgramFragment */
- R300_STATECHANGE(rmesa, vpp);
+ /* FIXME: r600SetupVertexProgramFragment */
+ R600_STATECHANGE(rmesa, vpp);
param_count =
- r300VertexProgUpdateParams(ctx,
- (struct r300_vertex_program_cont *)
+ r600VertexProgUpdateParams(ctx,
+ (struct r600_vertex_program_cont *)
ctx->VertexProgram._Current,
(float *)&rmesa->hw.vpp.
- cmd[R300_VPP_PARAM_0]);
+ cmd[R600_VPP_PARAM_0]);
bump_vpu_count(rmesa->hw.vpp.cmd, param_count);
param_count /= 4;
- r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START, &(prog->program));
+ r600SetupVertexProgramFragment(rmesa, R600_PVS_CODE_START, &(prog->program));
inst_count = (prog->program.length / 4) - 1;
- r300VapCntl(rmesa, bit_count(prog->key.InputsRead),
+ r600VapCntl(rmesa, bit_count(prog->key.InputsRead),
bit_count(prog->key.OutputsWritten), prog->num_temporaries);
- R300_STATECHANGE(rmesa, pvs);
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] =
- (0 << R300_PVS_FIRST_INST_SHIFT) |
- (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (inst_count << R300_PVS_LAST_INST_SHIFT);
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] =
- (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
- (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT);
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] =
- (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
+ R600_STATECHANGE(rmesa, pvs);
+ rmesa->hw.pvs.cmd[R600_PVS_CNTL_1] =
+ (0 << R600_PVS_FIRST_INST_SHIFT) |
+ (inst_count << R600_PVS_XYZW_VALID_INST_SHIFT) |
+ (inst_count << R600_PVS_LAST_INST_SHIFT);
+ rmesa->hw.pvs.cmd[R600_PVS_CNTL_2] =
+ (0 << R600_PVS_CONST_BASE_OFFSET_SHIFT) |
+ (param_count << R600_PVS_MAX_CONST_ADDR_SHIFT);
+ rmesa->hw.pvs.cmd[R600_PVS_CNTL_3] =
+ (inst_count << R600_PVS_LAST_VTX_SRC_INST_SHIFT);
}
-static void r300SetupVertexProgram(r300ContextPtr rmesa)
+static void r600SetupVertexProgram(r600ContextPtr rmesa)
{
GLcontext *ctx = rmesa->radeon.glCtx;
0x400 area might have something to do with pixel shaders as it appears right after pfs programming.
0x406 is set to { 0.0, 0.0, 1.0, 0.0 } most of the time but should change with smooth points and in other rare cases. */
//setup_vertex_shader_fragment(rmesa, 0x406, &unk4);
- if (hw_tcl_on && ((struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx))->translated) {
- r300SetupRealVertexProgram(rmesa);
+ if (hw_tcl_on && ((struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx))->translated) {
+ r600SetupRealVertexProgram(rmesa);
} else {
/* FIXME: This needs to be replaced by vertex shader generation code. */
- r300SetupDefaultVertexProgram(rmesa);
+ r600SetupDefaultVertexProgram(rmesa);
}
}
*
* \note Mesa already filters redundant calls to this function.
*/
-static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
+static void r600Enable(GLcontext * ctx, GLenum cap, GLboolean state)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
_mesa_lookup_enum_by_nr(cap),
/* empty */
break;
case GL_ALPHA_TEST:
- r300SetAlphaState(ctx);
+ r600SetAlphaState(ctx);
break;
case GL_COLOR_LOGIC_OP:
- r300SetLogicOpState(ctx);
+ r600SetLogicOpState(ctx);
/* fall-through, because logic op overrides blending */
case GL_BLEND:
- r300SetBlendState(ctx);
+ r600SetBlendState(ctx);
break;
case GL_CLIP_PLANE0:
case GL_CLIP_PLANE1:
case GL_CLIP_PLANE3:
case GL_CLIP_PLANE4:
case GL_CLIP_PLANE5:
- r300SetClipPlaneState(ctx, cap, state);
+ r600SetClipPlaneState(ctx, cap, state);
break;
case GL_DEPTH_TEST:
- r300SetDepthState(ctx);
+ r600SetDepthState(ctx);
break;
case GL_STENCIL_TEST:
- r300SetStencilState(ctx, state);
+ r600SetStencilState(ctx, state);
break;
case GL_CULL_FACE:
- r300UpdateCulling(ctx);
+ r600UpdateCulling(ctx);
break;
case GL_POLYGON_OFFSET_POINT:
case GL_POLYGON_OFFSET_LINE:
case GL_POLYGON_OFFSET_FILL:
- r300SetPolygonOffsetState(ctx, state);
+ r600SetPolygonOffsetState(ctx, state);
break;
case GL_SCISSOR_TEST:
radeon_firevertices(&rmesa->radeon);
/**
* Completely recalculates hardware state based on the Mesa state.
*/
-static void r300ResetHwState(r300ContextPtr r300)
+static void r600ResetHwState(r600ContextPtr r600)
{
- GLcontext *ctx = r300->radeon.glCtx;
+ GLcontext *ctx = r600->radeon.glCtx;
int has_tcl = 1;
- if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
+ if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
has_tcl = 0;
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s\n", __FUNCTION__);
- radeon_firevertices(&r300->radeon);
+ radeon_firevertices(&r600->radeon);
- r300ColorMask(ctx,
+ r600ColorMask(ctx,
ctx->Color.ColorMask[RCOMP],
ctx->Color.ColorMask[GCOMP],
ctx->Color.ColorMask[BCOMP], ctx->Color.ColorMask[ACOMP]);
- r300Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
- r300DepthMask(ctx, ctx->Depth.Mask);
- r300DepthFunc(ctx, ctx->Depth.Func);
+ r600Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
+ r600DepthMask(ctx, ctx->Depth.Mask);
+ r600DepthFunc(ctx, ctx->Depth.Func);
/* stencil */
- r300Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
- r300StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
- r300StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
+ r600Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
+ r600StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
+ r600StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
- r300StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
+ r600StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
ctx->Stencil.ZFailFunc[0],
ctx->Stencil.ZPassFunc[0]);
- r300UpdateCulling(ctx);
+ r600UpdateCulling(ctx);
- r300SetBlendState(ctx);
- r300SetLogicOpState(ctx);
+ r600SetBlendState(ctx);
+ r600SetLogicOpState(ctx);
- r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
- r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
+ r600AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
+ r600Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
- r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
- | R300_VPORT_X_OFFSET_ENA
- | R300_VPORT_Y_SCALE_ENA
- | R300_VPORT_Y_OFFSET_ENA
- | R300_VPORT_Z_SCALE_ENA
- | R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT;
- r300->hw.vte.cmd[2] = 0x00000008;
+ r600->hw.vte.cmd[1] = R600_VPORT_X_SCALE_ENA
+ | R600_VPORT_X_OFFSET_ENA
+ | R600_VPORT_Y_SCALE_ENA
+ | R600_VPORT_Y_OFFSET_ENA
+ | R600_VPORT_Z_SCALE_ENA
+ | R600_VPORT_Z_OFFSET_ENA | R600_VTX_W0_FMT;
+ r600->hw.vte.cmd[2] = 0x00000008;
- r300->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF;
- r300->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000;
+ r600->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF;
+ r600->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000;
#ifdef MESA_LITTLE_ENDIAN
- r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP;
+ r600->hw.vap_cntl_status.cmd[1] = R600_VC_NO_SWAP;
#else
- r300->hw.vap_cntl_status.cmd[1] = R300_VC_32BIT_SWAP;
+ r600->hw.vap_cntl_status.cmd[1] = R600_VC_32BIT_SWAP;
#endif
/* disable VAP/TCL on non-TCL capable chips */
if (!has_tcl)
- r300->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS;
+ r600->hw.vap_cntl_status.cmd[1] |= R600_VAP_TCL_BYPASS;
- r300->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA;
+ r600->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA;
/* XXX: Other families? */
if (has_tcl) {
- r300->hw.vap_clip_cntl.cmd[1] = R300_PS_UCP_MODE_DIST_COP;
+ r600->hw.vap_clip_cntl.cmd[1] = R600_PS_UCP_MODE_DIST_COP;
- r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */
- r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */
- r300->hw.vap_clip.cmd[3] = r300PackFloat32(1.0); /* Y */
- r300->hw.vap_clip.cmd[4] = r300PackFloat32(1.0); /* Y */
+ r600->hw.vap_clip.cmd[1] = r600PackFloat32(1.0); /* X */
+ r600->hw.vap_clip.cmd[2] = r600PackFloat32(1.0); /* X */
+ r600->hw.vap_clip.cmd[3] = r600PackFloat32(1.0); /* Y */
+ r600->hw.vap_clip.cmd[4] = r600PackFloat32(1.0); /* Y */
- switch (r300->radeon.radeonScreen->chip_family) {
- case CHIP_FAMILY_R300:
- r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_R300;
+ switch (r600->radeon.radeonScreen->chip_family) {
+ case CHIP_FAMILY_R600:
+ r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_R600;
break;
default:
- r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_RV350;
+ r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_RV350;
break;
}
}
- r300->hw.gb_enable.cmd[1] = R300_GB_POINT_STUFF_ENABLE
- | R300_GB_LINE_STUFF_ENABLE
- | R300_GB_TRIANGLE_STUFF_ENABLE;
+ r600->hw.gb_enable.cmd[1] = R600_GB_POINT_STUFF_ENABLE
+ | R600_GB_LINE_STUFF_ENABLE
+ | R600_GB_TRIANGLE_STUFF_ENABLE;
- r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
- r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
+ r600->hw.gb_misc.cmd[R600_GB_MISC_MSPOS_0] = 0x66666666;
+ r600->hw.gb_misc.cmd[R600_GB_MISC_MSPOS_1] = 0x06666666;
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] =
- R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/;
- switch (r300->radeon.radeonScreen->num_gb_pipes) {
+ r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] =
+ R600_GB_TILE_ENABLE | R600_GB_TILE_SIZE_16 /*| R600_GB_SUBPIXEL_1_16*/;
+ switch (r600->radeon.radeonScreen->num_gb_pipes) {
case 1:
default:
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_RV300;
+ r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] |=
+ R600_GB_TILE_PIPE_COUNT_RV300;
break;
case 2:
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_R300;
+ r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] |=
+ R600_GB_TILE_PIPE_COUNT_R600;
break;
case 3:
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_R420_3P;
+ r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] |=
+ R600_GB_TILE_PIPE_COUNT_R420_3P;
break;
case 4:
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_R420;
+ r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] |=
+ R600_GB_TILE_PIPE_COUNT_R420;
break;
}
/* XXX: Enable anti-aliasing? */
- r300->hw.gb_misc.cmd[R300_GB_MISC_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE;
- r300->hw.gb_misc.cmd[R300_GB_MISC_SELECT] = 0;
+ r600->hw.gb_misc.cmd[R600_GB_MISC_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE;
+ r600->hw.gb_misc.cmd[R600_GB_MISC_SELECT] = 0;
- r300->hw.ga_point_s0.cmd[1] = r300PackFloat32(0.0);
- r300->hw.ga_point_s0.cmd[2] = r300PackFloat32(0.0);
- r300->hw.ga_point_s0.cmd[3] = r300PackFloat32(1.0);
- r300->hw.ga_point_s0.cmd[4] = r300PackFloat32(1.0);
+ r600->hw.ga_point_s0.cmd[1] = r600PackFloat32(0.0);
+ r600->hw.ga_point_s0.cmd[2] = r600PackFloat32(0.0);
+ r600->hw.ga_point_s0.cmd[3] = r600PackFloat32(1.0);
+ r600->hw.ga_point_s0.cmd[4] = r600PackFloat32(1.0);
- r300->hw.ga_triangle_stipple.cmd[1] = 0x00050005;
+ r600->hw.ga_triangle_stipple.cmd[1] = 0x00050005;
- r300PointSize(ctx, 1.0);
+ r600PointSize(ctx, 1.0);
- r300->hw.ga_point_minmax.cmd[1] = 0x18000006;
- r300->hw.ga_point_minmax.cmd[2] = 0x00020006;
- r300->hw.ga_point_minmax.cmd[3] = r300PackFloat32(1.0 / 192.0);
+ r600->hw.ga_point_minmax.cmd[1] = 0x18000006;
+ r600->hw.ga_point_minmax.cmd[2] = 0x00020006;
+ r600->hw.ga_point_minmax.cmd[3] = r600PackFloat32(1.0 / 192.0);
- r300LineWidth(ctx, 1.0);
+ r600LineWidth(ctx, 1.0);
- r300->hw.ga_line_stipple.cmd[1] = 0;
- r300->hw.ga_line_stipple.cmd[2] = r300PackFloat32(0.0);
- r300->hw.ga_line_stipple.cmd[3] = r300PackFloat32(1.0);
+ r600->hw.ga_line_stipple.cmd[1] = 0;
+ r600->hw.ga_line_stipple.cmd[2] = r600PackFloat32(0.0);
+ r600->hw.ga_line_stipple.cmd[3] = r600PackFloat32(1.0);
- r300ShadeModel(ctx, ctx->Light.ShadeModel);
+ r600ShadeModel(ctx, ctx->Light.ShadeModel);
- r300PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
- r300PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
- r300->hw.zbias_cntl.cmd[1] = 0x00000000;
+ r600PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
+ r600PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
+ r600->hw.zbias_cntl.cmd[1] = 0x00000000;
- r300PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
+ r600PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
ctx->Polygon.OffsetUnits);
- r300Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
- r300Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
- r300Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
+ r600Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
+ r600Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
+ r600Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
- r300->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF;
- r300->hw.su_depth_scale.cmd[2] = 0x00000000;
+ r600->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF;
+ r600->hw.su_depth_scale.cmd[2] = 0x00000000;
- r300->hw.sc_hyperz.cmd[1] = 0x0000001C;
- r300->hw.sc_hyperz.cmd[2] = 0x2DA49525;
+ r600->hw.sc_hyperz.cmd[1] = 0x0000001C;
+ r600->hw.sc_hyperz.cmd[2] = 0x2DA49525;
- r300->hw.sc_screendoor.cmd[1] = 0x00FFFFFF;
+ r600->hw.sc_screendoor.cmd[1] = 0x00FFFFFF;
- r300->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 |
+ r600->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 |
R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
- r300->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED |
+ r600->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED |
R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
- r300->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED |
+ r600->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED |
R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
- r300->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED |
+ r600->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED |
R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
- r300->hw.us_out_fmt.cmd[5] = R300_W_FMT_W0 | R300_W_SRC_US;
+ r600->hw.us_out_fmt.cmd[5] = R600_W_FMT_W0 | R600_W_SRC_US;
/* disable fog unit */
- r300->hw.fogs.cmd[R300_FOGS_STATE] = 0;
- r300->hw.fg_depth_src.cmd[1] = R300_FG_DEPTH_SRC_SCAN;
+ r600->hw.fogs.cmd[R600_FOGS_STATE] = 0;
+ r600->hw.fg_depth_src.cmd[1] = R600_FG_DEPTH_SRC_SCAN;
- r300->hw.rb3d_cctl.cmd[1] = 0;
+ r600->hw.rb3d_cctl.cmd[1] = 0;
- r300BlendColor(ctx, ctx->Color.BlendColor);
+ r600BlendColor(ctx, ctx->Color.BlendColor);
- r300->hw.rb3d_dither_ctl.cmd[1] = 0;
- r300->hw.rb3d_dither_ctl.cmd[2] = 0;
- r300->hw.rb3d_dither_ctl.cmd[3] = 0;
- r300->hw.rb3d_dither_ctl.cmd[4] = 0;
- r300->hw.rb3d_dither_ctl.cmd[5] = 0;
- r300->hw.rb3d_dither_ctl.cmd[6] = 0;
- r300->hw.rb3d_dither_ctl.cmd[7] = 0;
- r300->hw.rb3d_dither_ctl.cmd[8] = 0;
- r300->hw.rb3d_dither_ctl.cmd[9] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[1] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[2] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[3] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[4] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[5] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[6] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[7] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[8] = 0;
+ r600->hw.rb3d_dither_ctl.cmd[9] = 0;
- r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0;
+ r600->hw.rb3d_aaresolve_ctl.cmd[1] = 0;
- r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
- r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
+ r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
+ r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
- r300->hw.zb_depthclearvalue.cmd[1] = 0;
+ r600->hw.zb_depthclearvalue.cmd[1] = 0;
- r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE;
- r300->hw.zstencil_format.cmd[3] = 0x00000003;
- r300->hw.zstencil_format.cmd[4] = 0x00000000;
- r300SetEarlyZState(ctx);
+ r600->hw.zstencil_format.cmd[2] = R600_ZTOP_DISABLE;
+ r600->hw.zstencil_format.cmd[3] = 0x00000003;
+ r600->hw.zstencil_format.cmd[4] = 0x00000000;
+ r600SetEarlyZState(ctx);
- r300->hw.unk4F30.cmd[1] = 0;
- r300->hw.unk4F30.cmd[2] = 0;
+ r600->hw.unk4F30.cmd[1] = 0;
+ r600->hw.unk4F30.cmd[2] = 0;
- r300->hw.zb_hiz_offset.cmd[1] = 0;
+ r600->hw.zb_hiz_offset.cmd[1] = 0;
- r300->hw.zb_hiz_pitch.cmd[1] = 0;
+ r600->hw.zb_hiz_pitch.cmd[1] = 0;
- r300VapCntl(r300, 0, 0, 0);
+ r600VapCntl(r600, 0, 0, 0);
if (has_tcl) {
- r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0;
- r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0;
- r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0);
- r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0;
+ r600->hw.vps.cmd[R600_VPS_ZERO_0] = 0;
+ r600->hw.vps.cmd[R600_VPS_ZERO_1] = 0;
+ r600->hw.vps.cmd[R600_VPS_POINTSIZE] = r600PackFloat32(1.0);
+ r600->hw.vps.cmd[R600_VPS_ZERO_3] = 0;
}
- r300->radeon.hw.all_dirty = GL_TRUE;
+ r600->radeon.hw.all_dirty = GL_TRUE;
}
-void r300UpdateShaders(r300ContextPtr rmesa)
+void r600UpdateShaders(r600ContextPtr rmesa)
{
GLcontext *ctx;
- struct r300_vertex_program *vp;
+ struct r600_vertex_program *vp;
int i;
ctx = rmesa->radeon.glCtx;
rmesa->temp_attrib[i];
}
- r300SelectVertexShader(rmesa);
- vp = (struct r300_vertex_program *)
+ r600SelectVertexShader(rmesa);
+ vp = (struct r600_vertex_program *)
CURRENT_VERTEX_SHADER(ctx);
/*if (vp->translated == GL_FALSE)
- r300TranslateVertexShader(vp); */
+ r600TranslateVertexShader(vp); */
if (vp->translated == GL_FALSE) {
fprintf(stderr, "Failing back to sw-tcl\n");
hw_tcl_on = future_hw_tcl_on = 0;
- r300ResetHwState(rmesa);
+ r600ResetHwState(rmesa);
- r300UpdateStateParameters(ctx, _NEW_PROGRAM);
+ r600UpdateStateParameters(ctx, _NEW_PROGRAM);
return;
}
}
- r300UpdateStateParameters(ctx, _NEW_PROGRAM);
+ r600UpdateStateParameters(ctx, _NEW_PROGRAM);
}
static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx,
}
-static void r300SetupPixelShader(r300ContextPtr rmesa)
+static void r600SetupPixelShader(r600ContextPtr rmesa)
{
GLcontext *ctx = rmesa->radeon.glCtx;
- struct r300_fragment_program *fp = (struct r300_fragment_program *)
+ struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
- struct r300_fragment_program_code *code;
+ struct r600_fragment_program_code *code;
int i, k;
if (!fp) /* should only happenen once, just after context is created */
return;
- r300TranslateFragmentShader(rmesa, fp);
+ r600TranslateFragmentShader(rmesa, fp);
if (!fp->translated) {
fprintf(stderr, "%s: No valid fragment shader, exiting\n",
__FUNCTION__);
}
code = &fp->code;
- r300SetupTextures(ctx);
+ r600SetupTextures(ctx);
- R300_STATECHANGE(rmesa, fpi[0]);
- R300_STATECHANGE(rmesa, fpi[1]);
- R300_STATECHANGE(rmesa, fpi[2]);
- R300_STATECHANGE(rmesa, fpi[3]);
- rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, code->alu.length);
- rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, code->alu.length);
- rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, code->alu.length);
- rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
+ R600_STATECHANGE(rmesa, fpi[0]);
+ R600_STATECHANGE(rmesa, fpi[1]);
+ R600_STATECHANGE(rmesa, fpi[2]);
+ R600_STATECHANGE(rmesa, fpi[3]);
+ rmesa->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, code->alu.length);
+ rmesa->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, code->alu.length);
+ rmesa->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, code->alu.length);
+ rmesa->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, code->alu.length);
for (i = 0; i < code->alu.length; i++) {
- rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0;
- rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1;
- rmesa->hw.fpi[2].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst2;
- rmesa->hw.fpi[3].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst3;
- }
-
- R300_STATECHANGE(rmesa, fp);
- rmesa->hw.fp.cmd[R300_FP_CNTL0] = code->cur_node | (code->first_node_has_tex << 3);
- rmesa->hw.fp.cmd[R300_FP_CNTL1] = code->max_temp_idx;
- rmesa->hw.fp.cmd[R300_FP_CNTL2] =
- (0 << R300_PFS_CNTL_ALU_OFFSET_SHIFT) |
- ((code->alu.length-1) << R300_PFS_CNTL_ALU_END_SHIFT) |
- (0 << R300_PFS_CNTL_TEX_OFFSET_SHIFT) |
- ((code->tex.length ? code->tex.length-1 : 0) << R300_PFS_CNTL_TEX_END_SHIFT);
+ rmesa->hw.fpi[0].cmd[R600_FPI_INSTR_0 + i] = code->alu.inst[i].inst0;
+ rmesa->hw.fpi[1].cmd[R600_FPI_INSTR_0 + i] = code->alu.inst[i].inst1;
+ rmesa->hw.fpi[2].cmd[R600_FPI_INSTR_0 + i] = code->alu.inst[i].inst2;
+ rmesa->hw.fpi[3].cmd[R600_FPI_INSTR_0 + i] = code->alu.inst[i].inst3;
+ }
+
+ R600_STATECHANGE(rmesa, fp);
+ rmesa->hw.fp.cmd[R600_FP_CNTL0] = code->cur_node | (code->first_node_has_tex << 3);
+ rmesa->hw.fp.cmd[R600_FP_CNTL1] = code->max_temp_idx;
+ rmesa->hw.fp.cmd[R600_FP_CNTL2] =
+ (0 << R600_PFS_CNTL_ALU_OFFSET_SHIFT) |
+ ((code->alu.length-1) << R600_PFS_CNTL_ALU_END_SHIFT) |
+ (0 << R600_PFS_CNTL_TEX_OFFSET_SHIFT) |
+ ((code->tex.length ? code->tex.length-1 : 0) << R600_PFS_CNTL_TEX_END_SHIFT);
/* I just want to say, the way these nodes are stored.. weird.. */
for (i = 0, k = (4 - (code->cur_node + 1)); i < 4; i++, k++) {
if (i < (code->cur_node + 1)) {
- rmesa->hw.fp.cmd[R300_FP_NODE0 + k] =
- (code->node[i].alu_offset << R300_ALU_START_SHIFT) |
- (code->node[i].alu_end << R300_ALU_SIZE_SHIFT) |
- (code->node[i].tex_offset << R300_TEX_START_SHIFT) |
- (code->node[i].tex_end << R300_TEX_SIZE_SHIFT) |
+ rmesa->hw.fp.cmd[R600_FP_NODE0 + k] =
+ (code->node[i].alu_offset << R600_ALU_START_SHIFT) |
+ (code->node[i].alu_end << R600_ALU_SIZE_SHIFT) |
+ (code->node[i].tex_offset << R600_TEX_START_SHIFT) |
+ (code->node[i].tex_end << R600_TEX_SIZE_SHIFT) |
code->node[i].flags;
} else {
- rmesa->hw.fp.cmd[R300_FP_NODE0 + (3 - i)] = 0;
+ rmesa->hw.fp.cmd[R600_FP_NODE0 + (3 - i)] = 0;
}
}
- R300_STATECHANGE(rmesa, fpp);
- rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_PFS_PARAM_0_X, code->const_nr * 4);
+ R600_STATECHANGE(rmesa, fpp);
+ rmesa->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_PFS_PARAM_0_X, code->const_nr * 4);
for (i = 0; i < code->const_nr; i++) {
const GLfloat *constant = get_fragmentprogram_constant(ctx,
&fp->mesa_program.Base, code->constant[i]);
- rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(constant[0]);
- rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(constant[1]);
- rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]);
- rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(constant[3]);
+ rmesa->hw.fpp.cmd[R600_FPP_PARAM_0 + 4 * i + 0] = r600PackFloat24(constant[0]);
+ rmesa->hw.fpp.cmd[R600_FPP_PARAM_0 + 4 * i + 1] = r600PackFloat24(constant[1]);
+ rmesa->hw.fpp.cmd[R600_FPP_PARAM_0 + 4 * i + 2] = r600PackFloat24(constant[2]);
+ rmesa->hw.fpp.cmd[R600_FPP_PARAM_0 + 4 * i + 3] = r600PackFloat24(constant[3]);
}
}
if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
} while(0)
-static void r500SetupPixelShader(r300ContextPtr rmesa)
+static void r500SetupPixelShader(r600ContextPtr rmesa)
{
GLcontext *ctx = rmesa->radeon.glCtx;
struct r500_fragment_program *fp = (struct r500_fragment_program *)
}
code = &fp->code;
- r300SetupTextures(ctx);
+ r600SetupTextures(ctx);
- R300_STATECHANGE(rmesa, fp);
+ R600_STATECHANGE(rmesa, fp);
rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx;
rmesa->hw.fp.cmd[R500_FP_CODE_ADDR] =
rmesa->hw.fp.cmd[R500_FP_CODE_OFFSET] =
R500_US_CODE_OFFSET_ADDR(0); /* FIXME when we add flow control */
- R300_STATECHANGE(rmesa, r500fp);
+ R600_STATECHANGE(rmesa, r500fp);
/* Emit our shader... */
for (i = 0; i < code->inst_end+1; i++) {
rmesa->hw.r500fp.cmd[i*6+1] = code->inst[i].inst0;
bump_r500fp_count(rmesa->hw.r500fp.cmd, (code->inst_end + 1) * 6);
- R300_STATECHANGE(rmesa, r500fp_const);
+ R600_STATECHANGE(rmesa, r500fp_const);
for (i = 0; i < code->const_nr; i++) {
const GLfloat *constant = get_fragmentprogram_constant(ctx,
&fp->mesa_program.Base, code->constant[i]);
- rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat32(constant[0]);
- rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat32(constant[1]);
- rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat32(constant[2]);
- rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat32(constant[3]);
+ rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 0] = r600PackFloat32(constant[0]);
+ rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 1] = r600PackFloat32(constant[1]);
+ rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 2] = r600PackFloat32(constant[2]);
+ rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 3] = r600PackFloat32(constant[3]);
}
bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4);
}
-void r300UpdateShaderStates(r300ContextPtr rmesa)
+void r600UpdateShaderStates(r600ContextPtr rmesa)
{
GLcontext *ctx;
ctx = rmesa->radeon.glCtx;
- r300SetEarlyZState(ctx);
+ r600SetEarlyZState(ctx);
/* w_fmt value is set to get best performance
* see p.130 R5xx 3D acceleration guide v1.3 */
GLuint w_fmt, fgdepthsrc;
if (current_fragment_program_writes_depth(ctx)) {
- fgdepthsrc = R300_FG_DEPTH_SRC_SHADER;
- w_fmt = R300_W_FMT_W24 | R300_W_SRC_US;
+ fgdepthsrc = R600_FG_DEPTH_SRC_SHADER;
+ w_fmt = R600_W_FMT_W24 | R600_W_SRC_US;
} else {
- fgdepthsrc = R300_FG_DEPTH_SRC_SCAN;
- w_fmt = R300_W_FMT_W0 | R300_W_SRC_US;
+ fgdepthsrc = R600_FG_DEPTH_SRC_SCAN;
+ w_fmt = R600_W_FMT_W0 | R600_W_SRC_US;
}
if (w_fmt != rmesa->hw.us_out_fmt.cmd[5]) {
- R300_STATECHANGE(rmesa, us_out_fmt);
+ R600_STATECHANGE(rmesa, us_out_fmt);
rmesa->hw.us_out_fmt.cmd[5] = w_fmt;
}
if (fgdepthsrc != rmesa->hw.fg_depth_src.cmd[1]) {
- R300_STATECHANGE(rmesa, fg_depth_src);
+ R600_STATECHANGE(rmesa, fg_depth_src);
rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc;
}
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
r500SetupPixelShader(rmesa);
else
- r300SetupPixelShader(rmesa);
+ r600SetupPixelShader(rmesa);
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
r500SetupRSUnit(ctx);
else
- r300SetupRSUnit(ctx);
+ r600SetupRSUnit(ctx);
if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
- r300SetupVertexProgram(rmesa);
+ r600SetupVertexProgram(rmesa);
}
/**
* Called by Mesa after an internal state update.
*/
-static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
+static void r600InvalidateState(GLcontext * ctx, GLuint new_state)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
+ r600ContextPtr r600 = R600_CONTEXT(ctx);
_swrast_InvalidateState(ctx, new_state);
_swsetup_InvalidateState(ctx, new_state);
/* this updates the DrawBuffer's Width/Height if it's a FBO */
_mesa_update_draw_buffer_bounds(ctx);
- R300_STATECHANGE(r300, cb);
+ R600_STATECHANGE(r600, cb);
}
- r300UpdateStateParameters(ctx, new_state);
+ r600UpdateStateParameters(ctx, new_state);
- r300->radeon.NewGLState |= new_state;
+ r600->radeon.NewGLState |= new_state;
}
/**
* Assumes that the command buffer and state atoms have been
* initialized already.
*/
-void r300InitState(r300ContextPtr r300)
+void r600InitState(r600ContextPtr r600)
{
- memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
+ memset(&(r600->state.texture), 0, sizeof(r600->state.texture));
- r300ResetHwState(r300);
+ r600ResetHwState(r600);
}
-static void r300RenderMode(GLcontext * ctx, GLenum mode)
+static void r600RenderMode(GLcontext * ctx, GLenum mode)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
(void)rmesa;
(void)mode;
}
-void r300UpdateClipPlanes( GLcontext *ctx )
+void r600UpdateClipPlanes( GLcontext *ctx )
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLuint p;
for (p = 0; p < ctx->Const.MaxClipPlanes; p++) {
if (ctx->Transform.ClipPlanesEnabled & (1 << p)) {
GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
- R300_STATECHANGE( rmesa, vpucp[p] );
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
+ R600_STATECHANGE( rmesa, vpucp[p] );
+ rmesa->hw.vpucp[p].cmd[R600_VPUCP_X] = ip[0];
+ rmesa->hw.vpucp[p].cmd[R600_VPUCP_Y] = ip[1];
+ rmesa->hw.vpucp[p].cmd[R600_VPUCP_Z] = ip[2];
+ rmesa->hw.vpucp[p].cmd[R600_VPUCP_W] = ip[3];
}
}
}
/**
* Initialize driver's state callback functions
*/
-void r300InitStateFuncs(struct dd_function_table *functions)
-{
-
- functions->UpdateState = r300InvalidateState;
- functions->AlphaFunc = r300AlphaFunc;
- functions->BlendColor = r300BlendColor;
- functions->BlendEquationSeparate = r300BlendEquationSeparate;
- functions->BlendFuncSeparate = r300BlendFuncSeparate;
- functions->Enable = r300Enable;
- functions->ColorMask = r300ColorMask;
- functions->DepthFunc = r300DepthFunc;
- functions->DepthMask = r300DepthMask;
- functions->CullFace = r300CullFace;
- functions->FrontFace = r300FrontFace;
- functions->ShadeModel = r300ShadeModel;
- functions->LogicOpcode = r300LogicOpcode;
+void r600InitStateFuncs(struct dd_function_table *functions)
+{
+
+ functions->UpdateState = r600InvalidateState;
+ functions->AlphaFunc = r600AlphaFunc;
+ functions->BlendColor = r600BlendColor;
+ functions->BlendEquationSeparate = r600BlendEquationSeparate;
+ functions->BlendFuncSeparate = r600BlendFuncSeparate;
+ functions->Enable = r600Enable;
+ functions->ColorMask = r600ColorMask;
+ functions->DepthFunc = r600DepthFunc;
+ functions->DepthMask = r600DepthMask;
+ functions->CullFace = r600CullFace;
+ functions->FrontFace = r600FrontFace;
+ functions->ShadeModel = r600ShadeModel;
+ functions->LogicOpcode = r600LogicOpcode;
/* ARB_point_parameters */
- functions->PointParameterfv = r300PointParameter;
+ functions->PointParameterfv = r600PointParameter;
/* Stencil related */
- functions->StencilFuncSeparate = r300StencilFuncSeparate;
- functions->StencilMaskSeparate = r300StencilMaskSeparate;
- functions->StencilOpSeparate = r300StencilOpSeparate;
+ functions->StencilFuncSeparate = r600StencilFuncSeparate;
+ functions->StencilMaskSeparate = r600StencilMaskSeparate;
+ functions->StencilOpSeparate = r600StencilOpSeparate;
/* Viewport related */
- functions->Viewport = r300Viewport;
- functions->DepthRange = r300DepthRange;
- functions->PointSize = r300PointSize;
- functions->LineWidth = r300LineWidth;
+ functions->Viewport = r600Viewport;
+ functions->DepthRange = r600DepthRange;
+ functions->PointSize = r600PointSize;
+ functions->LineWidth = r600LineWidth;
- functions->PolygonOffset = r300PolygonOffset;
- functions->PolygonMode = r300PolygonMode;
+ functions->PolygonOffset = r600PolygonOffset;
+ functions->PolygonMode = r600PolygonMode;
- functions->RenderMode = r300RenderMode;
+ functions->RenderMode = r600RenderMode;
- functions->ClipPlane = r300ClipPlane;
+ functions->ClipPlane = r600ClipPlane;
functions->Scissor = radeonScissor;
functions->DrawBuffer = radeonDrawBuffer;
#include "r600_context.h"
-#define R300_NEWPRIM( rmesa ) \
+#define R600_NEWPRIM( rmesa ) \
do { \
if ( rmesa->radeon.dma.flush ) \
rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
} while (0)
-#define R300_STATECHANGE(r300, atom) \
+#define R600_STATECHANGE(r600, atom) \
do { \
- R300_NEWPRIM(r300); \
- r300->hw.atom.dirty = GL_TRUE; \
- r300->radeon.hw.is_dirty = GL_TRUE; \
+ R600_NEWPRIM(r600); \
+ r600->hw.atom.dirty = GL_TRUE; \
+ r600->radeon.hw.is_dirty = GL_TRUE; \
} while(0)
-// r300_state.c
+// r600_state.c
extern int future_hw_tcl_on;
void _tnl_UpdateFixedFunctionProgram (GLcontext * ctx);
-void r300UpdateViewportOffset (GLcontext * ctx);
-void r300UpdateDrawBuffer (GLcontext * ctx);
-void r300UpdateStateParameters (GLcontext * ctx, GLuint new_state);
-void r300UpdateShaders (r300ContextPtr rmesa);
-void r300UpdateShaderStates (r300ContextPtr rmesa);
-void r300InitState (r300ContextPtr r300);
-void r300UpdateClipPlanes (GLcontext * ctx);
-void r300InitStateFuncs (struct dd_function_table *functions);
+void r600UpdateViewportOffset (GLcontext * ctx);
+void r600UpdateDrawBuffer (GLcontext * ctx);
+void r600UpdateStateParameters (GLcontext * ctx, GLuint new_state);
+void r600UpdateShaders (r600ContextPtr rmesa);
+void r600UpdateShaderStates (r600ContextPtr rmesa);
+void r600InitState (r600ContextPtr r600);
+void r600UpdateClipPlanes (GLcontext * ctx);
+void r600InitStateFuncs (struct dd_function_table *functions);
-#endif /* __R300_STATE_H__ */
+#endif /* __R600_STATE_H__ */
++num_attrs; \
} while (0)
-static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten)
+static void r600SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten)
{
- r300ContextPtr rmesa = R300_CONTEXT( ctx );
+ r600ContextPtr rmesa = R600_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs;
uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1];
uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1];
- for (i = 0; i < R300_VIR_CMDSIZE-1; ++i)
+ for (i = 0; i < R600_VIR_CMDSIZE-1; ++i)
vir0[i] = vir1[i] = 0;
for (i = 0, j = 0; i < rmesa->radeon.swtcl.vertex_attr_count; ++i) {
int tmp, data_format;
switch (attrs[i].format) {
case EMIT_1F:
- data_format = R300_DATA_TYPE_FLOAT_1;
+ data_format = R600_DATA_TYPE_FLOAT_1;
break;
case EMIT_2F:
- data_format = R300_DATA_TYPE_FLOAT_2;
+ data_format = R600_DATA_TYPE_FLOAT_2;
break;
case EMIT_3F:
- data_format = R300_DATA_TYPE_FLOAT_3;
+ data_format = R600_DATA_TYPE_FLOAT_3;
break;
case EMIT_4F:
- data_format = R300_DATA_TYPE_FLOAT_4;
+ data_format = R600_DATA_TYPE_FLOAT_4;
break;
case EMIT_4UB_4F_RGBA:
case EMIT_4UB_4F_ABGR:
- data_format = R300_DATA_TYPE_BYTE | R300_NORMALIZE;
+ data_format = R600_DATA_TYPE_BYTE | R600_NORMALIZE;
break;
default:
fprintf(stderr, "%s: Invalid data format type", __FUNCTION__);
break;
}
- tmp = data_format | (attrs[i].dst_loc << R300_DST_VEC_LOC_SHIFT);
+ tmp = data_format | (attrs[i].dst_loc << R600_DST_VEC_LOC_SHIFT);
if (i % 2 == 0) {
- vir0[j] = tmp << R300_DATA_TYPE_0_SHIFT;
- vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT);
+ vir0[j] = tmp << R600_DATA_TYPE_0_SHIFT;
+ vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R600_WRITE_ENA_SHIFT);
} else {
- vir0[j] |= tmp << R300_DATA_TYPE_1_SHIFT;
- vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT;
+ vir0[j] |= tmp << R600_DATA_TYPE_1_SHIFT;
+ vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE1_SHIFT;
++j;
}
}
reg_count = (rmesa->radeon.swtcl.vertex_attr_count + 1) >> 1;
if (rmesa->radeon.swtcl.vertex_attr_count % 2 != 0) {
- vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
+ vir0[reg_count-1] |= R600_LAST_VEC << R600_DATA_TYPE_0_SHIFT;
} else {
- vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
+ vir0[reg_count-1] |= R600_LAST_VEC << R600_DATA_TYPE_1_SHIFT;
}
- R300_STATECHANGE(rmesa, vir[0]);
- R300_STATECHANGE(rmesa, vir[1]);
- R300_STATECHANGE(rmesa, vof);
- R300_STATECHANGE(rmesa, vte);
- R300_STATECHANGE(rmesa, vic);
+ R600_STATECHANGE(rmesa, vir[0]);
+ R600_STATECHANGE(rmesa, vir[1]);
+ R600_STATECHANGE(rmesa, vof);
+ R600_STATECHANGE(rmesa, vte);
+ R600_STATECHANGE(rmesa, vic);
if (rmesa->radeon.radeonScreen->kernel_mm) {
rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF;
((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count;
}
- rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead);
- rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead);
- rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten);
- rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten);
+ rmesa->hw.vic.cmd[R600_VIC_CNTL_0] = r600VAPInputCntl0(ctx, InputsRead);
+ rmesa->hw.vic.cmd[R600_VIC_CNTL_1] = r600VAPInputCntl1(ctx, InputsRead);
+ rmesa->hw.vof.cmd[R600_VOF_CNTL_0] = r600VAPOutputCntl0(ctx, OutputsWritten);
+ rmesa->hw.vof.cmd[R600_VOF_CNTL_1] = r600VAPOutputCntl1(ctx, OutputsWritten);
vte = rmesa->hw.vte.cmd[1];
- vte &= ~(R300_VTX_XY_FMT | R300_VTX_Z_FMT | R300_VTX_W0_FMT);
+ vte &= ~(R600_VTX_XY_FMT | R600_VTX_Z_FMT | R600_VTX_W0_FMT);
/* Important:
*/
if ( VB->NdcPtr != NULL ) {
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
- vte |= R300_VTX_XY_FMT | R300_VTX_Z_FMT;
+ vte |= R600_VTX_XY_FMT | R600_VTX_Z_FMT;
}
else {
VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
- vte |= R300_VTX_W0_FMT;
+ vte |= R600_VTX_W0_FMT;
}
assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
}
-static void r300SetVertexFormat( GLcontext *ctx )
+static void r600SetVertexFormat( GLcontext *ctx )
{
- r300ContextPtr rmesa = R300_CONTEXT( ctx );
+ r600ContextPtr rmesa = R600_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
int fog_id = -1;
ADD_ATTR(VERT_ATTRIB_TEX0 + first_free_tex, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW);
}
- R300_NEWPRIM(rmesa);
- r300SwtclVAPSetup(ctx, InputsRead, OutputsWritten);
+ R600_NEWPRIM(rmesa);
+ r600SwtclVAPSetup(ctx, InputsRead, OutputsWritten);
rmesa->radeon.swtcl.vertex_size =
_tnl_install_attrs( ctx,
GL_TRIANGLES,
};
-static void r300RasterPrimitive( GLcontext *ctx, GLuint prim );
-static void r300RenderPrimitive( GLcontext *ctx, GLenum prim );
+static void r600RasterPrimitive( GLcontext *ctx, GLuint prim );
+static void r600RenderPrimitive( GLcontext *ctx, GLenum prim );
/***********************************************************************
* Emit primitives as inline vertices *
#undef LOCAL_VARS
#undef ALLOC_VERTS
-#define CTX_ARG r300ContextPtr rmesa
+#define CTX_ARG r600ContextPtr rmesa
#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 )
#define LOCAL_VARS \
- r300ContextPtr rmesa = R300_CONTEXT(ctx); \
- const char *r300verts = (char *)rmesa->radeon.swtcl.verts;
-#define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int)))
-#define VERTEX r300Vertex
+ r600ContextPtr rmesa = R600_CONTEXT(ctx); \
+ const char *r600verts = (char *)rmesa->radeon.swtcl.verts;
+#define VERT(x) (r600Vertex *)(r600verts + ((x) * vertsize * sizeof(int)))
+#define VERTEX r600Vertex
#undef TAG
-#define TAG(x) r300_##x
+#define TAG(x) r600_##x
#include "tnl_dd/t_dd_triemit.h"
* Macros for t_dd_tritmp.h to draw basic primitives *
***********************************************************************/
-#define QUAD( a, b, c, d ) r300_quad( rmesa, a, b, c, d )
-#define TRI( a, b, c ) r300_triangle( rmesa, a, b, c )
-#define LINE( a, b ) r300_line( rmesa, a, b )
-#define POINT( a ) r300_point( rmesa, a )
+#define QUAD( a, b, c, d ) r600_quad( rmesa, a, b, c, d )
+#define TRI( a, b, c ) r600_triangle( rmesa, a, b, c )
+#define LINE( a, b ) r600_line( rmesa, a, b )
+#define POINT( a ) r600_point( rmesa, a )
/***********************************************************************
* Build render functions from dd templates *
***********************************************************************/
-#define R300_TWOSIDE_BIT 0x01
-#define R300_UNFILLED_BIT 0x02
-#define R300_MAX_TRIFUNC 0x04
+#define R600_TWOSIDE_BIT 0x01
+#define R600_UNFILLED_BIT 0x02
+#define R600_MAX_TRIFUNC 0x04
static struct {
tnl_points_func points;
tnl_line_func line;
tnl_triangle_func triangle;
tnl_quad_func quad;
-} rast_tab[R300_MAX_TRIFUNC];
+} rast_tab[R600_MAX_TRIFUNC];
#define DO_FALLBACK 0
-#define DO_UNFILLED (IND & R300_UNFILLED_BIT)
-#define DO_TWOSIDE (IND & R300_TWOSIDE_BIT)
+#define DO_UNFILLED (IND & R600_UNFILLED_BIT)
+#define DO_TWOSIDE (IND & R600_TWOSIDE_BIT)
#define DO_FLAT 0
#define DO_OFFSET 0
#define DO_TRI 1
#define VERT_SET_RGBA( v, c ) \
do { \
- r300_color_t *color = (r300_color_t *)&((v)->ui[coloroffset]); \
+ r600_color_t *color = (r600_color_t *)&((v)->ui[coloroffset]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
#undef INIT
#define LOCAL_VARS(n) \
- r300ContextPtr rmesa = R300_CONTEXT(ctx); \
+ r600ContextPtr rmesa = R600_CONTEXT(ctx); \
GLuint color[n] = { 0, }, spec[n] = { 0, }; \
GLuint coloroffset = rmesa->swtcl.coloroffset; \
GLuint specoffset = rmesa->swtcl.specoffset; \
* Helpers for rendering unfilled primitives *
***********************************************************************/
-#define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] )
+#define RASTERIZE(x) r600RasterPrimitive( ctx, reduced_prim[x] )
#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
#undef TAG
#define TAG(x) x
#define TAG(x) x
#include "tnl_dd/t_dd_tritmp.h"
-#define IND (R300_TWOSIDE_BIT)
+#define IND (R600_TWOSIDE_BIT)
#define TAG(x) x##_twoside
#include "tnl_dd/t_dd_tritmp.h"
-#define IND (R300_UNFILLED_BIT)
+#define IND (R600_UNFILLED_BIT)
#define TAG(x) x##_unfilled
#include "tnl_dd/t_dd_tritmp.h"
-#define IND (R300_TWOSIDE_BIT|R300_UNFILLED_BIT)
+#define IND (R600_TWOSIDE_BIT|R600_UNFILLED_BIT)
#define TAG(x) x##_twoside_unfilled
#include "tnl_dd/t_dd_tritmp.h"
#define RENDER_POINTS( start, count ) \
for ( ; start < count ; start++) \
- r300_point( rmesa, VERT(start) )
+ r600_point( rmesa, VERT(start) )
#define RENDER_LINE( v0, v1 ) \
- r300_line( rmesa, VERT(v0), VERT(v1) )
+ r600_line( rmesa, VERT(v0), VERT(v1) )
#define RENDER_TRI( v0, v1, v2 ) \
- r300_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
+ r600_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
#define RENDER_QUAD( v0, v1, v2, v3 ) \
- r300_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
+ r600_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
#define INIT(x) do { \
- r300RenderPrimitive( ctx, x ); \
+ r600RenderPrimitive( ctx, x ); \
} while (0)
#undef LOCAL_VARS
#define LOCAL_VARS \
- r300ContextPtr rmesa = R300_CONTEXT(ctx); \
+ r600ContextPtr rmesa = R600_CONTEXT(ctx); \
const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \
- const char *r300verts = (char *)rmesa->radeon.swtcl.verts; \
+ const char *r600verts = (char *)rmesa->radeon.swtcl.verts; \
const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
const GLboolean stipple = ctx->Line.StippleFlag; \
(void) elt; (void) stipple;
#define RESET_OCCLUSION
#define PRESERVE_VB_DEFS
#define ELT(x) (x)
-#define TAG(x) r300_##x##_verts
+#define TAG(x) r600_##x##_verts
#include "tnl/t_vb_rendertmp.h"
#undef ELT
#undef TAG
-#define TAG(x) r300_##x##_elts
+#define TAG(x) r600_##x##_elts
#define ELT(x) elt[x]
#include "tnl/t_vb_rendertmp.h"
/**********************************************************************/
/* Choose render functions */
/**********************************************************************/
-static void r300ChooseRenderState( GLcontext *ctx )
+static void r600ChooseRenderState( GLcontext *ctx )
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLuint index = 0;
GLuint flags = ctx->_TriangleCaps;
- if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R300_TWOSIDE_BIT;
- if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT;
+ if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R600_TWOSIDE_BIT;
+ if (flags & DD_TRI_UNFILLED) index |= R600_UNFILLED_BIT;
if (index != rmesa->radeon.swtcl.RenderIndex) {
tnl->Driver.Render.Points = rast_tab[index].points;
tnl->Driver.Render.Quad = rast_tab[index].quad;
if (index == 0) {
- tnl->Driver.Render.PrimTabVerts = r300_render_tab_verts;
- tnl->Driver.Render.PrimTabElts = r300_render_tab_elts;
- tnl->Driver.Render.ClippedPolygon = r300_fast_clipped_poly;
+ tnl->Driver.Render.PrimTabVerts = r600_render_tab_verts;
+ tnl->Driver.Render.PrimTabElts = r600_render_tab_elts;
+ tnl->Driver.Render.ClippedPolygon = r600_fast_clipped_poly;
} else {
tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
}
-static void r300RenderStart(GLcontext *ctx)
+static void r600RenderStart(GLcontext *ctx)
{
- r300ContextPtr rmesa = R300_CONTEXT( ctx );
+ r600ContextPtr rmesa = R600_CONTEXT( ctx );
- r300ChooseRenderState(ctx);
- r300SetVertexFormat(ctx);
+ r600ChooseRenderState(ctx);
+ r600SetVertexFormat(ctx);
- r300ValidateBuffers(ctx);
+ r600ValidateBuffers(ctx);
- r300UpdateShaders(rmesa);
- r300UpdateShaderStates(rmesa);
+ r600UpdateShaders(rmesa);
+ r600UpdateShaderStates(rmesa);
- r300EmitCacheFlush(rmesa);
+ r600EmitCacheFlush(rmesa);
/* investigate if we can put back flush optimisation if needed */
if (rmesa->radeon.dma.flush != NULL) {
}
}
-static void r300RenderFinish(GLcontext *ctx)
+static void r600RenderFinish(GLcontext *ctx)
{
}
-static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim )
+static void r600RasterPrimitive( GLcontext *ctx, GLuint hwprim )
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
- R300_NEWPRIM( rmesa );
+ R600_NEWPRIM( rmesa );
rmesa->radeon.swtcl.hw_primitive = hwprim;
}
}
-static void r300RenderPrimitive(GLcontext *ctx, GLenum prim)
+static void r600RenderPrimitive(GLcontext *ctx, GLenum prim)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
rmesa->radeon.swtcl.render_primitive = prim;
if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED))
return;
- r300RasterPrimitive( ctx, reduced_prim[prim] );
+ r600RasterPrimitive( ctx, reduced_prim[prim] );
}
-static void r300ResetLineStipple(GLcontext *ctx)
+static void r600ResetLineStipple(GLcontext *ctx)
{
}
-void r300InitSwtcl(GLcontext *ctx)
+void r600InitSwtcl(GLcontext *ctx)
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
static int firsttime = 1;
if (firsttime) {
firsttime = 0;
}
- tnl->Driver.Render.Start = r300RenderStart;
- tnl->Driver.Render.Finish = r300RenderFinish;
- tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive;
- tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple;
+ tnl->Driver.Render.Start = r600RenderStart;
+ tnl->Driver.Render.Finish = r600RenderFinish;
+ tnl->Driver.Render.PrimitiveNotify = r600RenderPrimitive;
+ tnl->Driver.Render.ResetLineStipple = r600ResetLineStipple;
tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
tnl->Driver.Render.CopyPV = _tnl_copy_pv;
tnl->Driver.Render.Interp = _tnl_interp;
_tnl_invalidate_vertices( ctx, ~0 );
_tnl_need_projected_coords( ctx, GL_FALSE );
- r300ChooseRenderState(ctx);
+ r600ChooseRenderState(ctx);
}
-void r300DestroySwtcl(GLcontext *ctx)
+void r600DestroySwtcl(GLcontext *ctx)
{
}
-static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset)
+static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset)
{
BATCH_LOCALS(&rmesa->radeon);
__FUNCTION__, vertex_size, offset);
BEGIN_BATCH(7);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2);
+ OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, 2);
OUT_BATCH(1);
OUT_BATCH(vertex_size | (vertex_size << 8));
OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
}
-static void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr)
+static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vertex_nr)
{
BATCH_LOCALS(&rmesa->radeon);
int type, num_verts;
- type = r300PrimitiveType(rmesa, primitive);
- num_verts = r300NumVerts(rmesa, vertex_nr, primitive);
+ type = r600PrimitiveType(rmesa, primitive);
+ num_verts = r600NumVerts(rmesa, vertex_nr, primitive);
BEGIN_BATCH(3);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
- OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
+ OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0);
+ OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
END_BATCH();
}
-void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
+void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
rcommonEnsureCmdBufSpace(&rmesa->radeon,
rmesa->radeon.hw.max_state_size + (12*sizeof(int)),
__FUNCTION__);
radeonEmitState(&rmesa->radeon);
- r300EmitVertexAOS(rmesa,
+ r600EmitVertexAOS(rmesa,
rmesa->radeon.swtcl.vertex_size,
rmesa->radeon.dma.current,
current_offset);
- r300EmitVbufPrim(rmesa,
+ r600EmitVbufPrim(rmesa,
rmesa->radeon.swtcl.hw_primitive,
rmesa->radeon.swtcl.numverts);
- r300EmitCacheFlush(rmesa);
+ r600EmitCacheFlush(rmesa);
COMMIT_BATCH();
}
#include "swrast/swrast.h"
#include "r600_context.h"
-#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-#define MASK_X R300_WRITE_ENA_X
-#define MASK_Y R300_WRITE_ENA_Y
-#define MASK_Z R300_WRITE_ENA_Z
-#define MASK_W R300_WRITE_ENA_W
+#define MASK_XYZW (R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W)
+#define MASK_X R600_WRITE_ENA_X
+#define MASK_Y R600_WRITE_ENA_Y
+#define MASK_Z R600_WRITE_ENA_Z
+#define MASK_W R600_WRITE_ENA_W
/*
* Here are definitions of OVM locations of vertex attributes for non TCL hw
#define SWTCL_OVM_POINT_SIZE 15
-extern void r300InitSwtcl( GLcontext *ctx );
-extern void r300DestroySwtcl( GLcontext *ctx );
+extern void r600InitSwtcl( GLcontext *ctx );
+extern void r600DestroySwtcl( GLcontext *ctx );
-extern void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset);
+extern void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset);
#endif
static unsigned int translate_wrap_mode(GLenum wrapmode)
{
switch(wrapmode) {
- case GL_REPEAT: return R300_TX_REPEAT;
- case GL_CLAMP: return R300_TX_CLAMP;
- case GL_CLAMP_TO_EDGE: return R300_TX_CLAMP_TO_EDGE;
- case GL_CLAMP_TO_BORDER: return R300_TX_CLAMP_TO_BORDER;
- case GL_MIRRORED_REPEAT: return R300_TX_REPEAT | R300_TX_MIRRORED;
- case GL_MIRROR_CLAMP_EXT: return R300_TX_CLAMP | R300_TX_MIRRORED;
- case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED;
- case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED;
+ case GL_REPEAT: return R600_TX_REPEAT;
+ case GL_CLAMP: return R600_TX_CLAMP;
+ case GL_CLAMP_TO_EDGE: return R600_TX_CLAMP_TO_EDGE;
+ case GL_CLAMP_TO_BORDER: return R600_TX_CLAMP_TO_BORDER;
+ case GL_MIRRORED_REPEAT: return R600_TX_REPEAT | R600_TX_MIRRORED;
+ case GL_MIRROR_CLAMP_EXT: return R600_TX_CLAMP | R600_TX_MIRRORED;
+ case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R600_TX_CLAMP_TO_EDGE | R600_TX_MIRRORED;
+ case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R600_TX_CLAMP_TO_BORDER | R600_TX_MIRRORED;
default:
_mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__);
return 0;
*
* \param t Texture object whose wrap modes are to be set
*/
-static void r300UpdateTexWrap(radeonTexObjPtr t)
+static void r600UpdateTexWrap(radeonTexObjPtr t)
{
struct gl_texture_object *tObj = &t->base;
t->pp_txfilter &=
- ~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK);
+ ~(R600_TX_WRAP_S_MASK | R600_TX_WRAP_T_MASK | R600_TX_WRAP_R_MASK);
- t->pp_txfilter |= translate_wrap_mode(tObj->WrapS) << R300_TX_WRAP_S_SHIFT;
+ t->pp_txfilter |= translate_wrap_mode(tObj->WrapS) << R600_TX_WRAP_S_SHIFT;
if (tObj->Target != GL_TEXTURE_1D) {
- t->pp_txfilter |= translate_wrap_mode(tObj->WrapT) << R300_TX_WRAP_T_SHIFT;
+ t->pp_txfilter |= translate_wrap_mode(tObj->WrapT) << R600_TX_WRAP_T_SHIFT;
if (tObj->Target == GL_TEXTURE_3D)
- t->pp_txfilter |= translate_wrap_mode(tObj->WrapR) << R300_TX_WRAP_R_SHIFT;
+ t->pp_txfilter |= translate_wrap_mode(tObj->WrapR) << R600_TX_WRAP_R_SHIFT;
}
}
static GLuint aniso_filter(GLfloat anisotropy)
{
if (anisotropy >= 16.0) {
- return R300_TX_MAX_ANISO_16_TO_1;
+ return R600_TX_MAX_ANISO_16_TO_1;
} else if (anisotropy >= 8.0) {
- return R300_TX_MAX_ANISO_8_TO_1;
+ return R600_TX_MAX_ANISO_8_TO_1;
} else if (anisotropy >= 4.0) {
- return R300_TX_MAX_ANISO_4_TO_1;
+ return R600_TX_MAX_ANISO_4_TO_1;
} else if (anisotropy >= 2.0) {
- return R300_TX_MAX_ANISO_2_TO_1;
+ return R600_TX_MAX_ANISO_2_TO_1;
} else {
- return R300_TX_MAX_ANISO_1_TO_1;
+ return R600_TX_MAX_ANISO_1_TO_1;
}
}
* \param magf Texture magnification mode
* \param anisotropy Maximum anisotropy level
*/
-static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
+static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
{
/* Force revalidation to account for switches from/to mipmapping. */
t->validated = GL_FALSE;
- t->pp_txfilter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK);
- t->pp_txfilter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY;
+ t->pp_txfilter &= ~(R600_TX_MIN_FILTER_MASK | R600_TX_MIN_FILTER_MIP_MASK | R600_TX_MAG_FILTER_MASK | R600_TX_MAX_ANISO_MASK);
+ t->pp_txfilter_1 &= ~R600_EDGE_ANISO_EDGE_ONLY;
/* Note that EXT_texture_filter_anisotropic is extremely vague about
* how anisotropic filtering interacts with the "normal" filter modes.
* filter settings completely. This includes driconf's settings.
*/
if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) {
- t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO
- | R300_TX_MIN_FILTER_ANISO
- | R300_TX_MIN_FILTER_MIP_LINEAR
+ t->pp_txfilter |= R600_TX_MAG_FILTER_ANISO
+ | R600_TX_MIN_FILTER_ANISO
+ | R600_TX_MIN_FILTER_MIP_LINEAR
| aniso_filter(anisotropy);
if (RADEON_DEBUG & DEBUG_TEXTURE)
fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy);
switch (minf) {
case GL_NEAREST:
- t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST;
+ t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST;
break;
case GL_LINEAR:
- t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR;
+ t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR;
break;
case GL_NEAREST_MIPMAP_NEAREST:
- t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_NEAREST;
+ t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST|R600_TX_MIN_FILTER_MIP_NEAREST;
break;
case GL_NEAREST_MIPMAP_LINEAR:
- t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_LINEAR;
+ t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST|R600_TX_MIN_FILTER_MIP_LINEAR;
break;
case GL_LINEAR_MIPMAP_NEAREST:
- t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_NEAREST;
+ t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR|R600_TX_MIN_FILTER_MIP_NEAREST;
break;
case GL_LINEAR_MIPMAP_LINEAR:
- t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_LINEAR;
+ t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR|R600_TX_MIN_FILTER_MIP_LINEAR;
break;
}
*/
switch (magf) {
case GL_NEAREST:
- t->pp_txfilter |= R300_TX_MAG_FILTER_NEAREST;
+ t->pp_txfilter |= R600_TX_MAG_FILTER_NEAREST;
break;
case GL_LINEAR:
- t->pp_txfilter |= R300_TX_MAG_FILTER_LINEAR;
+ t->pp_txfilter |= R600_TX_MAG_FILTER_LINEAR;
break;
}
}
-static void r300SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4])
+static void r600SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4])
{
t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]);
}
* next UpdateTextureState
*/
-static void r300TexParameter(GLcontext * ctx, GLenum target,
+static void r600TexParameter(GLcontext * ctx, GLenum target,
struct gl_texture_object *texObj,
GLenum pname, const GLfloat * params)
{
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- r300SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
+ r600SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
case GL_TEXTURE_WRAP_R:
- r300UpdateTexWrap(t);
+ r600UpdateTexWrap(t);
break;
case GL_TEXTURE_BORDER_COLOR:
- r300SetTexBorderColor(t, texObj->_BorderChan);
+ r600SetTexBorderColor(t, texObj->_BorderChan);
break;
case GL_TEXTURE_BASE_LEVEL:
return;
if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat
== GL_DEPTH_COMPONENT) {
- r300SetDepthTexMode(texObj);
+ r600SetDepthTexMode(texObj);
break;
} else {
/* If the texture isn't a depth texture, changing this
}
}
-static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
+static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
radeonTexObj* t = radeon_tex_obj(texObj);
if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) {
int i;
radeon_firevertices(&rmesa->radeon);
- for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i)
+ for(i = 0; i < R600_MAX_TEXTURE_UNITS; ++i)
if (rmesa->hw.textures[i] == t)
rmesa->hw.textures[i] = 0;
}
* allocate the default texture objects.
* Fixup MaxAnisotropy according to user preference.
*/
-static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx,
+static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx,
GLuint name,
GLenum target)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
/* Initialize hardware state */
- r300UpdateTexWrap(t);
- r300SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
- r300SetTexBorderColor(t, t->base._BorderChan);
+ r600UpdateTexWrap(t);
+ r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
+ r600SetTexBorderColor(t, t->base._BorderChan);
return &t->base;
}
-void r300InitTextureFuncs(struct dd_function_table *functions)
+void r600InitTextureFuncs(struct dd_function_table *functions)
{
/* Note: we only plug in the functions we implement in the driver
* since _mesa_init_driver_functions() was already called.
functions->TexSubImage3D = radeonTexSubImage3D;
functions->GetTexImage = radeonGetTexImage;
functions->GetCompressedTexImage = radeonGetCompressedTexImage;
- functions->NewTextureObject = r300NewTextureObject;
- functions->DeleteTexture = r300DeleteTexture;
+ functions->NewTextureObject = r600NewTextureObject;
+ functions->DeleteTexture = r600DeleteTexture;
functions->IsTextureResident = driIsTextureResident;
- functions->TexParameter = r300TexParameter;
+ functions->TexParameter = r600TexParameter;
functions->CompressedTexImage2D = radeonCompressedTexImage2D;
functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D;
#ifndef __r600_TEX_H__
#define __r600_TEX_H__
-extern void r300SetDepthTexMode(struct gl_texture_object *tObj);
+extern void r600SetDepthTexMode(struct gl_texture_object *tObj);
-extern void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target,
+extern void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target,
__DRIdrawable *dPriv);
-extern void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
+extern void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
GLint format, __DRIdrawable *dPriv);
-extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname,
+extern void r600SetTexOffset(__DRIcontext *pDRICtx, GLint texname,
unsigned long long offset, GLint depth,
GLuint pitch);
-extern GLboolean r300ValidateBuffers(GLcontext * ctx);
+extern GLboolean r600ValidateBuffers(GLcontext * ctx);
-extern void r300InitTextureFuncs(struct dd_function_table *functions);
+extern void r600InitTextureFuncs(struct dd_function_table *functions);
#endif /* __r600_TEX_H__ */
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*
- * \todo Enable R300 texture tiling code?
+ * \todo Enable R600 texture tiling code?
*/
#include "main/glheader.h"
* Note that the _REV formats are the same as the non-REV formats. This is
* because the REV and non-REV formats are identical as a byte string, but
* differ when accessed as 16-bit or 32-bit words depending on the endianness of
- * the host. Since the textures are transferred to the R300 as a byte string
- * (i.e. without any byte-swapping), the R300 sees the REV and non-REV formats
+ * the host. Since the textures are transferred to the R600 as a byte string
+ * (i.e. without any byte-swapping), the R600 sees the REV and non-REV formats
* identically. -- paulus
*/
} tx_table[] = {
/* *INDENT-OFF* */
#ifdef MESA_LITTLE_ENDIAN
- _ASSIGN(RGBA8888, R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)),
- _ASSIGN(RGBA8888_REV, R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)),
- _ASSIGN(ARGB8888, R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)),
- _ASSIGN(ARGB8888_REV, R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)),
+ _ASSIGN(RGBA8888, R600_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)),
+ _ASSIGN(RGBA8888_REV, R600_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)),
+ _ASSIGN(ARGB8888, R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)),
+ _ASSIGN(ARGB8888_REV, R600_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)),
#else
- _ASSIGN(RGBA8888, R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)),
- _ASSIGN(RGBA8888_REV, R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)),
- _ASSIGN(ARGB8888, R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)),
- _ASSIGN(ARGB8888_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)),
+ _ASSIGN(RGBA8888, R600_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)),
+ _ASSIGN(RGBA8888_REV, R600_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)),
+ _ASSIGN(ARGB8888, R600_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)),
+ _ASSIGN(ARGB8888_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)),
#endif
- _ASSIGN(RGB888, R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8)),
- _ASSIGN(RGB565, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)),
- _ASSIGN(RGB565_REV, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)),
- _ASSIGN(ARGB4444, R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)),
- _ASSIGN(ARGB4444_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)),
- _ASSIGN(ARGB1555, R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)),
- _ASSIGN(ARGB1555_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)),
- _ASSIGN(AL88, R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8)),
- _ASSIGN(AL88_REV, R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8)),
- _ASSIGN(RGB332, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2)),
- _ASSIGN(A8, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8)),
- _ASSIGN(L8, R300_EASY_TX_FORMAT(X, X, X, ONE, X8)),
- _ASSIGN(I8, R300_EASY_TX_FORMAT(X, X, X, X, X8)),
- _ASSIGN(CI8, R300_EASY_TX_FORMAT(X, X, X, X, X8)),
- _ASSIGN(YCBCR, R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE),
- _ASSIGN(YCBCR_REV, R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE),
- _ASSIGN(RGB_DXT1, R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1)),
- _ASSIGN(RGBA_DXT1, R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1)),
- _ASSIGN(RGBA_DXT3, R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3)),
- _ASSIGN(RGBA_DXT5, R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5)),
- _ASSIGN(RGBA_FLOAT32, R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32)),
- _ASSIGN(RGBA_FLOAT16, R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16)),
+ _ASSIGN(RGB888, R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8)),
+ _ASSIGN(RGB565, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)),
+ _ASSIGN(RGB565_REV, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)),
+ _ASSIGN(ARGB4444, R600_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)),
+ _ASSIGN(ARGB4444_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)),
+ _ASSIGN(ARGB1555, R600_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)),
+ _ASSIGN(ARGB1555_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)),
+ _ASSIGN(AL88, R600_EASY_TX_FORMAT(X, X, X, Y, Y8X8)),
+ _ASSIGN(AL88_REV, R600_EASY_TX_FORMAT(X, X, X, Y, Y8X8)),
+ _ASSIGN(RGB332, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2)),
+ _ASSIGN(A8, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8)),
+ _ASSIGN(L8, R600_EASY_TX_FORMAT(X, X, X, ONE, X8)),
+ _ASSIGN(I8, R600_EASY_TX_FORMAT(X, X, X, X, X8)),
+ _ASSIGN(CI8, R600_EASY_TX_FORMAT(X, X, X, X, X8)),
+ _ASSIGN(YCBCR, R600_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R600_TX_FORMAT_YUV_MODE),
+ _ASSIGN(YCBCR_REV, R600_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R600_TX_FORMAT_YUV_MODE),
+ _ASSIGN(RGB_DXT1, R600_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1)),
+ _ASSIGN(RGBA_DXT1, R600_EASY_TX_FORMAT(X, Y, Z, W, DXT1)),
+ _ASSIGN(RGBA_DXT3, R600_EASY_TX_FORMAT(X, Y, Z, W, DXT3)),
+ _ASSIGN(RGBA_DXT5, R600_EASY_TX_FORMAT(Y, Z, W, X, DXT5)),
+ _ASSIGN(RGBA_FLOAT32, R600_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32)),
+ _ASSIGN(RGBA_FLOAT16, R600_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16)),
_ASSIGN(RGB_FLOAT32, 0xffffffff),
_ASSIGN(RGB_FLOAT16, 0xffffffff),
- _ASSIGN(ALPHA_FLOAT32, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32)),
- _ASSIGN(ALPHA_FLOAT16, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16)),
- _ASSIGN(LUMINANCE_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I32)),
- _ASSIGN(LUMINANCE_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I16)),
- _ASSIGN(LUMINANCE_ALPHA_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32)),
- _ASSIGN(LUMINANCE_ALPHA_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16)),
- _ASSIGN(INTENSITY_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, X, FL_I32)),
- _ASSIGN(INTENSITY_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, X, FL_I16)),
- _ASSIGN(Z16, R300_EASY_TX_FORMAT(X, X, X, X, X16)),
- _ASSIGN(Z24_S8, R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8)),
- _ASSIGN(Z32, R300_EASY_TX_FORMAT(X, X, X, X, X32)),
+ _ASSIGN(ALPHA_FLOAT32, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32)),
+ _ASSIGN(ALPHA_FLOAT16, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16)),
+ _ASSIGN(LUMINANCE_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, ONE, FL_I32)),
+ _ASSIGN(LUMINANCE_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, ONE, FL_I16)),
+ _ASSIGN(LUMINANCE_ALPHA_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32)),
+ _ASSIGN(LUMINANCE_ALPHA_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16)),
+ _ASSIGN(INTENSITY_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, X, FL_I32)),
+ _ASSIGN(INTENSITY_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, X, FL_I16)),
+ _ASSIGN(Z16, R600_EASY_TX_FORMAT(X, X, X, X, X16)),
+ _ASSIGN(Z24_S8, R600_EASY_TX_FORMAT(X, X, X, X, X24_Y8)),
+ _ASSIGN(Z32, R600_EASY_TX_FORMAT(X, X, X, X, X32)),
/* *INDENT-ON* */
};
#undef _ASSIGN
-void r300SetDepthTexMode(struct gl_texture_object *tObj)
+void r600SetDepthTexMode(struct gl_texture_object *tObj)
{
static const GLuint formats[3][3] = {
{
- R300_EASY_TX_FORMAT(X, X, X, ONE, X16),
- R300_EASY_TX_FORMAT(X, X, X, X, X16),
- R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16),
+ R600_EASY_TX_FORMAT(X, X, X, ONE, X16),
+ R600_EASY_TX_FORMAT(X, X, X, X, X16),
+ R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16),
},
{
- R300_EASY_TX_FORMAT(X, X, X, ONE, X24_Y8),
- R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8),
- R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X24_Y8),
+ R600_EASY_TX_FORMAT(X, X, X, ONE, X24_Y8),
+ R600_EASY_TX_FORMAT(X, X, X, X, X24_Y8),
+ R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X24_Y8),
},
{
- R300_EASY_TX_FORMAT(X, X, X, ONE, X32),
- R300_EASY_TX_FORMAT(X, X, X, X, X32),
- R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32),
+ R600_EASY_TX_FORMAT(X, X, X, ONE, X32),
+ R600_EASY_TX_FORMAT(X, X, X, X, X32),
+ R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32),
},
};
const GLuint *format;
* Compute the cached hardware register values for the given texture object.
*
* \param rmesa Context pointer
- * \param t the r300 texture object
+ * \param t the r600 texture object
*/
-static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
+static void setup_hardware_state(r600ContextPtr rmesa, radeonTexObj *t)
{
const struct gl_texture_image *firstImage;
int firstlevel = t->mt ? t->mt->firstLevel : 0;
if (!t->image_override
&& VALID_FORMAT(firstImage->TexFormat->MesaFormat)) {
if (firstImage->TexFormat->BaseFormat == GL_DEPTH_COMPONENT) {
- r300SetDepthTexMode(&t->base);
+ r600SetDepthTexMode(&t->base);
} else {
t->pp_txformat = tx_table[firstImage->TexFormat->MesaFormat].format;
}
if (t->image_override && t->bo)
return;
- t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT)
- | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)
- | ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT)
- | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT));
+ t->pp_txsize = (((firstImage->Width - 1) << R600_TX_WIDTHMASK_SHIFT)
+ | ((firstImage->Height - 1) << R600_TX_HEIGHTMASK_SHIFT)
+ | ((firstImage->DepthLog2) << R600_TX_DEPTHMASK_SHIFT)
+ | ((t->mt->lastLevel - t->mt->firstLevel) << R600_TX_MAX_MIP_LEVEL_SHIFT));
t->tile_bits = 0;
if (t->base.Target == GL_TEXTURE_CUBE_MAP)
- t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP;
+ t->pp_txformat |= R600_TX_FORMAT_CUBIC_MAP;
if (t->base.Target == GL_TEXTURE_3D)
- t->pp_txformat |= R300_TX_FORMAT_3D;
+ t->pp_txformat |= R600_TX_FORMAT_3D;
if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
unsigned int align = (64 / t->mt->bpp) - 1;
- t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
+ t->pp_txsize |= R600_TX_SIZE_TXPITCH_EN;
if (!t->image_override)
t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1;
}
*
* Mostly this means populating the texture object's mipmap tree.
*/
-static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj)
+static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
if (!radeon_validate_texture_miptree(ctx, texObj))
/**
* Ensure all enabled and complete textures are uploaded along with any buffers being used.
*/
-GLboolean r300ValidateBuffers(GLcontext * ctx)
+GLboolean r600ValidateBuffers(GLcontext * ctx)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ r600ContextPtr rmesa = R600_CONTEXT(ctx);
struct radeon_renderbuffer *rrb;
int i;
if (!ctx->Texture.Unit[i]._ReallyEnabled)
continue;
- if (!r300_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) {
+ if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) {
_mesa_warning(ctx,
"failed to validate texture for unit %d.\n",
i);
return radeon_revalidate_bos(ctx);
}
-void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
+void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
unsigned long long offset, GLint depth, GLuint pitch)
{
- r300ContextPtr rmesa = pDRICtx->driverPrivate;
+ r600ContextPtr rmesa = pDRICtx->driverPrivate;
struct gl_texture_object *tObj =
_mesa_lookup_texture(rmesa->radeon.glCtx, texname);
radeonTexObjPtr t = radeon_tex_obj(tObj);
switch (depth) {
case 32:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
+ t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
t->pp_txfilter |= tx_table[2].filter;
pitch_val /= 4;
break;
case 24:
default:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
+ t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
t->pp_txfilter |= tx_table[4].filter;
pitch_val /= 4;
break;
case 16:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
+ t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
t->pp_txfilter |= tx_table[5].filter;
pitch_val /= 2;
break;
t->pp_txpitch |= pitch_val;
}
-void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv)
+void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv)
{
struct gl_texture_unit *texUnit;
struct gl_texture_object *texObj;
struct radeon_renderbuffer *rb;
radeon_texture_image *rImage;
radeonContextPtr radeon;
- r300ContextPtr rmesa;
+ r600ContextPtr rmesa;
struct radeon_framebuffer *rfb;
radeonTexObjPtr t;
uint32_t pitch_val;
pitch_val = rb->pitch;
switch (rb->cpp) {
case 4:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
+ t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
t->pp_txfilter |= tx_table[2].filter;
pitch_val /= 4;
break;
case 3:
default:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
+ t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
t->pp_txfilter |= tx_table[4].filter;
pitch_val /= 4;
break;
case 2:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
+ t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
t->pp_txfilter |= tx_table[5].filter;
pitch_val /= 2;
break;
}
pitch_val--;
- t->pp_txsize = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) |
- ((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT);
- t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
+ t->pp_txsize = ((rb->width - 1) << R600_TX_WIDTHMASK_SHIFT) |
+ ((rb->height - 1) << R600_TX_HEIGHTMASK_SHIFT);
+ t->pp_txsize |= R600_TX_SIZE_TXPITCH_EN;
t->pp_txpitch |= pitch_val;
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
return;
}
-void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
+void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
{
- r300SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv);
+ r600SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv);
}
u_temp_i=VSF_MAX_FRAGMENT_TEMPS-1; \
} while (0)
-int r300VertexProgUpdateParams(GLcontext * ctx,
- struct r300_vertex_program_cont *vp, float *dst)
+int r600VertexProgUpdateParams(GLcontext * ctx,
+ struct r600_vertex_program_cont *vp, float *dst)
{
int pi;
struct gl_vertex_program *mesa_vp = &vp->mesa_program;
}
}
-static unsigned long t_dst_index(struct r300_vertex_program *vp,
+static unsigned long t_dst_index(struct r600_vertex_program *vp,
struct prog_dst_register *dst)
{
if (dst->File == PROGRAM_OUTPUT)
}
#if 0
-static void vp_dump_inputs(struct r300_vertex_program *vp, char *caller)
+static void vp_dump_inputs(struct r600_vertex_program *vp, char *caller)
{
int i;
}
#endif
-static unsigned long t_src_index(struct r300_vertex_program *vp,
+static unsigned long t_src_index(struct r600_vertex_program *vp,
struct prog_src_register *src)
{
int i;
/* these two functions should probably be merged... */
-static unsigned long t_src(struct r300_vertex_program *vp,
+static unsigned long t_src(struct r600_vertex_program *vp,
struct prog_src_register *src)
{
/* src->NegateBase uses the NEGATE_ flags from program_instruction.h,
src->NegateBase) | (src->RelAddr << 4);
}
-static unsigned long t_src_scalar(struct r300_vertex_program *vp,
+static unsigned long t_src_scalar(struct r600_vertex_program *vp,
struct prog_src_register *src)
{
/* src->NegateBase uses the NEGATE_ flags from program_instruction.h,
(src->RelAddr << 4);
}
-static GLboolean valid_dst(struct r300_vertex_program *vp,
+static GLboolean valid_dst(struct r600_vertex_program *vp,
struct prog_dst_register *dst)
{
if (dst->File == PROGRAM_OUTPUT && vp->outputs[dst->Index] == -1) {
return GL_TRUE;
}
-static GLuint *r300TranslateOpcodeABS(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeABS(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeADD(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeADD(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeARL(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeARL(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeDP3(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeDP3(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeDP4(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeDP4(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeDPH(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeDPH(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeDST(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeDST(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeEX2(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeEX2(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeEXP(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeEXP(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeFLR(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeFLR(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3],
return inst;
}
-static GLuint *r300TranslateOpcodeFRC(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeFRC(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeLG2(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeLG2(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeLIT(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeLIT(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeLOG(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeLOG(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeMAD(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeMAD(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeMAX(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeMAX(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeMIN(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeMIN(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeMOV(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeMOV(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeMUL(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeMUL(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodePOW(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodePOW(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeRCP(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeRCP(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeRSQ(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeRSQ(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeSGE(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeSGE(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeSLT(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeSLT(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeSUB(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeSUB(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeSWZ(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeSWZ(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
return inst;
}
-static GLuint *r300TranslateOpcodeXPD(struct r300_vertex_program *vp,
+static GLuint *r600TranslateOpcodeXPD(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3],
return inst;
}
-static void t_inputs_outputs(struct r300_vertex_program *vp)
+static void t_inputs_outputs(struct r600_vertex_program *vp)
{
int i;
int cur_reg = 0;
}
}
-static void r300TranslateVertexShader(struct r300_vertex_program *vp,
+static void r600TranslateVertexShader(struct r600_vertex_program *vp,
struct prog_instruction *vpi)
{
int i;
GLuint *inst;
unsigned long num_operands;
/* Initial value should be last tmp reg that hw supports.
- Strangely enough r300 doesnt mind even though these would be out of range.
+ Strangely enough r600 doesnt mind even though these would be out of range.
Smart enough to realize that it doesnt need it? */
int u_temp_i = VSF_MAX_FRAGMENT_TEMPS - 1;
struct prog_src_register src[3];
switch (vpi->Opcode) {
case OPCODE_ABS:
- inst = r300TranslateOpcodeABS(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeABS(vp, vpi, inst, src);
break;
case OPCODE_ADD:
- inst = r300TranslateOpcodeADD(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeADD(vp, vpi, inst, src);
break;
case OPCODE_ARL:
- inst = r300TranslateOpcodeARL(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeARL(vp, vpi, inst, src);
break;
case OPCODE_DP3:
- inst = r300TranslateOpcodeDP3(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeDP3(vp, vpi, inst, src);
break;
case OPCODE_DP4:
- inst = r300TranslateOpcodeDP4(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeDP4(vp, vpi, inst, src);
break;
case OPCODE_DPH:
- inst = r300TranslateOpcodeDPH(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeDPH(vp, vpi, inst, src);
break;
case OPCODE_DST:
- inst = r300TranslateOpcodeDST(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeDST(vp, vpi, inst, src);
break;
case OPCODE_EX2:
- inst = r300TranslateOpcodeEX2(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeEX2(vp, vpi, inst, src);
break;
case OPCODE_EXP:
- inst = r300TranslateOpcodeEXP(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeEXP(vp, vpi, inst, src);
break;
case OPCODE_FLR:
- inst = r300TranslateOpcodeFLR(vp, vpi, inst, src, /* FIXME */
+ inst = r600TranslateOpcodeFLR(vp, vpi, inst, src, /* FIXME */
&u_temp_i);
break;
case OPCODE_FRC:
- inst = r300TranslateOpcodeFRC(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeFRC(vp, vpi, inst, src);
break;
case OPCODE_LG2:
- inst = r300TranslateOpcodeLG2(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeLG2(vp, vpi, inst, src);
break;
case OPCODE_LIT:
- inst = r300TranslateOpcodeLIT(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeLIT(vp, vpi, inst, src);
break;
case OPCODE_LOG:
- inst = r300TranslateOpcodeLOG(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeLOG(vp, vpi, inst, src);
break;
case OPCODE_MAD:
- inst = r300TranslateOpcodeMAD(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeMAD(vp, vpi, inst, src);
break;
case OPCODE_MAX:
- inst = r300TranslateOpcodeMAX(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeMAX(vp, vpi, inst, src);
break;
case OPCODE_MIN:
- inst = r300TranslateOpcodeMIN(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeMIN(vp, vpi, inst, src);
break;
case OPCODE_MOV:
- inst = r300TranslateOpcodeMOV(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeMOV(vp, vpi, inst, src);
break;
case OPCODE_MUL:
- inst = r300TranslateOpcodeMUL(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeMUL(vp, vpi, inst, src);
break;
case OPCODE_POW:
- inst = r300TranslateOpcodePOW(vp, vpi, inst, src);
+ inst = r600TranslateOpcodePOW(vp, vpi, inst, src);
break;
case OPCODE_RCP:
- inst = r300TranslateOpcodeRCP(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeRCP(vp, vpi, inst, src);
break;
case OPCODE_RSQ:
- inst = r300TranslateOpcodeRSQ(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeRSQ(vp, vpi, inst, src);
break;
case OPCODE_SGE:
- inst = r300TranslateOpcodeSGE(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeSGE(vp, vpi, inst, src);
break;
case OPCODE_SLT:
- inst = r300TranslateOpcodeSLT(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeSLT(vp, vpi, inst, src);
break;
case OPCODE_SUB:
- inst = r300TranslateOpcodeSUB(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeSUB(vp, vpi, inst, src);
break;
case OPCODE_SWZ:
- inst = r300TranslateOpcodeSWZ(vp, vpi, inst, src);
+ inst = r600TranslateOpcodeSWZ(vp, vpi, inst, src);
break;
case OPCODE_XPD:
- inst = r300TranslateOpcodeXPD(vp, vpi, inst, src, /* FIXME */
+ inst = r600TranslateOpcodeXPD(vp, vpi, inst, src, /* FIXME */
&u_temp_i);
break;
default:
assert(vpi->Opcode == OPCODE_END);
}
-static void insert_wpos(struct r300_vertex_program *vp, struct gl_program *prog,
+static void insert_wpos(struct r600_vertex_program *vp, struct gl_program *prog,
GLuint temp_index)
{
struct prog_instruction *vpi;
assert(vpi->Opcode == OPCODE_END);
}
-static void pos_as_texcoord(struct r300_vertex_program *vp,
+static void pos_as_texcoord(struct r600_vertex_program *vp,
struct gl_program *prog)
{
struct prog_instruction *vpi;
insert_wpos(vp, prog, tempregi);
}
-static struct r300_vertex_program *build_program(struct r300_vertex_program_key
+static struct r600_vertex_program *build_program(struct r600_vertex_program_key
*wanted_key, struct gl_vertex_program
*mesa_vp, GLint wpos_idx)
{
- struct r300_vertex_program *vp;
+ struct r600_vertex_program *vp;
vp = _mesa_calloc(sizeof(*vp));
_mesa_memcpy(&vp->key, wanted_key, sizeof(vp->key));
assert(mesa_vp->Base.NumInstructions);
vp->num_temporaries = mesa_vp->Base.NumTemporaries;
- r300TranslateVertexShader(vp, mesa_vp->Base.Instructions);
+ r600TranslateVertexShader(vp, mesa_vp->Base.Instructions);
return vp;
}
-static void add_outputs(struct r300_vertex_program_key *key, GLint vert)
+static void add_outputs(struct r600_vertex_program_key *key, GLint vert)
{
if (key->OutputsWritten & (1 << vert))
return;
key->OutputsAdded |= 1 << vert;
}
-void r300SelectVertexShader(r300ContextPtr r300)
+void r600SelectVertexShader(r600ContextPtr r600)
{
- GLcontext *ctx = ctx = r300->radeon.glCtx;
+ GLcontext *ctx = ctx = r600->radeon.glCtx;
GLuint InputsRead;
- struct r300_vertex_program_key wanted_key = { 0 };
+ struct r600_vertex_program_key wanted_key = { 0 };
GLint i;
- struct r300_vertex_program_cont *vpc;
- struct r300_vertex_program *vp;
+ struct r600_vertex_program_cont *vpc;
+ struct r600_vertex_program *vp;
GLint wpos_idx;
- vpc = (struct r300_vertex_program_cont *)ctx->VertexProgram._Current;
+ vpc = (struct r600_vertex_program_cont *)ctx->VertexProgram._Current;
wanted_key.InputsRead = vpc->mesa_program.Base.InputsRead;
wanted_key.OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
for (vp = vpc->progs; vp; vp = vp->next)
if (_mesa_memcmp(&vp->key, &wanted_key, sizeof(wanted_key))
== 0) {
- r300->selected_vp = vp;
+ r600->selected_vp = vp;
return;
}
//_mesa_print_program(&vpc->mesa_program.Base);
vp = build_program(&wanted_key, &vpc->mesa_program, wpos_idx);
vp->next = vpc->progs;
vpc->progs = vp;
- r300->selected_vp = vp;
+ r600->selected_vp = vp;
}
}
-static void update_params(r300ContextPtr r300, struct r500_fragment_program *fp)
+static void update_params(r600ContextPtr r600, struct r500_fragment_program *fp)
{
struct gl_fragment_program *mp = &fp->mesa_program;
/* Ask Mesa nicely to fill in ParameterValues for us */
if (mp->Base.Parameters)
- _mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters);
+ _mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters);
}
return;
static gl_state_index tokens[STATE_LENGTH] = {
- STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0
+ STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0
};
struct prog_instruction *fpi;
GLuint window_index;
* fragment program.
*/
static void build_state(
- r300ContextPtr r300,
+ r600ContextPtr r600,
struct r500_fragment_program *fp,
struct r500_fragment_program_external_state *state)
{
for(unit = 0; unit < 16; ++unit) {
if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) {
- struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current;
+ struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current;
state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode);
state->unit[unit].texture_compare_func = build_func(tex->CompareFunc);
static void dump_program(struct r500_fragment_program_code *code);
-void r500TranslateFragmentShader(r300ContextPtr r300,
+void r500TranslateFragmentShader(r600ContextPtr r600,
struct r500_fragment_program *fp)
{
struct r500_fragment_program_external_state state;
- build_state(r300, fp, &state);
+ build_state(r600, fp, &state);
if (_mesa_memcmp(&fp->state, &state, sizeof(state))) {
/* TODO: cache compiled programs */
fp->translated = GL_FALSE;
if (!fp->translated) {
struct r500_fragment_program_compiler compiler;
- compiler.r300 = r300;
+ compiler.r600 = r600;
compiler.fp = fp;
compiler.code = &fp->code;
- compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base);
+ compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: Initial program:\n");
{ &radeonTransformDeriv, 0 },
{ &radeonTransformTrigScale, 0 }
};
- radeonLocalTransform(r300->radeon.glCtx, compiler.program,
+ radeonLocalTransform(r600->radeon.glCtx, compiler.program,
4, transformations);
if (RADEON_DEBUG & DEBUG_PIXEL) {
.BuildSwizzle = &nqssadce_build_swizzle,
.RewriteDepthOut = GL_TRUE
};
- radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce);
+ radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: after NqSSA-DCE:\n");
fp->mesa_program.Base.Parameters = compiler.program->Parameters;
compiler.program->Parameters = 0;
- _mesa_reference_program(r300->radeon.glCtx, &compiler.program, 0);
+ _mesa_reference_program(r600->radeon.glCtx, &compiler.program, 0);
- r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM);
+ r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM);
if (RADEON_DEBUG & DEBUG_PIXEL) {
if (fp->translated) {
}
- update_params(r300, fp);
+ update_params(r600, fp);
}
struct r500_fragment_program;
-extern void r500TranslateFragmentShader(r300ContextPtr r300,
+extern void r500TranslateFragmentShader(r600ContextPtr r600,
struct r500_fragment_program *fp);
struct r500_fragment_program_compiler {
- r300ContextPtr r300;
+ r600ContextPtr r600;
struct r500_fragment_program *fp;
struct r500_fragment_program_code *code;
struct gl_program *program;
code->inst_offset = 0;
code->inst_end = -1;
- if (!radeonPairProgram(compiler->r300->radeon.glCtx, compiler->program, &pair_handler, compiler))
+ if (!radeonPairProgram(compiler->r600->radeon.glCtx, compiler->program, &pair_handler, compiler))
return GL_FALSE;
if ((code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) {
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
-static const __DRItexOffsetExtension r300texOffsetExtension = {
+static const __DRItexOffsetExtension r600texOffsetExtension = {
{ __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
- r300SetTexOffset,
+ r600SetTexOffset,
};
-static const __DRItexBufferExtension r300TexBufferExtension = {
+static const __DRItexBufferExtension r600TexBufferExtension = {
{ __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
- r300SetTexBuffer,
- r300SetTexBuffer2,
+ r600SetTexBuffer,
+ r600SetTexBuffer2,
};
#endif
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
- screen->extensions[i++] = &r300texOffsetExtension.base;
+ screen->extensions[i++] = &r600texOffsetExtension.base;
#endif
}
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
- screen->extensions[i++] = &r300TexBufferExtension.base;
+ screen->extensions[i++] = &r600TexBufferExtension.base;
#endif
screen->extensions[i++] = NULL;
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
if (IS_R600_CLASS(screen))
- return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
+ return r600CreateContext(glVisual, driContextPriv, sharedContextPriv);
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
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