void DISPLAY::reset_cpuonly()
{
int i;
+ double usec;
keyboard->write_signal(SIG_FM7KEY_SET_INSLED, 0x00, 0x01);
mainio->write_signal(SIG_FM7_SUB_HALT, 0x00, 0xff);
sub_busy = true;
+ multimode_accessmask = 0;
+ multimode_dispmask = 0;
//firq_mask = false;
firq_mask = (mainio->read_signal(FM7_MAINIO_KEYBOARDIRQ_MASK) != 0) ? false : true;
//cancel_request = false;
}
is_cyclesteal = ((config.dipswitch & FM7_DIPSW_CYCLESTEAL) != 0) ? true : false;
enter_display();
+
offset_point = 0;
-
for(i = 0; i < 2; i++) {
offset_changed[i] = true;
tmp_offset_point[i].d = 0;
}
-
+
#if defined(_FM77AV_VARIANTS)
- subcpu_resetreq = false;
- power_on_reset = true;
offset_77av = false;
- subrom_bank_using = subrom_bank;
-
offset_point_bank1 = 0;
offset_point_bak = 0;
offset_point_bank1_bak = 0;
display_page = 0;
active_page = 0;
- //nmi_enable = true;
+
+ subcpu_resetreq = false;
+ //offset_77av = false;
+ subrom_bank_using = subrom_bank;
+
+ nmi_enable = true;
+ //nmi_enable = false;
use_alu = false;
vram_wrote_shadow = false;
for(i = 0; i < 400; i++) vram_wrote_table[i] = true;
for(i = 0; i < 400; i++) vram_draw_table[i] = true;
-#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- vram_bank = 0;
- vram_display_block = 0;
- vram_active_block = 0;
- monitor_ram_using = monitor_ram;
-# if defined(_FM77AV40EX) || defined(_FM77AV40SX)
- window_low = 0;
- window_high = 0;
- window_xbegin = 0;
- window_xend = 0;
- window_opened = false;
-# endif
-#endif
-#endif
- vram_wrote = true;
- clr_count = 0;
- frame_skip_count = 3;
- subcpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
-}
-
-
-void DISPLAY::reset()
-{
- int i;
-
- memset(io_w_latch, 0xff, sizeof(io_w_latch));
- halt_flag = false;
- vram_accessflag = true;
- display_mode = DISPLAY_MODE_8_200L;
- crt_flag = true;
-
-#if defined(_FM77AV_VARIANTS)
- double usec;
vsync = true;
vblank = true;
hblank = false;
vblank_count = 0;
displine = 0;
+
if(hblank_event_id >= 0) cancel_event(this, hblank_event_id);
if(hdisp_event_id >= 0) cancel_event(this, hdisp_event_id);
if(vsync_event_id >= 0) cancel_event(this, vsync_event_id);
register_event(this, EVENT_FM7SUB_VSTART, usec, false, &vstart_event_id); // NEXT CYCLE_
mainio->write_signal(SIG_DISPLAY_DISPLAY, 0x00, 0xff);
mainio->write_signal(SIG_DISPLAY_VSYNC, 0xff, 0xff);
-#endif
+
+# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
+ vram_bank = 0;
+ vram_display_block = 0;
+ vram_active_block = 0;
+
+# if defined(_FM77AV40EX) || defined(_FM77AV40SX)
+ window_low = 0;
+ window_high = 0;
+ window_xbegin = 0;
+ window_xend = 0;
+ window_opened = false;
+# endif
+# endif
+
+ alu->reset();
+# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
+ alu->write_signal(SIG_ALU_X_WIDTH, ((mode320 || mode256k) && !(mode400line)) ? 40 : 80, 0xffff);
+ alu->write_signal(SIG_ALU_Y_HEIGHT, (mode400line) ? 400: 200, 0xffff);
+ alu->write_signal(SIG_ALU_400LINE, (mode400line) ? 0xffffffff : 0, 0xffffffff);
+# else
+ alu->write_signal(SIG_ALU_X_WIDTH, (mode320) ? 40 : 80, 0xffff);
+ alu->write_signal(SIG_ALU_Y_HEIGHT, 200, 0xffff);
+ alu->write_signal(SIG_ALU_400LINE, 0, 0xffffffff);
+# endif
+ alu->write_signal(SIG_ALU_MULTIPAGE, multimode_accessmask, 0x07);
+ alu->write_signal(SIG_ALU_PLANES, 3, 3);
+
+ if(nmi_event_id >= 0) cancel_event(this, nmi_event_id);
+ nmi_event_id = -1;
+ register_event(this, EVENT_FM7SUB_DISPLAY_NMI, 20000.0, true, &nmi_event_id); // NEXT CYCLE_
+
+#endif
+ for(i = 0; i < 8; i++) set_dpalette(i, i);
+ do_firq(!firq_mask && key_firq_req);
+
#if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
kanjisub = false;
kanjiaddr.d = 0x00000000;
stat_400linecard = false;
# endif
#endif
- offset_point = 0;
+ vram_wrote = true;
+ clr_count = 0;
+ frame_skip_count = 3;
+}
+
+
+void DISPLAY::reset()
+{
+ int i;
+
+ memset(io_w_latch, 0xff, sizeof(io_w_latch));
+ halt_flag = false;
+ vram_accessflag = true;
+ display_mode = DISPLAY_MODE_8_200L;
+ crt_flag = true;
- for(i = 0; i < 2; i++) {
- offset_changed[i] = true;
- tmp_offset_point[i].d = 0;
- }
cancel_request = false;
#if defined(_FM77AV_VARIANTS)
mode320 = false;
#endif
#if defined(_FM77AV_VARIANTS)
subrom_bank = 0;
- subrom_bank_using = subrom_bank;
cgrom_bank = 0;
- offset_77av = false;
- use_alu = false;
- nmi_enable = true;
# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
monitor_ram = false;
- monitor_ram_using = monitor_ram;
ram_protect = true;
-# endif
-#endif
-#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
+
mode400line = false;
mode256k = false;
- vram_bank = 0;
- vram_display_block = 0;
- vram_active_block = 0;
-
-# if defined(_FM77AV40EX) || defined(_FM77AV40SX)
- window_low = 0;
- window_high = 0;
- window_xbegin = 0;
- window_xend = 0;
- window_opened = false;
-# endif
-#endif
-#if defined(_FM77L4)
+# endif
+#
+#elif defined(_FM77L4)
mode400line = false;
#endif
+
mainio->write_signal(FM7_MAINIO_KEYBOARDIRQ, 0x00 , 0xff);
keyboard->reset();
keyboard->write_signal(SIG_FM7KEY_SET_INSLED, 0x00, 0x01);
firq_mask = (mainio->read_signal(FM7_MAINIO_KEYBOARDIRQ_MASK) != 0) ? false : true;
- multimode_accessmask = 0;
- multimode_dispmask = 0;
reset_cpuonly();
#if defined(_FM77AV_VARIANTS)
power_on_reset = false;
- use_alu = false;
for(i = 0; i < 411; i++) vram_wrote_table[i] = false;
+ nmi_enable = true;
-# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- alu->write_signal(SIG_ALU_X_WIDTH, ((mode320 || mode256k) && !(mode400line)) ? 40 : 80, 0xffff);
- alu->write_signal(SIG_ALU_Y_HEIGHT, (mode400line) ? 400: 200, 0xffff);
- alu->write_signal(SIG_ALU_400LINE, (mode400line) ? 0xffffffff : 0, 0xffffffff);
-# else
- alu->write_signal(SIG_ALU_X_WIDTH, (mode320) ? 40 : 80, 0xffff);
- alu->write_signal(SIG_ALU_Y_HEIGHT, 200, 0xffff);
- alu->write_signal(SIG_ALU_400LINE, 0, 0xffffffff);
-# endif
- alu->write_signal(SIG_ALU_MULTIPAGE, multimode_accessmask, 0x07);
- alu->write_signal(SIG_ALU_PLANES, 3, 3);
-#endif
-
- if(nmi_event_id >= 0) cancel_event(this, nmi_event_id);
- nmi_event_id = -1;
- register_event(this, EVENT_FM7SUB_DISPLAY_NMI, 20000.0, true, &nmi_event_id); // NEXT CYCLE_
- for(i = 0; i < 8; i++) set_dpalette(i, i);
+ //if(nmi_event_id >= 0) cancel_event(this, nmi_event_id);
+ //nmi_event_id = -1;
+ //register_event(this, EVENT_FM7SUB_DISPLAY_NMI, 20000.0, true, &nmi_event_id); // NEXT CYCLE_
+ //for(i = 0; i < 8; i++) set_dpalette(i, i);
subcpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
do_firq(!firq_mask && key_firq_req);
+#endif
subcpu->reset();
}
void DISPLAY::do_nmi(bool flag)
{
#if defined(_FM77AV_VARIANTS)
- if(!nmi_enable && flag) flag = false;
+ if(!nmi_enable) flag = false;
#endif
subcpu->write_signal(SIG_CPU_NMI, flag ? 1 : 0, 1);
}
halt_flag = false;
#if defined(_FM77AV_VARIANTS)
if(subcpu_resetreq) {
-#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- monitor_ram_using = monitor_ram;
-#endif
- subrom_bank_using = subrom_bank;
reset_cpuonly();
+ power_on_reset = true;
subcpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
subcpu->reset();
do_firq(!firq_mask && key_firq_req);
if(!hblank) ret |= 0x80;
if(vsync) ret |= 0x04;
if(alu->read_signal(SIG_ALU_BUSYSTAT) == 0) ret |= 0x10;
- if(!power_on_reset) ret |= 0x01;
+ if(power_on_reset) ret |= 0x01;
#else // 77 or older.
ret = 0xff;
#endif
int old_display_page = display_page;
#if defined(_FM77AV_VARIANTS)
nmi_enable = ((val & 0x80) == 0) ? true : false;
+ if(!nmi_enable) do_nmi(false);
#endif
if((val & 0x40) == 0) {
display_page = 0;
} else {
monitor_ram = false;
}
- monitor_ram_using = monitor_ram;
#endif
subrom_bank = var & 0x03;
vram_wrote = true;
if(!halt_flag) {
subcpu_resetreq = false;
- subrom_bank_using = subrom_bank;
-#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- monitor_ram_using = monitor_ram;
-#endif
+ power_on_reset = true;
reset_cpuonly();
subcpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
subcpu->reset();
if(nmi_enable) {
do_nmi(true);
} else {
- do_nmi(false);
+ //do_nmi(false);
}
#else
do_nmi(true);
retval = (!hblank) ? 0x02: 0x00;
break;
case SIG_FM7_SUB_BANK: // Main: FD13
- retval = subrom_bank;
+ retval = subrom_bank & 0x03;
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
if(monitor_ram) retval |= 0x04;
#endif
case SIG_FM7_SUB_BANK: // Main: FD13
set_monitor_bank(data & 0xff);
break;
+#endif
case SIG_DISPLAY_EXTRA_MODE: // FD04 bit 4, 3
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
{
{
int oldmode = display_mode;
kanjisub = ((data & 0x20) == 0) ? true : false;
-#if defined(_FM77L4)
+# if defined(_FM77L4)
stat_400linecard = ((data & 0x20) != 0) ? true : false;
mode400line = ((data & 0x08) != 0) ? false : true;
if(mode400line && stat_400linecard) {
} else {
display_mode = DISPLAY_MODE_8_200L;
}
-#endif
+# endif
}
#endif
break;
vram_wrote = true;
#endif
break;
-#endif // _FM77AV_VARIANTS
case SIG_DISPLAY_MULTIPAGE:
set_multimode(data);
break;
{
uint32 retval = 0xff;
uint32 raddr;
+ if(addr < 0xd400) return 0xff;
+
#if !defined(_FM77AV_VARIANTS)
raddr = (addr - 0xd400) & 0x000f;
-#else
+#elif !defined(_FM77AV40SX) && !defined(_FM77AV40EX)
raddr = (addr - 0xd400) & 0x003f;
+#else // FM77AV40EX || FM77AV40SX
+ raddr = (addr - 0xd400) & 0x00ff;
#endif
switch(raddr) {
case 0x00: // Read keyboard
if(addr < 0xc000) {
#if defined(_FM77AV_VARIANTS)
if(use_alu) {
- return alu->read_data8(addr + ALU_WRITE_PROXY);
+ alu->read_data8(addr + ALU_WRITE_PROXY);
}
# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
if(display_mode == DISPLAY_MODE_8_400L) {
} else if(addr < 0xd000) {
raddr = addr - 0xc000;
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- if(monitor_ram_using) {
+ if(monitor_ram) {
if(console_ram_bank >= 1) {
return submem_console_av40[((console_ram_bank - 1) << 12) + raddr];
}
#else
if(addr < 0xe000) {
# if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
- if(monitor_ram_using) {
+ if(monitor_ram) {
return submem_cgram[cgram_bank * 0x0800 + (addr - 0xd800)]; //FIXME
}
#endif
return subsys_cg[(addr - 0xd800) + cgrom_bank * 0x800];
} else if(addr < 0x10000) {
# if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
- if(monitor_ram_using) {
+ if(monitor_ram) {
return subsys_ram[addr - 0xe000];
}
#endif
// ACCESS VIA ALU.
else if((addr >= DISPLAY_VRAM_DIRECT_ACCESS) && (addr < (DISPLAY_VRAM_DIRECT_ACCESS + 0x18000))) {
addr = addr - DISPLAY_VRAM_DIRECT_ACCESS;
- uint32 color = (addr & 0x0c000) >> 14;
-# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- if(display_mode == DISPLAY_MODE_8_400L){
- color = (addr & 0x18000) >> 15;
- }
-# endif
- if((multimode_accessmask & (1 << color)) != 0) return 0xff;
+
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
if(mode400line) {
return read_vram_8_400l_direct(addr, offset << 1);
{
uint8 rval = 0;
pair tmpvar;
+ if(addr < 0xd400) return;
+
#if !defined(_FM77AV_VARIANTS)
- addr = addr & 0x000f;
-#else
- addr = addr & 0x003f;
+ addr = (addr - 0xd400) & 0x000f;
+#elif !defined(_FM77AV40SX) && !defined(_FM77AV40EX)
+ addr = (addr - 0xd400) & 0x003f;
+#else // FM77AV40EX || FM77AV40SX
+ addr = (addr - 0xd400) & 0x00ff;
#endif
io_w_latch[addr] = (uint8)data;
switch(addr) {
uint8 val8 = data & 0xff;
uint32 offset;
uint32 raddr;
+ uint32 page_offset = 0x0000;
#if defined(_FM77AV_VARIANTS)
if (active_page != 0) {
#else
offset = offset_point;
#endif
+
if(addr < 0xc000) {
#if defined(_FM77AV_VARIANTS)
uint32 color;
color = (addr & 0x0c000) >> 14;
- if(use_alu) {
- alu->read_data8(addr + ALU_WRITE_PROXY);
- return;
- }
+ //if(use_alu) {
+ // alu->read_data8(addr + ALU_WRITE_PROXY);
+ // return;
+ //}
# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
if(display_mode == DISPLAY_MODE_8_400L){
color = vram_bank;
# endif
if((multimode_accessmask & (1 << color)) != 0) return;
# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- if(mode400line) {
+ if(display_mode == DISPLAY_MODE_8_400L) {
if(addr < 0x8000) {
write_vram_8_400l(addr, offset << 1, data);
vram_wrote_table[((addr + offset) % 0x8000) / 80] = true;
}
- } else if(mode256k) {
+ } else if(display_mode == DISPLAY_MODE_256k) {
write_vram_256k(addr, offset, data);
vram_wrote_table[((addr + offset) % 0x2000) / 40] = true;
- } else if(mode320) {
+ } else if(display_mode == DISPLAY_MODE_4096) {
write_vram_4096(addr, offset, data);
vram_wrote_table[((addr + offset) % 0x2000) / 40] = true;
} else { // 8Colors, 200LINE
} else if(addr < 0xd000) {
raddr = addr - 0xc000;
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- if(monitor_ram_using) {
+ if(monitor_ram) {
if(console_ram_bank >= 1) {
submem_console_av40[((console_ram_bank - 1) << 12) + raddr] = val8;
return;
return;
} else if(addr < 0x10000) {
# if defined(_FM77AV40) || defined(_FM77AV40SX) || defined(_FM77AV40EX)
- if(ram_protect || !(monitor_ram_using)) return;
- if(addr < 0xe000) {
- submem_cgram[cgram_bank * 0x0800 + (addr - 0xd800)] = val8; //FIXME
- } else {
- subsys_ram[addr - 0xe000] = val8;
+ if(ram_protect) return;
+ if(monitor_ram) {
+ if(addr < 0xe000) {
+ submem_cgram[cgram_bank * 0x0800 + (addr - 0xd800)] = val8; //FIXME
+ } else {
+ subsys_ram[addr - 0xe000] = val8;
+ }
}
#endif
return;
// ACCESS VIA ALU.
else if((addr >= DISPLAY_VRAM_DIRECT_ACCESS) && (addr < (DISPLAY_VRAM_DIRECT_ACCESS + 0x18000))) {
addr = addr - DISPLAY_VRAM_DIRECT_ACCESS;
- uint32 color = (addr & 0x0c000) >> 14;
-# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- if(display_mode == DISPLAY_MODE_8_400L){
- color = (addr & 0x18000) >> 15;
- }
-# endif
- if((multimode_accessmask & (1 << color)) != 0) return;
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
if(mode400line) {
write_vram_8_400l_direct(addr, offset << 1, data);
state_fio->FputBool(mode256k);
state_fio->FputBool(monitor_ram);
- state_fio->FputBool(monitor_ram_using);
-
# if defined(_FM77AV40EX) || defined(_FM77AV40SX)
state_fio->FputUint16_BE(window_low);
state_fio->FputUint16_BE(window_high);
mode256k = state_fio->FgetBool();
monitor_ram = state_fio->FgetBool();
- monitor_ram_using = state_fio->FgetBool();
-
# if defined(_FM77AV40EX) || defined(_FM77AV40SX)
window_low = state_fio->FgetUint16_BE();
window_high = state_fio->FgetUint16_BE();