}
}
+static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu,
+ KVMScratchCPU *kvmcpu)
+{
+ CPURISCVState *env = &cpu->env;
+ struct kvm_one_reg reg;
+ int ret;
+
+ reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
+ KVM_REG_RISCV_CONFIG_REG(isa));
+ reg.addr = (uint64_t)&env->misa_ext_mask;
+ ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®);
+
+ if (ret) {
+ error_report("Unable to fetch ISA register from KVM, "
+ "error %d", ret);
+ kvm_riscv_destroy_scratch_vcpu(kvmcpu);
+ exit(EXIT_FAILURE);
+ }
+
+ env->misa_ext = env->misa_ext_mask;
+}
+
void kvm_riscv_init_user_properties(Object *cpu_obj)
{
RISCVCPU *cpu = RISCV_CPU(cpu_obj);
}
kvm_riscv_init_machine_ids(cpu, &kvmcpu);
+ kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
kvm_riscv_destroy_scratch_vcpu(&kvmcpu);
}
int kvm_arch_init_vcpu(CPUState *cs)
{
int ret = 0;
- target_ulong isa;
RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- uint64_t id;
qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
- id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
- KVM_REG_RISCV_CONFIG_REG(isa));
- ret = kvm_get_one_reg(cs, id, &isa);
- if (ret) {
- return ret;
- }
- env->misa_ext = isa;
-
if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
ret = kvm_vcpu_set_machine_ids(cpu, cs);
}