radeon_emit(cs, va >> 8); /* BUFFER_BASE */
r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE, RADEON_PRIO_RINGS_STREAMOUT);
+ RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RW_BUFFER);
/* R7xx requires this packet after updating BUFFER_BASE.
* Without this, R7xx locks up. */
radeon_emit(cs, va >> 8);
r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE, RADEON_PRIO_RINGS_STREAMOUT);
+ RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RW_BUFFER);
}
}
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)buffer,
buffers->shader_usage,
- buffers->priority, true);
+ RADEON_PRIO_SHADER_RW_BUFFER,
+ true);
buffers->enabled_mask |= 1u << bufidx;
} else {
/* Clear the descriptor and unset the resource. */
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rbuffer, buffers->shader_usage,
- buffers->priority, true);
+ RADEON_PRIO_SHADER_RW_BUFFER,
+ true);
/* Update the streamout state. */
if (sctx->b.streamout.begin_emitted)