intel/isl/gen4: Make depth/stencil buffers Y-Tiled

Rendering to a linear depth buffer on gen4 is causing a GPU hang in the
CI system. Until a better explanation is found, assume that errata is
applicable to all gen4 platforms.

Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").

Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
index 14706c8..a212d0e 100644 (file)
--- a/src/intel/isl/isl_gen4.c
+++ b/src/intel/isl/isl_gen4.c
@@ -51,8 +51,15 @@ isl_gen4_filter_tiling(const struct isl_device *dev,
       /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
        *
        *    "The Depth Buffer, if tiled, must use Y-Major tiling"
+       *
+       *    Errata   Description    Project
+       *    BWT014   The Depth Buffer Must be Tiled, it cannot be linear. This
+       *    field must be set to 1 on DevBW-A.  [DevBW -A,B]
+       *
+       * In testing, the linear configuration doesn't seem to work on gen4.
        */
-      *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_Y0_BIT);
+      *flags &= (ISL_DEV_GEN(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ?
+                ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT);
    }
 
    if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |