ARM: dts: Configure interconnect target module for am3 sham

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

I could not find any documentation for the sysc register on this one,
but it seems to work just fine with "ti,sysc-omap3-sham" compatible
style configuration.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 646f114..0d7323b 100644 (file)
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -439,13 +439,33 @@
                        status = "disabled";
                };
 
-               sham: sham@53100000 {
-                       compatible = "ti,omap4-sham";
+               sham_target: target-module@53100000 {
+                       compatible = "ti,sysc-omap3-sham", "ti,sysc";
                        ti,hwmods = "sham";
-                       reg = <0x53100000 0x200>;
-                       interrupts = <109>;
-                       dmas = <&edma 36 0>;
-                       dma-names = "rx";
+                       reg = <0x53100100 0x4>,
+                             <0x53100110 0x4>,
+                             <0x53100114 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,syss-mask = <1>;
+                       /* Domains (P, C): per_pwrdm, l3_clkdm */
+                       clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x53100000 0x1000>;
+
+                       sham: sham@0 {
+                               compatible = "ti,omap4-sham";
+                               reg = <0 0x200>;
+                               interrupts = <109>;
+                               dmas = <&edma 36 0>;
+                               dma-names = "rx";
+                       };
                };
 
                aes: aes@53500000 {