constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
- constant CFG_GRGPIO_ENABLE : integer := 0;
+ constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
- constant CFG_GRGPIO_WIDTH : integer := 1;
+ constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
- constant CFG_KBD_ENABLE : integer := 1;
+ constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
library esa;
use esa.memoryctrl.all;
+library kuri;
+use kuri.mjpeg.all;
use work.config.all;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
- CFG_ATA+CFG_GRUSBDC;
+ CFG_ATA+CFG_GRUSBDC + 1;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
end generate;
-------------------------------------------------------------------------------
+-- YCC-RGB translation module ---------------------------------------
+-------------------------------------------------------------------------------
+ jpgycc : yccrgbs
+ generic map(shindex => 4, haddr => 16#A00#, hirq => 10, pindex => 12,
+ paddr => 12, mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
+ CFG_GRUSBDC+CFG_ATA )
+ port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
+ ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
+ CFG_GRUSBDC+CFG_ATA), ahbsi => ahbsi, ahbso => ahbso(4),
+ apbi => apbi, apbo => apbo(12)
+ );
+
+
+
+-------------------------------------------------------------------------------
-- For BLANCA
-------------------------------------------------------------------------------
uart_ensig <= '0';
+//#define NORMALTEST
+//#define IP_CONNECT
+#define BOARD_TEST
main()
-
{
+#ifdef NORMALTEST
report_start();
-
base_test();
greth_test(0x80000d00);
-// spw_test(0x80000A00);
-// spw_test(0x80000B00);
-// spw_test(0x80000C00);
report_end();
+#endif
+
+#ifdef IP_CONNECT
+ yccrgbs_connect();
+#endif
+
+#ifdef BOARD_TEST
+ yccrgbs_pic();
+#endif
+
}
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Synthesis
+#
+# CONFIG_SYN_INFERRED is not set
+# CONFIG_SYN_STRATIX is not set
+# CONFIG_SYN_STRATIXII is not set
+# CONFIG_SYN_STRATIXIII is not set
+CONFIG_SYN_CYCLONEIII=y
+# CONFIG_SYN_ALTERA is not set
+# CONFIG_SYN_AXCEL is not set
+# CONFIG_SYN_AXDSP is not set
+# CONFIG_SYN_PROASIC is not set
+# CONFIG_SYN_PROASICPLUS is not set
+# CONFIG_SYN_PROASIC3 is not set
+# CONFIG_SYN_IGLOO is not set
+# CONFIG_SYN_UT025CRH is not set
+# CONFIG_SYN_ATC18 is not set
+# CONFIG_SYN_ATC18RHA is not set
+# CONFIG_SYN_CUSTOM1 is not set
+# CONFIG_SYN_EASIC90 is not set
+# CONFIG_SYN_IHP25 is not set
+# CONFIG_SYN_IHP25RH is not set
+# CONFIG_SYN_LATTICE is not set
+# CONFIG_SYN_ECLIPSE is not set
+# CONFIG_SYN_PEREGRINE is not set
+# CONFIG_SYN_RH_LIB18T is not set
+# CONFIG_SYN_RHUMC is not set
+# CONFIG_SYN_SMIC13 is not set
+# CONFIG_SYN_SPARTAN2 is not set
+# CONFIG_SYN_SPARTAN3 is not set
+# CONFIG_SYN_SPARTAN3E is not set
+# CONFIG_SYN_VIRTEX is not set
+# CONFIG_SYN_VIRTEXE is not set
+# CONFIG_SYN_VIRTEX2 is not set
+# CONFIG_SYN_VIRTEX4 is not set
+# CONFIG_SYN_VIRTEX5 is not set
+# CONFIG_SYN_UMC is not set
+# CONFIG_SYN_TSMC90 is not set
+# CONFIG_SYN_INFER_RAM is not set
+# CONFIG_SYN_INFER_PADS is not set
+# CONFIG_SYN_NO_ASYNC is not set
+# CONFIG_SYN_SCAN is not set
+
+#
+# Clock generation
+#
+# CONFIG_CLK_INFERRED is not set
+# CONFIG_CLK_HCLKBUF is not set
+CONFIG_CLK_ALTDLL=y
+# CONFIG_CLK_LATDLL is not set
+# CONFIG_CLK_PRO3PLL is not set
+# CONFIG_CLK_LIB18T is not set
+# CONFIG_CLK_RHUMC is not set
+# CONFIG_CLK_CLKDLL is not set
+# CONFIG_CLK_DCM is not set
+CONFIG_CLK_MUL=5
+CONFIG_CLK_DIV=5
+# CONFIG_PCI_SYSCLK is not set
+CONFIG_LEON3=y
+CONFIG_PROC_NUM=1
+
+#
+# Processor
+#
+
+#
+# Integer unit
+#
+CONFIG_IU_NWINDOWS=8
+CONFIG_IU_V8MULDIV=y
+# CONFIG_IU_MUL_LATENCY_2 is not set
+# CONFIG_IU_MUL_LATENCY_4 is not set
+CONFIG_IU_MUL_LATENCY_5=y
+# CONFIG_IU_MUL_MAC is not set
+# CONFIG_IU_SVT is not set
+CONFIG_IU_LDELAY=1
+CONFIG_IU_WATCHPOINTS=2
+# CONFIG_PWD is not set
+CONFIG_IU_RSTADDR=00000
+
+#
+# Floating-point unit
+#
+# CONFIG_FPU_ENABLE is not set
+
+#
+# Cache system
+#
+CONFIG_ICACHE_ENABLE=y
+# CONFIG_ICACHE_ASSO1 is not set
+CONFIG_ICACHE_ASSO2=y
+# CONFIG_ICACHE_ASSO3 is not set
+# CONFIG_ICACHE_ASSO4 is not set
+# CONFIG_ICACHE_SZ1 is not set
+# CONFIG_ICACHE_SZ2 is not set
+CONFIG_ICACHE_SZ4=y
+# CONFIG_ICACHE_SZ8 is not set
+# CONFIG_ICACHE_SZ16 is not set
+# CONFIG_ICACHE_SZ32 is not set
+# CONFIG_ICACHE_SZ64 is not set
+# CONFIG_ICACHE_SZ128 is not set
+# CONFIG_ICACHE_SZ256 is not set
+# CONFIG_ICACHE_LZ16 is not set
+CONFIG_ICACHE_LZ32=y
+# CONFIG_ICACHE_ALGORND is not set
+CONFIG_ICACHE_ALGOLRR=y
+# CONFIG_ICACHE_ALGOLRU is not set
+# CONFIG_ICACHE_LOCK is not set
+CONFIG_DCACHE_ENABLE=y
+# CONFIG_DCACHE_ASSO1 is not set
+CONFIG_DCACHE_ASSO2=y
+# CONFIG_DCACHE_ASSO3 is not set
+# CONFIG_DCACHE_ASSO4 is not set
+# CONFIG_DCACHE_SZ1 is not set
+# CONFIG_DCACHE_SZ2 is not set
+CONFIG_DCACHE_SZ4=y
+# CONFIG_DCACHE_SZ8 is not set
+# CONFIG_DCACHE_SZ16 is not set
+# CONFIG_DCACHE_SZ32 is not set
+# CONFIG_DCACHE_SZ64 is not set
+# CONFIG_DCACHE_SZ128 is not set
+# CONFIG_DCACHE_SZ256 is not set
+CONFIG_DCACHE_LZ16=y
+# CONFIG_DCACHE_LZ32 is not set
+# CONFIG_DCACHE_ALGORND is not set
+CONFIG_DCACHE_ALGOLRR=y
+# CONFIG_DCACHE_ALGOLRU is not set
+# CONFIG_DCACHE_LOCK is not set
+CONFIG_DCACHE_SNOOP=y
+# CONFIG_DCACHE_SNOOP_FAST is not set
+# CONFIG_DCACHE_SNOOP_SEPTAG is not set
+CONFIG_CACHE_FIXED=0
+
+#
+# MMU
+#
+CONFIG_MMU_ENABLE=y
+# CONFIG_MMU_COMBINED is not set
+CONFIG_MMU_SPLIT=y
+# CONFIG_MMU_REPARRAY is not set
+CONFIG_MMU_REPINCREMENT=y
+# CONFIG_MMU_I2 is not set
+# CONFIG_MMU_I4 is not set
+CONFIG_MMU_I8=y
+# CONFIG_MMU_I16 is not set
+# CONFIG_MMU_I32 is not set
+# CONFIG_MMU_D2 is not set
+# CONFIG_MMU_D4 is not set
+CONFIG_MMU_D8=y
+# CONFIG_MMU_D16 is not set
+# CONFIG_MMU_D32 is not set
+CONFIG_MMU_FASTWB=y
+CONFIG_MMU_PAGE_4K=y
+# CONFIG_MMU_PAGE_8K is not set
+# CONFIG_MMU_PAGE_16K is not set
+# CONFIG_MMU_PAGE_32K is not set
+# CONFIG_MMU_PAGE_PROG is not set
+
+#
+# Debug Support Unit
+#
+CONFIG_DSU_ENABLE=y
+CONFIG_DSU_ITRACE=y
+# CONFIG_DSU_ITRACESZ1 is not set
+CONFIG_DSU_ITRACESZ2=y
+# CONFIG_DSU_ITRACESZ4 is not set
+# CONFIG_DSU_ITRACESZ8 is not set
+# CONFIG_DSU_ITRACESZ16 is not set
+CONFIG_DSU_ATRACE=y
+# CONFIG_DSU_ATRACESZ1 is not set
+CONFIG_DSU_ATRACESZ2=y
+# CONFIG_DSU_ATRACESZ4 is not set
+# CONFIG_DSU_ATRACESZ8 is not set
+# CONFIG_DSU_ATRACESZ16 is not set
+
+#
+# Fault-tolerance
+#
+
+#
+# VHDL debug settings
+#
+# CONFIG_IU_DISAS is not set
+# CONFIG_DEBUG_PC32 is not set
+
+#
+# AMBA configuration
+#
+CONFIG_AHB_DEFMST=0
+CONFIG_AHB_RROBIN=y
+# CONFIG_AHB_SPLIT is not set
+CONFIG_AHB_IOADDR=FFF
+CONFIG_APB_HADDR=800
+# CONFIG_AHB_MON is not set
+
+#
+# Debug Link
+#
+# CONFIG_DSU_UART is not set
+CONFIG_DSU_JTAG=y
+
+#
+# Peripherals
+#
+
+#
+# Memory controllers
+#
+
+#
+# Leon2 memory controller
+#
+CONFIG_MCTRL_LEON2=y
+# CONFIG_MCTRL_8BIT is not set
+CONFIG_MCTRL_16BIT=y
+# CONFIG_MCTRL_5CS is not set
+# CONFIG_MCTRL_SDRAM is not set
+
+#
+# Synchronous SRAM controller
+#
+# CONFIG_SSCTRL is not set
+
+#
+# DDR266 SDRAM controller
+#
+CONFIG_DDRSP=y
+CONFIG_DDRSP_INIT=y
+CONFIG_DDRSP_FREQ=100
+CONFIG_DDRSP_COL=9
+CONFIG_DDRSP_MBYTE=8
+CONFIG_DDRSP_RSKEW=2500
+
+#
+# SPI memory controller
+#
+# CONFIG_SPIMCTRL is not set
+
+#
+# On-chip RAM/ROM
+#
+# CONFIG_AHBROM_ENABLE is not set
+# CONFIG_AHBRAM_ENABLE is not set
+
+#
+# Ethernet
+#
+# CONFIG_GRETH_ENABLE is not set
+
+#
+# UARTs, timers and irq control
+#
+CONFIG_UART1_ENABLE=y
+# CONFIG_UA1_FIFO1 is not set
+# CONFIG_UA1_FIFO2 is not set
+# CONFIG_UA1_FIFO4 is not set
+CONFIG_UA1_FIFO8=y
+# CONFIG_UA1_FIFO16 is not set
+# CONFIG_UA1_FIFO32 is not set
+CONFIG_IRQ3_ENABLE=y
+# CONFIG_IRQ3_SEC is not set
+CONFIG_GPT_ENABLE=y
+CONFIG_GPT_NTIM=2
+CONFIG_GPT_SW=8
+CONFIG_GPT_TW=32
+CONFIG_GPT_IRQ=8
+CONFIG_GPT_SEPIRQ=y
+# CONFIG_GPT_WDOGEN is not set
+CONFIG_GRGPIO_ENABLE=y
+CONFIG_GRGPIO_WIDTH=5
+CONFIG_GRGPIO_IMASK=0
+
+#
+# Serial interfaces; I2C, PS/2 and SPI
+#
+CONFIG_I2C_ENABLE=y
+CONFIG_PS2_ENABLE=y
+
+#
+# SPI controller
+#
+CONFIG_SPICTRL_ENABLE=y
+CONFIG_SPICTRL_SLVS=1
+CONFIG_SPICTRL_FIFO=2
+CONFIG_SPICTRL_SLVREG=y
+# CONFIG_SPICTRL_ASEL is not set
+# CONFIG_SPICTRL_AM is not set
+# CONFIG_SPICTRL_ODMODE is not set
+
+#
+# LCD and VGA DAC
+#
+CONFIG_LCD_ENABLE=y
+CONFIG_LCD3T_ENABLE=y
+# CONFIG_SVGA_ENABLE is not set
+
+#
+# VHDL Debugging
+#
+# CONFIG_DEBUG_UART is not set
--- /dev/null
+GRLIB=../..
+TOP=leon3mp
+BOARD=altera-ep3c25-eek
+include $(GRLIB)/boards/$(BOARD)/Makefile.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
+QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
+EFFORT=std
+XSTOPT=
+SYNPOPT="set_option -pipe 1; set_option -retiming 1"
+VHDLSYNFILES=config.vhd ahbrom.vhd serializer.vhd altera_eek_clkgen.vhd \
+ leon3mp.vhd
+VHDLSIMFILES=testbench.vhd
+SIMTOP=testbench
+SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
+BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
+CLEAN=soft-clean
+
+TECHLIBS = altera altera_mf cycloneiii
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+ tmtc openchip ihp gleichmann stratixii stratixiii usbhc spw
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
+ grusbhc spacewire hcan
+FILESKIP = grcan.vhd
+
+include $(GRLIB)/software/leon3/Makefile
+include $(GRLIB)/bin/Makefile
+
+
+################## project specific targets ##########################
+
--- /dev/null
+
+This leon3 design is tailored to the Altera NiosII Cyclone III
+Embedded Evaluation Kit, with 16-bit DDR SDRAM and 1 Mbyte of SSRAM.
+The kit consists of a Cyclone III FPGA starter board and the LCD
+Multimedia Daughter Card.
+
+0. Introduction
+---------------
+
+The leon3 design can be synthesized with quartus or synplify,
+and can reach 60 - 70 MHz depending on configuration and synthesis
+options. Use 'make quartus' or 'make quartus-synp' to run the
+complete flow. To program the FPGA in batch mode, use
+'make quartus-prog-fpga' or
+'make quartus-prog-fpga-ref (reference config).
+
+This template design does not require modification of the logic in the
+daughter card CPLD. The CPLD is assumed to have its default configuration.
+
+The daughter card documentation has the following notice to avoid
+bus contention:
+
+"There are two LVDS termination resistors on the Cyclone III FPGA
+Starter Board, R3 and R4. R3 connects HC_RX_CLK and HC_TD_27MHZ;
+R4 connects HC_ADC_PENIRQ_n and HC_TX_CLK."
+
+When using Disable Setting
+Video decoder Ethernet PHY HC_ETH_RESET_N to 0
+Touch panel Ethernet PHY HC_ETH_RESET_N to 0
+Ethernet PHY Video decoder HC_TD_RESET to 0 and do not
+ use the touch panel function
+ when the ethernet PHY is
+ enabled.
+
+In the template design, HC_TD_RESET is always driven to '0'.
+The user is responsible for not using the touch panel at
+the same time as the Ethernet PHY is in use.
+
+1. Unsupported peripherals / Further development
+------------------------------------------------
+
+The video decoder and audio decoder are not used.
+
+2. System
+---------
+
+The output from grmon should look something like this:
+
+grmon -altjtag -jtagdevice 1 -ramrws 1 -normw
+
+ GRMON LEON debug monitor v1.1.30
+
+ Copyright (C) 2004-2008 Gaisler Research - all rights reserved.
+ For latest updates, go to http://www.gaisler.com/
+ Comments or bug-reports to support@gaisler.com
+
+ using Altera JTAG cable
+ Selected cable 1 - USB-Blaster [USB 1-1.1]
+JTAG chain:
+@1: EP3C25 (0x020F30DD)
+
+ GRLIB build version: 3050
+
+ initialising ................
+ detected frequency: 50 MHz
+
+ Component Vendor
+ LEON3 SPARC V8 Processor Gaisler Research
+ AHB Debug JTAG TAP Gaisler Research
+ SVGA frame buffer Gaisler Research
+ GR Ethernet MAC Gaisler Research
+ LEON2 Memory Controller European Space Agency
+ AHB/APB Bridge Gaisler Research
+ LEON3 Debug Support Unit Gaisler Research
+ DDR266 Controller Gaisler Research
+ Generic APB UART Gaisler Research
+ Multi-processor Interrupt Ctrl Gaisler Research
+ Modular Timer Unit Gaisler Research
+ General purpose I/O port Gaisler Research
+ Keyboard PS/2 interface Gaisler Research
+ AMBA Wrapper for OC I2C-master Gaisler Research
+ SPI Controller Gaisler Research
+ SPI Controller Gaisler Research
+
+ Use command 'info sys' to print a detailed report of attached cores
+
+grlib> inf sys
+00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
+ ahb master 0
+01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
+ ahb master 1
+02.01:063 Gaisler Research SVGA frame buffer (ver 0x0)
+ ahb master 2
+ apb: 80000b00 - 80000c00
+ clk0: 33.20 MHz
+03.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
+ ahb master 3, irq 10
+ apb: 80000a00 - 80000b00
+ edcl ip 192.168.0.57, buffer 2 kbyte
+00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
+ ahb: 00000000 - 20000000
+ ahb: 20000000 - 40000000
+ ahb: a0000000 - b0000000
+ apb: 80000000 - 80000100
+ 16-bit prom @ 0x00000000
+ 32-bit static ram: 1 * 1024 kbyte @ 0xa0000000
+01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
+ ahb: 80000000 - 80100000
+02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
+ ahb: 90000000 - a0000000
+ AHB trace 128 lines, stack pointer 0xa00ffff0
+ CPU#0 win 8, hwbp 2, itrace 128, V8 mul/div, lddel 1
+ icache 2 * 8 kbyte, 32 byte/line lru
+ dcache 2 * 4 kbyte, 16 byte/line lru
+03.01:025 Gaisler Research DDR266 Controller (ver 0x0)
+ ahb: 40000000 - 50000000
+ ahb: fff00100 - fff00200
+ 16-bit DDR : 1 * 32 Mbyte @ 0x40000000
+ 100 MHz, col 9, ref 7.8 us
+01.01:00c Gaisler Research Generic APB UART (ver 0x1)
+ irq 2
+ apb: 80000100 - 80000200
+ baud rate 38343
+02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
+ apb: 80000200 - 80000300
+03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
+ irq 8
+ apb: 80000300 - 80000400
+ 8-bit scaler, 2 * 32-bit timers, divisor 50
+05.01:01a Gaisler Research General purpose I/O port (ver 0x0)
+ apb: 80000500 - 80000600
+06.01:060 Gaisler Research Keyboard PS/2 interface (ver 0x1)
+ irq 6
+ apb: 80000600 - 80000700
+08.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x0)
+ irq 11
+ apb: 80000800 - 80000900
+09.01:02d Gaisler Research SPI Controller (ver 0x1)
+ irq 9
+ apb: 80000900 - 80000a00
+ FIFO depth: 4, 1 slave select signals
+ Controller index for use in GRMON: 1
+0c.01:02d Gaisler Research SPI Controller (ver 0x1)
+ irq 12
+ apb: 80000c00 - 80000d00
+ FIFO depth: 4, 2 slave select signals
+ Controller index for use in GRMON: 2
+grlib>
+
+3. DDR interface
+----------------
+
+The DDR interface is supported and runs at 100 MHz.
+The read data clock phase shift should be set to 90' (rskew = 2500).
+
+4. SSRAM interface
+------------------
+
+The SSRAM can be accessed using the standard LEON2 MCTRL core.
+One read waitstate is needed, start grmon with :
+
+ grmon -altjtag -jtagdevice 1 -ramrws 1 -normw
+
+5. Flash memory
+---------------
+
+The 16-bit flash memory can be accessed and programmed by grmon,
+if the SSRAM is working. The output from the 'flash' command is
+listed below:
+
+grlib> fla
+
+ Intel-style 16-bit flash on D[31:16]
+
+ Manuf. Intel
+ Device 0x881B
+
+ Device ID 70a6ffff00684403
+ User ID ffffffffffffffff
+
+
+ 1 x 16 Mbyte = 16 Mbyte total @ 0x00000000
+
+
+ CFI info
+ flash family : 1
+ flash size : 128 Mbit
+ erase regions : 2
+ erase blocks : 131
+ write buffer : 64 bytes
+ region 0 : 4 blocks of 32 Kbytes
+ region 1 : 127 blocks of 128 Kbytes
+
+
+5.1 How to program the flash prom with a FPGA programming file
+--------------------------------------------------------------
+
+There are two ways of programming the Flash memory. One using
+Altera's Parallel Flash Loader and one using GRMON.
+
+Programming the Flash using Altera's Parallel Flash Loader:
+
+ 1. Start Quartus II and select File -> Convert Programming Files
+
+ 2. Make the following settings:
+
+ Programming File Type: Programmer Object file (.pof)
+ Mode: Active Parallel
+ Configuration device: CFI_128MB
+
+ 3. Select "Configuration Master" under "Input files to convert" and click
+ "Add file"
+
+ 4. Select the leon3mp.sof file and click OK
+
+ 5. Select "SOF data" and click "Properties"
+
+ 6. Change the following properties:
+
+ Address mode for selected pages: Start
+ Start address: 0x020000
+
+ 7. Generate the programmer object file by clicking "Generate"
+
+ 8. Start the Quartus II programmer
+
+ 9. Click "Auto Detect"
+
+ 10. Right-click on the detected EP3C25 device and select "Attach Flash Device"
+
+ 11. Select Flash Memory, CFI_128MB and click "OK"
+
+ 12. Right click on the added CFI_128MB Flash device and select "Change File"
+
+ 13. Select the .pof file that was generated in step 7 and click "OK".
+
+ 14. Check the "Program/Configure" box for the added file under the Flash
+ device. Checking this box will change the Device File to "Factory
+ default PFL image"
+
+ 15. Click "Start"
+
+ 16. When programming has successfully finished press "Reconfigure" on the
+ board to load the leon3mp design.
+
+Programming the Flash with GRMON:
+
+ 1. Create a hex file of the programming file with Quartus. Choose
+ "Active Parallel" as the Mode. This mode is available in Quartus II 7.2
+
+ 2. Convert the Intel Hex file to srecord format. The hexfile needs to be byte
+ swapped. This can be done with a tool from the SRecord package which can be
+ downloaded from http://srecord.sourceforge.net/. Issue the command:
+
+ srec_cat output_file.hexout -Intel -byteswap > fpga.srec
+
+ If the resulting fpga.srec file does not have the correct offset, the
+ offset may have to be given as an argument to srec_cat:
+
+ srec_cat output_file.hexout -Intel -byteswap -offset 0x20000 > fpga.srec
+
+ To see that the data has the correct offset, issue the command:
+
+ srec_info fpga.srec
+
+ The "Data:" area should start at 020000.
+
+ 3. Program the flash memory using grmon:
+
+ flash unlock all
+ flash erase 0x20000 0x100000
+ flash load fpga.srec
+
+The programming is slow, and will take at approximately 30 minutes with a JTAG
+connection. The ethernet debug link is significantly faster.
+
+6. SPI SD Card interface
+----------------
+
+The design instantiates a SPICTRL core which is connected to the SD card slot.
+The user may deselect the SPI controller (SPICTRL) and enable the SPI memory
+controller instead. SPIMCTRL allows reading SD cards without additonal software
+support. The design will not synthesize if both cores are enabled.
+
+Suitable configuration values for SPIMCTRL are; SD Card = 1, Clock divisor = 2,
+Alt. clock divisor = 7. Note that the SPIMCTRL core will insert a large amount
+of wait states on the system bus if AMBA SPLIT support is not enabled.
+
+7. Ethernet interface
+---------------------
+
+The design can be configured to instantiate a GRETH. Note that if the
+LCD touch panel interface is enabled the GRETH is not instantiated
+even if it is selected in xconfig. See the note about bus contention
+in section 0. Introduction of this file.
+
+
+8. I2C interface
+----------------
+
+The design instantiates an I2C-master that is connected to the daughter
+card EEPROM. The daughter card uses uni-directional I2C clock lines
+and this prevents slaves from stretching the master clock.
+
+grlib> i2c read 0x50 0 16
+
+ 00: 10 10 00 07
+ 04: ed 08 07 6d
+ 08: 0f 6a 0f 09
+ 0c: 00 84 00 94
+
+9. LCD support
+---------------
+
+Two cores must be instantiated to fully support all the functionality
+of the LCD touch panel. For video display an SVGACTRL core is
+instantiated. The 3-wire interface and panel ADC is interfaced with
+an instantiation of a SPICTRL core. The designer can configure the
+design to exclude any of these cores.
+
+The 3-wire serial interface and the touch panel ADC are wired to
+share the same clock. The touch panel slave select signal is wired
+to the first slave select signal of the SPICTRL core. The three wire
+enable signal is wired to the second slave select signal.
+
+The ADC busy and interrupt signals are connected to GPIO 3 and 4,
+respectively, and can be accessed via the GRGPIO core.
+
+10. VGA support
+---------------
+
+The designer can enable a SVGACTRL core to drive the VGA DAC.
+
+
+11. Loading and starting an OS from GRMON
+-----------------------------------------
+
+Before loading an OS with GRMON it may be necessary to adjust
+the stack pointer. This can be done by supplying the flag
+
+ -stack 0x41ffff00
+
+or by using the GRMON command
+
+ stack 0x41ffff00
+
+after a connection has been made to the board.
+
--- /dev/null
+
+----------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2004 GAISLER RESEARCH
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- See the file COPYING for the full details of the license.
+--
+-----------------------------------------------------------------------------
+-- Entity: ahbrom
+-- File: ahbrom.vhd
+-- Author: Jiri Gaisler - Gaisler Research
+-- Description: AHB rom. 0/1-waitstate read
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+entity ahbrom is
+ generic (
+ hindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ pipe : integer := 0;
+ tech : integer := 0;
+ kbytes : integer := 1);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type
+ );
+end;
+
+architecture rtl of ahbrom is
+constant abits : integer := 9;
+constant bytes : integer := 288;
+
+constant hconfig : ahb_config_type := (
+ 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
+ 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
+
+signal romdata : std_logic_vector(31 downto 0);
+signal addr : std_logic_vector(abits-1 downto 2);
+signal hsel, hready : std_ulogic;
+
+begin
+
+ ahbso.hresp <= "00";
+ ahbso.hsplit <= (others => '0');
+ ahbso.hirq <= (others => '0');
+ ahbso.hcache <= '1';
+ ahbso.hconfig <= hconfig;
+ ahbso.hindex <= hindex;
+
+ reg : process (clk)
+ begin
+ if rising_edge(clk) then
+ addr <= ahbsi.haddr(abits-1 downto 2);
+ end if;
+ end process;
+
+ p0 : if pipe = 0 generate
+ ahbso.hrdata <= romdata;
+ ahbso.hready <= '1';
+ end generate;
+
+ p1 : if pipe = 1 generate
+ reg2 : process (clk)
+ begin
+ if rising_edge(clk) then
+ hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
+ hready <= ahbsi.hready;
+ ahbso.hready <= (not rst) or (hsel and hready) or
+ (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
+ ahbso.hrdata <= romdata;
+ end if;
+ end process;
+ end generate;
+
+ comb : process (addr)
+ begin
+ case conv_integer(addr) is
+ when 16#00000# => romdata <= X"81D82000";
+ when 16#00001# => romdata <= X"03000004";
+ when 16#00002# => romdata <= X"821060C0";
+ when 16#00003# => romdata <= X"81884000";
+ when 16#00004# => romdata <= X"81900000";
+ when 16#00005# => romdata <= X"81980000";
+ when 16#00006# => romdata <= X"81800000";
+ when 16#00007# => romdata <= X"01000000";
+ when 16#00008# => romdata <= X"03000040";
+ when 16#00009# => romdata <= X"8210600F";
+ when 16#0000A# => romdata <= X"C2A00040";
+ when 16#0000B# => romdata <= X"87444000";
+ when 16#0000C# => romdata <= X"8608E01F";
+ when 16#0000D# => romdata <= X"88100000";
+ when 16#0000E# => romdata <= X"8A100000";
+ when 16#0000F# => romdata <= X"8C100000";
+ when 16#00010# => romdata <= X"8E100000";
+ when 16#00011# => romdata <= X"A0100000";
+ when 16#00012# => romdata <= X"A2100000";
+ when 16#00013# => romdata <= X"A4100000";
+ when 16#00014# => romdata <= X"A6100000";
+ when 16#00015# => romdata <= X"A8100000";
+ when 16#00016# => romdata <= X"AA100000";
+ when 16#00017# => romdata <= X"AC100000";
+ when 16#00018# => romdata <= X"AE100000";
+ when 16#00019# => romdata <= X"90100000";
+ when 16#0001A# => romdata <= X"92100000";
+ when 16#0001B# => romdata <= X"94100000";
+ when 16#0001C# => romdata <= X"96100000";
+ when 16#0001D# => romdata <= X"98100000";
+ when 16#0001E# => romdata <= X"9A100000";
+ when 16#0001F# => romdata <= X"9C100000";
+ when 16#00020# => romdata <= X"9E100000";
+ when 16#00021# => romdata <= X"86A0E001";
+ when 16#00022# => romdata <= X"16BFFFEF";
+ when 16#00023# => romdata <= X"81E00000";
+ when 16#00024# => romdata <= X"82102002";
+ when 16#00025# => romdata <= X"81904000";
+ when 16#00026# => romdata <= X"03000004";
+ when 16#00027# => romdata <= X"821060E0";
+ when 16#00028# => romdata <= X"81884000";
+ when 16#00029# => romdata <= X"01000000";
+ when 16#0002A# => romdata <= X"01000000";
+ when 16#0002B# => romdata <= X"01000000";
+ when 16#0002C# => romdata <= X"03200000";
+ when 16#0002D# => romdata <= X"84102233";
+ when 16#0002E# => romdata <= X"C4204000";
+ when 16#0002F# => romdata <= X"0539AE13";
+ when 16#00030# => romdata <= X"8410A260";
+ when 16#00031# => romdata <= X"C4206004";
+ when 16#00032# => romdata <= X"050003FC";
+ when 16#00033# => romdata <= X"C4206008";
+ when 16#00034# => romdata <= X"3D1003FF";
+ when 16#00035# => romdata <= X"BC17A3E0";
+ when 16#00036# => romdata <= X"9C27A060";
+ when 16#00037# => romdata <= X"03100000";
+ when 16#00038# => romdata <= X"81C04000";
+ when 16#00039# => romdata <= X"01000000";
+ when 16#0003A# => romdata <= X"01000000";
+ when 16#0003B# => romdata <= X"01000000";
+ when 16#0003C# => romdata <= X"01000000";
+ when 16#0003D# => romdata <= X"01000000";
+ when 16#0003E# => romdata <= X"01000000";
+ when 16#0003F# => romdata <= X"01000000";
+ when 16#00040# => romdata <= X"00000004";
+ when 16#00041# => romdata <= X"00000000";
+ when 16#00042# => romdata <= X"00000004";
+ when 16#00043# => romdata <= X"00000000";
+ when 16#00044# => romdata <= X"FFFFFFFC";
+ when 16#00045# => romdata <= X"00000000";
+ when 16#00046# => romdata <= X"FFFFFFFC";
+ when 16#00047# => romdata <= X"00000000";
+ when 16#00048# => romdata <= X"00000000";
+ when others => romdata <= (others => '-');
+ end case;
+ end process;
+ -- pragma translate_off
+ bootmsg : report_version
+ generic map ("ahbrom" & tost(hindex) &
+ ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
+ -- pragma translate_on
+ end;
--- /dev/null
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+-- pragma translate_off
+library altera_mf;
+use altera_mf.altpll;
+library grlib;
+use grlib.stdlib.all;
+-- pragma translate_on
+library techmap;
+use techmap.gencomp.all;
+
+entity altera_eek_clkgen is
+ generic (
+ clk0_mul : integer := 1;
+ clk0_div : integer := 1;
+ clk1_mul : integer := 1;
+ clk1_div : integer := 1;
+ clk_freq : integer := 25000);
+ port (
+ inclk0 : in std_ulogic;
+ clk0 : out std_ulogic;
+ clk0x3 : out std_ulogic;
+ clksel : in std_logic_vector(1 downto 0);
+ locked : out std_ulogic);
+end;
+
+architecture rtl of altera_eek_clkgen is
+
+ component altpll
+ generic (
+ intended_device_family : string := "CycloneIII" ;
+ operation_mode : string := "NORMAL" ;
+ compensate_clock : string := "clock0";
+ inclk0_input_frequency : positive;
+ width_clock : positive := 6;
+ clk0_multiply_by : positive := 1;
+ clk0_divide_by : positive := 1;
+ clk1_multiply_by : positive := 1;
+ clk1_divide_by : positive := 1;
+ clk2_multiply_by : positive := 1;
+ clk2_divide_by : positive := 1;
+ clk3_multiply_by : positive := 1;
+ clk3_divide_by : positive := 1
+ );
+ port (
+ inclk : in std_logic_vector(1 downto 0);
+ clkena : in std_logic_vector(5 downto 0);
+ clk : out std_logic_vector(width_clock-1 downto 0);
+ locked : out std_logic
+ );
+ end component;
+
+ signal clkena : std_logic_vector (5 downto 0);
+ signal clkout : std_logic_vector (4 downto 0);
+ signal inclk : std_logic_vector (1 downto 0);
+
+ constant clk_period : integer := 1000000000/clk_freq;
+ constant CLK0_MUL3X : integer := clk0_mul * 3;
+ constant CLK1_MUL3X : integer := clk1_mul * 3;
+
+ constant VERSION : integer := 1;
+
+ attribute syn_keep : boolean;
+ attribute syn_keep of clkout : signal is true;
+
+begin
+
+ clkena(5 downto 4) <= (others => '0');
+ clkena(0) <= '1';
+ clkena(1) <= '1';
+ clkena(2) <= '1';
+ clkena(3) <= '1';
+
+ inclk <= '0' & inclk0;
+
+ clk_select: process (clkout, clksel)
+ begin -- process clk_select
+ case clksel is
+ when "00" => clk0 <= clkout(0); clk0x3 <= clkout(1);
+ when "01" => clk0 <= clkout(2); clk0x3 <= clkout(3);
+ when others => clk0 <= '0'; clk0x3 <= '0';
+ end case;
+ end process clk_select;
+
+ altpll0 : altpll
+ generic map (
+ intended_device_family => "Cyclone III",
+ operation_mode => "NO_COMPENSATION", inclk0_input_frequency => clk_period,
+ width_clock => 5, compensate_clock => "CLK1",
+ clk0_multiply_by => clk0_mul, clk0_divide_by => clk0_div,
+ clk1_multiply_by => CLK0_MUL3X, clk1_divide_by => clk0_div,
+ clk2_multiply_by => clk1_mul, clk2_divide_by => clk1_div,
+ clk3_multiply_by => CLK1_MUL3X, clk3_divide_by => clk1_div)
+ port map (clkena => clkena, inclk => inclk,
+ clk => clkout, locked => locked);
+
+-- pragma translate_off
+ bootmsg : report_version
+ generic map (
+ "clkgen_cycloneiii" & ": altpll lcd/vga clock generator, version " & tost(VERSION)
+ );
+-- pragma translate_on
+
+
+end;
+
+
--- /dev/null
+
+
+Prompt for target technology
+CONFIG_SYN_INFERRED
+ Selects the target technology for memory and pads.
+ The following are available:
+
+ - Inferred: Generic FPGA or ASIC targets if your synthesis tool
+ is capable of inferring RAMs and pads automatically.
+
+ - Actel ProAsic/P/3, IGLOO and Axcelerator FPGAs
+ - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS
+ - Altera: Most Altera FPGA families
+ - Altera-Stratix: Altera Stratix FPGA family
+ - Altera-StratixII: Altera Stratix-II FPGA family
+ - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
+ - IHP25: IHP 0.25 um CMOS
+ - IHP25RH: IHP Rad-Hard 0.25 um CMOS
+ - Lattice : EC/ECP/XP FPGAs
+ - Quicklogic : Eclipse/E/II FPGAs
+ - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
+ - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries
+ - Xilinx-Spartan3E: Xilinx Spartan3E libraries
+ - Xilinx-Virtex/E: Xilinx Virtex/E libraries
+ - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries
+
+
+Ram library
+CONFIG_MEM_VIRAGE
+ Select RAM generators for ASIC targets.
+
+Infer ram
+CONFIG_SYN_INFER_RAM
+ Say Y here if you want the synthesis tool to infer your
+ RAM automatically. Say N to directly instantiate technology-
+ specific RAM cells for the selected target technology package.
+
+Infer pads
+CONFIG_SYN_INFER_PADS
+ Say Y here if you want the synthesis tool to infer pads.
+ Say N to directly instantiate technology-specific pads from
+ the selected target technology package.
+
+No async reset
+CONFIG_SYN_NO_ASYNC
+ Say Y here if you disable asynchronous reset in some of the IP cores.
+ Might be necessary if the target library does not have cells with
+ asynchronous set/reset.
+
+Scan support
+CONFIG_SYN_SCAN
+ Say Y here to enable scan support in some cores. This will enable
+ the scan support generics where available and add logic to make
+ the design testable using full-scan.
+
+Use Virtex CLKDLL for clock synchronisation
+CONFIG_CLK_INFERRED
+ Certain target technologies include clock generators to scale or
+ phase-adjust the system and SDRAM clocks. This is currently supported
+ for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you
+ can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2),
+ the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL
+ (Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred'
+ option to skip a clock generator.
+
+Clock multiplier
+CONFIG_CLK_MUL
+ When using the Xilinx DCM or Altera ALTPLL, the system clock can
+ be multiplied with a factor of 2 - 32, and divided by a factor of
+ 1 - 32. This makes it possible to generate almost any desired
+ processor frequency. When using the Xilinx CLKDLL generator,
+ the resulting frequency scale factor (mul/div) must be one of
+ 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
+
+ WARNING: The resulting clock must be within the limits specified
+ by the target FPGA family.
+
+Clock divider
+CONFIG_CLK_DIV
+ When using the Xilinx DCM or Altera ALTPLL, the system clock can
+ be multiplied with a factor of 2 - 32, and divided by a factor of
+ 1 - 32. This makes it possible to generate almost any desired
+ processor frequency. When using the Xilinx CLKDLL generator,
+ the resulting frequency scale factor (mul/div) must be one of
+ 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
+
+ WARNING: The resulting clock must be within the limits specified
+ by the target FPGA family.
+
+Output clock divider
+CONFIG_OCLK_DIV
+ When using the Proasic3 PLL, the system clock is generated by three
+ parameters: input clock multiplication, input clock division and
+ output clock division. Only certain values of these parameters
+ are allowed, but unfortunately this is not documented by Actel.
+ To find the correct values, run the Libero Smartgen tool and
+ insert you desired input and output clock frequencies in the
+ Static PLL configurator. The mul/div factors can then be read
+ out from tool.
+
+System clock multiplier
+CONFIG_CLKDLL_1_2
+ The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0,
+ or 2.0. Useful when the target board has an oscillator with a too high
+ (or low) frequency for your design. The divided clock will be used as the
+ main clock for the whole processor (except PCI and ethernet clocks).
+
+System clock multiplier
+CONFIG_DCM_2_3
+ The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
+ range of factors. Useful when the target board has an oscillator with a
+ too high (or low) frequency for your design. The divided clock will
+ be used as the main clock for the whole processor (except PCI and
+ ethernet clocks). NOTE: the resulting frequency must be at least
+ 24 MHz or the DCM and ALTDLL might not work.
+
+Enable CLKDLL for PCI clock
+CONFIG_PCI_CLKDLL
+ Say Y here to re-synchronize the PCI clock using a
+ Virtex BUFGDLL macro. Will improve PCI clock-to-output
+ delays on the expense of input-setup requirements.
+
+Use PCI clock system clock
+CONFIG_PCI_SYSCLK
+ Say Y here to the PCI clock to generate the system clock.
+ The PCI clock can be scaled using the DCM or CLKDLL to
+ generate a suitable processor clock.
+
+External SDRAM clock feedback
+CONFIG_CLK_NOFB
+ Say Y here to disable the external clock feedback to synchronize the
+ SDRAM clock. This option is necessary if your board or design does not
+ have an external clock feedback that is connected to the pllref input
+ of the clock generator.
+
+Number of processors
+CONFIG_PROC_NUM
+ The number of processor cores. The LEON3MP design can accomodate
+ up to 4 LEON3 processor cores. Use 1 unless you know what you are
+ doing ...
+
+Number of SPARC register windows
+CONFIG_IU_NWINDOWS
+ The SPARC architecture (and LEON) allows 2 - 32 register windows.
+ However, any number except 8 will require that you modify and
+ recompile your run-time system or kernel. Unless you know what
+ you are doing, use 8.
+
+SPARC V8 multiply and divide instruction
+CONFIG_IU_V8MULDIV
+ If you say Y here, the SPARC V8 multiply and divide instructions
+ will be implemented. The instructions are: UMUL, UMULCC, SMUL,
+ SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
+ integer multiplications and divisions, significant performance
+ increase can be achieved. Emulated floating-point operations will
+ also benefit from this option.
+
+ By default, the gcc compiler does not emit multiply or divide
+ instructions and your code must be compiled with -mv8 to see any
+ performance increase. On the other hand, code compiled with -mv8
+ will generate an illegal instruction trap when executed on processors
+ with this option disabled.
+
+ The divider consumes approximately 2 kgates, the multiplier 6 kgates.
+
+Multiplier latency
+CONFIG_IU_MUL_LATENCY_2
+ Implementation options for the integer multiplier.
+
+ Type Implementation issue-rate/latency
+ 2-clocks 32x32 pipelined multiplier 1/2
+ 4-clocks 16x16 standard multiplier 4/4
+ 5-clocks 16x16 pipelined multiplier 4/5
+
+Multiplier latency
+CONFIG_IU_MUL_MAC
+ If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
+ instructions will be enabled. The instructions implement a
+ single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
+ The details of these instructions can be found in the LEON manual,
+ This option is only available when 16x16 multiplier is used.
+
+Single vector trapping
+CONFIG_IU_SVT
+ Single-vector trapping is a SPARC V8e option to reduce code-size
+ in small applications. If enabled, the processor will jump to
+ the address of trap 0 (tt = 0x00) for all traps. No trap table
+ is then needed. The trap type is present in %psr.tt and must
+ be decoded by the O/S. Saves 4 Kbyte of code, but increases
+ trap and interrupt overhead. Currently, the only O/S supporting
+ this option is eCos. To enable SVT, the O/S must also set bit 13
+ in %asr17.
+
+Load latency
+CONFIG_IU_LDELAY
+ Defines the pipeline load delay (= pipeline cycles before the data
+ from a load instruction is available for the next instruction).
+ One cycle gives best performance, but might create a critical path
+ on targets with slow (data) cache memories. A 2-cycle delay can
+ improve timing but will reduce performance with about 5%.
+
+Reset address
+CONFIG_IU_RSTADDR
+ By default, a SPARC processor starts execution at address 0.
+ With this option, any 4-kbyte aligned reset start address can be
+ choosen. Keep at 0 unless you really know what you are doing.
+
+Power-down
+CONFIG_PWD
+ Say Y here to enable the power-down feature of the processor.
+ Might reduce the maximum frequency slightly on FPGA targets.
+ For details on the power-down operation, see the LEON3 manual.
+
+Hardware watchpoints
+CONFIG_IU_WATCHPOINTS
+ The processor can have up to 4 hardware watchpoints, allowing to
+ create both data and instruction breakpoints at any memory location,
+ also in PROM. Each watchpoint will use approximately 500 gates.
+ Use 0 to disable the watchpoint function.
+
+Floating-point enable
+CONFIG_FPU_ENABLE
+ Say Y here to enable the floating-point interface for the MEIKO
+ or GRFPU. Note that no FPU's are provided with the GPL version
+ of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial
+ cores and must be obtained separately.
+
+FPU selection
+CONFIG_FPU_GRFPU
+ Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun
+ Meiko FPU core. All cores are fully IEEE-754 compatible and support
+ all SPARC FPU instructions.
+
+GRFPU Multiplier
+CONFIG_FPU_GRFPU_INFMUL
+ On FPGA targets choose inferred multiplier. For ASIC implementations
+ choose between Synopsys Design Ware (DW) multiplier or Module
+ Generator (ModGen) multiplier. The DW multiplier gives better results
+ (smaller area and better timing) but requires a DW license.
+ The ModGen multiplier is part of GRLIB and does not require a license.
+ The Technology Specific multiplier option selects a pre-designed
+ multiplier using technology specific macrocells when available, else
+ an inferred multiplier is used.
+
+Shared GRFPU
+CONFIG_FPU_GRFPU_SH
+ If enabled multiple CPU cores will share one GRFPU.
+
+GRFPC Configuration
+CONFIG_FPU_GRFPC0
+ Configures the GRFPU-LITE controller.
+
+ In simple configuration controller executes FP instructions
+ in parallel with integer instructions. FP operands are fetched
+ in the register file stage and the result is written in the write
+ stage. This option uses least area resources.
+
+ Data forwarding configuration gives ~ 10 % higher FP performance than
+ the simple configuration by adding data forwarding between the pipeline
+ stages.
+
+ Non-blocking controller allows FP load and store instructions to
+ execute in parallel with FP instructions. The performance increase is
+ ~ 20 % for FP applications. This option uses most logic resources and
+ is suitable for ASIC implementations.
+
+Floating-point netlist
+CONFIG_FPU_NETLIST
+ Say Y here to use a VHDL netlist of the GRFPU-Lite. This is
+ only available in certain versions of grlib.
+
+Enable Instruction cache
+CONFIG_ICACHE_ENABLE
+ The instruction cache should always be enabled to allow
+ maximum performance. Some low-end system might want to
+ save area and disable the cache, but this will reduce
+ the performance with a factor of 2 - 3.
+
+Enable Data cache
+CONFIG_DCACHE_ENABLE
+ The data cache should always be enabled to allow
+ maximum performance. Some low-end system might want to
+ save area and disable the cache, but this will reduce
+ the performance with a factor of 2 at least.
+
+Instruction cache associativity
+CONFIG_ICACHE_ASSO1
+ The instruction cache can be implemented as a multi-set cache with
+ 1 - 4 sets. Higher associativity usually increases the cache hit
+ rate and thereby the performance. The downside is higher power
+ consumption and increased gate-count for tag comparators.
+
+ Note that a 1-set cache is effectively a direct-mapped cache.
+
+Instruction cache set size
+CONFIG_ICACHE_SZ1
+ The size of each set in the instuction cache (kbytes). Valid values
+ are 1 - 64 in binary steps. Note that the full range is only supported
+ by the generic and virtex2 targets. Most target packages are limited
+ to 2 - 16 kbyte. Large set size gives higher performance but might
+ affect the maximum frequency (on ASIC targets). The total instruction
+ cache size is the number of set multiplied with the set size.
+
+Instruction cache line size
+CONFIG_ICACHE_LZ16
+ The instruction cache line size. Can be set to either 16 or 32
+ bytes per line. Instruction caches typically benefit from larger
+ line sizes, but on small caches it migh be better with 16 bytes/line
+ to limit eviction miss rate.
+
+Instruction cache replacement algorithm
+CONFIG_ICACHE_ALGORND
+ Cache replacement algorithm for caches with 2 - 4 sets. The 'random'
+ algorithm selects the set to evict randomly. The least-recently-replaced
+ (LRR) algorithm evicts the set least recently replaced. The least-
+ recently-used (LRU) algorithm evicts the set least recently accessed.
+ The random algorithm uses a simple 1- or 2-bit counter to select
+ the eviction set and has low area overhead. The LRR scheme uses one
+ extra bit in the tag ram and has therefore also low area overhead.
+ However, the LRR scheme can only be used with 2-set caches. The LRU
+ scheme has typically the best performance but also highest area overhead.
+ A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops
+ per line, and a 4-set LRU uses 5 flip-flops per line to store the access
+ history.
+
+Instruction cache locking
+CONFIG_ICACHE_LOCK
+ Say Y here to enable cache locking in the instruction cache.
+ Locking can be done on cache-line level, but will increase the
+ width of the tag ram with one bit. If you don't know what
+ locking is good for, it is safe to say N.
+
+Data cache associativity
+CONFIG_DCACHE_ASSO1
+ The data cache can be implemented as a multi-set cache with
+ 1 - 4 sets. Higher associativity usually increases the cache hit
+ rate and thereby the performance. The downside is higher power
+ consumption and increased gate-count for tag comparators.
+
+ Note that a 1-set cache is effectively a direct-mapped cache.
+
+Data cache set size
+CONFIG_DCACHE_SZ1
+ The size of each set in the data cache (kbytes). Valid values are
+ 1 - 64 in binary steps. Note that the full range is only supported
+ by the generic and virtex2 targets. Most target packages are limited
+ to 2 - 16 kbyte. A large cache gives higher performance but the
+ data cache is timing critical an a too large setting might affect
+ the maximum frequency (on ASIC targets). The total data cache size
+ is the number of set multiplied with the set size.
+
+Data cache line size
+CONFIG_DCACHE_LZ16
+ The data cache line size. Can be set to either 16 or 32 bytes per
+ line. A smaller line size gives better associativity and higher
+ cache hit rate, but requires a larger tag memory.
+
+Data cache replacement algorithm
+CONFIG_DCACHE_ALGORND
+ See the explanation for instruction cache replacement algorithm.
+
+Data cache locking
+CONFIG_DCACHE_LOCK
+ Say Y here to enable cache locking in the data cache.
+ Locking can be done on cache-line level, but will increase the
+ width of the tag ram with one bit. If you don't know what
+ locking is good for, it is safe to say N.
+
+Data cache snooping
+CONFIG_DCACHE_SNOOP
+ Say Y here to enable data cache snooping on the AHB bus. Is only
+ useful if you have additional AHB masters such as the DSU or a
+ target PCI interface. Note that the target technology must support
+ dual-port RAMs for this option to be enabled. Dual-port RAMS are
+ currently supported on Virtex/2, Virage and Actel targets.
+
+Data cache snooping implementation
+CONFIG_DCACHE_SNOOP_FAST
+ The default snooping implementation is 'slow', which works if you
+ don't have AHB slaves in cacheable areas capable of zero-waitstates
+ non-sequential write accesses. Otherwise use 'fast' and suffer a
+ few kgates extra area. This option is currently only needed in
+ multi-master systems with the SSRAM or DDR memory controllers.
+
+Separate snoop tags
+CONFIG_DCACHE_SNOOP_SEPTAG
+ Enable a separate memory to store the data tags used for snooping.
+ This is necessary when snooping support is wanted in systems
+ with MMU, typically for SMP systems. In this case, the snoop
+ tags will contain the physical tag address while the normal
+ tags contain the virtual tag address. This option can also be
+ together with the 'fast snooping' option to enable snooping
+ support on technologies without dual-port RAMs. In such case,
+ the snoop tag RAM will be implemented using a two-port RAM.
+
+Fixed cacheability map
+CONFIG_CACHE_FIXED
+ If this variable is 0, the cacheable memory regions are defined
+ by the AHB plug&play information (default). To overriden the
+ plug&play settings, this variable can be set to indicate which
+ areas should be cached. The value is treated as a 16-bit hex value
+ with each bit defining if a 256 Mbyte segment should be cached or not.
+ The right-most (LSB) bit defines the cacheability of AHB address
+ 0 - 256 MByte, while the left-most bit (MSB) defines AHB address
+ 3840 - 4096 MByte. If the bit is set, the corresponding area is
+ cacheable. A value of 00F3 defines address 0 - 0x20000000 and
+ 0x40000000 - 0x80000000 as cacheable.
+
+Local data ram
+CONFIG_DCACHE_LRAM
+ Say Y here to add a local ram to the data cache controller.
+ Accesses to the ram (load/store) will be performed at 0 waitstates
+ and store data will never be written back to the AHB bus.
+
+Size of local data ram
+CONFIG_DCACHE_LRAM_SZ1
+ Defines the size of the local data ram in Kbytes. Note that most
+ technology libraries do not support larger rams than 16 Kbyte.
+
+Start address of local data ram
+CONFIG_DCACHE_LRSTART
+ Defines the 8 MSB bits of start address of the local data ram.
+ By default set to 8f (start address = 0x8f000000), but any value
+ (except 0) is possible. Note that the local data ram 'shadows'
+ a 16 Mbyte block of the address space.
+
+MMU enable
+CONFIG_MMU_ENABLE
+ Say Y here to enable the Memory Management Unit.
+
+MMU split icache/dcache table lookaside buffer
+CONFIG_MMU_COMBINED
+ Select "combined" for a combined icache/dcache table lookaside buffer,
+ "split" for a split icache/dcache table lookaside buffer
+
+MMU tlb replacement scheme
+CONFIG_MMU_REPARRAY
+ Select "LRU" to use the "least recently used" algorithm for TLB
+ replacement, or "Increment" for a simple incremental replacement
+ scheme.
+
+Combined i/dcache tlb
+CONFIG_MMU_I2
+ Select the number of entries for the instruction TLB, or the
+ combined icache/dcache TLB if such is used.
+
+Split tlb, dcache
+CONFIG_MMU_D2
+ Select the number of entries for the dcache TLB.
+
+Fast writebuffer
+CONFIG_MMU_FASTWB
+ Only selectable if split tlb is enabled. In case fast writebuffer is
+ enabled the tlb hit will be made concurrent to the cache hit. This
+ leads to higher store performance, but increased power and area.
+
+MMU pagesize
+CONFIG_MMU_PAGE_4K
+ The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the
+ cache way size to 4 Kbyte, and total data cache size to 16 Kbyte,
+ when the MMU is used. To increase the maximum data cache size,
+ the MMU pages size can be increased to up 32 Kbyte. This will
+ give a maximum data cache size of 128 Kbyte.
+
+ Note that an MMU page size different than 4 Kbyte will require
+ a special linux tool-chain if glibc is used. If you don't know
+ what you are doing, stay with 4 Kbyte ...
+
+DSU enable
+CONFIG_DSU_ENABLE
+ The debug support unit (DSU) allows non-intrusive debugging and tracing
+ of both executed instructions and AHB transfers. If you want to enable
+ the DSU, say Y here and select the configuration below.
+
+Trace buffer enable
+CONFIG_DSU_TRACEBUF
+ Say Y to enable the trace buffer. The buffer is not necessary for
+ debugging, only for tracing instructions and data transfers.
+
+Enable instruction tracing
+CONFIG_DSU_ITRACE
+ If you say Y here, an instruction trace buffer will be implemented
+ in each processor. The trace buffer will trace executed instructions
+ and their results, and place them in a circular buffer. The buffer
+ can be read out by any AHB master, and in particular by the debug
+ communication link.
+
+Size of trace buffer
+CONFIG_DSU_ITRACESZ1
+ Select the buffer size (in kbytes) for the instruction trace buffer.
+ Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
+ need 2 kbyte.
+
+Enable AHB tracing
+CONFIG_DSU_ATRACE
+ If you say Y here, an AHB trace buffer will be implemented in the
+ debug support unit processor. The AHB buffer will trace all transfers
+ on the AHB bus and save them in a circular buffer. The trace buffer
+ can be read out by any AHB master, and in particular by the debug
+ communication link.
+
+Size of trace buffer
+CONFIG_DSU_ATRACESZ1
+ Select the buffer size (in kbytes) for the AHB trace buffer.
+ Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
+ need 2 kbyte.
+
+
+LEON3FT enable
+CONFIG_LEON3FT_EN
+ Say Y here to use the fault-tolerant LEON3FT core instead of the
+ standard non-FT LEON3.
+
+IU Register file protection
+CONFIG_IUFT_NONE
+ Select the FT implementation in the LEON3FT integer unit
+ register file. The options include parity, parity with
+ sparing, 7-bit BCH and TMR.
+
+FPU Register file protection
+CONFIG_FPUFT_EN
+ Say Y to enable SEU protection of the FPU register file.
+ The GRFPU will be protected using 8-bit parity without restart, while
+ the GRFPU-Lite will be protected with 4-bit parity with restart. If
+ disabled the FPU register file will be implemented using flip-flops.
+
+Cache memory error injection
+CONFIG_RF_ERRINJ
+ Say Y here to enable error injection in to the IU/FPU regfiles.
+ Affects only simulation.
+
+Cache memory protection
+CONFIG_CACHE_FT_EN
+ Enable SEU error-correction in the cache memories.
+
+Cache memory error injection
+CONFIG_CACHE_ERRINJ
+ Say Y here to enable error injection in to the cache memories.
+ Affects only simulation.
+
+Leon3ft netlist
+CONFIG_LEON3_NETLIST
+ Say Y here to use a VHDL netlist of the LEON3FT. This is
+ only available in certain versions of grlib.
+
+IU assembly printing
+CONFIG_IU_DISAS
+ Enable printing of executed instructions to the console.
+
+IU assembly printing in netlist
+CONFIG_IU_DISAS_NET
+ Enable printing of executed instructions to the console also
+ when simulating a netlist. NOTE: with this option enabled, it
+ will not be possible to pass place&route.
+
+32-bit program counters
+CONFIG_DEBUG_PC32
+ Since the LSB 2 bits of the program counters always are zero, they are
+ normally not implemented. If you say Y here, the program counters will
+ be implemented with full 32 bits, making debugging of the VHDL model
+ much easier. Turn of this option for synthesis or you will be wasting
+ area.
+CONFIG_AHB_DEFMST
+ Sets the default AHB master (see AMBA 2.0 specification for definition).
+ Should not be set to a value larger than the number of AHB masters - 1.
+ For highest processor performance, leave it at 0.
+
+Default AHB master
+CONFIG_AHB_RROBIN
+ Say Y here to enable round-robin arbitration of the AHB bus. A N will
+ select fixed priority, with the master with the highest bus index having
+ the highest priority.
+
+Support AHB split-transactions
+CONFIG_AHB_SPLIT
+ Say Y here to enable AHB split-transaction support in the AHB arbiter.
+ Unless you actually have an AHB slave that can generate AHB split
+ responses, say N and save some gates.
+
+Default AHB master
+CONFIG_AHB_IOADDR
+ Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined
+ in the plug&play extentions of the AMBA bus. Should be kept to FFF
+ unless you really know what you are doing.
+
+APB bridge address
+CONFIG_APB_HADDR
+ Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
+ kept at 800 for software compatibility.
+
+AHB monitor
+CONFIG_AHB_MON
+ Say Y to enable the AHB bus monitor. The monitor will check for
+ illegal AHB transactions during simulation. It has no impact on
+ synthesis.
+
+Report AHB errors
+CONFIG_AHB_MONERR
+ Print out detected AHB violations on console.
+
+Report AHB warnings
+CONFIG_AHB_MONWAR
+ Print out detected AHB warnings on console.
+
+
+DSU enable
+CONFIG_DSU_UART
+ Say Y to enable the AHB uart (serial-to-AHB). This is the most
+ commonly used debug communication link.
+
+JTAG Enable
+CONFIG_DSU_JTAG
+ Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done
+ with GRMON through the boards JTAG chain at speeds of up to 800 kbits/s.
+ Supported JTAG cables are Xilinx Parallel Cable III and IV,
+ Xilinx Platform cables (USB), and Altera parallel and USB cables.
+
+Ethernet DSU enable
+CONFIG_DSU_ETH
+ Say Y to enable the Ethernet Debug Communication Link (EDCL). The link
+ provides a DSU gateway between ethernet and the AHB bus. Debugging is
+ done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must
+ enable the GRETH Ethernet MAC for this option to become active.
+
+Size of EDCL trace buffer
+CONFIG_DSU_ETHSZ1
+ Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is
+ usually enough, while a larger buffer will increase the transfer rate.
+ When operating at 100 Mbit, use a buffer size of at least 8 kbyte for
+ maximum throughput.
+
+MSB IP address
+CONFIG_DSU_IPMSB
+ Set the MSB 16 bits of the IP address of the EDCL.
+
+LSB IP address
+CONFIG_DSU_IPLSB
+ Set the LSB 16 bits of the IP address of the EDCL.
+
+MSB ethernet address
+CONFIG_DSU_ETHMSB
+ Set the MSB 24 bits of the ethernet address of the EDCL.
+
+LSB ethernet address
+CONFIG_DSU_ETHLSB
+ Set the LSB 24 bits of the ethernet address of the EDCL.
+
+Programmable MAC/IP address
+CONFIG_DSU_ETH_PROG
+ Say Y to make the LSB 4 bits of the EDCL MAC and IP address
+ configurable using the ethi.edcladdr inputs.
+Leon2 memory controller
+CONFIG_MCTRL_LEON2
+ Say Y here to enable the LEON2 memory controller. The controller
+ can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
+ and SRAM is programmable to 8-, 16- or 32-bits.
+
+8-bit memory support
+CONFIG_MCTRL_8BIT
+ If you say Y here, the PROM/SRAM memory controller will support
+ 8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
+ Say N to save a few hundred gates.
+
+16-bit memory support
+CONFIG_MCTRL_16BIT
+ If you say Y here, the PROM/SRAM memory controller will support
+ 16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
+ Say N to save a few hundred gates.
+
+Write strobe feedback
+CONFIG_MCTRL_WFB
+ If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
+ be used to enable the data bus drivers during write cycles. This
+ will guarantee that the data is still valid on the rising edge of
+ the write strobe. If you say N, the write strobes and the data bus
+ drivers will be clocked on the rising edge, potentially creating
+ a hold time problem in external memory or I/O. However, in all
+ practical cases, there is enough capacitance in the data bus lines
+ to keep the value stable for a few (many?) nano-seconds after the
+ buffers have been disabled, making it safe to say N and remove a
+ combinational path in the netlist that might be difficult to
+ analyze.
+
+Write strobe feedback
+CONFIG_MCTRL_5CS
+ If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
+ be enabled. If you don't intend to use it, say N and save some gates.
+
+SDRAM controller enable
+CONFIG_MCTRL_SDRAM
+ Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
+ intend to use SDRAM, say N and save about 1 kgates.
+
+SDRAM controller inverted clock
+CONFIG_MCTRL_SDRAM_INVCLK
+ If you say Y here, the SDRAM controller output signals will be delayed
+ with 1/2 clock in respect to the SDRAM clock. This will allow the used
+ of an SDRAM clock which in not strictly in phase with the internal
+ clock. This option will limit the SDRAM frequency to 40 - 50 MHz.
+
+ On FPGA targets without SDRAM clock synchronizations through PLL/DLL,
+ say Y. On ASIC targets, say N and tell your foundry to balance the
+ SDRAM clock output.
+
+SDRAM separate address buses
+CONFIG_MCTRL_SDRAM_SEPBUS
+ Say Y here if your SDRAM is connected through separate address
+ and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
+ board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.
+
+64-bit data bus
+CONFIG_MCTRL_SDRAM_BUS64
+ Say Y here to enable 64-bit SDRAM data bus.
+
+Page burst enable
+CONFIG_MCTRL_PAGE
+ Say Y here to enable SDRAM page burst operation. This will implement
+ read operations using page bursts rather than 8-word bursts and save
+ about 500 gates (100 LUTs). Note that not all SDRAM supports page
+ burst, so use this option with care.
+
+Programmable page burst enable
+CONFIG_MCTRL_PROGPAGE
+ Say Y here to enable programmable SDRAM page burst operation. This
+ will allow to dynamically enable/disable page burst by setting
+ bit 17 in MCFG2.
+
+SDRAM controller enable
+CONFIG_SSCTRL
+ Say Y here to enabled a 32-bit synchronous SRAM (SSRAM) controller.
+ The controller is designed for piplined ZBT SSRAM.
+
+CONFIG_SSCTRL_PROM16
+ Say Y here to enabled a 16-bit PROM support. The PROM should be
+ connected to D[31:16] of the data bus.
+
+SDRAM controller enable
+CONFIG_DDRSP
+ Say Y here to enabled a 16-bit DDR266 SDRAM controller.
+
+Power-on init
+CONFIG_DDRSP_INIT
+ Say Y here to enable the automatic DDR initialization sequence.
+ If disabled, the sequencemust be performed in software before
+ the DDR can be used. If unsure, say Y.
+
+Memory frequency
+CONFIG_DDRSP_FREQ
+ Enter the frequency of the DDR clock (in MHz). The value is
+ typically between 80 - 133, depending on system configuration.
+ Some template design (such as the leon3-avnet-eval-lx25)
+ calculate this value automatically and this value is not used.
+
+Column bits
+CONFIG_DDRSP_COL
+ Select the number of colomn address bits of the DDR memory.
+ Typical values are 8 - 11. Only needed when automatic DDR
+ initialisation is choosen. The column size can always be
+ programmed by software as well.
+
+Chip select size
+CONFIG_DDRSP_MBYTE
+ Select the memory size (Mbytes) that each chip select should decode.
+ Only needed when automatic DDR initialisation is choosen. The chip
+ select size can always be programmed by software as well.
+
+Read clock phase shift
+CONFIG_DDRSP_RSKEW
+ On Xilinx targets, the read clock is de-skewed and phase-shifted
+ using a DCM connected to the feed-back clock input. On some boards,
+ the de-skewing does not work perfectly, and some extra phase shifting
+ must be added manually. The entered value is set to the PHASE_SHIFT
+ generic on the Xilinx DCM. The Digilent Sparten3E-1600 board typically
+ needs a value of 35, while the Avnet Virtex4 Eval board needs -90.
+ For Altera CycloneIII, the entered value is set to the PHASE_SHIFT of
+ the PLL in ps (e.g 2500 for 90' shift in 100MHz)
+SPI memory controller
+CONFIG_SPIMCTRL
+ Say Y here to enable a simple SPI memory controller.
+ The controller maps a SPI memory device into AMBA address space and
+ also has a simple interface that allows sending commands directly
+ to the SPI device.
+
+SD card support
+CONFIG_SPIMCTRL_SDCARD
+ Memory device connected to controller is SD card.
+
+Read command
+CONFIG_SPIMCTRL_READCMD
+ Read instruction for SPI memory device
+
+Dummy byte
+CONFIG_SPIMCTRL_DUMMYBYTE
+ Output dummy byte after address when issuing read instruction.
+
+Dual output
+CONFIG_SPIMCTRL_DUALOUTPUT
+ Memory device supports dual output when reading data.
+
+Clock scaler
+CONFIG_SPIMCTRL_SCALER
+ Selects the divisor used when dividing the system clock to produce
+ the memory device clock. The divisor used is two to the power of the
+ specified value. This value must be at least 1.
+
+Alternate clock scaler
+CONFIG_SPIMCTRL_ASCALER
+ Selects the divisor used when dividing the system clock to produce
+ the alternate memory device clock. If the selected memory device is
+ a SD Card this clock will be used during card initialization. The
+ divisor used is two to the power of the specified value. This
+ value must be at least 1.
+
+Power-up cnt
+CONFIG_SPIMCTRL_PWRUPCNT
+ Number of system clock cycles to wait before issuing first command.
+On-chip rom
+CONFIG_AHBROM_ENABLE
+ Say Y here to add a block on on-chip rom to the AHB bus. The ram
+ provides 0-waitstates read access, burst support, and 8-, 16-
+ and 32-bit data size. The rom will be syntheised into block rams
+ on Xilinx and Altera FPGA devices, and into gates on ASIC
+ technologies. GRLIB includes a utility to automatically create
+ the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
+ documentation for details.
+
+On-chip rom address
+CONFIG_AHBROM_START
+ Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
+ a 1 Mbyte slot at the selected address. Default is 000, corresponding
+ to AHB address 0x00000000. When address 0x0 is selected, the rom area
+ of any other memory controller is set to 0x10000000 to avoid conflicts.
+
+Enable pipeline register for on-chip rom
+CONFIG_AHBROM_PIPE
+ Say Y here to add a data pipeline register to the on-chip rom.
+ This should be done when the rom is implemenented in (ASIC) gates,
+ or in logic cells on FPGAs. Do not use this option when the rom is
+ implemented in block rams. If enabled, the rom will operate with
+ one waitstate.
+
+On-chip ram
+CONFIG_AHBRAM_ENABLE
+ Say Y here to add a block on on-chip ram to the AHB bus. The ram
+ provides 0-waitstates read access and 0/1 waitstates write access.
+ All AHB burst types are supported, as well as 8-, 16- and 32-bit
+ data size.
+
+On-chip ram size
+CONFIG_AHBRAM_SZ1
+ Set the size of the on-chip AHB ram. The ram is infered/instantiated
+ as four byte-wide ram slices to allow byte and half-word write
+ accesses. It is therefore essential that the target package can
+ infer byte-wide rams. This is currently supported on the generic,
+ virtex, virtex2, proasic and axellerator targets.
+
+On-chip ram address
+CONFIG_AHBRAM_START
+ Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
+ a 1 Mbyte slot at the selected address. Default is A00, corresponding
+ to AHB address 0xA0000000.
+
+Gaisler Ethernet MAC enable
+CONFIG_GRETH_ENABLE
+ Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has
+ one AHB master interface to read and write packets to memory, and one
+ APB slave interface for accessing the control registers.
+
+Gaisler Ethernet 1G MAC enable
+CONFIG_GRETH_GIGA
+ Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC .
+ The 1G MAC is only available in the commercial version of GRLIB,
+ so do NOT enable it if you are using the GPL version.
+
+CONFIG_GRETH_FIFO4
+ Set the depth of the receive and transmit FIFOs in the MAC core.
+ The MAC core will perform AHB burst read/writes with half the
+ size of the FIFO depth.
+
+
+UART1 enable
+CONFIG_UART1_ENABLE
+ Say Y here to enable UART1, or the console UART. This is needed to
+ get any print-out from LEON3 systems regardless of operating system.
+
+UART1 FIFO
+CONFIG_UA1_FIFO1
+ The UART has configurable transmitt and receive FIFO's, which can
+ be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
+ maximum throughput.
+
+
+LEON3 interrupt controller
+CONFIG_IRQ3_ENABLE
+ Say Y here to enable the LEON3 interrupt controller. This is needed
+ if you want to be able to receive interrupts. Operating systems like
+ Linux, RTEMS and eCos needs this option to be enabled. If you intend
+ to use the Bare-C run-time and not use interrupts, you could disable
+ the interrupt controller and save about 500 gates.
+
+LEON3 interrupt controller broadcast
+CONFIG_IRQ3_BROADCAST_ENABLE
+ If enabled the broadcast register is used to determine which
+ interrupt should be sent to all cpus instead of just the first
+ one that consumes it.
+
+Secondary interrupts
+CONFIG_IRQ3_SEC
+ The interrupt controller handles 15 interrupts by default (1 - 15).
+ These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F),
+ and AMBA interrupts 1 - 15. This option will enable 16 additional
+ (secondary) interrupts, corresponding to AMBA interrupts 16 - 31.
+ The secondary interrupts will be multiplexed onto one of the first
+ 15 interrupts. The total number of handled interrupts can then
+ be up to 30 (14 primary and 16 secondary).
+
+Number of interrupts
+CONFIG_IRQ3_NSEC
+ Defines which of the first 15 interrupts should be used for the
+ secondary (16 - 31) interrupts. Interrupt 15 should be avoided
+ since it is not maskable by the processor.
+Timer module enable
+CONFIG_GPT_ENABLE
+ Say Y here to enable the Modular Timer Unit. The timer unit consists
+ of one common scaler and up to 7 independent timers. The timer unit
+ is needed for Linux, RTEMS, eCos and the Bare-C run-times.
+
+Timer module enable
+CONFIG_GPT_NTIM
+ Set the number of timers in the timer unit (1 - 7).
+
+Scaler width
+CONFIG_GPT_SW
+ Set the width if the common pre-scaler (2 - 16 bits). The scaler
+ is used to divide the system clock down to 1 MHz, so 8 bits should
+ be sufficient for most implementations (allows clocks up to 256 MHz).
+
+Timer width
+CONFIG_GPT_TW
+ Set the width if the timers (2 - 32 bits). 32 bits is recommended
+ for the Bare-C run-time, lower values (e.g. 16 bits) can work with
+ RTEMS and Linux.
+
+Timer Interrupt
+CONFIG_GPT_IRQ
+ Set the interrupt number for the first timer. Remaining timers will
+ have incrementing interrupts, unless the separate-interrupts option
+ below is disabled.
+
+Watchdog enable
+CONFIG_GPT_WDOGEN
+ Say Y here to enable the watchdog functionality in the timer unit.
+
+Watchdog time-out value
+CONFIG_GPT_WDOG
+ This value will be loaded in the watchdog timer at reset.
+
+GPIO port
+CONFIG_GRGPIO_ENABLE
+ Say Y here to enable a general purpose I/O port. The port can be
+ configured from 1 - 32 bits, whith each port signal individually
+ programmable as input or output. The port signals can also serve
+ as interrupt inputs.
+
+GPIO port witdth
+CONFIG_GRGPIO_WIDTH
+ Number of bits in the I/O port. Must be in the range of 1 - 32.
+
+GPIO interrupt mask
+CONFIG_GRGPIO_IMASK
+ The I/O port interrupt mask defines which bits in the I/O port
+ should be able to create an interrupt.
+
+OpenCores I2C Master
+CONFIG_I2C_ENABLE
+ Say Y here to enable the OpenCores I2C master.
+PS2 interface
+CONFIG_PS2_ENABLE
+ Say Y here to enable a PS/2 keyboard or mouse interface.
+
+Gaisler Research SPI controller
+CONFIG_SPICTRL_ENABLE
+ Say Y here to enable the SPI controller
+LCD frame buffer
+CONFIG_LCD_ENABLE
+ Say Y here to enable a graphical frame buffer. The frame buffer
+ can be configured up to 1024x768 pixels and 8-, 16- or 32-bit
+ colour depth.
+
+LCD 3-wire serial interface and touch panel support
+CONFIG_LCD3T_ENABLE
+ Say Y here to instantiate a SPI controller that allows LCD touch
+ panel and LCD 3-wire serial interface support
+
+SVGA frame buffer
+CONFIG_SVGA_ENABLE
+ Say Y here to enable a graphical frame buffer. The frame buffer
+ can be configured up to 1024x768 pixels and 8-, 16- or 32-bit
+ colour depth.
+
+UART debugging
+CONFIG_DEBUG_UART
+ During simulation, the output from the UARTs is printed on the
+ simulator console. Since the ratio between the system clock and
+ UART baud-rate is quite high, simulating UART output will be very
+ slow. If you say Y here, the UARTs will print a character as soon
+ as it is stored in the transmitter data register. The transmitter
+ ready flag will be permanently set, speeding up simulation. However,
+ the output on the UART tx line will be garbled. Has not impact on
+ synthesis, but will cause the LEON test bench to fail.
+
+FPU register tracing
+CONFIG_DEBUG_FPURF
+ If you say Y here, all writes to the floating-point unit register file
+ will be printed on the simulator console.
+
--- /dev/null
+#
+# LEON3 configuration written in linux configuration language
+#
+# Written by Jiri Gaisler, Gaisler Research
+#
+# Comments and bug reports to jiri@gaisler.com
+#
+#
+
+#define_bool CONFIG_MCTRL_RMW y
+
+mainmenu_name "LEON3 Altera EP3C25-EEK Design Configuration"
+
+mainmenu_option next_comment
+ comment 'Synthesis '
+ source lib/techmap/gencomp/tech.in
+endmenu
+
+mainmenu_option next_comment
+ comment 'Clock generation'
+ source lib/techmap/clocks/clkgen.in
+endmenu
+
+source lib/gaisler/leon3/leon3.in
+source lib/grlib/amba/amba.in
+
+mainmenu_option next_comment
+ comment 'Debug Link '
+ source lib/gaisler/uart/dcom.in
+ source lib/gaisler/jtag/jtag.in
+ source lib/gaisler/net/edcl.in
+endmenu
+
+mainmenu_option next_comment
+comment 'Peripherals '
+
+ mainmenu_option next_comment
+ comment 'Memory controllers '
+ source lib/esa/memoryctrl/mctrl.in
+ source lib/gaisler/memctrl/ssrctrl.in
+ source lib/gaisler/ddr/ddrsp.in
+ source lib/gaisler/memctrl/spimctrl.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'On-chip RAM/ROM '
+ source lib/gaisler/misc/ahbrom.in
+ source lib/gaisler/misc/ahbram.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'Ethernet '
+ source lib/gaisler/greth/greth.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'UARTs, timers and irq control '
+ source lib/gaisler/uart/uart1.in
+ source lib/gaisler/leon3/irqmp.in
+ source lib/gaisler/misc/gptimer.in
+ source lib/gaisler/misc/grgpio.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'Serial interfaces; I2C, PS/2 and SPI '
+ source lib/gaisler/misc/i2c.in
+ source lib/gaisler/misc/ps2.in
+ source lib/gaisler/misc/spictrl.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'LCD and VGA DAC '
+ source designs/leon3-altera-ep3c25-eek/lcd.in
+ source lib/gaisler/misc/svgactrl.in
+ endmenu
+
+endmenu
+
+mainmenu_option next_comment
+comment 'VHDL Debugging '
+ source lib/grlib/util/debug.in
+endmenu
--- /dev/null
+
+
+
+
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench configuration
+-- Copyright (C) 2009 Aeroflex Gaisler
+------------------------------------------------------------------------------
+
+
+library techmap;
+use techmap.gencomp.all;
+
+package config is
+-- Technology and synthesis options
+ constant CFG_FABTECH : integer := cyclone3;
+ constant CFG_MEMTECH : integer := cyclone3;
+ constant CFG_PADTECH : integer := cyclone3;
+ constant CFG_NOASYNC : integer := 0;
+ constant CFG_SCAN : integer := 0;
+-- Clock generator
+ constant CFG_CLKTECH : integer := cyclone3;
+ constant CFG_CLKMUL : integer := (5);
+ constant CFG_CLKDIV : integer := (5);
+ constant CFG_OCLKDIV : integer := 2;
+ constant CFG_PCIDLL : integer := 0;
+ constant CFG_PCISYSCLK: integer := 0;
+ constant CFG_CLK_NOFB : integer := 0;
+-- LEON3 processor core
+ constant CFG_LEON3 : integer := 1;
+ constant CFG_NCPU : integer := (1);
+ constant CFG_NWIN : integer := (8);
+ constant CFG_V8 : integer := 2;
+ constant CFG_MAC : integer := 0;
+ constant CFG_SVT : integer := 0;
+ constant CFG_RSTADDR : integer := 16#00000#;
+ constant CFG_LDDEL : integer := (1);
+ constant CFG_NWP : integer := (2);
+ constant CFG_PWD : integer := 0*2;
+ constant CFG_FPU : integer := 0 + 16*0;
+ constant CFG_GRFPUSH : integer := 0;
+ constant CFG_ICEN : integer := 1;
+ constant CFG_ISETS : integer := 2;
+ constant CFG_ISETSZ : integer := 4;
+ constant CFG_ILINE : integer := 8;
+ constant CFG_IREPL : integer := 1;
+ constant CFG_ILOCK : integer := 0;
+ constant CFG_ILRAMEN : integer := 0;
+ constant CFG_ILRAMADDR: integer := 16#8E#;
+ constant CFG_ILRAMSZ : integer := 1;
+ constant CFG_DCEN : integer := 1;
+ constant CFG_DSETS : integer := 2;
+ constant CFG_DSETSZ : integer := 4;
+ constant CFG_DLINE : integer := 4;
+ constant CFG_DREPL : integer := 1;
+ constant CFG_DLOCK : integer := 0;
+ constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
+ constant CFG_DFIXED : integer := 16#0#;
+ constant CFG_DLRAMEN : integer := 0;
+ constant CFG_DLRAMADDR: integer := 16#8F#;
+ constant CFG_DLRAMSZ : integer := 1;
+ constant CFG_MMUEN : integer := 1;
+ constant CFG_ITLBNUM : integer := 8;
+ constant CFG_DTLBNUM : integer := 8;
+ constant CFG_TLB_TYPE : integer := 0 + 1*2;
+ constant CFG_TLB_REP : integer := 1;
+ constant CFG_MMU_PAGE : integer := 0;
+ constant CFG_DSU : integer := 1;
+ constant CFG_ITBSZ : integer := 2;
+ constant CFG_ATBSZ : integer := 2;
+ constant CFG_LEON3FT_EN : integer := 0;
+ constant CFG_IUFT_EN : integer := 0;
+ constant CFG_FPUFT_EN : integer := 0;
+ constant CFG_RF_ERRINJ : integer := 0;
+ constant CFG_CACHE_FT_EN : integer := 0;
+ constant CFG_CACHE_ERRINJ : integer := 0;
+ constant CFG_LEON3_NETLIST: integer := 0;
+ constant CFG_DISAS : integer := 0 + 0;
+ constant CFG_PCLOW : integer := 2;
+-- AMBA settings
+ constant CFG_DEFMST : integer := (0);
+ constant CFG_RROBIN : integer := 1;
+ constant CFG_SPLIT : integer := 0;
+ constant CFG_AHBIO : integer := 16#FFF#;
+ constant CFG_APBADDR : integer := 16#800#;
+ constant CFG_AHB_MON : integer := 0;
+ constant CFG_AHB_MONERR : integer := 0;
+ constant CFG_AHB_MONWAR : integer := 0;
+-- DSU UART
+ constant CFG_AHB_UART : integer := 0;
+-- JTAG based DSU interface
+ constant CFG_AHB_JTAG : integer := 1;
+-- Ethernet DSU
+ constant CFG_DSU_ETH : integer := 0 + 0;
+ constant CFG_ETH_BUF : integer := 1;
+ constant CFG_ETH_IPM : integer := 16#C0A8#;
+ constant CFG_ETH_IPL : integer := 16#0033#;
+ constant CFG_ETH_ENM : integer := 16#020000#;
+ constant CFG_ETH_ENL : integer := 16#000009#;
+-- LEON2 memory controller
+ constant CFG_MCTRL_LEON2 : integer := 1;
+ constant CFG_MCTRL_RAM8BIT : integer := 0;
+ constant CFG_MCTRL_RAM16BIT : integer := 1;
+ constant CFG_MCTRL_5CS : integer := 0;
+ constant CFG_MCTRL_SDEN : integer := 0;
+ constant CFG_MCTRL_SEPBUS : integer := 0;
+ constant CFG_MCTRL_INVCLK : integer := 0;
+ constant CFG_MCTRL_SD64 : integer := 0;
+ constant CFG_MCTRL_PAGE : integer := 0 + 0;
+-- SSRAM controller
+ constant CFG_SSCTRL : integer := 0;
+ constant CFG_SSCTRLP16 : integer := 0;
+-- DDR controller
+ constant CFG_DDRSP : integer := 1;
+ constant CFG_DDRSP_INIT : integer := 1;
+ constant CFG_DDRSP_FREQ : integer := (100);
+ constant CFG_DDRSP_COL : integer := (9);
+ constant CFG_DDRSP_SIZE : integer := (8);
+ constant CFG_DDRSP_RSKEW : integer := (2500);
+-- SPI memory controller
+ constant CFG_SPIMCTRL : integer := 0;
+ constant CFG_SPIMCTRL_SDCARD : integer := 0;
+ constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
+ constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
+ constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
+ constant CFG_SPIMCTRL_SCALER : integer := 1;
+ constant CFG_SPIMCTRL_ASCALER : integer := 1;
+ constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
+-- AHB ROM
+ constant CFG_AHBROMEN : integer := 0;
+ constant CFG_AHBROPIP : integer := 0;
+ constant CFG_AHBRODDR : integer := 16#000#;
+ constant CFG_ROMADDR : integer := 16#000#;
+ constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
+-- AHB RAM
+ constant CFG_AHBRAMEN : integer := 0;
+ constant CFG_AHBRSZ : integer := 1;
+ constant CFG_AHBRADDR : integer := 16#A00#;
+
+-- Gaisler Ethernet core
+ constant CFG_GRETH : integer := 0;
+ constant CFG_GRETH1G : integer := 0;
+ constant CFG_ETH_FIFO : integer := 8;
+
+-- UART 1
+ constant CFG_UART1_ENABLE : integer := 1;
+ constant CFG_UART1_FIFO : integer := 8;
+
+-- LEON3 interrupt controller
+ constant CFG_IRQ3_ENABLE : integer := 1;
+ constant CFG_IRQ3_NSEC : integer := 0;
+
+-- Modular timer
+ constant CFG_GPT_ENABLE : integer := 1;
+ constant CFG_GPT_NTIM : integer := (2);
+ constant CFG_GPT_SW : integer := (8);
+ constant CFG_GPT_TW : integer := (32);
+ constant CFG_GPT_IRQ : integer := (8);
+ constant CFG_GPT_SEPIRQ : integer := 1;
+ constant CFG_GPT_WDOGEN : integer := 0;
+ constant CFG_GPT_WDOG : integer := 16#0#;
+
+-- GPIO port
+ constant CFG_GRGPIO_ENABLE : integer := 1;
+ constant CFG_GRGPIO_IMASK : integer := 16#0#;
+ constant CFG_GRGPIO_WIDTH : integer := (5);
+
+-- I2C master
+ constant CFG_I2C_ENABLE : integer := 1;
+
+-- PS/2 interface
+ constant CFG_PS2_ENABLE : integer := 1;
+
+-- SPI controller
+ constant CFG_SPICTRL_ENABLE : integer := 1;
+ constant CFG_SPICTRL_SLVS : integer := (1);
+ constant CFG_SPICTRL_FIFO : integer := (2);
+ constant CFG_SPICTRL_SLVREG : integer := 1;
+ constant CFG_SPICTRL_ODMODE : integer := 0;
+ constant CFG_SPICTRL_AM : integer := 0;
+ constant CFG_SPICTRL_ASEL : integer := 0;
+
+-- LCD SVGA controller
+ constant CFG_LCD_ENABLE : integer := 1;
+
+-- LCD 3-wire serial interface
+ constant CFG_LCD3T_ENABLE : integer := 1;
+
+-- SVGA controller
+ constant CFG_SVGA_ENABLE : integer := 0;
+
+-- GRLIB debugging
+ constant CFG_DUART : integer := 0;
+end;
--- /dev/null
+-- Technology and synthesis options
+ constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
+ constant CFG_MEMTECH : integer := CFG_RAM_TECH;
+ constant CFG_PADTECH : integer := CFG_PAD_TECH;
+ constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
+ constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
+
+-- Clock generator
+ constant CFG_CLKTECH : integer := CFG_CLK_TECH;
+ constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
+ constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
+ constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
+ constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
+ constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
+ constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
+
+-- LEON3 processor core
+ constant CFG_LEON3 : integer := CONFIG_LEON3;
+ constant CFG_NCPU : integer := CONFIG_PROC_NUM;
+ constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
+ constant CFG_V8 : integer := CFG_IU_V8;
+ constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
+ constant CFG_SVT : integer := CONFIG_IU_SVT;
+ constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
+ constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
+ constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
+ constant CFG_PWD : integer := CONFIG_PWD*2;
+ constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
+ constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
+ constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
+ constant CFG_ISETS : integer := CFG_IU_ISETS;
+ constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
+ constant CFG_ILINE : integer := CFG_ILINE_SZ;
+ constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
+ constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
+ constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
+ constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
+ constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
+ constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
+ constant CFG_DSETS : integer := CFG_IU_DSETS;
+ constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
+ constant CFG_DLINE : integer := CFG_DLINE_SZ;
+ constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
+ constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
+ constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
+ constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
+ constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
+ constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
+ constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
+ constant CFG_MMUEN : integer := CONFIG_MMUEN;
+ constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
+ constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
+ constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
+ constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
+ constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
+ constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
+ constant CFG_ITBSZ : integer := CFG_DSU_ITB;
+ constant CFG_ATBSZ : integer := CFG_DSU_ATB;
+ constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
+ constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
+ constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
+ constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
+ constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
+ constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
+ constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
+ constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
+ constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
+
+-- AMBA settings
+ constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
+ constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
+ constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
+ constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
+ constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
+ constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
+ constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
+ constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
+
+-- DSU UART
+ constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
+
+-- JTAG based DSU interface
+ constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
+
+-- Ethernet DSU
+ constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
+ constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
+ constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
+ constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
+ constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
+ constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
+
+-- LEON2 memory controller
+ constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
+ constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
+ constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
+ constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
+ constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
+ constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
+ constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
+ constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
+ constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
+
+-- SSRAM controller
+ constant CFG_SSCTRL : integer := CONFIG_SSCTRL;
+ constant CFG_SSCTRLP16 : integer := CONFIG_SSCTRL_PROM16;
+
+-- DDR controller
+ constant CFG_DDRSP : integer := CONFIG_DDRSP;
+ constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT;
+ constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ;
+ constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL;
+ constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE;
+ constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW;
+
+-- SPI memory controller
+ constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
+ constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
+ constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
+ constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
+ constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
+ constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
+ constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
+ constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
+
+-- AHB ROM
+ constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
+ constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
+ constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
+ constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
+ constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
+
+-- AHB RAM
+ constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
+ constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
+ constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
+
+-- Gaisler Ethernet core
+ constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
+ constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
+ constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
+
+-- UART 1
+ constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
+ constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
+
+-- LEON3 interrupt controller
+ constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
+ constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
+
+-- Modular timer
+ constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
+ constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
+ constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
+ constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
+ constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
+ constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
+ constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
+ constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
+
+-- GPIO port
+ constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
+ constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
+ constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
+
+-- I2C master
+ constant CFG_I2C_ENABLE : integer := CONFIG_I2C_ENABLE;
+
+-- PS/2 interface
+ constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
+
+-- SPI controller
+ constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
+ constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
+ constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
+ constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
+ constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
+ constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
+ constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
+
+-- LCD SVGA controller
+ constant CFG_LCD_ENABLE : integer := CONFIG_LCD_ENABLE;
+
+-- LCD 3-wire serial interface
+ constant CFG_LCD3T_ENABLE : integer := CONFIG_LCD3T_ENABLE;
+
+-- SVGA controller
+ constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
+
+-- GRLIB debugging
+ constant CFG_DUART : integer := CONFIG_DEBUG_UART;
+
--- /dev/null
+#include "config.h"
+#include "tkconfig.h"
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench configuration
+-- Copyright (C) 2009 Aeroflex Gaisler
+------------------------------------------------------------------------------
+
+
+library techmap;
+use techmap.gencomp.all;
+
+package config is
+
+#include "config.vhd.h"
+
+end;
--- /dev/null
+/*
+ * Processor
+ */
+/*
+ * Integer unit
+ */
+#define CONFIG_IU_NWINDOWS (8)
+#undef CONFIG_IU_V8MULDIV
+/*
+ * Cache system
+ */
+#define CONFIG_ICACHE_ENABLE 1
+#define CONFIG_ICACHE_SZ1 1
+#undef CONFIG_ICACHE_SZ2
+#undef CONFIG_ICACHE_SZ4
+#undef CONFIG_ICACHE_SZ8
+#undef CONFIG_ICACHE_SZ16
+#undef CONFIG_ICACHE_SZ32
+#undef CONFIG_ICACHE_SZ64
+#undef CONFIG_ICACHE_LRAM
+#define CONFIG_DCACHE_ENABLE 1
+#define CONFIG_DCACHE_SZ1 1
+#undef CONFIG_DCACHE_SZ2
+#undef CONFIG_DCACHE_SZ4
+#undef CONFIG_DCACHE_SZ8
+#undef CONFIG_DCACHE_SZ16
+#undef CONFIG_DCACHE_SZ32
+#undef CONFIG_DCACHE_SZ64
+#undef CONFIG_DCACHE_LRAM
+/*
+ * MMU
+ */
+#undef CONFIG_MMU_ENABLE
+/*
+ * Debug Support Unit
+ */
+#define CONFIG_DSU_ENABLE 1
+#undef CONFIG_DSU_ITRACE
+#undef CONFIG_DSU_ATRACE
+/*
+ * Debug Link
+ */
+#define CONFIG_DSU_UART 1
+#define CONFIG_DSU_ETH 1
+#undef CONFIG_DSU_ETHSZ1
+#define CONFIG_DSU_ETHSZ2 1
+#undef CONFIG_DSU_ETHSZ4
+#undef CONFIG_DSU_ETHSZ8
+#undef CONFIG_DSU_ETHSZ16
+/*
+ * Peripherals
+ */
+/*
+ * Memory controllers
+ */
+#undef CONFIG_MCTRL_NONE
+#define CONFIG_MCTRL_LEON2 1
+#define CONFIG_MCTRL_SDRAM 1
+/*
+ * Ethernet
+ */
+#undef CONFIG_ETH_ENABLE
+/*
+ * PCI
+ */
+#undef CONFIG_PCI_ENABLE
+/*
+ * CAN
+ */
+#undef CONFIG_CAN_ENABLE
+/*
+ * UARTs, timers and irq control
+ */
+#define CONFIG_UART1_ENABLE 1
+#define CONFIG_GPT_ENABLE 1
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Synthesis
+#
+# CONFIG_SYN_INFERRED is not set
+# CONFIG_SYN_STRATIX is not set
+# CONFIG_SYN_STRATIXII is not set
+# CONFIG_SYN_STRATIXIII is not set
+CONFIG_SYN_CYCLONEIII=y
+# CONFIG_SYN_ALTERA is not set
+# CONFIG_SYN_AXCEL is not set
+# CONFIG_SYN_PROASIC is not set
+# CONFIG_SYN_PROASICPLUS is not set
+# CONFIG_SYN_PROASIC3 is not set
+# CONFIG_SYN_UT025CRH is not set
+# CONFIG_SYN_ATC18 is not set
+# CONFIG_SYN_CUSTOM1 is not set
+# CONFIG_SYN_IHP25 is not set
+# CONFIG_SYN_IHP25RH is not set
+# CONFIG_SYN_LATTICE is not set
+# CONFIG_SYN_ECLIPSE is not set
+# CONFIG_SYN_PEREGRINE is not set
+# CONFIG_SYN_RH_LIB18T is not set
+# CONFIG_SYN_RHUMC is not set
+# CONFIG_SYN_SPARTAN2 is not set
+# CONFIG_SYN_SPARTAN3 is not set
+# CONFIG_SYN_SPARTAN3E is not set
+# CONFIG_SYN_VIRTEX is not set
+# CONFIG_SYN_VIRTEXE is not set
+# CONFIG_SYN_VIRTEX2 is not set
+# CONFIG_SYN_VIRTEX4 is not set
+# CONFIG_SYN_VIRTEX5 is not set
+# CONFIG_SYN_INFER_RAM is not set
+# CONFIG_SYN_INFER_PADS is not set
+# CONFIG_SYN_NO_ASYNC is not set
+
+#
+# Clock generation
+#
+# CONFIG_CLK_INFERRED is not set
+# CONFIG_CLK_HCLKBUF is not set
+CONFIG_CLK_ALTDLL=y
+# CONFIG_CLK_LATDLL is not set
+# CONFIG_CLK_PRO3PLL is not set
+# CONFIG_CLK_LIB18T is not set
+# CONFIG_CLK_CLKDLL is not set
+# CONFIG_CLK_DCM is not set
+CONFIG_CLK_MUL=2
+CONFIG_CLK_DIV=2
+# CONFIG_PCI_SYSCLK is not set
+CONFIG_LEON3=y
+CONFIG_PROC_NUM=1
+
+#
+# Processor
+#
+
+#
+# Integer unit
+#
+CONFIG_IU_NWINDOWS=8
+CONFIG_IU_V8MULDIV=y
+# CONFIG_IU_MUL_LATENCY_4 is not set
+CONFIG_IU_MUL_LATENCY_5=y
+# CONFIG_IU_MUL_MAC is not set
+# CONFIG_IU_SVT is not set
+CONFIG_IU_LDELAY=1
+CONFIG_IU_WATCHPOINTS=2
+# CONFIG_PWD is not set
+CONFIG_IU_RSTADDR=00000
+
+#
+# Floating-point unit
+#
+# CONFIG_FPU_ENABLE is not set
+
+#
+# Cache system
+#
+CONFIG_ICACHE_ENABLE=y
+# CONFIG_ICACHE_ASSO1 is not set
+CONFIG_ICACHE_ASSO2=y
+# CONFIG_ICACHE_ASSO3 is not set
+# CONFIG_ICACHE_ASSO4 is not set
+# CONFIG_ICACHE_SZ1 is not set
+# CONFIG_ICACHE_SZ2 is not set
+# CONFIG_ICACHE_SZ4 is not set
+CONFIG_ICACHE_SZ8=y
+# CONFIG_ICACHE_SZ16 is not set
+# CONFIG_ICACHE_SZ32 is not set
+# CONFIG_ICACHE_SZ64 is not set
+# CONFIG_ICACHE_SZ128 is not set
+# CONFIG_ICACHE_SZ256 is not set
+# CONFIG_ICACHE_LZ16 is not set
+CONFIG_ICACHE_LZ32=y
+# CONFIG_ICACHE_ALGORND is not set
+# CONFIG_ICACHE_ALGOLRR is not set
+CONFIG_ICACHE_ALGOLRU=y
+# CONFIG_ICACHE_LOCK is not set
+CONFIG_DCACHE_ENABLE=y
+# CONFIG_DCACHE_ASSO1 is not set
+CONFIG_DCACHE_ASSO2=y
+# CONFIG_DCACHE_ASSO3 is not set
+# CONFIG_DCACHE_ASSO4 is not set
+# CONFIG_DCACHE_SZ1 is not set
+# CONFIG_DCACHE_SZ2 is not set
+CONFIG_DCACHE_SZ4=y
+# CONFIG_DCACHE_SZ8 is not set
+# CONFIG_DCACHE_SZ16 is not set
+# CONFIG_DCACHE_SZ32 is not set
+# CONFIG_DCACHE_SZ64 is not set
+# CONFIG_DCACHE_SZ128 is not set
+# CONFIG_DCACHE_SZ256 is not set
+CONFIG_DCACHE_LZ16=y
+# CONFIG_DCACHE_LZ32 is not set
+# CONFIG_DCACHE_ALGORND is not set
+# CONFIG_DCACHE_ALGOLRR is not set
+CONFIG_DCACHE_ALGOLRU=y
+# CONFIG_DCACHE_LOCK is not set
+CONFIG_DCACHE_SNOOP=y
+# CONFIG_DCACHE_SNOOP_FAST is not set
+# CONFIG_DCACHE_SNOOP_SEPTAG is not set
+CONFIG_CACHE_FIXED=0
+
+#
+# MMU
+#
+CONFIG_MMU_ENABLE=y
+# CONFIG_MMU_COMBINED is not set
+CONFIG_MMU_SPLIT=y
+# CONFIG_MMU_REPARRAY is not set
+CONFIG_MMU_REPINCREMENT=y
+# CONFIG_MMU_I2 is not set
+# CONFIG_MMU_I4 is not set
+CONFIG_MMU_I8=y
+# CONFIG_MMU_I16 is not set
+# CONFIG_MMU_I32 is not set
+# CONFIG_MMU_D2 is not set
+# CONFIG_MMU_D4 is not set
+CONFIG_MMU_D8=y
+# CONFIG_MMU_D16 is not set
+# CONFIG_MMU_D32 is not set
+
+#
+# Debug Support Unit
+#
+CONFIG_DSU_ENABLE=y
+CONFIG_DSU_ITRACE=y
+# CONFIG_DSU_ITRACESZ1 is not set
+CONFIG_DSU_ITRACESZ2=y
+# CONFIG_DSU_ITRACESZ4 is not set
+# CONFIG_DSU_ITRACESZ8 is not set
+# CONFIG_DSU_ITRACESZ16 is not set
+CONFIG_DSU_ATRACE=y
+# CONFIG_DSU_ATRACESZ1 is not set
+CONFIG_DSU_ATRACESZ2=y
+# CONFIG_DSU_ATRACESZ4 is not set
+# CONFIG_DSU_ATRACESZ8 is not set
+# CONFIG_DSU_ATRACESZ16 is not set
+
+#
+# Fault-tolerance
+#
+
+#
+# VHDL debug settings
+#
+# CONFIG_IU_DISAS is not set
+# CONFIG_DEBUG_PC32 is not set
+
+#
+# AMBA configuration
+#
+CONFIG_AHB_DEFMST=0
+CONFIG_AHB_RROBIN=y
+# CONFIG_AHB_SPLIT is not set
+CONFIG_AHB_IOADDR=FFF
+CONFIG_APB_HADDR=800
+# CONFIG_AHB_MON is not set
+
+#
+# Debug Link
+#
+# CONFIG_DSU_UART is not set
+CONFIG_DSU_JTAG=y
+
+#
+# Peripherals
+#
+
+#
+# Memory controllers
+#
+
+#
+# Leon2 memory controller
+#
+# CONFIG_MCTRL_LEON2 is not set
+
+#
+# Synchronous SRAM controller
+#
+CONFIG_SSCTRL=y
+CONFIG_SSCTRL_PROM16=y
+
+#
+# DDR266 SDRAM controller
+#
+# CONFIG_DDRSP is not set
+
+#
+# On-chip RAM/ROM
+#
+# CONFIG_AHBROM_ENABLE is not set
+# CONFIG_AHBRAM_ENABLE is not set
+
+#
+# UARTs, timers and irq control
+#
+CONFIG_UART1_ENABLE=y
+# CONFIG_UA1_FIFO1 is not set
+# CONFIG_UA1_FIFO2 is not set
+# CONFIG_UA1_FIFO4 is not set
+CONFIG_UA1_FIFO8=y
+# CONFIG_UA1_FIFO16 is not set
+# CONFIG_UA1_FIFO32 is not set
+CONFIG_IRQ3_ENABLE=y
+CONFIG_GPT_ENABLE=y
+CONFIG_GPT_NTIM=2
+CONFIG_GPT_SW=8
+CONFIG_GPT_TW=32
+CONFIG_GPT_IRQ=8
+CONFIG_GPT_SEPIRQ=y
+# CONFIG_GPT_WDOGEN is not set
+CONFIG_GRGPIO_ENABLE=y
+CONFIG_GRGPIO_WIDTH=3
+CONFIG_GRGPIO_IMASK=6
+
+#
+# ATA Controller
+#
+CONFIG_ATA_ENABLE=y
+CONFIG_ATAIO=A00
+CONFIG_ATAIRQ=10
+
+#
+# VHDL Debugging
+#
+# CONFIG_DEBUG_UART is not set
--- /dev/null
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--- /dev/null
+ bool 'LCD graphical frame buffer ' CONFIG_LCD_ENABLE
+ bool 'LCD 3-wire and touch panel ' CONFIG_LCD3T_ENABLE
+
--- /dev/null
+#ifndef CONFIG_LCD_ENABLE
+#define CONFIG_LCD_ENABLE 0
+#endif
+#ifndef CONFIG_LCD3T_ENABLE
+#define CONFIG_LCD3T_ENABLE 0
+#endif
+
--- /dev/null
+LCD frame buffer
+CONFIG_LCD_ENABLE
+ Say Y here to enable a graphical frame buffer. The frame buffer
+ can be configured up to 1024x768 pixels and 8-, 16- or 32-bit
+ colour depth.
+
+LCD 3-wire serial interface and touch panel support
+CONFIG_LCD3T_ENABLE
+ Say Y here to instantiate a SPI controller that allows LCD touch
+ panel and LCD 3-wire serial interface support
+
--- /dev/null
+-- LCD SVGA controller
+ constant CFG_LCD_ENABLE : integer := CONFIG_LCD_ENABLE;
+
+-- LCD 3-wire serial interface
+ constant CFG_LCD3T_ENABLE : integer := CONFIG_LCD3T_ENABLE;
+
--- /dev/null
+# FILE: header.tk
+# This file is boilerplate TCL/TK function definitions for 'make xconfig'.
+#
+# CHANGES
+# =======
+#
+# 8 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
+# - Remove unused do_cmd function (part of the 2.0 sound support).
+# - Arrange buttons in three columns for better screen fitting.
+# - Add CONSTANT_Y, CONSTANT_M, CONSTANT_N for commands like:
+# dep_tristate 'foo' CONFIG_FOO m
+#
+# 23 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
+# - Shut vfix the hell up.
+#
+# 24 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
+# - Improve the exit message (Jeff Ronne).
+
+#
+# This is a handy replacement for ".widget cget" that requires neither tk4
+# nor additional source code uglification.
+#
+proc cget { w option } {
+ return "[lindex [$w configure $option] 4]"
+}
+
+#
+# Function to compensate for broken config.in scripts like the sound driver,
+# which make dependencies on variables that are never even conditionally
+# defined.
+#
+proc vfix { var } {
+ global $var
+ if [ catch {eval concat $$var} ] {
+ set $var 4
+ }
+}
+
+#
+# Constant values used by certain dep_tristate commands.
+#
+set CONSTANT_Y 1
+set CONSTANT_M 2
+set CONSTANT_N 0
+set CONSTANT_E 4
+
+#
+# Create a "reference" object to steal colors from.
+#
+button .ref
+
+#
+# On monochrome displays, -disabledforeground is blank by default; that's
+# bad. Fill it with -foreground instead.
+#
+if { [cget .ref -disabledforeground] == "" } {
+ .ref configure -disabledforeground [cget .ref -foreground]
+}
+
+
+#
+# Define some macros we will need to parse the config.in file.
+#
+
+proc mainmenu_name { text } {
+ wm title . "$text"
+}
+
+proc menu_option { w menu_num text } {
+ global menus_per_column
+ global processed_top_level
+ set processed_top_level [expr $processed_top_level + 1]
+ if { $processed_top_level <= $menus_per_column } then {
+ set myframe left
+ } elseif { $processed_top_level <= [expr 2 * $menus_per_column] } then {
+ set myframe middle
+ } else {
+ set myframe right
+ }
+ button .f0.x$menu_num -anchor w -text "$text" \
+ -command "$w .$w \"$text\""
+ pack .f0.x$menu_num -pady 0 -side top -fill x -in .f0.$myframe
+}
+
+proc load_configfile { w title func } {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+ global loadfile
+ frame $w.x
+ label $w.bm -bitmap questhead
+ pack $w.bm -pady 10 -side top -padx 10
+ label $w.x.l -text "Enter filename:" -relief raised
+ entry $w.x.x -width 35 -relief sunken -borderwidth 2 \
+ -textvariable loadfile
+ pack $w.x.l $w.x.x -anchor w -side left
+ pack $w.x -side top -pady 10
+ wm title $w "$title"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "OK" -width 20 \
+ -command "destroy $w; focus $oldFocus;$func .fileio"
+ button $w.f.canc -text "Cancel" \
+ -width 20 -command "destroy $w; focus $oldFocus"
+ pack $w.f.back $w.f.canc -side left -pady 10 -padx 45
+ pack $w.f -pady 10 -side bottom -padx 10 -anchor w
+ focus $w
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+}
+
+bind all <Alt-q> {maybe_exit .maybe}
+
+proc maybe_exit { w } {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+ label $w.bm -bitmap questhead
+ pack $w.bm -pady 10 -side top -padx 10
+ message $w.m -width 400 -aspect 300 \
+ -text "Changes will be lost. Are you sure?" -relief flat
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Are you sure?"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "OK" -width 20 \
+ -command "exit 1"
+ button $w.f.canc -text "Cancel" \
+ -width 20 -command "destroy $w; focus $oldFocus"
+ pack $w.f.back $w.f.canc -side left -pady 10 -padx 45
+ pack $w.f -pady 10 -side bottom -padx 10 -anchor w
+ bind $w <Return> "exit 1"
+ bind $w <Escape> "destroy $w; focus $oldFocus"
+ focus $w
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+}
+
+proc read_config_file { w } {
+ global loadfile
+ if { [string length $loadfile] != 0 && [file readable $loadfile] == 1 } then {
+ read_config $loadfile
+ } else {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+ message $w.m -width 400 -aspect 300 -text \
+ "Unable to read file $loadfile" \
+ -relief raised
+ label $w.bm -bitmap error
+ pack $w.bm $w.m -pady 10 -side top -padx 10
+ wm title $w "Xconfig Internal Error"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "Bummer" \
+ -width 10 -command "destroy $w; focus $oldFocus"
+ pack $w.f.back -side bottom -pady 10 -anchor s
+ pack $w.f -pady 10 -side top -padx 10 -anchor s
+ focus $w
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+ }
+}
+
+proc write_config_file { w } {
+ global loadfile
+ if { [string length $loadfile] != 0
+ && ([file writable $loadfile] == 1 || ([file exists $loadfile] == 0 && [file writable [file dirname $loadfile]] == 1)) } then {
+ writeconfig $loadfile .null
+ } else {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+ message $w.m -width 400 -aspect 300 -text \
+ "Unable to write file $loadfile" \
+ -relief raised
+ label $w.bm -bitmap error
+ pack $w.bm $w.m -pady 10 -side top -padx 10
+ wm title $w "Xconfig Internal Error"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 10 -command "destroy $w; focus $oldFocus"
+ pack $w.f.back -side bottom -pady 10 -anchor s
+ pack $w.f -pady 10 -side top -padx 10 -anchor s
+ focus $w
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+ }
+}
+
+proc read_config { filename } {
+ set file1 [open $filename r]
+ clear_choices
+ while { [gets $file1 line] >= 0} {
+ if [regexp {([0-9A-Za-z_]+)=([ynm])} $line foo var value] {
+ if { $value == "y" } then { set cmd "global $var; set $var 1" }
+ if { $value == "n" } then { set cmd "global $var; set $var 0" }
+ if { $value == "m" } then { set cmd "global $var; set $var 2" }
+ eval $cmd
+ }
+ if [regexp {# ([0-9A-Za-z_]+) is not set} $line foo var] {
+ set cmd "global $var; set $var 0"
+ eval $cmd
+ }
+ if [regexp {([0-9A-Za-z_]+)=([0-9A-Fa-f]+)} $line foo var value] {
+ set cmd "global $var; set $var $value"
+ eval $cmd
+ }
+ if [regexp {([0-9A-Za-z_]+)="([^"]*)"} $line foo var value] {
+ set cmd "global $var; set $var \"$value\""
+ eval $cmd
+ }
+ }
+ close $file1
+ update_choices
+ update_mainmenu
+}
+proc write_comment { file1 file2 text } {
+ puts $file1 ""
+ puts $file1 "#"
+ puts $file1 "# $text"
+ puts $file1 "#"
+ puts $file2 "/*"
+ puts $file2 " * $text"
+ puts $file2 " */"
+}
+
+proc effective_dep { deplist } {
+ global CONFIG_MODULES
+ set depend 1
+ foreach i $deplist {
+ if {$i == 0} then {set depend 0}
+ if {$i == 2 && $depend == 1} then {set depend 2}
+ }
+ if {$depend == 2 && $CONFIG_MODULES == 0} then {set depend 0}
+ return $depend
+}
+
+proc sync_tristate { var dep } {
+ global CONFIG_MODULES
+ if {$dep == 0 && ($var == 1 || $var == 2)} then {
+ set var 0
+ } elseif {$dep == 2 && $var == 1} then {
+ set var 2
+ } elseif {$var == 2 && $CONFIG_MODULES == 0} then {
+ if {$dep == 1} then {set var 1} else {set var 0}
+ }
+ return $var
+}
+
+proc sync_bool { var dep modset } {
+ set var [sync_tristate $var $dep]
+ if {$dep == 2 && $var == 2} then {
+ set var $modset
+ }
+ return $var
+}
+
+proc write_tristate { file1 file2 varname variable deplist modset } {
+ set variable [sync_tristate $variable [effective_dep $deplist]]
+ if { $variable == 2 } \
+ then { set variable $modset }
+ if { $variable == 1 } \
+ then { puts $file1 "$varname=y"; \
+ puts $file2 "#define $varname 1" } \
+ elseif { $variable == 2 } \
+ then { puts $file1 "$varname=m"; \
+ puts $file2 "#undef $varname"; \
+ puts $file2 "#define ${varname}_MODULE 1" } \
+ elseif { $variable == 0 } \
+ then { puts $file1 "# $varname is not set"; \
+ puts $file2 "#undef $varname"} \
+ else { \
+ puts stdout "ERROR - Attempting to write value for unconfigured variable ($varname)." \
+ }
+}
+
+proc write_int { file1 file2 varname variable dep } {
+ if { $dep == 0 } \
+ then { puts $file1 "# $varname is not set"; \
+ puts $file2 "#undef $varname"} \
+ else {
+ puts $file1 "$varname=$variable"; \
+ puts $file2 "#define $varname ($variable)"; \
+ }
+}
+
+proc write_hex { file1 file2 varname variable dep } {
+ if { $dep == 0 } \
+ then { puts $file1 "# $varname is not set"; \
+ puts $file2 "#undef $varname"} \
+ else {
+ puts $file1 "$varname=$variable"; \
+ puts -nonewline $file2 "#define $varname "; \
+ puts $file2 [exec echo $variable | sed s/^0\[xX\]//]; \
+ }
+}
+
+proc write_string { file1 file2 varname variable dep } {
+ if { $dep == 0 } \
+ then { puts $file1 "# $varname is not set"; \
+ puts $file2 "#undef $varname"} \
+ else {
+ puts $file1 "$varname=\"$variable\""; \
+ puts $file2 "#define $varname \"$variable\""; \
+ }
+}
+
+proc option_name {w mnum line text helpidx} {
+ button $w.x$line.l -text "$text" -relief groove -anchor w
+ $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
+ -activeback [cget $w.x$line.l -bg]
+ button $w.x$line.help -text "Help" -relief raised \
+ -command "dohelp .dohelp $helpidx .menu$mnum"
+ pack $w.x$line.help -side right -fill y
+ pack $w.x$line.l -side right -fill both -expand on
+}
+
+proc toggle_switch2 {w mnum line text variable} {
+ frame $w.x$line -relief sunken
+ radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \
+ -relief groove -width 2 -command "update_active"
+# radiobutton $w.x$line.m -text "-" -variable $variable -value 2 \
+# -relief groove -width 2 -command "update_active"
+ radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \
+ -relief groove -width 2 -command "update_active"
+
+ option_name $w $mnum $line $text $variable
+
+ pack $w.x$line.n $w.x$line.y -side right -fill y
+}
+
+proc toggle_switch3 {w mnum line text variable} {
+ frame $w.x$line -relief sunken
+ radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \
+ -relief groove -width 2 -command "update_active"
+ radiobutton $w.x$line.m -text "m" -variable $variable -value 2 \
+ -relief groove -width 2 -command "update_active"
+ radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \
+ -relief groove -width 2 -command "update_active"
+
+ option_name $w $mnum $line $text $variable
+
+ global CONFIG_MODULES
+ if {($CONFIG_MODULES == 0)} then {
+ $w.x$line.m configure -state disabled
+ }
+ pack $w.x$line.n $w.x$line.m $w.x$line.y -side right -fill y
+}
+
+proc bool {w mnum line text variable} {
+ toggle_switch2 $w $mnum $line $text $variable
+# $w.x$line.m configure -state disabled
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc tristate {w mnum line text variable } {
+ toggle_switch3 $w $mnum $line $text $variable
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc dep_tristate {w mnum line text variable } {
+ tristate $w $mnum $line $text $variable
+}
+
+proc dep_bool {w mnum line text variable } {
+ bool $w $mnum $line $text $variable
+}
+
+proc int { w mnum line text variable } {
+ frame $w.x$line
+ entry $w.x$line.x -width 11 -relief sunken -borderwidth 2 \
+ -textvariable $variable
+ option_name $w $mnum $line $text $variable
+ pack $w.x$line.x -anchor w -side right -fill y
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc hex { w mnum line text variable } {
+ int $w $mnum $line $text $variable
+}
+
+proc istring { w mnum line text variable } {
+ frame $w.x$line
+ entry $w.x$line.x -width 18 -relief sunken -borderwidth 2 \
+ -textvariable $variable
+ option_name $w $mnum $line $text $variable
+ pack $w.x$line.x -anchor w -side right -fill y
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc minimenu { w mnum line text variable helpidx } {
+ frame $w.x$line
+ menubutton $w.x$line.x -textvariable $variable -menu \
+ $w.x$line.x.menu -relief raised \
+ -anchor w
+ option_name $w $mnum $line $text $helpidx
+ pack $w.x$line.x -anchor w -side right -fill y
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc menusplit {w m n} {
+ if { $n > 2 } then {
+ update idletasks
+ set menuoptsize [expr [$m yposition 2] - [$m yposition 1]]
+ set maxsize [winfo screenheight $w]
+ set splitpoint [expr $maxsize * 4 / 5 / $menuoptsize - 1]
+ for {set i [expr $splitpoint + 1]} {$i <= $n} {incr i $splitpoint} {
+ $m entryconfigure $i -columnbreak 1
+ }
+ }
+}
+
+proc menutitle {text menu w} {
+ wm title $w "$text"
+}
+
+proc submenu { w mnum line text subnum } {
+ frame $w.x$line
+ button $w.x$line.l -text "" -width 9 -relief groove
+ $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
+ -activeback [cget $w.x$line.l -bg] -state disabled
+ button $w.x$line.m -text "$text" -relief raised -anchor w \
+ -command "catch {destroy .menu$subnum}; menu$subnum .menu$subnum \"$text\""
+ pack $w.x$line.l -side left -fill both
+ pack $w.x$line.m -anchor w -side right -fill both -expand on
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc comment {w mnum line text } {
+ frame $w.x$line
+ button $w.x$line.l -text "" -width 15 -relief groove
+ $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
+ -activeback [cget $w.x$line.l -bg] -state disabled
+ button $w.x$line.m -text "$text" -relief groove -anchor w
+ $w.x$line.m configure -activefore [cget $w.x$line.m -fg] \
+ -activeback [cget $w.x$line.m -bg]
+ pack $w.x$line.l -side left -fill both
+ pack $w.x$line.m -anchor w -side right -fill both -expand on
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc readhelp {tag fn} {
+ set message ""
+ set b 0
+ if { [file readable $fn] == 1} then {
+ set fhandle [open $fn r]
+ while {[gets $fhandle inline] >= 0} {
+ if { $b == 0 } {
+ if { [regexp $tag $inline ] } {
+ set b 1
+ set message "$inline:\n"
+ }
+ } else {
+ if { [regexp {^[^ \t]} $inline]} {
+ break
+ }
+ set message "$message\n$inline"
+ }
+ }
+ close $fhandle
+ }
+ return $message
+}
+
+proc dohelp {w var parent} {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+
+ set filefound 0
+ set found 0
+ set lineno 0
+
+ if { [file readable config.help] == 1} then {
+ set filefound 1
+ # First escape sed regexp special characters in var:
+ set var [exec echo "$var" | sed s/\[\]\[\/.^$*\]/\\\\&/g]
+ # Now pick out right help text:
+ set message [readhelp $var config.help]
+ set found [expr [string length "$message"] > 0]
+ }
+
+ frame $w.f1
+ pack $w.f1 -fill both -expand on
+
+ # Do the OK button
+ #
+ set oldFocus [focus]
+ frame $w.f2
+ button $w.f2.ok -text "OK" \
+ -width 10 -command "destroy $w; catch {focus $oldFocus}"
+ pack $w.f2.ok -side bottom -pady 6 -anchor n
+ pack $w.f2 -side bottom -padx 10 -anchor s
+
+ scrollbar $w.f1.vscroll -command "$w.f1.canvas yview"
+ pack $w.f1.vscroll -side right -fill y
+
+ canvas $w.f1.canvas -relief flat -borderwidth 0 \
+ -yscrollcommand "$w.f1.vscroll set"
+ frame $w.f1.f
+ pack $w.f1.canvas -side right -fill y -expand on
+
+ if { $found == 0 } then {
+ if { $filefound == 0 } then {
+ message $w.f1.f.m -width 750 -aspect 300 -relief flat -text \
+ "No help available - unable to open file config.help."
+ } else {
+ message $w.f1.f.m -width 400 -aspect 300 -relief flat -text \
+ "No help available for $var"
+ }
+ label $w.f1.bm -bitmap error
+ wm title $w "RTFM"
+ } else {
+ text $w.f1.f.m -width 73 -relief flat -wrap word
+ $w.f1.f.m insert 0.0 $message
+ $w.f1.f.m conf -state disabled -height [$w.f1.f.m index end]
+
+ label $w.f1.bm -bitmap info
+ wm title $w "Configuration help"
+ }
+ pack $w.f1.f.m -side left
+ pack $w.f1.bm $w.f1.f -side left -padx 10
+
+ focus $w
+ set winx [expr [winfo x $parent]+20]
+ set winy [expr [winfo y $parent]+20]
+ wm geometry $w +$winx+$winy
+ set sizok [expr [winfo reqheight $w.f2.ok] + 12]
+ set maxy [expr [winfo screenheight .] * 3 / 4]
+ set canvtotal [winfo reqheight $w.f1.f.m]
+ if [expr $sizok + $canvtotal < $maxy] {
+ set sizy $canvtotal
+ } else {
+ set sizy [expr $maxy - $sizok]
+ }
+ $w.f1.canvas configure -height $sizy -width [winfo reqwidth $w.f1.f.m] \
+ -scrollregion "0 0 [winfo reqwidth $w.f1.f.m] \
+ [winfo reqheight $w.f1.f.m]"
+ $w.f1.canvas create window 0 0 -anchor nw -window $w.f1.f
+ update idletasks
+
+ set maxy [winfo screenheight .]
+ if [expr $sizok + $canvtotal < $maxy] {
+ set sizy [expr $sizok + $canvtotal]
+ } else {
+ set sizy $maxy
+ }
+ wm maxsize $w [winfo width $w] $sizy
+}
+
+bind all <Alt-s> { catch {exec cp -f .config .config.old}; \
+ writeconfig .config config.h; wrapup .wrap }
+
+proc wrapup {w } {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+
+ global CONFIG_MODVERSIONS; vfix CONFIG_MODVERSIONS
+ message $w.m -width 460 -aspect 300 -relief raised -text \
+ "End of design configuration. "
+ label $w.bm -bitmap info
+ pack $w.bm $w.m -pady 10 -side top -padx 10
+ wm title $w "LEON build instructions"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 10 -command "exit 2"
+ pack $w.f.back -side bottom -pady 10 -anchor s
+ pack $w.f -pady 10 -side top -padx 10 -anchor s
+ focus $w
+ bind $w <Return> "exit 2"
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+
+}
+
+proc unregister_active {num} {
+ global active_menus
+ set index [lsearch -exact $active_menus $num]
+ if {$index != -1} then {set active_menus [lreplace $active_menus $index $index]}
+}
+
+proc update_active {} {
+ global active_menus total_menus
+ set max 0
+ if {[llength $active_menus] > 0} then {
+ set max [lindex $active_menus end]
+ update_define [toplevel_menu [lindex $active_menus 0]] $max 0
+ }
+ foreach i $active_menus {
+ if {[winfo exists .menu$i] == 0} then {
+ unregister_active $i
+ } else {
+ update_menu$i
+ }
+ }
+ update_define [expr $max + 1] $total_menus 1
+ update_mainmenu
+}
+
+proc configure_entry {w option items} {
+ foreach i $items {
+ $w.$i configure -state $option
+ }
+}
+
+proc validate_int {name val default} {
+ if {([exec echo $val | sed s/^-//g | tr -d \[:digit:\] ] != "")} then {
+ global $name; set $name $default
+ }
+}
+
+proc validate_hex {name val default} {
+ if {([exec echo $val | tr -d \[:xdigit:\] ] != "")} then {
+ global $name; set $name $default
+ }
+}
+
+proc update_define {first last allow_update} {
+ for {set i $first} {$i <= $last} {incr i} {
+ update_define_menu$i
+ if {$allow_update == 1} then update
+ }
+}
+
+#
+# Next set up the particulars for the top level menu, and define a few
+# buttons which we will stick down at the bottom.
+#
+
+frame .f0
+frame .f0.left
+frame .f0.middle
+frame .f0.right
+
+set active_menus [list]
+set processed_top_level 0
+set ARCH sparc
+set menus_per_column 4
+set total_menus 25
+
+proc toplevel_menu {num} {
+ if {$num == 4} then {return 3}
+ if {$num == 5} then {return 3}
+ if {$num == 6} then {return 3}
+ if {$num == 7} then {return 3}
+ if {$num == 8} then {return 3}
+ if {$num == 9} then {return 3}
+ if {$num == 10} then {return 3}
+ if {$num == 14} then {return 13}
+ if {$num == 15} then {return 14}
+ if {$num == 16} then {return 14}
+ if {$num == 17} then {return 14}
+ if {$num == 18} then {return 14}
+ if {$num == 19} then {return 13}
+ if {$num == 20} then {return 13}
+ if {$num == 21} then {return 13}
+ if {$num == 22} then {return 13}
+ if {$num == 23} then {return 22}
+ if {$num == 24} then {return 13}
+ return $num
+}
+
+mainmenu_name "LEON3 Altera EP3C25-EEK Design Configuration"
+menu_option menu1 1 "Synthesis "
+proc menu1 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 1}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 1]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Synthesis " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Synthesis "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 1; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu2 .menu2 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu0 .menu0 \"$title\""
+ $w.f.prev configure -state disabled
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ global tmpvar_0
+ minimenu $w.config.f 1 0 "Target technology " tmpvar_0 CONFIG_SYN_INFERRED
+ menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Target technology \""
+ $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_0 -value "Inferred" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-Stratix" -variable tmpvar_0 -value "Altera-Stratix" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixII" -variable tmpvar_0 -value "Altera-StratixII" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixIII" -variable tmpvar_0 -value "Altera-StratixIII" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-CycloneIII" -variable tmpvar_0 -value "Altera-CycloneIII" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-Others" -variable tmpvar_0 -value "Altera-Others" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator" -variable tmpvar_0 -value "Actel-Axcelerator" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator-DSP" -variable tmpvar_0 -value "Actel-Axcelerator-DSP" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic" -variable tmpvar_0 -value "Actel-Proasic" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-ProasicPlus" -variable tmpvar_0 -value "Actel-ProasicPlus" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic3/E/L" -variable tmpvar_0 -value "Actel-Proasic3/E/L" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-IGLOO/p/L" -variable tmpvar_0 -value "Actel-IGLOO/p/L" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT025CRH" -variable tmpvar_0 -value "Aeroflex-UT025CRH" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18" -variable tmpvar_0 -value "Atmel-ATC18" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18RHA" -variable tmpvar_0 -value "Atmel-ATC18RHA" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Custom1" -variable tmpvar_0 -value "Custom1" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "eASIC90" -variable tmpvar_0 -value "eASIC90" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "IHP25" -variable tmpvar_0 -value "IHP25" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "IHP25RH" -variable tmpvar_0 -value "IHP25RH" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Lattice-EC/ECP/XP" -variable tmpvar_0 -value "Lattice-EC/ECP/XP" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Quicklogic-Eclipse" -variable tmpvar_0 -value "Quicklogic-Eclipse" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Peregrine" -variable tmpvar_0 -value "Peregrine" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T" -variable tmpvar_0 -value "RH-LIB18T" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_0 -value "RH-UMC" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "SMIC130" -variable tmpvar_0 -value "SMIC130" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan2" -variable tmpvar_0 -value "Xilinx-Spartan2" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3" -variable tmpvar_0 -value "Xilinx-Spartan3" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3E" -variable tmpvar_0 -value "Xilinx-Spartan3E" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex" -variable tmpvar_0 -value "Xilinx-Virtex" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-VirtexE" -variable tmpvar_0 -value "Xilinx-VirtexE" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex2" -variable tmpvar_0 -value "Xilinx-Virtex2" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex4" -variable tmpvar_0 -value "Xilinx-Virtex4" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex5" -variable tmpvar_0 -value "Xilinx-Virtex5" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "UMC180" -variable tmpvar_0 -value "UMC180" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "TSMC90" -variable tmpvar_0 -value "TSMC90" -command "update_active"
+ menusplit $w $w.config.f.x0.x.menu 35
+ global tmpvar_1
+ minimenu $w.config.f 1 1 "Memory Library " tmpvar_1 CONFIG_MEM_INFERRED
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Memory Library \""
+ $w.config.f.x1.x.menu add radiobutton -label "Inferred" -variable tmpvar_1 -value "Inferred" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "UMC18" -variable tmpvar_1 -value "UMC18" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_1 -value "RH-UMC" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Artisan" -variable tmpvar_1 -value "Artisan" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Custom1" -variable tmpvar_1 -value "Custom1" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Virage" -variable tmpvar_1 -value "Virage" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Virage-TSMC90" -variable tmpvar_1 -value "Virage-TSMC90" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 7
+ bool $w.config.f 1 2 "Infer RAM" CONFIG_SYN_INFER_RAM
+ bool $w.config.f 1 3 "Infer pads" CONFIG_SYN_INFER_PADS
+ bool $w.config.f 1 4 "Disable asynchronous reset" CONFIG_SYN_NO_ASYNC
+ bool $w.config.f 1 5 "Enable scan support " CONFIG_SYN_SCAN
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu1 {} {
+ global CONFIG_SYN_INFERRED
+ global CONFIG_SYN_CUSTOM1
+ global CONFIG_SYN_ATC18
+ global CONFIG_SYN_TSMC90
+ global CONFIG_SYN_UMC
+ global CONFIG_SYN_RHUMC
+ global CONFIG_SYN_ARTISAN
+ if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then {configure_entry .menu1.config.f.x1 normal {x l}} else {configure_entry .menu1.config.f.x1 disabled {x l}}
+ global CONFIG_SYN_INFER_RAM
+ if {($CONFIG_SYN_INFERRED != 1)} then {
+ configure_entry .menu1.config.f.x2 normal {n l y}} else {configure_entry .menu1.config.f.x2 disabled {y n l}}
+ global CONFIG_SYN_INFER_PADS
+ if {($CONFIG_SYN_INFERRED != 1)} then {
+ configure_entry .menu1.config.f.x3 normal {n l y}} else {configure_entry .menu1.config.f.x3 disabled {y n l}}
+}
+
+
+proc update_define_menu1 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global tmpvar_0
+ global CONFIG_SYN_INFERRED
+ if {$tmpvar_0 == "Inferred"} then {set CONFIG_SYN_INFERRED 1} else {set CONFIG_SYN_INFERRED 0}
+ global CONFIG_SYN_STRATIX
+ if {$tmpvar_0 == "Altera-Stratix"} then {set CONFIG_SYN_STRATIX 1} else {set CONFIG_SYN_STRATIX 0}
+ global CONFIG_SYN_STRATIXII
+ if {$tmpvar_0 == "Altera-StratixII"} then {set CONFIG_SYN_STRATIXII 1} else {set CONFIG_SYN_STRATIXII 0}
+ global CONFIG_SYN_STRATIXIII
+ if {$tmpvar_0 == "Altera-StratixIII"} then {set CONFIG_SYN_STRATIXIII 1} else {set CONFIG_SYN_STRATIXIII 0}
+ global CONFIG_SYN_CYCLONEIII
+ if {$tmpvar_0 == "Altera-CycloneIII"} then {set CONFIG_SYN_CYCLONEIII 1} else {set CONFIG_SYN_CYCLONEIII 0}
+ global CONFIG_SYN_ALTERA
+ if {$tmpvar_0 == "Altera-Others"} then {set CONFIG_SYN_ALTERA 1} else {set CONFIG_SYN_ALTERA 0}
+ global CONFIG_SYN_AXCEL
+ if {$tmpvar_0 == "Actel-Axcelerator"} then {set CONFIG_SYN_AXCEL 1} else {set CONFIG_SYN_AXCEL 0}
+ global CONFIG_SYN_AXDSP
+ if {$tmpvar_0 == "Actel-Axcelerator-DSP"} then {set CONFIG_SYN_AXDSP 1} else {set CONFIG_SYN_AXDSP 0}
+ global CONFIG_SYN_PROASIC
+ if {$tmpvar_0 == "Actel-Proasic"} then {set CONFIG_SYN_PROASIC 1} else {set CONFIG_SYN_PROASIC 0}
+ global CONFIG_SYN_PROASICPLUS
+ if {$tmpvar_0 == "Actel-ProasicPlus"} then {set CONFIG_SYN_PROASICPLUS 1} else {set CONFIG_SYN_PROASICPLUS 0}
+ global CONFIG_SYN_PROASIC3
+ if {$tmpvar_0 == "Actel-Proasic3/E/L"} then {set CONFIG_SYN_PROASIC3 1} else {set CONFIG_SYN_PROASIC3 0}
+ global CONFIG_SYN_IGLOO
+ if {$tmpvar_0 == "Actel-IGLOO/p/L"} then {set CONFIG_SYN_IGLOO 1} else {set CONFIG_SYN_IGLOO 0}
+ global CONFIG_SYN_UT025CRH
+ if {$tmpvar_0 == "Aeroflex-UT025CRH"} then {set CONFIG_SYN_UT025CRH 1} else {set CONFIG_SYN_UT025CRH 0}
+ global CONFIG_SYN_ATC18
+ if {$tmpvar_0 == "Atmel-ATC18"} then {set CONFIG_SYN_ATC18 1} else {set CONFIG_SYN_ATC18 0}
+ global CONFIG_SYN_ATC18RHA
+ if {$tmpvar_0 == "Atmel-ATC18RHA"} then {set CONFIG_SYN_ATC18RHA 1} else {set CONFIG_SYN_ATC18RHA 0}
+ global CONFIG_SYN_CUSTOM1
+ if {$tmpvar_0 == "Custom1"} then {set CONFIG_SYN_CUSTOM1 1} else {set CONFIG_SYN_CUSTOM1 0}
+ global CONFIG_SYN_EASIC90
+ if {$tmpvar_0 == "eASIC90"} then {set CONFIG_SYN_EASIC90 1} else {set CONFIG_SYN_EASIC90 0}
+ global CONFIG_SYN_IHP25
+ if {$tmpvar_0 == "IHP25"} then {set CONFIG_SYN_IHP25 1} else {set CONFIG_SYN_IHP25 0}
+ global CONFIG_SYN_IHP25RH
+ if {$tmpvar_0 == "IHP25RH"} then {set CONFIG_SYN_IHP25RH 1} else {set CONFIG_SYN_IHP25RH 0}
+ global CONFIG_SYN_LATTICE
+ if {$tmpvar_0 == "Lattice-EC/ECP/XP"} then {set CONFIG_SYN_LATTICE 1} else {set CONFIG_SYN_LATTICE 0}
+ global CONFIG_SYN_ECLIPSE
+ if {$tmpvar_0 == "Quicklogic-Eclipse"} then {set CONFIG_SYN_ECLIPSE 1} else {set CONFIG_SYN_ECLIPSE 0}
+ global CONFIG_SYN_PEREGRINE
+ if {$tmpvar_0 == "Peregrine"} then {set CONFIG_SYN_PEREGRINE 1} else {set CONFIG_SYN_PEREGRINE 0}
+ global CONFIG_SYN_RH_LIB18T
+ if {$tmpvar_0 == "RH-LIB18T"} then {set CONFIG_SYN_RH_LIB18T 1} else {set CONFIG_SYN_RH_LIB18T 0}
+ global CONFIG_SYN_RHUMC
+ if {$tmpvar_0 == "RH-UMC"} then {set CONFIG_SYN_RHUMC 1} else {set CONFIG_SYN_RHUMC 0}
+ global CONFIG_SYN_SMIC13
+ if {$tmpvar_0 == "SMIC130"} then {set CONFIG_SYN_SMIC13 1} else {set CONFIG_SYN_SMIC13 0}
+ global CONFIG_SYN_SPARTAN2
+ if {$tmpvar_0 == "Xilinx-Spartan2"} then {set CONFIG_SYN_SPARTAN2 1} else {set CONFIG_SYN_SPARTAN2 0}
+ global CONFIG_SYN_SPARTAN3
+ if {$tmpvar_0 == "Xilinx-Spartan3"} then {set CONFIG_SYN_SPARTAN3 1} else {set CONFIG_SYN_SPARTAN3 0}
+ global CONFIG_SYN_SPARTAN3E
+ if {$tmpvar_0 == "Xilinx-Spartan3E"} then {set CONFIG_SYN_SPARTAN3E 1} else {set CONFIG_SYN_SPARTAN3E 0}
+ global CONFIG_SYN_VIRTEX
+ if {$tmpvar_0 == "Xilinx-Virtex"} then {set CONFIG_SYN_VIRTEX 1} else {set CONFIG_SYN_VIRTEX 0}
+ global CONFIG_SYN_VIRTEXE
+ if {$tmpvar_0 == "Xilinx-VirtexE"} then {set CONFIG_SYN_VIRTEXE 1} else {set CONFIG_SYN_VIRTEXE 0}
+ global CONFIG_SYN_VIRTEX2
+ if {$tmpvar_0 == "Xilinx-Virtex2"} then {set CONFIG_SYN_VIRTEX2 1} else {set CONFIG_SYN_VIRTEX2 0}
+ global CONFIG_SYN_VIRTEX4
+ if {$tmpvar_0 == "Xilinx-Virtex4"} then {set CONFIG_SYN_VIRTEX4 1} else {set CONFIG_SYN_VIRTEX4 0}
+ global CONFIG_SYN_VIRTEX5
+ if {$tmpvar_0 == "Xilinx-Virtex5"} then {set CONFIG_SYN_VIRTEX5 1} else {set CONFIG_SYN_VIRTEX5 0}
+ global CONFIG_SYN_UMC
+ if {$tmpvar_0 == "UMC180"} then {set CONFIG_SYN_UMC 1} else {set CONFIG_SYN_UMC 0}
+ global CONFIG_SYN_TSMC90
+ if {$tmpvar_0 == "TSMC90"} then {set CONFIG_SYN_TSMC90 1} else {set CONFIG_SYN_TSMC90 0}
+ global tmpvar_1
+ global CONFIG_MEM_INFERRED
+ if {$tmpvar_1 == "Inferred"} then {set CONFIG_MEM_INFERRED 1} else {set CONFIG_MEM_INFERRED 0}
+ global CONFIG_MEM_UMC
+ if {$tmpvar_1 == "UMC18"} then {set CONFIG_MEM_UMC 1} else {set CONFIG_MEM_UMC 0}
+ global CONFIG_MEM_RHUMC
+ if {$tmpvar_1 == "RH-UMC"} then {set CONFIG_MEM_RHUMC 1} else {set CONFIG_MEM_RHUMC 0}
+ global CONFIG_MEM_ARTISAN
+ if {$tmpvar_1 == "Artisan"} then {set CONFIG_MEM_ARTISAN 1} else {set CONFIG_MEM_ARTISAN 0}
+ global CONFIG_MEM_CUSTOM1
+ if {$tmpvar_1 == "Custom1"} then {set CONFIG_MEM_CUSTOM1 1} else {set CONFIG_MEM_CUSTOM1 0}
+ global CONFIG_MEM_VIRAGE
+ if {$tmpvar_1 == "Virage"} then {set CONFIG_MEM_VIRAGE 1} else {set CONFIG_MEM_VIRAGE 0}
+ global CONFIG_MEM_VIRAGE90
+ if {$tmpvar_1 == "Virage-TSMC90"} then {set CONFIG_MEM_VIRAGE90 1} else {set CONFIG_MEM_VIRAGE90 0}
+ global CONFIG_SYN_INFER_RAM
+ if {($CONFIG_SYN_INFERRED != 1)} then {
+ set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM&15]} else {set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM|16]}
+ global CONFIG_SYN_INFER_PADS
+ if {($CONFIG_SYN_INFERRED != 1)} then {
+ set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS&15]} else {set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS|16]}
+}
+
+
+menu_option menu2 2 "Clock generation"
+proc menu2 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 2}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 2]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Clock generation" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Clock generation"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 2; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu3 .menu3 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ global tmpvar_2
+ minimenu $w.config.f 2 0 "Clock generator " tmpvar_2 CONFIG_CLK_INFERRED
+ menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Clock generator \""
+ $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_2 -value "Inferred" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-HCLKBUF" -variable tmpvar_2 -value "Actel-HCLKBUF" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-ALTPLL" -variable tmpvar_2 -value "Altera-ALTPLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Lattice-EXPLL" -variable tmpvar_2 -value "Lattice-EXPLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Proasic3-PLLL" -variable tmpvar_2 -value "Proasic3-PLLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T-PLL" -variable tmpvar_2 -value "RH-LIB18T-PLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "DARE-PLL" -variable tmpvar_2 -value "DARE-PLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-CLKDLL" -variable tmpvar_2 -value "Xilinx-CLKDLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-DCM" -variable tmpvar_2 -value "Xilinx-DCM" -command "update_active"
+ menusplit $w $w.config.f.x0.x.menu 9
+ int $w.config.f 2 1 "Clock multiplication factor (2 - 32)" CONFIG_CLK_MUL
+ int $w.config.f 2 2 "Clock division factor (2 - 32)" CONFIG_CLK_DIV
+ int $w.config.f 2 3 "Outout division factor (2 - 32)" CONFIG_OCLK_DIV
+ bool $w.config.f 2 4 "Enable Xilinx CLKDLL for PCI clock" CONFIG_PCI_CLKDLL
+ bool $w.config.f 2 5 "Disable external feedback for SDRAM clock" CONFIG_CLK_NOFB
+ bool $w.config.f 2 6 "Use PCI clock as system clock" CONFIG_PCI_SYSCLK
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu2 {} {
+ global CONFIG_CLK_DCM
+ global CONFIG_CLK_ALTDLL
+ global CONFIG_CLK_LATDLL
+ global CONFIG_CLK_PRO3PLL
+ global CONFIG_CLK_CLKDLL
+ global CONFIG_CLK_LIB18T
+ global CONFIG_CLK_MUL
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x1.l configure -state normal; } else {.menu2.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x1.l configure -state disabled}
+ global CONFIG_CLK_DIV
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x2.l configure -state normal; } else {.menu2.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x2.l configure -state disabled}
+ global CONFIG_OCLK_DIV
+ if {($CONFIG_CLK_PRO3PLL == 1)} then {.menu2.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x3.l configure -state normal; } else {.menu2.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x3.l configure -state disabled}
+ global CONFIG_PCI_CLKDLL
+ if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {
+ configure_entry .menu2.config.f.x4 normal {n l y}} else {configure_entry .menu2.config.f.x4 disabled {y n l}}
+ global CONFIG_CLK_NOFB
+ if {($CONFIG_CLK_DCM == 1)} then {
+ configure_entry .menu2.config.f.x5 normal {n l y}} else {configure_entry .menu2.config.f.x5 disabled {y n l}}
+ global CONFIG_PCI_ENABLE
+ global CONFIG_PCI_SYSCLK
+ if {($CONFIG_PCI_ENABLE != 1)} then {
+ configure_entry .menu2.config.f.x6 normal {n l y}} else {configure_entry .menu2.config.f.x6 disabled {y n l}}
+}
+
+
+proc update_define_menu2 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global tmpvar_2
+ global CONFIG_CLK_INFERRED
+ if {$tmpvar_2 == "Inferred"} then {set CONFIG_CLK_INFERRED 1} else {set CONFIG_CLK_INFERRED 0}
+ global CONFIG_CLK_HCLKBUF
+ if {$tmpvar_2 == "Actel-HCLKBUF"} then {set CONFIG_CLK_HCLKBUF 1} else {set CONFIG_CLK_HCLKBUF 0}
+ global CONFIG_CLK_ALTDLL
+ if {$tmpvar_2 == "Altera-ALTPLL"} then {set CONFIG_CLK_ALTDLL 1} else {set CONFIG_CLK_ALTDLL 0}
+ global CONFIG_CLK_LATDLL
+ if {$tmpvar_2 == "Lattice-EXPLL"} then {set CONFIG_CLK_LATDLL 1} else {set CONFIG_CLK_LATDLL 0}
+ global CONFIG_CLK_PRO3PLL
+ if {$tmpvar_2 == "Proasic3-PLLL"} then {set CONFIG_CLK_PRO3PLL 1} else {set CONFIG_CLK_PRO3PLL 0}
+ global CONFIG_CLK_LIB18T
+ if {$tmpvar_2 == "RH-LIB18T-PLL"} then {set CONFIG_CLK_LIB18T 1} else {set CONFIG_CLK_LIB18T 0}
+ global CONFIG_CLK_RHUMC
+ if {$tmpvar_2 == "DARE-PLL"} then {set CONFIG_CLK_RHUMC 1} else {set CONFIG_CLK_RHUMC 0}
+ global CONFIG_CLK_CLKDLL
+ if {$tmpvar_2 == "Xilinx-CLKDLL"} then {set CONFIG_CLK_CLKDLL 1} else {set CONFIG_CLK_CLKDLL 0}
+ global CONFIG_CLK_DCM
+ if {$tmpvar_2 == "Xilinx-DCM"} then {set CONFIG_CLK_DCM 1} else {set CONFIG_CLK_DCM 0}
+ global CONFIG_CLK_MUL
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_MUL "$CONFIG_CLK_MUL" 2}
+ global CONFIG_CLK_DIV
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_DIV "$CONFIG_CLK_DIV" 2}
+ global CONFIG_OCLK_DIV
+ if {($CONFIG_CLK_PRO3PLL == 1)} then {validate_int CONFIG_OCLK_DIV "$CONFIG_OCLK_DIV" 2}
+ global CONFIG_PCI_CLKDLL
+ if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {
+ set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL&15]} else {set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL|16]}
+ global CONFIG_CLK_NOFB
+ if {($CONFIG_CLK_DCM == 1)} then {
+ set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB&15]} else {set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB|16]}
+ global CONFIG_PCI_ENABLE
+ global CONFIG_PCI_SYSCLK
+ if {($CONFIG_PCI_ENABLE != 1)} then {
+ set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK&15]} else {set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK|16]}
+}
+
+
+menu_option menu3 3 "Processor "
+proc menu3 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 3}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 3]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Processor " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Processor "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 3; break"
+ set nextscript "catch {focus $oldFocus}; menu4 .menu4 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 3 0 "Enable LEON3 SPARC V8 Processor" CONFIG_LEON3
+ int $w.config.f 3 1 "Number of processors" CONFIG_PROC_NUM
+ submenu $w.config.f 3 2 "Integer unit " 4
+ submenu $w.config.f 3 3 "Floating-point unit" 5
+ submenu $w.config.f 3 4 "Cache system" 6
+ submenu $w.config.f 3 5 "MMU" 7
+ submenu $w.config.f 3 6 "Debug Support Unit " 8
+ submenu $w.config.f 3 7 "Fault-tolerance " 9
+ submenu $w.config.f 3 8 "VHDL debug settings " 10
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu3 {} {
+ global CONFIG_LEON3
+ global CONFIG_PROC_NUM
+ if {($CONFIG_LEON3 == 1)} then {.menu3.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu3.config.f.x1.l configure -state normal; } else {.menu3.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu3.config.f.x1.l configure -state disabled}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x2 normal {m}} else {configure_entry .menu3.config.f.x2 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x3 normal {m}} else {configure_entry .menu3.config.f.x3 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x4 normal {m}} else {configure_entry .menu3.config.f.x4 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x5 normal {m}} else {configure_entry .menu3.config.f.x5 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x6 normal {m}} else {configure_entry .menu3.config.f.x6 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x7 normal {m}} else {configure_entry .menu3.config.f.x7 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x8 normal {m}} else {configure_entry .menu3.config.f.x8 disabled {m}}
+}
+
+
+proc update_define_menu3 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_PROC_NUM
+ if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_PROC_NUM "$CONFIG_PROC_NUM" 1}
+}
+
+
+proc menu4 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 4}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 4]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Integer unit " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Integer unit "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 4; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu5 .menu5 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ int $w.config.f 4 0 "SPARC register windows" CONFIG_IU_NWINDOWS
+ bool $w.config.f 4 1 "SPARC V8 MUL/DIV instructions" CONFIG_IU_V8MULDIV
+ global tmpvar_3
+ minimenu $w.config.f 4 2 "Hardware multiplier latency" tmpvar_3 CONFIG_IU_MUL_LATENCY_2
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Hardware multiplier latency\""
+ $w.config.f.x2.x.menu add radiobutton -label "2-cycles" -variable tmpvar_3 -value "2-cycles" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "4-cycles" -variable tmpvar_3 -value "4-cycles" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "5-cycles" -variable tmpvar_3 -value "5-cycles" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 3
+ bool $w.config.f 4 3 "SPARC V8e SMAC/UMAC instructions " CONFIG_IU_MUL_MAC
+ bool $w.config.f 4 4 "Single-vector trapping" CONFIG_IU_SVT
+ int $w.config.f 4 5 "Load delay" CONFIG_IU_LDELAY
+ int $w.config.f 4 6 "Hardware watchpoints" CONFIG_IU_WATCHPOINTS
+ bool $w.config.f 4 7 "Enable power-down mode " CONFIG_PWD
+ hex $w.config.f 4 8 " Reset start address (addr\[31:12\]) " CONFIG_IU_RSTADDR
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu4 {} {
+ global CONFIG_LEON3
+ global CONFIG_IU_NWINDOWS
+ if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x0.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x0.l configure -state normal; } else {.menu4.config.f.x0.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x0.l configure -state disabled}
+ global CONFIG_IU_V8MULDIV
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu4.config.f.x1 normal {n l y}} else {configure_entry .menu4.config.f.x1 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {configure_entry .menu4.config.f.x2 normal {x l}} else {configure_entry .menu4.config.f.x2 disabled {x l}}
+ global CONFIG_IU_MUL_LATENCY_4
+ global CONFIG_IU_MUL_LATENCY_5
+ global CONFIG_IU_MUL_MAC
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {
+ configure_entry .menu4.config.f.x3 normal {n l y}} else {configure_entry .menu4.config.f.x3 disabled {y n l}}
+ global CONFIG_IU_SVT
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu4.config.f.x4 normal {n l y}} else {configure_entry .menu4.config.f.x4 disabled {y n l}}
+ global CONFIG_IU_LDELAY
+ if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x5.l configure -state normal; } else {.menu4.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x5.l configure -state disabled}
+ global CONFIG_IU_WATCHPOINTS
+ if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x6.l configure -state normal; } else {.menu4.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x6.l configure -state disabled}
+ global CONFIG_PWD
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu4.config.f.x7 normal {n l y}} else {configure_entry .menu4.config.f.x7 disabled {y n l}}
+ global CONFIG_IU_RSTADDR
+ if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x8.l configure -state normal; } else {.menu4.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x8.l configure -state disabled}
+}
+
+
+proc update_define_menu4 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_IU_NWINDOWS
+ if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_NWINDOWS "$CONFIG_IU_NWINDOWS" 8}
+ global CONFIG_IU_V8MULDIV
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV&15]} else {set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV|16]}
+ global tmpvar_3
+ global CONFIG_IU_MUL_LATENCY_2
+ if {$tmpvar_3 == "2-cycles"} then {set CONFIG_IU_MUL_LATENCY_2 1} else {set CONFIG_IU_MUL_LATENCY_2 0}
+ global CONFIG_IU_MUL_LATENCY_4
+ if {$tmpvar_3 == "4-cycles"} then {set CONFIG_IU_MUL_LATENCY_4 1} else {set CONFIG_IU_MUL_LATENCY_4 0}
+ global CONFIG_IU_MUL_LATENCY_5
+ if {$tmpvar_3 == "5-cycles"} then {set CONFIG_IU_MUL_LATENCY_5 1} else {set CONFIG_IU_MUL_LATENCY_5 0}
+ global CONFIG_IU_MUL_MAC
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {
+ set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC&15]} else {set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC|16]}
+ global CONFIG_IU_SVT
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_IU_SVT [expr $CONFIG_IU_SVT&15]} else {set CONFIG_IU_SVT [expr $CONFIG_IU_SVT|16]}
+ global CONFIG_IU_LDELAY
+ if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_LDELAY "$CONFIG_IU_LDELAY" 1}
+ global CONFIG_IU_WATCHPOINTS
+ if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_WATCHPOINTS "$CONFIG_IU_WATCHPOINTS" 0}
+ global CONFIG_PWD
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_PWD [expr $CONFIG_PWD&15]} else {set CONFIG_PWD [expr $CONFIG_PWD|16]}
+ global CONFIG_IU_RSTADDR
+ if {($CONFIG_LEON3 == 1)} then {validate_hex CONFIG_IU_RSTADDR "$CONFIG_IU_RSTADDR" 00000}
+}
+
+
+proc menu5 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 5}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 5]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Floating-point unit" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Floating-point unit"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 5; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu6 .menu6 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 5 0 "Enable FPU " CONFIG_FPU_ENABLE
+ global tmpvar_4
+ minimenu $w.config.f 5 1 "FPU core" tmpvar_4 CONFIG_FPU_GRFPU
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"FPU core\""
+ $w.config.f.x1.x.menu add radiobutton -label "GRFPU" -variable tmpvar_4 -value "GRFPU" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "GRFPU-LITE" -variable tmpvar_4 -value "GRFPU-LITE" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Meiko" -variable tmpvar_4 -value "Meiko" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 3
+ global tmpvar_5
+ minimenu $w.config.f 5 2 "GRFPU multiplier" tmpvar_5 CONFIG_FPU_GRFPU_INFMUL
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"GRFPU multiplier\""
+ $w.config.f.x2.x.menu add radiobutton -label "Inferred" -variable tmpvar_5 -value "Inferred" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "DW" -variable tmpvar_5 -value "DW" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "ModGen" -variable tmpvar_5 -value "ModGen" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "TechSpec" -variable tmpvar_5 -value "TechSpec" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 4
+ global tmpvar_6
+ minimenu $w.config.f 5 3 "GRFPU-LITE controller" tmpvar_6 CONFIG_FPU_GRFPC0
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"GRFPU-LITE controller\""
+ $w.config.f.x3.x.menu add radiobutton -label "Simple" -variable tmpvar_6 -value "Simple" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "Data-forwarding" -variable tmpvar_6 -value "Data-forwarding" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "Non-blocking" -variable tmpvar_6 -value "Non-blocking" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 3
+ bool $w.config.f 5 4 "Use VHDL netlist " CONFIG_FPU_NETLIST
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu5 {} {
+ global CONFIG_LEON3
+ global CONFIG_FPU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu5.config.f.x0 normal {n l y}} else {configure_entry .menu5.config.f.x0 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {configure_entry .menu5.config.f.x1 normal {x l}} else {configure_entry .menu5.config.f.x1 disabled {x l}}
+ global CONFIG_FPU_GRFPU
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then {configure_entry .menu5.config.f.x2 normal {x l}} else {configure_entry .menu5.config.f.x2 disabled {x l}}
+ global CONFIG_FPU_GRFPULITE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then {configure_entry .menu5.config.f.x3 normal {x l}} else {configure_entry .menu5.config.f.x3 disabled {x l}}
+ global CONFIG_FPU_NETLIST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {
+ configure_entry .menu5.config.f.x4 normal {n l y}} else {configure_entry .menu5.config.f.x4 disabled {y n l}}
+}
+
+
+proc update_define_menu5 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_FPU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE&15]} else {set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE|16]}
+ global tmpvar_4
+ global CONFIG_FPU_GRFPU
+ if {$tmpvar_4 == "GRFPU"} then {set CONFIG_FPU_GRFPU 1} else {set CONFIG_FPU_GRFPU 0}
+ global CONFIG_FPU_GRFPULITE
+ if {$tmpvar_4 == "GRFPU-LITE"} then {set CONFIG_FPU_GRFPULITE 1} else {set CONFIG_FPU_GRFPULITE 0}
+ global CONFIG_FPU_MEIKO
+ if {$tmpvar_4 == "Meiko"} then {set CONFIG_FPU_MEIKO 1} else {set CONFIG_FPU_MEIKO 0}
+ global tmpvar_5
+ global CONFIG_FPU_GRFPU_INFMUL
+ if {$tmpvar_5 == "Inferred"} then {set CONFIG_FPU_GRFPU_INFMUL 1} else {set CONFIG_FPU_GRFPU_INFMUL 0}
+ global CONFIG_FPU_GRFPU_DWMUL
+ if {$tmpvar_5 == "DW"} then {set CONFIG_FPU_GRFPU_DWMUL 1} else {set CONFIG_FPU_GRFPU_DWMUL 0}
+ global CONFIG_FPU_GRFPU_MODGEN
+ if {$tmpvar_5 == "ModGen"} then {set CONFIG_FPU_GRFPU_MODGEN 1} else {set CONFIG_FPU_GRFPU_MODGEN 0}
+ global CONFIG_FPU_GRFPU_TECHSPEC
+ if {$tmpvar_5 == "TechSpec"} then {set CONFIG_FPU_GRFPU_TECHSPEC 1} else {set CONFIG_FPU_GRFPU_TECHSPEC 0}
+ global tmpvar_6
+ global CONFIG_FPU_GRFPC0
+ if {$tmpvar_6 == "Simple"} then {set CONFIG_FPU_GRFPC0 1} else {set CONFIG_FPU_GRFPC0 0}
+ global CONFIG_FPU_GRFPC1
+ if {$tmpvar_6 == "Data-forwarding"} then {set CONFIG_FPU_GRFPC1 1} else {set CONFIG_FPU_GRFPC1 0}
+ global CONFIG_FPU_GRFPC2
+ if {$tmpvar_6 == "Non-blocking"} then {set CONFIG_FPU_GRFPC2 1} else {set CONFIG_FPU_GRFPC2 0}
+ global CONFIG_FPU_NETLIST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {
+ set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST&15]} else {set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST|16]}
+}
+
+
+proc menu6 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 6}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 6]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Cache system" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Cache system"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 6; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu7 .menu7 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 6 0 "Enable instruction cache " CONFIG_ICACHE_ENABLE
+ global tmpvar_7
+ minimenu $w.config.f 6 1 "Associativity (sets) " tmpvar_7 CONFIG_ICACHE_ASSO1
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Associativity (sets) \""
+ $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_7 -value "1" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_7 -value "2" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "3" -variable tmpvar_7 -value "3" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_7 -value "4" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 4
+ global tmpvar_8
+ minimenu $w.config.f 6 2 "Set size (kbytes/set)" tmpvar_8 CONFIG_ICACHE_SZ1
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\""
+ $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_8 -value "1" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_8 -value "2" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_8 -value "4" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_8 -value "8" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_8 -value "16" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_8 -value "32" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_8 -value "64" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "128" -variable tmpvar_8 -value "128" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "256" -variable tmpvar_8 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 9
+ global tmpvar_9
+ minimenu $w.config.f 6 3 "Line size (bytes/line)" tmpvar_9 CONFIG_ICACHE_LZ16
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\""
+ $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_9 -value "16" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_9 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 2
+ global tmpvar_10
+ minimenu $w.config.f 6 4 "Replacement alorithm" tmpvar_10 CONFIG_ICACHE_ALGORND
+ menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Replacement alorithm\""
+ $w.config.f.x4.x.menu add radiobutton -label "Random" -variable tmpvar_10 -value "Random" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "LRR" -variable tmpvar_10 -value "LRR" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "LRU" -variable tmpvar_10 -value "LRU" -command "update_active"
+ menusplit $w $w.config.f.x4.x.menu 3
+ bool $w.config.f 6 5 "Cache locking " CONFIG_ICACHE_LOCK
+ bool $w.config.f 6 6 "Enable local instruction RAM " CONFIG_ICACHE_LRAM
+ global tmpvar_11
+ minimenu $w.config.f 6 7 "Local data RAM size (kbytes)" tmpvar_11 CONFIG_ICACHE_LRAM_SZ1
+ menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\""
+ $w.config.f.x7.x.menu add radiobutton -label "1" -variable tmpvar_11 -value "1" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "2" -variable tmpvar_11 -value "2" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "4" -variable tmpvar_11 -value "4" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_11 -value "8" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_11 -value "16" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_11 -value "32" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_11 -value "64" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_11 -value "128" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_11 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x7.x.menu 9
+ hex $w.config.f 6 8 " Local instruction RAM start address (8 MSB) " CONFIG_ICACHE_LRSTART
+ bool $w.config.f 6 9 "Enable data cache " CONFIG_DCACHE_ENABLE
+ global tmpvar_12
+ minimenu $w.config.f 6 10 "Associativity (sets)" tmpvar_12 CONFIG_DCACHE_ASSO1
+ menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Associativity (sets)\""
+ $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_12 -value "1" -command "update_active"
+ $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_12 -value "2" -command "update_active"
+ $w.config.f.x10.x.menu add radiobutton -label "3" -variable tmpvar_12 -value "3" -command "update_active"
+ $w.config.f.x10.x.menu add radiobutton -label "4" -variable tmpvar_12 -value "4" -command "update_active"
+ menusplit $w $w.config.f.x10.x.menu 4
+ global tmpvar_13
+ minimenu $w.config.f 6 11 "Set size (kbytes/set)" tmpvar_13 CONFIG_DCACHE_SZ1
+ menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\""
+ $w.config.f.x11.x.menu add radiobutton -label "1" -variable tmpvar_13 -value "1" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "2" -variable tmpvar_13 -value "2" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "4" -variable tmpvar_13 -value "4" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "8" -variable tmpvar_13 -value "8" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "16" -variable tmpvar_13 -value "16" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "32" -variable tmpvar_13 -value "32" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "64" -variable tmpvar_13 -value "64" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "128" -variable tmpvar_13 -value "128" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_13 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x11.x.menu 9
+ global tmpvar_14
+ minimenu $w.config.f 6 12 "Line size (bytes/line)" tmpvar_14 CONFIG_DCACHE_LZ16
+ menu $w.config.f.x12.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\""
+ $w.config.f.x12.x.menu add radiobutton -label "16" -variable tmpvar_14 -value "16" -command "update_active"
+ $w.config.f.x12.x.menu add radiobutton -label "32" -variable tmpvar_14 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x12.x.menu 2
+ global tmpvar_15
+ minimenu $w.config.f 6 13 "Replacement alorithm" tmpvar_15 CONFIG_DCACHE_ALGORND
+ menu $w.config.f.x13.x.menu -tearoffcommand "menutitle \"Replacement alorithm\""
+ $w.config.f.x13.x.menu add radiobutton -label "Random" -variable tmpvar_15 -value "Random" -command "update_active"
+ $w.config.f.x13.x.menu add radiobutton -label "LRR" -variable tmpvar_15 -value "LRR" -command "update_active"
+ $w.config.f.x13.x.menu add radiobutton -label "LRU" -variable tmpvar_15 -value "LRU" -command "update_active"
+ menusplit $w $w.config.f.x13.x.menu 3
+ bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK
+ bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP
+ bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST
+ bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG
+ hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED
+ bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM
+ global tmpvar_16
+ minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_16 CONFIG_DCACHE_LRAM_SZ1
+ menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\""
+ $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_16 -value "1" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_16 -value "2" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_16 -value "4" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_16 -value "8" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_16 -value "16" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_16 -value "32" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_16 -value "64" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_16 -value "128" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_16 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x20.x.menu 9
+ hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu6 {} {
+ global CONFIG_LEON3
+ global CONFIG_ICACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu6.config.f.x0 normal {n l y}} else {configure_entry .menu6.config.f.x0 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x1 normal {x l}} else {configure_entry .menu6.config.f.x1 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x2 normal {x l}} else {configure_entry .menu6.config.f.x2 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x3 normal {x l}} else {configure_entry .menu6.config.f.x3 disabled {x l}}
+ global CONFIG_ICACHE_ASSO1
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x4 normal {x l}} else {configure_entry .menu6.config.f.x4 disabled {x l}}
+ global CONFIG_ICACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {
+ configure_entry .menu6.config.f.x5 normal {n l y}} else {configure_entry .menu6.config.f.x5 disabled {y n l}}
+ global CONFIG_MMU_ENABLE
+ global CONFIG_ICACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {
+ configure_entry .menu6.config.f.x6 normal {n l y}} else {configure_entry .menu6.config.f.x6 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x7 normal {x l}} else {configure_entry .menu6.config.f.x7 disabled {x l}}
+ global CONFIG_ICACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {.menu6.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x8.l configure -state normal; } else {.menu6.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x8.l configure -state disabled}
+ global CONFIG_DCACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu6.config.f.x9 normal {n l y}} else {configure_entry .menu6.config.f.x9 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x10 normal {x l}} else {configure_entry .menu6.config.f.x10 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x11 normal {x l}} else {configure_entry .menu6.config.f.x11 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x12 normal {x l}} else {configure_entry .menu6.config.f.x12 disabled {x l}}
+ global CONFIG_DCACHE_ASSO1
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x13 normal {x l}} else {configure_entry .menu6.config.f.x13 disabled {x l}}
+ global CONFIG_DCACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {
+ configure_entry .menu6.config.f.x14 normal {n l y}} else {configure_entry .menu6.config.f.x14 disabled {y n l}}
+ global CONFIG_DCACHE_SNOOP
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}}
+ global CONFIG_DCACHE_SNOOP_FAST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {
+ configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}}
+ global CONFIG_DCACHE_SNOOP_SEPTAG
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {
+ configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}}
+ global CONFIG_CACHE_FIXED
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled}
+ global CONFIG_DCACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {
+ configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}}
+ global CONFIG_DCACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled}
+}
+
+
+proc update_define_menu6 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_ICACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE&15]} else {set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE|16]}
+ global tmpvar_7
+ global CONFIG_ICACHE_ASSO1
+ if {$tmpvar_7 == "1"} then {set CONFIG_ICACHE_ASSO1 1} else {set CONFIG_ICACHE_ASSO1 0}
+ global CONFIG_ICACHE_ASSO2
+ if {$tmpvar_7 == "2"} then {set CONFIG_ICACHE_ASSO2 1} else {set CONFIG_ICACHE_ASSO2 0}
+ global CONFIG_ICACHE_ASSO3
+ if {$tmpvar_7 == "3"} then {set CONFIG_ICACHE_ASSO3 1} else {set CONFIG_ICACHE_ASSO3 0}
+ global CONFIG_ICACHE_ASSO4
+ if {$tmpvar_7 == "4"} then {set CONFIG_ICACHE_ASSO4 1} else {set CONFIG_ICACHE_ASSO4 0}
+ global tmpvar_8
+ global CONFIG_ICACHE_SZ1
+ if {$tmpvar_8 == "1"} then {set CONFIG_ICACHE_SZ1 1} else {set CONFIG_ICACHE_SZ1 0}
+ global CONFIG_ICACHE_SZ2
+ if {$tmpvar_8 == "2"} then {set CONFIG_ICACHE_SZ2 1} else {set CONFIG_ICACHE_SZ2 0}
+ global CONFIG_ICACHE_SZ4
+ if {$tmpvar_8 == "4"} then {set CONFIG_ICACHE_SZ4 1} else {set CONFIG_ICACHE_SZ4 0}
+ global CONFIG_ICACHE_SZ8
+ if {$tmpvar_8 == "8"} then {set CONFIG_ICACHE_SZ8 1} else {set CONFIG_ICACHE_SZ8 0}
+ global CONFIG_ICACHE_SZ16
+ if {$tmpvar_8 == "16"} then {set CONFIG_ICACHE_SZ16 1} else {set CONFIG_ICACHE_SZ16 0}
+ global CONFIG_ICACHE_SZ32
+ if {$tmpvar_8 == "32"} then {set CONFIG_ICACHE_SZ32 1} else {set CONFIG_ICACHE_SZ32 0}
+ global CONFIG_ICACHE_SZ64
+ if {$tmpvar_8 == "64"} then {set CONFIG_ICACHE_SZ64 1} else {set CONFIG_ICACHE_SZ64 0}
+ global CONFIG_ICACHE_SZ128
+ if {$tmpvar_8 == "128"} then {set CONFIG_ICACHE_SZ128 1} else {set CONFIG_ICACHE_SZ128 0}
+ global CONFIG_ICACHE_SZ256
+ if {$tmpvar_8 == "256"} then {set CONFIG_ICACHE_SZ256 1} else {set CONFIG_ICACHE_SZ256 0}
+ global tmpvar_9
+ global CONFIG_ICACHE_LZ16
+ if {$tmpvar_9 == "16"} then {set CONFIG_ICACHE_LZ16 1} else {set CONFIG_ICACHE_LZ16 0}
+ global CONFIG_ICACHE_LZ32
+ if {$tmpvar_9 == "32"} then {set CONFIG_ICACHE_LZ32 1} else {set CONFIG_ICACHE_LZ32 0}
+ global tmpvar_10
+ global CONFIG_ICACHE_ALGORND
+ if {$tmpvar_10 == "Random"} then {set CONFIG_ICACHE_ALGORND 1} else {set CONFIG_ICACHE_ALGORND 0}
+ global CONFIG_ICACHE_ALGOLRR
+ if {$tmpvar_10 == "LRR"} then {set CONFIG_ICACHE_ALGOLRR 1} else {set CONFIG_ICACHE_ALGOLRR 0}
+ global CONFIG_ICACHE_ALGOLRU
+ if {$tmpvar_10 == "LRU"} then {set CONFIG_ICACHE_ALGOLRU 1} else {set CONFIG_ICACHE_ALGOLRU 0}
+ global CONFIG_ICACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {
+ set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK&15]} else {set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK|16]}
+ global CONFIG_MMU_ENABLE
+ global CONFIG_ICACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {
+ set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM&15]} else {set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM|16]}
+ global tmpvar_11
+ global CONFIG_ICACHE_LRAM_SZ1
+ if {$tmpvar_11 == "1"} then {set CONFIG_ICACHE_LRAM_SZ1 1} else {set CONFIG_ICACHE_LRAM_SZ1 0}
+ global CONFIG_ICACHE_LRAM_SZ2
+ if {$tmpvar_11 == "2"} then {set CONFIG_ICACHE_LRAM_SZ2 1} else {set CONFIG_ICACHE_LRAM_SZ2 0}
+ global CONFIG_ICACHE_LRAM_SZ4
+ if {$tmpvar_11 == "4"} then {set CONFIG_ICACHE_LRAM_SZ4 1} else {set CONFIG_ICACHE_LRAM_SZ4 0}
+ global CONFIG_ICACHE_LRAM_SZ8
+ if {$tmpvar_11 == "8"} then {set CONFIG_ICACHE_LRAM_SZ8 1} else {set CONFIG_ICACHE_LRAM_SZ8 0}
+ global CONFIG_ICACHE_LRAM_SZ16
+ if {$tmpvar_11 == "16"} then {set CONFIG_ICACHE_LRAM_SZ16 1} else {set CONFIG_ICACHE_LRAM_SZ16 0}
+ global CONFIG_ICACHE_LRAM_SZ32
+ if {$tmpvar_11 == "32"} then {set CONFIG_ICACHE_LRAM_SZ32 1} else {set CONFIG_ICACHE_LRAM_SZ32 0}
+ global CONFIG_ICACHE_LRAM_SZ64
+ if {$tmpvar_11 == "64"} then {set CONFIG_ICACHE_LRAM_SZ64 1} else {set CONFIG_ICACHE_LRAM_SZ64 0}
+ global CONFIG_ICACHE_LRAM_SZ128
+ if {$tmpvar_11 == "128"} then {set CONFIG_ICACHE_LRAM_SZ128 1} else {set CONFIG_ICACHE_LRAM_SZ128 0}
+ global CONFIG_ICACHE_LRAM_SZ256
+ if {$tmpvar_11 == "256"} then {set CONFIG_ICACHE_LRAM_SZ256 1} else {set CONFIG_ICACHE_LRAM_SZ256 0}
+ global CONFIG_ICACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {validate_hex CONFIG_ICACHE_LRSTART "$CONFIG_ICACHE_LRSTART" 8e}
+ global CONFIG_DCACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE&15]} else {set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE|16]}
+ global tmpvar_12
+ global CONFIG_DCACHE_ASSO1
+ if {$tmpvar_12 == "1"} then {set CONFIG_DCACHE_ASSO1 1} else {set CONFIG_DCACHE_ASSO1 0}
+ global CONFIG_DCACHE_ASSO2
+ if {$tmpvar_12 == "2"} then {set CONFIG_DCACHE_ASSO2 1} else {set CONFIG_DCACHE_ASSO2 0}
+ global CONFIG_DCACHE_ASSO3
+ if {$tmpvar_12 == "3"} then {set CONFIG_DCACHE_ASSO3 1} else {set CONFIG_DCACHE_ASSO3 0}
+ global CONFIG_DCACHE_ASSO4
+ if {$tmpvar_12 == "4"} then {set CONFIG_DCACHE_ASSO4 1} else {set CONFIG_DCACHE_ASSO4 0}
+ global tmpvar_13
+ global CONFIG_DCACHE_SZ1
+ if {$tmpvar_13 == "1"} then {set CONFIG_DCACHE_SZ1 1} else {set CONFIG_DCACHE_SZ1 0}
+ global CONFIG_DCACHE_SZ2
+ if {$tmpvar_13 == "2"} then {set CONFIG_DCACHE_SZ2 1} else {set CONFIG_DCACHE_SZ2 0}
+ global CONFIG_DCACHE_SZ4
+ if {$tmpvar_13 == "4"} then {set CONFIG_DCACHE_SZ4 1} else {set CONFIG_DCACHE_SZ4 0}
+ global CONFIG_DCACHE_SZ8
+ if {$tmpvar_13 == "8"} then {set CONFIG_DCACHE_SZ8 1} else {set CONFIG_DCACHE_SZ8 0}
+ global CONFIG_DCACHE_SZ16
+ if {$tmpvar_13 == "16"} then {set CONFIG_DCACHE_SZ16 1} else {set CONFIG_DCACHE_SZ16 0}
+ global CONFIG_DCACHE_SZ32
+ if {$tmpvar_13 == "32"} then {set CONFIG_DCACHE_SZ32 1} else {set CONFIG_DCACHE_SZ32 0}
+ global CONFIG_DCACHE_SZ64
+ if {$tmpvar_13 == "64"} then {set CONFIG_DCACHE_SZ64 1} else {set CONFIG_DCACHE_SZ64 0}
+ global CONFIG_DCACHE_SZ128
+ if {$tmpvar_13 == "128"} then {set CONFIG_DCACHE_SZ128 1} else {set CONFIG_DCACHE_SZ128 0}
+ global CONFIG_DCACHE_SZ256
+ if {$tmpvar_13 == "256"} then {set CONFIG_DCACHE_SZ256 1} else {set CONFIG_DCACHE_SZ256 0}
+ global tmpvar_14
+ global CONFIG_DCACHE_LZ16
+ if {$tmpvar_14 == "16"} then {set CONFIG_DCACHE_LZ16 1} else {set CONFIG_DCACHE_LZ16 0}
+ global CONFIG_DCACHE_LZ32
+ if {$tmpvar_14 == "32"} then {set CONFIG_DCACHE_LZ32 1} else {set CONFIG_DCACHE_LZ32 0}
+ global tmpvar_15
+ global CONFIG_DCACHE_ALGORND
+ if {$tmpvar_15 == "Random"} then {set CONFIG_DCACHE_ALGORND 1} else {set CONFIG_DCACHE_ALGORND 0}
+ global CONFIG_DCACHE_ALGOLRR
+ if {$tmpvar_15 == "LRR"} then {set CONFIG_DCACHE_ALGOLRR 1} else {set CONFIG_DCACHE_ALGOLRR 0}
+ global CONFIG_DCACHE_ALGOLRU
+ if {$tmpvar_15 == "LRU"} then {set CONFIG_DCACHE_ALGOLRU 1} else {set CONFIG_DCACHE_ALGOLRU 0}
+ global CONFIG_DCACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {
+ set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK&15]} else {set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK|16]}
+ global CONFIG_DCACHE_SNOOP
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]}
+ global CONFIG_DCACHE_SNOOP_FAST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {
+ set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]}
+ global CONFIG_DCACHE_SNOOP_SEPTAG
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {
+ set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]}
+ global CONFIG_CACHE_FIXED
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {validate_hex CONFIG_CACHE_FIXED "$CONFIG_CACHE_FIXED" 0}
+ global CONFIG_DCACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {
+ set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM&15]} else {set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM|16]}
+ global tmpvar_16
+ global CONFIG_DCACHE_LRAM_SZ1
+ if {$tmpvar_16 == "1"} then {set CONFIG_DCACHE_LRAM_SZ1 1} else {set CONFIG_DCACHE_LRAM_SZ1 0}
+ global CONFIG_DCACHE_LRAM_SZ2
+ if {$tmpvar_16 == "2"} then {set CONFIG_DCACHE_LRAM_SZ2 1} else {set CONFIG_DCACHE_LRAM_SZ2 0}
+ global CONFIG_DCACHE_LRAM_SZ4
+ if {$tmpvar_16 == "4"} then {set CONFIG_DCACHE_LRAM_SZ4 1} else {set CONFIG_DCACHE_LRAM_SZ4 0}
+ global CONFIG_DCACHE_LRAM_SZ8
+ if {$tmpvar_16 == "8"} then {set CONFIG_DCACHE_LRAM_SZ8 1} else {set CONFIG_DCACHE_LRAM_SZ8 0}
+ global CONFIG_DCACHE_LRAM_SZ16
+ if {$tmpvar_16 == "16"} then {set CONFIG_DCACHE_LRAM_SZ16 1} else {set CONFIG_DCACHE_LRAM_SZ16 0}
+ global CONFIG_DCACHE_LRAM_SZ32
+ if {$tmpvar_16 == "32"} then {set CONFIG_DCACHE_LRAM_SZ32 1} else {set CONFIG_DCACHE_LRAM_SZ32 0}
+ global CONFIG_DCACHE_LRAM_SZ64
+ if {$tmpvar_16 == "64"} then {set CONFIG_DCACHE_LRAM_SZ64 1} else {set CONFIG_DCACHE_LRAM_SZ64 0}
+ global CONFIG_DCACHE_LRAM_SZ128
+ if {$tmpvar_16 == "128"} then {set CONFIG_DCACHE_LRAM_SZ128 1} else {set CONFIG_DCACHE_LRAM_SZ128 0}
+ global CONFIG_DCACHE_LRAM_SZ256
+ if {$tmpvar_16 == "256"} then {set CONFIG_DCACHE_LRAM_SZ256 1} else {set CONFIG_DCACHE_LRAM_SZ256 0}
+ global CONFIG_DCACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {validate_hex CONFIG_DCACHE_LRSTART "$CONFIG_DCACHE_LRSTART" 8f}
+}
+
+
+proc menu7 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 7}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 7]]
+ message $w.m -width 400 -aspect 300 -text \
+ "MMU" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "MMU"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 7; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu8 .menu8 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 7 0 "Enable MMU " CONFIG_MMU_ENABLE
+ global tmpvar_17
+ minimenu $w.config.f 7 1 "MMU type " tmpvar_17 CONFIG_MMU_COMBINED
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"MMU type \""
+ $w.config.f.x1.x.menu add radiobutton -label "combined" -variable tmpvar_17 -value "combined" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "split" -variable tmpvar_17 -value "split" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 2
+ global tmpvar_18
+ minimenu $w.config.f 7 2 "TLB replacement sheme " tmpvar_18 CONFIG_MMU_REPARRAY
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"TLB replacement sheme \""
+ $w.config.f.x2.x.menu add radiobutton -label "LRU" -variable tmpvar_18 -value "LRU" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "Increment" -variable tmpvar_18 -value "Increment" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 2
+ global tmpvar_19
+ minimenu $w.config.f 7 3 "Instruction (or combined) TLB entries" tmpvar_19 CONFIG_MMU_I2
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Instruction (or combined) TLB entries\""
+ $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 5
+ global tmpvar_20
+ minimenu $w.config.f 7 4 "Data TLB entries" tmpvar_20 CONFIG_MMU_D2
+ menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Data TLB entries\""
+ $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_20 -value "2" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_20 -value "4" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_20 -value "8" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_20 -value "16" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_20 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x4.x.menu 5
+ bool $w.config.f 7 5 "Fast writebuffer " CONFIG_MMU_FASTWB
+ global tmpvar_21
+ minimenu $w.config.f 7 6 "MMU page size" tmpvar_21 CONFIG_MMU_PAGE_4K
+ menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"MMU page size\""
+ $w.config.f.x6.x.menu add radiobutton -label "4K" -variable tmpvar_21 -value "4K" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "8K" -variable tmpvar_21 -value "8K" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "16K" -variable tmpvar_21 -value "16K" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "32K" -variable tmpvar_21 -value "32K" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "Programmable" -variable tmpvar_21 -value "Programmable" -command "update_active"
+ menusplit $w $w.config.f.x6.x.menu 5
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu7 {} {
+ global CONFIG_LEON3
+ global CONFIG_MMU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu7.config.f.x0 normal {n l y}} else {configure_entry .menu7.config.f.x0 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x1 normal {x l}} else {configure_entry .menu7.config.f.x1 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x2 normal {x l}} else {configure_entry .menu7.config.f.x2 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x3 normal {x l}} else {configure_entry .menu7.config.f.x3 disabled {x l}}
+ global CONFIG_MMU_SPLIT
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {configure_entry .menu7.config.f.x4 normal {x l}} else {configure_entry .menu7.config.f.x4 disabled {x l}}
+ global CONFIG_MMU_FASTWB
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {
+ configure_entry .menu7.config.f.x5 normal {n l y}} else {configure_entry .menu7.config.f.x5 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x6 normal {x l}} else {configure_entry .menu7.config.f.x6 disabled {x l}}
+}
+
+
+proc update_define_menu7 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_MMU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE&15]} else {set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE|16]}
+ global tmpvar_17
+ global CONFIG_MMU_COMBINED
+ if {$tmpvar_17 == "combined"} then {set CONFIG_MMU_COMBINED 1} else {set CONFIG_MMU_COMBINED 0}
+ global CONFIG_MMU_SPLIT
+ if {$tmpvar_17 == "split"} then {set CONFIG_MMU_SPLIT 1} else {set CONFIG_MMU_SPLIT 0}
+ global tmpvar_18
+ global CONFIG_MMU_REPARRAY
+ if {$tmpvar_18 == "LRU"} then {set CONFIG_MMU_REPARRAY 1} else {set CONFIG_MMU_REPARRAY 0}
+ global CONFIG_MMU_REPINCREMENT
+ if {$tmpvar_18 == "Increment"} then {set CONFIG_MMU_REPINCREMENT 1} else {set CONFIG_MMU_REPINCREMENT 0}
+ global tmpvar_19
+ global CONFIG_MMU_I2
+ if {$tmpvar_19 == "2"} then {set CONFIG_MMU_I2 1} else {set CONFIG_MMU_I2 0}
+ global CONFIG_MMU_I4
+ if {$tmpvar_19 == "4"} then {set CONFIG_MMU_I4 1} else {set CONFIG_MMU_I4 0}
+ global CONFIG_MMU_I8
+ if {$tmpvar_19 == "8"} then {set CONFIG_MMU_I8 1} else {set CONFIG_MMU_I8 0}
+ global CONFIG_MMU_I16
+ if {$tmpvar_19 == "16"} then {set CONFIG_MMU_I16 1} else {set CONFIG_MMU_I16 0}
+ global CONFIG_MMU_I32
+ if {$tmpvar_19 == "32"} then {set CONFIG_MMU_I32 1} else {set CONFIG_MMU_I32 0}
+ global tmpvar_20
+ global CONFIG_MMU_D2
+ if {$tmpvar_20 == "2"} then {set CONFIG_MMU_D2 1} else {set CONFIG_MMU_D2 0}
+ global CONFIG_MMU_D4
+ if {$tmpvar_20 == "4"} then {set CONFIG_MMU_D4 1} else {set CONFIG_MMU_D4 0}
+ global CONFIG_MMU_D8
+ if {$tmpvar_20 == "8"} then {set CONFIG_MMU_D8 1} else {set CONFIG_MMU_D8 0}
+ global CONFIG_MMU_D16
+ if {$tmpvar_20 == "16"} then {set CONFIG_MMU_D16 1} else {set CONFIG_MMU_D16 0}
+ global CONFIG_MMU_D32
+ if {$tmpvar_20 == "32"} then {set CONFIG_MMU_D32 1} else {set CONFIG_MMU_D32 0}
+ global CONFIG_MMU_FASTWB
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {
+ set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB&15]} else {set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB|16]}
+ global tmpvar_21
+ global CONFIG_MMU_PAGE_4K
+ if {$tmpvar_21 == "4K"} then {set CONFIG_MMU_PAGE_4K 1} else {set CONFIG_MMU_PAGE_4K 0}
+ global CONFIG_MMU_PAGE_8K
+ if {$tmpvar_21 == "8K"} then {set CONFIG_MMU_PAGE_8K 1} else {set CONFIG_MMU_PAGE_8K 0}
+ global CONFIG_MMU_PAGE_16K
+ if {$tmpvar_21 == "16K"} then {set CONFIG_MMU_PAGE_16K 1} else {set CONFIG_MMU_PAGE_16K 0}
+ global CONFIG_MMU_PAGE_32K
+ if {$tmpvar_21 == "32K"} then {set CONFIG_MMU_PAGE_32K 1} else {set CONFIG_MMU_PAGE_32K 0}
+ global CONFIG_MMU_PAGE_PROG
+ if {$tmpvar_21 == "Programmable"} then {set CONFIG_MMU_PAGE_PROG 1} else {set CONFIG_MMU_PAGE_PROG 0}
+}
+
+
+proc menu8 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 8}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 8]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Debug Support Unit " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Debug Support Unit "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 8; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu9 .menu9 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 8 0 "Enable LEON3 Debug support unit " CONFIG_DSU_ENABLE
+ bool $w.config.f 8 1 "Instruction trace buffer" CONFIG_DSU_ITRACE
+ global tmpvar_22
+ minimenu $w.config.f 8 2 "Instruction trace buffer size (kbytes)" tmpvar_22 CONFIG_DSU_ITRACESZ1
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Instruction trace buffer size (kbytes)\""
+ $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_22 -value "1" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_22 -value "2" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_22 -value "4" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_22 -value "8" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_22 -value "16" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 5
+ bool $w.config.f 8 3 "AHB trace buffer" CONFIG_DSU_ATRACE
+ global tmpvar_23
+ minimenu $w.config.f 8 4 "AHB trace buffer size (kbytes)" tmpvar_23 CONFIG_DSU_ATRACESZ1
+ menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB trace buffer size (kbytes)\""
+ $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_23 -value "1" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_23 -value "2" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_23 -value "4" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_23 -value "8" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_23 -value "16" -command "update_active"
+ menusplit $w $w.config.f.x4.x.menu 5
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu8 {} {
+ global CONFIG_LEON3
+ global CONFIG_DSU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu8.config.f.x0 normal {n l y}} else {configure_entry .menu8.config.f.x0 disabled {y n l}}
+ global CONFIG_DSU_ITRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {
+ configure_entry .menu8.config.f.x1 normal {n l y}} else {configure_entry .menu8.config.f.x1 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then {configure_entry .menu8.config.f.x2 normal {x l}} else {configure_entry .menu8.config.f.x2 disabled {x l}}
+ global CONFIG_DSU_ATRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {
+ configure_entry .menu8.config.f.x3 normal {n l y}} else {configure_entry .menu8.config.f.x3 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then {configure_entry .menu8.config.f.x4 normal {x l}} else {configure_entry .menu8.config.f.x4 disabled {x l}}
+}
+
+
+proc update_define_menu8 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_DSU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE&15]} else {set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE|16]}
+ global CONFIG_DSU_ITRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {
+ set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE&15]} else {set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE|16]}
+ global tmpvar_22
+ global CONFIG_DSU_ITRACESZ1
+ if {$tmpvar_22 == "1"} then {set CONFIG_DSU_ITRACESZ1 1} else {set CONFIG_DSU_ITRACESZ1 0}
+ global CONFIG_DSU_ITRACESZ2
+ if {$tmpvar_22 == "2"} then {set CONFIG_DSU_ITRACESZ2 1} else {set CONFIG_DSU_ITRACESZ2 0}
+ global CONFIG_DSU_ITRACESZ4
+ if {$tmpvar_22 == "4"} then {set CONFIG_DSU_ITRACESZ4 1} else {set CONFIG_DSU_ITRACESZ4 0}
+ global CONFIG_DSU_ITRACESZ8
+ if {$tmpvar_22 == "8"} then {set CONFIG_DSU_ITRACESZ8 1} else {set CONFIG_DSU_ITRACESZ8 0}
+ global CONFIG_DSU_ITRACESZ16
+ if {$tmpvar_22 == "16"} then {set CONFIG_DSU_ITRACESZ16 1} else {set CONFIG_DSU_ITRACESZ16 0}
+ global CONFIG_DSU_ATRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {
+ set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE&15]} else {set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE|16]}
+ global tmpvar_23
+ global CONFIG_DSU_ATRACESZ1
+ if {$tmpvar_23 == "1"} then {set CONFIG_DSU_ATRACESZ1 1} else {set CONFIG_DSU_ATRACESZ1 0}
+ global CONFIG_DSU_ATRACESZ2
+ if {$tmpvar_23 == "2"} then {set CONFIG_DSU_ATRACESZ2 1} else {set CONFIG_DSU_ATRACESZ2 0}
+ global CONFIG_DSU_ATRACESZ4
+ if {$tmpvar_23 == "4"} then {set CONFIG_DSU_ATRACESZ4 1} else {set CONFIG_DSU_ATRACESZ4 0}
+ global CONFIG_DSU_ATRACESZ8
+ if {$tmpvar_23 == "8"} then {set CONFIG_DSU_ATRACESZ8 1} else {set CONFIG_DSU_ATRACESZ8 0}
+ global CONFIG_DSU_ATRACESZ16
+ if {$tmpvar_23 == "16"} then {set CONFIG_DSU_ATRACESZ16 1} else {set CONFIG_DSU_ATRACESZ16 0}
+}
+
+
+proc menu9 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 9}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 9]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Fault-tolerance " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Fault-tolerance "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 9; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu10 .menu10 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu9 {} {
+}
+
+
+proc update_define_menu9 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+proc menu10 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 10}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 10]]
+ message $w.m -width 400 -aspect 300 -text \
+ "VHDL debug settings " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "VHDL debug settings "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 10; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 10; catch {destroy .menu3}; unregister_active 3; menu11 .menu11 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 10 0 "Processor disassembly to console " CONFIG_IU_DISAS
+ bool $w.config.f 10 1 "Processor disassembly in netlist " CONFIG_IU_DISAS_NET
+ bool $w.config.f 10 2 "32-bit program counters " CONFIG_DEBUG_PC32
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu10 {} {
+ global CONFIG_LEON3
+ global CONFIG_IU_DISAS
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu10.config.f.x0 normal {n l y}} else {configure_entry .menu10.config.f.x0 disabled {y n l}}
+ global CONFIG_IU_DISAS_NET
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {
+ configure_entry .menu10.config.f.x1 normal {n l y}} else {configure_entry .menu10.config.f.x1 disabled {y n l}}
+ global CONFIG_DEBUG_PC32
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu10.config.f.x2 normal {n l y}} else {configure_entry .menu10.config.f.x2 disabled {y n l}}
+}
+
+
+proc update_define_menu10 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_IU_DISAS
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS&15]} else {set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS|16]}
+ global CONFIG_IU_DISAS_NET
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {
+ set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET&15]} else {set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET|16]}
+ global CONFIG_DEBUG_PC32
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32&15]} else {set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32|16]}
+}
+
+
+menu_option menu11 11 "AMBA configuration"
+proc menu11 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 11}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 11]]
+ message $w.m -width 400 -aspect 300 -text \
+ "AMBA configuration" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "AMBA configuration"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 11; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu12 .menu12 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ int $w.config.f 11 0 "Default AHB master" CONFIG_AHB_DEFMST
+ bool $w.config.f 11 1 "Round-robin arbiter " CONFIG_AHB_RROBIN
+ bool $w.config.f 11 2 "AHB split-transaction support " CONFIG_AHB_SPLIT
+ hex $w.config.f 11 3 "I/O area start address (haddr\[31:20\]) " CONFIG_AHB_IOADDR
+ hex $w.config.f 11 4 "AHB/APB bridge address (haddr\[31:20\]) " CONFIG_APB_HADDR
+ bool $w.config.f 11 5 "Enable AMBA AHB monitor " CONFIG_AHB_MON
+ bool $w.config.f 11 6 "Report AHB errors " CONFIG_AHB_MONERR
+ bool $w.config.f 11 7 "Report AHB warings " CONFIG_AHB_MONWAR
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu11 {} {
+ global CONFIG_AHB_MON
+ global CONFIG_AHB_MONERR
+ if {($CONFIG_AHB_MON == 1)} then {
+ configure_entry .menu11.config.f.x6 normal {n l y}} else {configure_entry .menu11.config.f.x6 disabled {y n l}}
+ global CONFIG_AHB_MONWAR
+ if {($CONFIG_AHB_MON == 1)} then {
+ configure_entry .menu11.config.f.x7 normal {n l y}} else {configure_entry .menu11.config.f.x7 disabled {y n l}}
+}
+
+
+proc update_define_menu11 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_AHB_MON
+ global CONFIG_AHB_MONERR
+ if {($CONFIG_AHB_MON == 1)} then {
+ set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR&15]} else {set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR|16]}
+ global CONFIG_AHB_MONWAR
+ if {($CONFIG_AHB_MON == 1)} then {
+ set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR&15]} else {set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR|16]}
+}
+
+
+menu_option menu12 12 "Debug Link "
+proc menu12 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 12}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 12]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Debug Link " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Debug Link "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 12; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu13 .menu13 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 12 0 "Serial Debug Link (RS232) " CONFIG_DSU_UART
+ bool $w.config.f 12 1 "JTAG Debug Link" CONFIG_DSU_JTAG
+ bool $w.config.f 12 2 "Ethernet Debug Communication Link (EDCL)" CONFIG_DSU_ETH
+ global tmpvar_25
+ minimenu $w.config.f 12 3 "Ethernet/AHB bridge buffer size (kbytes)" tmpvar_25 CONFIG_DSU_ETHSZ1
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Ethernet/AHB bridge buffer size (kbytes)\""
+ $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_25 -value "1" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_25 -value "2" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_25 -value "4" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_25 -value "8" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_25 -value "16" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 5
+ hex $w.config.f 12 4 "MSB 16 bits of IP address (hex) " CONFIG_DSU_IPMSB
+ hex $w.config.f 12 5 "LSB 16 bits of IP address (hex) " CONFIG_DSU_IPLSB
+ hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB
+ hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB
+ bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu12 {} {
+ global CONFIG_GRETH_ENABLE
+ global CONFIG_DSU_ETH
+ if {($CONFIG_GRETH_ENABLE == 1)} then {
+ configure_entry .menu12.config.f.x2 normal {n l y}} else {configure_entry .menu12.config.f.x2 disabled {y n l}}
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {configure_entry .menu12.config.f.x3 normal {x l}} else {configure_entry .menu12.config.f.x3 disabled {x l}}
+ global CONFIG_DSU_IPMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x4.l configure -state normal; } else {.menu12.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x4.l configure -state disabled}
+ global CONFIG_DSU_IPLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x5.l configure -state normal; } else {.menu12.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x5.l configure -state disabled}
+ global CONFIG_DSU_ETHMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled}
+ global CONFIG_DSU_ETHLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled}
+ global CONFIG_GRETH_GIGA
+ global CONFIG_DSU_ETH_PROG
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {
+ configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}}
+}
+
+
+proc update_define_menu12 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_GRETH_ENABLE
+ global CONFIG_DSU_ETH
+ if {($CONFIG_GRETH_ENABLE == 1)} then {
+ set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH&15]} else {set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH|16]}
+ global tmpvar_25
+ global CONFIG_DSU_ETHSZ1
+ if {$tmpvar_25 == "1"} then {set CONFIG_DSU_ETHSZ1 1} else {set CONFIG_DSU_ETHSZ1 0}
+ global CONFIG_DSU_ETHSZ2
+ if {$tmpvar_25 == "2"} then {set CONFIG_DSU_ETHSZ2 1} else {set CONFIG_DSU_ETHSZ2 0}
+ global CONFIG_DSU_ETHSZ4
+ if {$tmpvar_25 == "4"} then {set CONFIG_DSU_ETHSZ4 1} else {set CONFIG_DSU_ETHSZ4 0}
+ global CONFIG_DSU_ETHSZ8
+ if {$tmpvar_25 == "8"} then {set CONFIG_DSU_ETHSZ8 1} else {set CONFIG_DSU_ETHSZ8 0}
+ global CONFIG_DSU_ETHSZ16
+ if {$tmpvar_25 == "16"} then {set CONFIG_DSU_ETHSZ16 1} else {set CONFIG_DSU_ETHSZ16 0}
+ global CONFIG_DSU_IPMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPMSB "$CONFIG_DSU_IPMSB" C0A8}
+ global CONFIG_DSU_IPLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPLSB "$CONFIG_DSU_IPLSB" 0033}
+ global CONFIG_DSU_ETHMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000}
+ global CONFIG_DSU_ETHLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000}
+ global CONFIG_GRETH_GIGA
+ global CONFIG_DSU_ETH_PROG
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {
+ set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]}
+}
+
+
+menu_option menu13 13 "Peripherals "
+proc menu13 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 13}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 13]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Peripherals " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Peripherals "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 13; break"
+ set nextscript "catch {focus $oldFocus}; menu14 .menu14 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ submenu $w.config.f 13 0 "Memory controllers " 14
+ submenu $w.config.f 13 1 "On-chip RAM/ROM " 19
+ submenu $w.config.f 13 2 "Ethernet " 20
+ submenu $w.config.f 13 3 "UARTs, timers and irq control " 21
+ submenu $w.config.f 13 4 "Serial interfaces; I2C, PS/2 and SPI " 22
+ submenu $w.config.f 13 5 "LCD and VGA DAC " 24
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu13 {} {
+}
+
+
+proc update_define_menu13 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+proc menu14 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 14}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 14]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Memory controllers " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Memory controllers "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 14; break"
+ set nextscript "catch {focus $oldFocus}; menu15 .menu15 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ submenu $w.config.f 14 0 "Leon2 memory controller " 15
+ submenu $w.config.f 14 1 "Synchronous SRAM controller " 16
+ submenu $w.config.f 14 2 "DDR266 SDRAM controller " 17
+ submenu $w.config.f 14 3 "SPI memory controller " 18
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu14 {} {
+}
+
+
+proc update_define_menu14 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+proc menu15 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu14}
+ catch {destroy $w; unregister_active 15}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 15]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Leon2 memory controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Leon2 memory controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 15; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu16 .menu16 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 15 0 "Enable Leon2 memory controller " CONFIG_MCTRL_LEON2
+ bool $w.config.f 15 1 "8-bit PROM/SRAM bus support " CONFIG_MCTRL_8BIT
+ bool $w.config.f 15 2 "16-bit PROM/SRAM bus support " CONFIG_MCTRL_16BIT
+ bool $w.config.f 15 3 "5th SRAM chip-select " CONFIG_MCTRL_5CS
+ bool $w.config.f 15 4 "SDRAM controller " CONFIG_MCTRL_SDRAM
+ bool $w.config.f 15 5 "Separate address and data buses" CONFIG_MCTRL_SDRAM_SEPBUS
+ bool $w.config.f 15 6 "64-bit SDRAM data bus" CONFIG_MCTRL_SDRAM_BUS64
+ bool $w.config.f 15 7 "Unsynchronized sdclock" CONFIG_MCTRL_SDRAM_INVCLK
+ bool $w.config.f 15 8 "Enable page burst operation " CONFIG_MCTRL_PAGE
+ bool $w.config.f 15 9 "Enable programmable page burst " CONFIG_MCTRL_PROGPAGE
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "}
+ set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu15 {} {
+ global CONFIG_MCTRL_LEON2
+ global CONFIG_MCTRL_8BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ configure_entry .menu15.config.f.x1 normal {n l y}} else {configure_entry .menu15.config.f.x1 disabled {y n l}}
+ global CONFIG_MCTRL_16BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ configure_entry .menu15.config.f.x2 normal {n l y}} else {configure_entry .menu15.config.f.x2 disabled {y n l}}
+ global CONFIG_MCTRL_5CS
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ configure_entry .menu15.config.f.x3 normal {n l y}} else {configure_entry .menu15.config.f.x3 disabled {y n l}}
+ global CONFIG_MCTRL_SDRAM
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ configure_entry .menu15.config.f.x4 normal {n l y}} else {configure_entry .menu15.config.f.x4 disabled {y n l}}
+ global CONFIG_MCTRL_SDRAM_SEPBUS
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {
+ configure_entry .menu15.config.f.x5 normal {n l y}} else {configure_entry .menu15.config.f.x5 disabled {y n l}}
+ global CONFIG_MCTRL_SDRAM_BUS64
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {
+ configure_entry .menu15.config.f.x6 normal {n l y}} else {configure_entry .menu15.config.f.x6 disabled {y n l}}
+ global CONFIG_MCTRL_SDRAM_INVCLK
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {
+ configure_entry .menu15.config.f.x7 normal {n l y}} else {configure_entry .menu15.config.f.x7 disabled {y n l}}
+ global CONFIG_MCTRL_PAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {
+ configure_entry .menu15.config.f.x8 normal {n l y}} else {configure_entry .menu15.config.f.x8 disabled {y n l}}
+ global CONFIG_MCTRL_PROGPAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {
+ configure_entry .menu15.config.f.x9 normal {n l y}} else {configure_entry .menu15.config.f.x9 disabled {y n l}}
+}
+
+
+proc update_define_menu15 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_MCTRL_LEON2
+ global CONFIG_MCTRL_8BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT&15]} else {set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT|16]}
+ global CONFIG_MCTRL_16BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT&15]} else {set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT|16]}
+ global CONFIG_MCTRL_5CS
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS&15]} else {set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS|16]}
+ global CONFIG_MCTRL_SDRAM
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM&15]} else {set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM|16]}
+ global CONFIG_MCTRL_SDRAM_SEPBUS
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {
+ set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS&15]} else {set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS|16]}
+ global CONFIG_MCTRL_SDRAM_BUS64
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {
+ set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64&15]} else {set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64|16]}
+ global CONFIG_MCTRL_SDRAM_INVCLK
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {
+ set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK&15]} else {set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK|16]}
+ global CONFIG_MCTRL_PAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {
+ set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE&15]} else {set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE|16]}
+ global CONFIG_MCTRL_PROGPAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {
+ set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE&15]} else {set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE|16]}
+}
+
+
+proc menu16 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu14}
+ catch {destroy $w; unregister_active 16}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 16]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Synchronous SRAM controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Synchronous SRAM controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 16; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu17 .menu17 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 16 0 "Enable Synchronous SRAM controller " CONFIG_SSCTRL
+ bool $w.config.f 16 1 "Enable 16-bit PROM support " CONFIG_SSCTRL_PROM16
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "}
+ set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu16 {} {
+ global CONFIG_SSCTRL
+ global CONFIG_SSCTRL_PROM16
+ if {($CONFIG_SSCTRL == 1)} then {
+ configure_entry .menu16.config.f.x1 normal {n l y}} else {configure_entry .menu16.config.f.x1 disabled {y n l}}
+}
+
+
+proc update_define_menu16 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_SSCTRL
+ global CONFIG_SSCTRL_PROM16
+ if {($CONFIG_SSCTRL == 1)} then {
+ set CONFIG_SSCTRL_PROM16 [expr $CONFIG_SSCTRL_PROM16&15]} else {set CONFIG_SSCTRL_PROM16 [expr $CONFIG_SSCTRL_PROM16|16]}
+}
+
+
+proc menu17 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu14}
+ catch {destroy $w; unregister_active 17}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 17]]
+ message $w.m -width 400 -aspect 300 -text \
+ "DDR266 SDRAM controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "DDR266 SDRAM controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 17; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu18 .menu18 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 17 0 "Enable DDR266 SDRAM controller " CONFIG_DDRSP
+ bool $w.config.f 17 1 "Enable power-on initialization " CONFIG_DDRSP_INIT
+ int $w.config.f 17 2 "Memory frequency (MHz) " CONFIG_DDRSP_FREQ
+ int $w.config.f 17 3 "Column address bits (9 - 12) " CONFIG_DDRSP_COL
+ int $w.config.f 17 4 "Chip select bank size (Mbyte) " CONFIG_DDRSP_MBYTE
+ int $w.config.f 17 5 "Read clock phase shift " CONFIG_DDRSP_RSKEW
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "}
+ set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu17 {} {
+ global CONFIG_DDRSP
+ global CONFIG_DDRSP_INIT
+ if {($CONFIG_DDRSP == 1)} then {
+ configure_entry .menu17.config.f.x1 normal {n l y}} else {configure_entry .menu17.config.f.x1 disabled {y n l}}
+ global CONFIG_DDRSP_FREQ
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {.menu17.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu17.config.f.x2.l configure -state normal; } else {.menu17.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu17.config.f.x2.l configure -state disabled}
+ global CONFIG_DDRSP_COL
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {.menu17.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu17.config.f.x3.l configure -state normal; } else {.menu17.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu17.config.f.x3.l configure -state disabled}
+ global CONFIG_DDRSP_MBYTE
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {.menu17.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu17.config.f.x4.l configure -state normal; } else {.menu17.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu17.config.f.x4.l configure -state disabled}
+ global CONFIG_SYN_VIRTEX2
+ global CONFIG_SYN_VIRTEX4
+ global CONFIG_SYN_SPARTAN3
+ global CONFIG_SYN_VIRTEX5
+ global CONFIG_SYN_SPARTAN3E
+ global CONFIG_SYN_CYCLONEIII
+ global CONFIG_DDRSP_RSKEW
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_SYN_VIRTEX2 == 1 || $CONFIG_SYN_VIRTEX4 == 1 || $CONFIG_SYN_SPARTAN3 == 1 || $CONFIG_SYN_VIRTEX5 == 1 || $CONFIG_SYN_SPARTAN3E == 1 || $CONFIG_SYN_CYCLONEIII == 1)} then {.menu17.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu17.config.f.x5.l configure -state normal; } else {.menu17.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu17.config.f.x5.l configure -state disabled}
+}
+
+
+proc update_define_menu17 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_DDRSP
+ global CONFIG_DDRSP_INIT
+ if {($CONFIG_DDRSP == 1)} then {
+ set CONFIG_DDRSP_INIT [expr $CONFIG_DDRSP_INIT&15]} else {set CONFIG_DDRSP_INIT [expr $CONFIG_DDRSP_INIT|16]}
+ global CONFIG_DDRSP_FREQ
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {validate_int CONFIG_DDRSP_FREQ "$CONFIG_DDRSP_FREQ" 100}
+ global CONFIG_DDRSP_COL
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {validate_int CONFIG_DDRSP_COL "$CONFIG_DDRSP_COL" 9}
+ global CONFIG_DDRSP_MBYTE
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {validate_int CONFIG_DDRSP_MBYTE "$CONFIG_DDRSP_MBYTE" 16}
+ global CONFIG_SYN_VIRTEX2
+ global CONFIG_SYN_VIRTEX4
+ global CONFIG_SYN_SPARTAN3
+ global CONFIG_SYN_VIRTEX5
+ global CONFIG_SYN_SPARTAN3E
+ global CONFIG_SYN_CYCLONEIII
+ global CONFIG_DDRSP_RSKEW
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_SYN_VIRTEX2 == 1 || $CONFIG_SYN_VIRTEX4 == 1 || $CONFIG_SYN_SPARTAN3 == 1 || $CONFIG_SYN_VIRTEX5 == 1 || $CONFIG_SYN_SPARTAN3E == 1 || $CONFIG_SYN_CYCLONEIII == 1)} then {validate_int CONFIG_DDRSP_RSKEW "$CONFIG_DDRSP_RSKEW" 0}
+}
+
+
+proc menu18 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu14}
+ catch {destroy $w; unregister_active 18}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 18]]
+ message $w.m -width 400 -aspect 300 -text \
+ "SPI memory controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "SPI memory controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 18; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 18; catch {destroy .menu14}; unregister_active 14; menu19 .menu19 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 18 0 "Enable SPI memory controller " CONFIG_SPIMCTRL
+ bool $w.config.f 18 1 "Enable SD card support " CONFIG_SPIMCTRL_SDCARD
+ hex $w.config.f 18 2 "Read instruction " CONFIG_SPIMCTRL_READCMD
+ bool $w.config.f 18 3 "Read instruction requires dummy byte " CONFIG_SPIMCTRL_DUMMYBYTE
+ bool $w.config.f 18 4 "Enable dual output for reads " CONFIG_SPIMCTRL_DUALOUTPUT
+ int $w.config.f 18 5 "Clock divisor for device clock" CONFIG_SPIMCTRL_SCALER
+ int $w.config.f 18 6 "Clock divisor for alt. device clock" CONFIG_SPIMCTRL_ASCALER
+ int $w.config.f 18 7 "Number of clock cycles to idle after power up " CONFIG_SPIMCTRL_PWRUPCNT
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "}
+ set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu18 {} {
+ global CONFIG_SPIMCTRL
+ global CONFIG_SPIMCTRL_SDCARD
+ if {($CONFIG_SPIMCTRL == 1)} then {
+ configure_entry .menu18.config.f.x1 normal {n l y}} else {configure_entry .menu18.config.f.x1 disabled {y n l}}
+ global CONFIG_SPIMCTRL_READCMD
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {.menu18.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x2.l configure -state normal; } else {.menu18.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x2.l configure -state disabled}
+ global CONFIG_SPIMCTRL_DUMMYBYTE
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {
+ configure_entry .menu18.config.f.x3 normal {n l y}} else {configure_entry .menu18.config.f.x3 disabled {y n l}}
+ global CONFIG_SPIMCTRL_DUALOUTPUT
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {
+ configure_entry .menu18.config.f.x4 normal {n l y}} else {configure_entry .menu18.config.f.x4 disabled {y n l}}
+ global CONFIG_SPIMCTRL_SCALER
+ if {($CONFIG_SPIMCTRL == 1)} then {.menu18.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x5.l configure -state normal; } else {.menu18.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x5.l configure -state disabled}
+ global CONFIG_SPIMCTRL_ASCALER
+ if {($CONFIG_SPIMCTRL == 1)} then {.menu18.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x6.l configure -state normal; } else {.menu18.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x6.l configure -state disabled}
+ global CONFIG_SPIMCTRL_PWRUPCNT
+ if {($CONFIG_SPIMCTRL == 1)} then {.menu18.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x7.l configure -state normal; } else {.menu18.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x7.l configure -state disabled}
+}
+
+
+proc update_define_menu18 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_SPIMCTRL
+ global CONFIG_SPIMCTRL_SDCARD
+ if {($CONFIG_SPIMCTRL == 1)} then {
+ set CONFIG_SPIMCTRL_SDCARD [expr $CONFIG_SPIMCTRL_SDCARD&15]} else {set CONFIG_SPIMCTRL_SDCARD [expr $CONFIG_SPIMCTRL_SDCARD|16]}
+ global CONFIG_SPIMCTRL_READCMD
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {validate_hex CONFIG_SPIMCTRL_READCMD "$CONFIG_SPIMCTRL_READCMD" 0B}
+ global CONFIG_SPIMCTRL_DUMMYBYTE
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {
+ set CONFIG_SPIMCTRL_DUMMYBYTE [expr $CONFIG_SPIMCTRL_DUMMYBYTE&15]} else {set CONFIG_SPIMCTRL_DUMMYBYTE [expr $CONFIG_SPIMCTRL_DUMMYBYTE|16]}
+ global CONFIG_SPIMCTRL_DUALOUTPUT
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {
+ set CONFIG_SPIMCTRL_DUALOUTPUT [expr $CONFIG_SPIMCTRL_DUALOUTPUT&15]} else {set CONFIG_SPIMCTRL_DUALOUTPUT [expr $CONFIG_SPIMCTRL_DUALOUTPUT|16]}
+ global CONFIG_SPIMCTRL_SCALER
+ if {($CONFIG_SPIMCTRL == 1)} then {validate_int CONFIG_SPIMCTRL_SCALER "$CONFIG_SPIMCTRL_SCALER" 1}
+ global CONFIG_SPIMCTRL_ASCALER
+ if {($CONFIG_SPIMCTRL == 1)} then {validate_int CONFIG_SPIMCTRL_ASCALER "$CONFIG_SPIMCTRL_ASCALER" 8}
+ global CONFIG_SPIMCTRL_PWRUPCNT
+ if {($CONFIG_SPIMCTRL == 1)} then {validate_int CONFIG_SPIMCTRL_PWRUPCNT "$CONFIG_SPIMCTRL_PWRUPCNT" 0}
+}
+
+
+proc menu19 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 19}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 19]]
+ message $w.m -width 400 -aspect 300 -text \
+ "On-chip RAM/ROM " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "On-chip RAM/ROM "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 19; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu20 .menu20 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 19 0 "On-chip AHB ROM " CONFIG_AHBROM_ENABLE
+ hex $w.config.f 19 1 "ROM start address (haddr\[31:20\]) " CONFIG_AHBROM_START
+ bool $w.config.f 19 2 "Pipelined ROM access " CONFIG_AHBROM_PIPE
+ bool $w.config.f 19 3 "On-chip AHB RAM " CONFIG_AHBRAM_ENABLE
+ global tmpvar_26
+ minimenu $w.config.f 19 4 "AHB RAM size (Kbyte)" tmpvar_26 CONFIG_AHBRAM_SZ1
+ menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB RAM size (Kbyte)\""
+ $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_26 -value "1" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_26 -value "2" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_26 -value "4" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_26 -value "8" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_26 -value "16" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_26 -value "32" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "64" -variable tmpvar_26 -value "64" -command "update_active"
+ menusplit $w $w.config.f.x4.x.menu 7
+ hex $w.config.f 19 5 "RAM start address (haddr\[31:20\]) " CONFIG_AHBRAM_START
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu19 {} {
+ global CONFIG_AHBROM_ENABLE
+ global CONFIG_AHBROM_START
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {.menu19.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x1.l configure -state normal; } else {.menu19.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x1.l configure -state disabled}
+ global CONFIG_AHBROM_PIPE
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {
+ configure_entry .menu19.config.f.x2 normal {n l y}} else {configure_entry .menu19.config.f.x2 disabled {y n l}}
+ global CONFIG_AHBRAM_ENABLE
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {configure_entry .menu19.config.f.x4 normal {x l}} else {configure_entry .menu19.config.f.x4 disabled {x l}}
+ global CONFIG_AHBRAM_START
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {.menu19.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x5.l configure -state normal; } else {.menu19.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x5.l configure -state disabled}
+}
+
+
+proc update_define_menu19 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_AHBROM_ENABLE
+ global CONFIG_AHBROM_START
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {validate_hex CONFIG_AHBROM_START "$CONFIG_AHBROM_START" 000}
+ global CONFIG_AHBROM_PIPE
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {
+ set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE&15]} else {set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE|16]}
+ global tmpvar_26
+ global CONFIG_AHBRAM_SZ1
+ if {$tmpvar_26 == "1"} then {set CONFIG_AHBRAM_SZ1 1} else {set CONFIG_AHBRAM_SZ1 0}
+ global CONFIG_AHBRAM_SZ2
+ if {$tmpvar_26 == "2"} then {set CONFIG_AHBRAM_SZ2 1} else {set CONFIG_AHBRAM_SZ2 0}
+ global CONFIG_AHBRAM_SZ4
+ if {$tmpvar_26 == "4"} then {set CONFIG_AHBRAM_SZ4 1} else {set CONFIG_AHBRAM_SZ4 0}
+ global CONFIG_AHBRAM_SZ8
+ if {$tmpvar_26 == "8"} then {set CONFIG_AHBRAM_SZ8 1} else {set CONFIG_AHBRAM_SZ8 0}
+ global CONFIG_AHBRAM_SZ16
+ if {$tmpvar_26 == "16"} then {set CONFIG_AHBRAM_SZ16 1} else {set CONFIG_AHBRAM_SZ16 0}
+ global CONFIG_AHBRAM_SZ32
+ if {$tmpvar_26 == "32"} then {set CONFIG_AHBRAM_SZ32 1} else {set CONFIG_AHBRAM_SZ32 0}
+ global CONFIG_AHBRAM_SZ64
+ if {$tmpvar_26 == "64"} then {set CONFIG_AHBRAM_SZ64 1} else {set CONFIG_AHBRAM_SZ64 0}
+ global CONFIG_AHBRAM_ENABLE
+ global CONFIG_AHBRAM_START
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {validate_hex CONFIG_AHBRAM_START "$CONFIG_AHBRAM_START" A00}
+}
+
+
+proc menu20 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 20}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 20]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Ethernet " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Ethernet "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 20; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu21 .menu21 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 20 0 "Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH_ENABLE
+ bool $w.config.f 20 1 "Enable 1000 Mbit support " CONFIG_GRETH_GIGA
+ global tmpvar_27
+ minimenu $w.config.f 20 2 "AHB FIFO size (words) " tmpvar_27 CONFIG_GRETH_FIFO4
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB FIFO size (words) \""
+ $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_27 -value "4" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_27 -value "8" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_27 -value "16" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_27 -value "32" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_27 -value "64" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 5
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu20 {} {
+ global CONFIG_GRETH_ENABLE
+ global CONFIG_GRETH_GIGA
+ if {($CONFIG_GRETH_ENABLE == 1)} then {
+ configure_entry .menu20.config.f.x1 normal {n l y}} else {configure_entry .menu20.config.f.x1 disabled {y n l}}
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {configure_entry .menu20.config.f.x2 normal {x l}} else {configure_entry .menu20.config.f.x2 disabled {x l}}
+}
+
+
+proc update_define_menu20 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_GRETH_ENABLE
+ global CONFIG_GRETH_GIGA
+ if {($CONFIG_GRETH_ENABLE == 1)} then {
+ set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA&15]} else {set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA|16]}
+ global tmpvar_27
+ global CONFIG_GRETH_FIFO4
+ if {$tmpvar_27 == "4"} then {set CONFIG_GRETH_FIFO4 1} else {set CONFIG_GRETH_FIFO4 0}
+ global CONFIG_GRETH_FIFO8
+ if {$tmpvar_27 == "8"} then {set CONFIG_GRETH_FIFO8 1} else {set CONFIG_GRETH_FIFO8 0}
+ global CONFIG_GRETH_FIFO16
+ if {$tmpvar_27 == "16"} then {set CONFIG_GRETH_FIFO16 1} else {set CONFIG_GRETH_FIFO16 0}
+ global CONFIG_GRETH_FIFO32
+ if {$tmpvar_27 == "32"} then {set CONFIG_GRETH_FIFO32 1} else {set CONFIG_GRETH_FIFO32 0}
+ global CONFIG_GRETH_FIFO64
+ if {$tmpvar_27 == "64"} then {set CONFIG_GRETH_FIFO64 1} else {set CONFIG_GRETH_FIFO64 0}
+}
+
+
+proc menu21 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 21}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 21]]
+ message $w.m -width 400 -aspect 300 -text \
+ "UARTs, timers and irq control " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "UARTs, timers and irq control "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 21; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu22 .menu22 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 21 0 "Enable console UART " CONFIG_UART1_ENABLE
+ global tmpvar_28
+ minimenu $w.config.f 21 1 "UART1 FIFO depth" tmpvar_28 CONFIG_UA1_FIFO1
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"UART1 FIFO depth\""
+ $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_28 -value "1" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_28 -value "2" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_28 -value "4" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_28 -value "8" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_28 -value "16" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_28 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 6
+ bool $w.config.f 21 2 "Enable LEON3 interrupt controller " CONFIG_IRQ3_ENABLE
+ bool $w.config.f 21 3 "Enable secondary interrupts " CONFIG_IRQ3_SEC
+ int $w.config.f 21 4 "Secondary interrupt number (1 - 15) " CONFIG_IRQ3_NSEC
+ bool $w.config.f 21 5 "Enable Timer Unit " CONFIG_GPT_ENABLE
+ int $w.config.f 21 6 "Number of timers (1 - 7) " CONFIG_GPT_NTIM
+ int $w.config.f 21 7 "Scaler width (2 - 16) " CONFIG_GPT_SW
+ int $w.config.f 21 8 "Timer width (2 - 32) " CONFIG_GPT_TW
+ int $w.config.f 21 9 "Timer unit interrupt " CONFIG_GPT_IRQ
+ bool $w.config.f 21 10 "Separate interrupts " CONFIG_GPT_SEPIRQ
+ bool $w.config.f 21 11 "Watchdog enable " CONFIG_GPT_WDOGEN
+ hex $w.config.f 21 12 "Initial watchdog time-out value " CONFIG_GPT_WDOG
+ bool $w.config.f 21 13 "Enable generic GPIO port " CONFIG_GRGPIO_ENABLE
+ int $w.config.f 21 14 "GPIO width " CONFIG_GRGPIO_WIDTH
+ hex $w.config.f 21 15 "GPIO interrupt mask " CONFIG_GRGPIO_IMASK
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu21 {} {
+ global CONFIG_UART1_ENABLE
+ if {($CONFIG_UART1_ENABLE == 1)} then {configure_entry .menu21.config.f.x1 normal {x l}} else {configure_entry .menu21.config.f.x1 disabled {x l}}
+ global CONFIG_IRQ3_ENABLE
+ global CONFIG_IRQ3_SEC
+ if {($CONFIG_IRQ3_ENABLE == 1)} then {
+ configure_entry .menu21.config.f.x3 normal {n l y}} else {configure_entry .menu21.config.f.x3 disabled {y n l}}
+ global CONFIG_IRQ3_NSEC
+ if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {.menu21.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x4.l configure -state normal; } else {.menu21.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x4.l configure -state disabled}
+ global CONFIG_GPT_ENABLE
+ global CONFIG_GPT_NTIM
+ if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x6.l configure -state normal; } else {.menu21.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x6.l configure -state disabled}
+ global CONFIG_GPT_SW
+ if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x7.l configure -state normal; } else {.menu21.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x7.l configure -state disabled}
+ global CONFIG_GPT_TW
+ if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x8.l configure -state normal; } else {.menu21.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x8.l configure -state disabled}
+ global CONFIG_GPT_IRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x9.l configure -state normal; } else {.menu21.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x9.l configure -state disabled}
+ global CONFIG_GPT_SEPIRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {
+ configure_entry .menu21.config.f.x10 normal {n l y}} else {configure_entry .menu21.config.f.x10 disabled {y n l}}
+ global CONFIG_GPT_WDOGEN
+ if {($CONFIG_GPT_ENABLE == 1)} then {
+ configure_entry .menu21.config.f.x11 normal {n l y}} else {configure_entry .menu21.config.f.x11 disabled {y n l}}
+ global CONFIG_GPT_WDOG
+ if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {.menu21.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x12.l configure -state normal; } else {.menu21.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x12.l configure -state disabled}
+ global CONFIG_GRGPIO_ENABLE
+ global CONFIG_GRGPIO_WIDTH
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu21.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x14.l configure -state normal; } else {.menu21.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x14.l configure -state disabled}
+ global CONFIG_GRGPIO_IMASK
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu21.config.f.x15.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x15.l configure -state normal; } else {.menu21.config.f.x15.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x15.l configure -state disabled}
+}
+
+
+proc update_define_menu21 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global tmpvar_28
+ global CONFIG_UA1_FIFO1
+ if {$tmpvar_28 == "1"} then {set CONFIG_UA1_FIFO1 1} else {set CONFIG_UA1_FIFO1 0}
+ global CONFIG_UA1_FIFO2
+ if {$tmpvar_28 == "2"} then {set CONFIG_UA1_FIFO2 1} else {set CONFIG_UA1_FIFO2 0}
+ global CONFIG_UA1_FIFO4
+ if {$tmpvar_28 == "4"} then {set CONFIG_UA1_FIFO4 1} else {set CONFIG_UA1_FIFO4 0}
+ global CONFIG_UA1_FIFO8
+ if {$tmpvar_28 == "8"} then {set CONFIG_UA1_FIFO8 1} else {set CONFIG_UA1_FIFO8 0}
+ global CONFIG_UA1_FIFO16
+ if {$tmpvar_28 == "16"} then {set CONFIG_UA1_FIFO16 1} else {set CONFIG_UA1_FIFO16 0}
+ global CONFIG_UA1_FIFO32
+ if {$tmpvar_28 == "32"} then {set CONFIG_UA1_FIFO32 1} else {set CONFIG_UA1_FIFO32 0}
+ global CONFIG_IRQ3_ENABLE
+ global CONFIG_IRQ3_SEC
+ if {($CONFIG_IRQ3_ENABLE == 1)} then {
+ set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC&15]} else {set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC|16]}
+ global CONFIG_IRQ3_NSEC
+ if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {validate_int CONFIG_IRQ3_NSEC "$CONFIG_IRQ3_NSEC" 12}
+ global CONFIG_GPT_ENABLE
+ global CONFIG_GPT_NTIM
+ if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_NTIM "$CONFIG_GPT_NTIM" 2}
+ global CONFIG_GPT_SW
+ if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_SW "$CONFIG_GPT_SW" 8}
+ global CONFIG_GPT_TW
+ if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_TW "$CONFIG_GPT_TW" 32}
+ global CONFIG_GPT_IRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_IRQ "$CONFIG_GPT_IRQ" 8}
+ global CONFIG_GPT_SEPIRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {
+ set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ&15]} else {set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ|16]}
+ global CONFIG_GPT_WDOGEN
+ if {($CONFIG_GPT_ENABLE == 1)} then {
+ set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN&15]} else {set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN|16]}
+ global CONFIG_GPT_WDOG
+ if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {validate_hex CONFIG_GPT_WDOG "$CONFIG_GPT_WDOG" FFFF}
+ global CONFIG_GRGPIO_ENABLE
+ global CONFIG_GRGPIO_WIDTH
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_int CONFIG_GRGPIO_WIDTH "$CONFIG_GRGPIO_WIDTH" 8}
+ global CONFIG_GRGPIO_IMASK
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_hex CONFIG_GRGPIO_IMASK "$CONFIG_GRGPIO_IMASK" 0000}
+}
+
+
+proc menu22 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 22}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 22]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Serial interfaces; I2C, PS/2 and SPI " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Serial interfaces; I2C, PS/2 and SPI "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 22; break"
+ set nextscript "catch {focus $oldFocus}; menu23 .menu23 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 22 0 "Enable I2C master " CONFIG_I2C_ENABLE
+ bool $w.config.f 22 1 "Keyboard/mouse (PS2) interface " CONFIG_PS2_ENABLE
+ submenu $w.config.f 22 2 "SPI controller " 23
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu22 {} {
+}
+
+
+proc update_define_menu22 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+proc menu23 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu22}
+ catch {destroy $w; unregister_active 23}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 23]]
+ message $w.m -width 400 -aspect 300 -text \
+ "SPI controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "SPI controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 23; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 23; catch {destroy .menu22}; unregister_active 22; menu24 .menu24 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 23 0 "Enable SPI controller " CONFIG_SPICTRL_ENABLE
+ int $w.config.f 23 1 "Slave select lines " CONFIG_SPICTRL_SLVS
+ int $w.config.f 23 2 "FIFO depth (2^N) " CONFIG_SPICTRL_FIFO
+ bool $w.config.f 23 3 "Enable slave select registers" CONFIG_SPICTRL_SLVREG
+ bool $w.config.f 23 4 "Enable automatic slave select" CONFIG_SPICTRL_ASEL
+ bool $w.config.f 23 5 "Support automated transfers " CONFIG_SPICTRL_AM
+ bool $w.config.f 23 6 "Support open drain mode " CONFIG_SPICTRL_ODMODE
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu22] == 0} then {menu22 .menu22 "Serial interfaces; I2C, PS/2 and SPI "}
+ set winx [expr [winfo x .menu22]+30]; set winy [expr [winfo y .menu22]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu23 {} {
+ global CONFIG_SPICTRL_ENABLE
+ global CONFIG_SPICTRL_SLVS
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu23.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x1.l configure -state normal; } else {.menu23.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x1.l configure -state disabled}
+ global CONFIG_SPICTRL_FIFO
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu23.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x2.l configure -state normal; } else {.menu23.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x2.l configure -state disabled}
+ global CONFIG_SPICTRL_SLVREG
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {
+ configure_entry .menu23.config.f.x3 normal {n l y}} else {configure_entry .menu23.config.f.x3 disabled {y n l}}
+ global CONFIG_SPICTRL_ASEL
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {
+ configure_entry .menu23.config.f.x4 normal {n l y}} else {configure_entry .menu23.config.f.x4 disabled {y n l}}
+ global CONFIG_SPICTRL_AM
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {
+ configure_entry .menu23.config.f.x5 normal {n l y}} else {configure_entry .menu23.config.f.x5 disabled {y n l}}
+ global CONFIG_SPICTRL_ODMODE
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {
+ configure_entry .menu23.config.f.x6 normal {n l y}} else {configure_entry .menu23.config.f.x6 disabled {y n l}}
+}
+
+
+proc update_define_menu23 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_SPICTRL_ENABLE
+ global CONFIG_SPICTRL_SLVS
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {validate_int CONFIG_SPICTRL_SLVS "$CONFIG_SPICTRL_SLVS" 1}
+ global CONFIG_SPICTRL_FIFO
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {validate_int CONFIG_SPICTRL_FIFO "$CONFIG_SPICTRL_FIFO" 1}
+ global CONFIG_SPICTRL_SLVREG
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {
+ set CONFIG_SPICTRL_SLVREG [expr $CONFIG_SPICTRL_SLVREG&15]} else {set CONFIG_SPICTRL_SLVREG [expr $CONFIG_SPICTRL_SLVREG|16]}
+ global CONFIG_SPICTRL_ASEL
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {
+ set CONFIG_SPICTRL_ASEL [expr $CONFIG_SPICTRL_ASEL&15]} else {set CONFIG_SPICTRL_ASEL [expr $CONFIG_SPICTRL_ASEL|16]}
+ global CONFIG_SPICTRL_AM
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {
+ set CONFIG_SPICTRL_AM [expr $CONFIG_SPICTRL_AM&15]} else {set CONFIG_SPICTRL_AM [expr $CONFIG_SPICTRL_AM|16]}
+ global CONFIG_SPICTRL_ODMODE
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {
+ set CONFIG_SPICTRL_ODMODE [expr $CONFIG_SPICTRL_ODMODE&15]} else {set CONFIG_SPICTRL_ODMODE [expr $CONFIG_SPICTRL_ODMODE|16]}
+}
+
+
+proc menu24 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 24}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 24]]
+ message $w.m -width 400 -aspect 300 -text \
+ "LCD and VGA DAC " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "LCD and VGA DAC "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 24; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 24; catch {destroy .menu13}; unregister_active 13; menu25 .menu25 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 24 0 "LCD graphical frame buffer " CONFIG_LCD_ENABLE
+ bool $w.config.f 24 1 "LCD 3-wire and touch panel " CONFIG_LCD3T_ENABLE
+ bool $w.config.f 24 2 "SVGA graphical frame buffer " CONFIG_SVGA_ENABLE
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu24 {} {
+}
+
+
+proc update_define_menu24 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+menu_option menu25 25 "VHDL Debugging "
+proc menu25 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 25}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 25]]
+ message $w.m -width 400 -aspect 300 -text \
+ "VHDL Debugging " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "VHDL Debugging "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 25; break"
+ set nextscript "catch {focus $oldFocus}; menu26 .menu26 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 25"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ $w.f.next configure -state disabled
+ bind all <Alt-n> "puts \"no more menus\" "
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 25; menu24 .menu24 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 25; menu24 .menu24 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 25 0 "Accelerated UART tracing " CONFIG_DEBUG_UART
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu25 {} {
+}
+
+
+proc update_define_menu25 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+proc update_mainmenu {} {
+}
+
+
+set tmpvar_0 "(not set)"
+set CONFIG_SYN_INFERRED 0
+set CONFIG_SYN_STRATIX 0
+set CONFIG_SYN_STRATIXII 0
+set CONFIG_SYN_STRATIXIII 0
+set CONFIG_SYN_CYCLONEIII 0
+set CONFIG_SYN_ALTERA 0
+set CONFIG_SYN_AXCEL 0
+set CONFIG_SYN_AXDSP 0
+set CONFIG_SYN_PROASIC 0
+set CONFIG_SYN_PROASICPLUS 0
+set CONFIG_SYN_PROASIC3 0
+set CONFIG_SYN_IGLOO 0
+set CONFIG_SYN_UT025CRH 0
+set CONFIG_SYN_ATC18 0
+set CONFIG_SYN_ATC18RHA 0
+set CONFIG_SYN_CUSTOM1 0
+set CONFIG_SYN_EASIC90 0
+set CONFIG_SYN_IHP25 0
+set CONFIG_SYN_IHP25RH 0
+set CONFIG_SYN_LATTICE 0
+set CONFIG_SYN_ECLIPSE 0
+set CONFIG_SYN_PEREGRINE 0
+set CONFIG_SYN_RH_LIB18T 0
+set CONFIG_SYN_RHUMC 0
+set CONFIG_SYN_SMIC13 0
+set CONFIG_SYN_SPARTAN2 0
+set CONFIG_SYN_SPARTAN3 0
+set CONFIG_SYN_SPARTAN3E 0
+set CONFIG_SYN_VIRTEX 0
+set CONFIG_SYN_VIRTEXE 0
+set CONFIG_SYN_VIRTEX2 0
+set CONFIG_SYN_VIRTEX4 0
+set CONFIG_SYN_VIRTEX5 0
+set CONFIG_SYN_UMC 0
+set CONFIG_SYN_TSMC90 0
+set tmpvar_1 "(not set)"
+set CONFIG_MEM_INFERRED 0
+set CONFIG_MEM_UMC 0
+set CONFIG_MEM_RHUMC 0
+set CONFIG_MEM_ARTISAN 0
+set CONFIG_MEM_CUSTOM1 0
+set CONFIG_MEM_VIRAGE 0
+set CONFIG_MEM_VIRAGE90 0
+set CONFIG_SYN_INFER_RAM 0
+set CONFIG_SYN_INFER_PADS 0
+set CONFIG_SYN_NO_ASYNC 0
+set CONFIG_SYN_SCAN 0
+set tmpvar_2 "(not set)"
+set CONFIG_CLK_INFERRED 0
+set CONFIG_CLK_HCLKBUF 0
+set CONFIG_CLK_ALTDLL 0
+set CONFIG_CLK_LATDLL 0
+set CONFIG_CLK_PRO3PLL 0
+set CONFIG_CLK_LIB18T 0
+set CONFIG_CLK_RHUMC 0
+set CONFIG_CLK_CLKDLL 0
+set CONFIG_CLK_DCM 0
+set CONFIG_CLK_MUL 2
+set CONFIG_CLK_DIV 2
+set CONFIG_OCLK_DIV 2
+set CONFIG_PCI_CLKDLL 0
+set CONFIG_CLK_NOFB 0
+set CONFIG_PCI_SYSCLK 0
+set CONFIG_LEON3 0
+set CONFIG_PROC_NUM 1
+set CONFIG_IU_NWINDOWS 8
+set CONFIG_IU_V8MULDIV 0
+set tmpvar_3 "(not set)"
+set CONFIG_IU_MUL_LATENCY_2 0
+set CONFIG_IU_MUL_LATENCY_4 0
+set CONFIG_IU_MUL_LATENCY_5 0
+set CONFIG_IU_MUL_MAC 0
+set CONFIG_IU_SVT 0
+set CONFIG_IU_LDELAY 1
+set CONFIG_IU_WATCHPOINTS 0
+set CONFIG_PWD 0
+set CONFIG_IU_RSTADDR 00000
+set CONFIG_FPU_ENABLE 0
+set tmpvar_4 "(not set)"
+set CONFIG_FPU_GRFPU 0
+set CONFIG_FPU_GRFPULITE 0
+set CONFIG_FPU_MEIKO 0
+set tmpvar_5 "(not set)"
+set CONFIG_FPU_GRFPU_INFMUL 0
+set CONFIG_FPU_GRFPU_DWMUL 0
+set CONFIG_FPU_GRFPU_MODGEN 0
+set CONFIG_FPU_GRFPU_TECHSPEC 0
+set tmpvar_6 "(not set)"
+set CONFIG_FPU_GRFPC0 0
+set CONFIG_FPU_GRFPC1 0
+set CONFIG_FPU_GRFPC2 0
+set CONFIG_FPU_NETLIST 0
+set CONFIG_ICACHE_ENABLE 0
+set tmpvar_7 "(not set)"
+set CONFIG_ICACHE_ASSO1 0
+set CONFIG_ICACHE_ASSO2 0
+set CONFIG_ICACHE_ASSO3 0
+set CONFIG_ICACHE_ASSO4 0
+set tmpvar_8 "(not set)"
+set CONFIG_ICACHE_SZ1 0
+set CONFIG_ICACHE_SZ2 0
+set CONFIG_ICACHE_SZ4 0
+set CONFIG_ICACHE_SZ8 0
+set CONFIG_ICACHE_SZ16 0
+set CONFIG_ICACHE_SZ32 0
+set CONFIG_ICACHE_SZ64 0
+set CONFIG_ICACHE_SZ128 0
+set CONFIG_ICACHE_SZ256 0
+set tmpvar_9 "(not set)"
+set CONFIG_ICACHE_LZ16 0
+set CONFIG_ICACHE_LZ32 0
+set tmpvar_10 "(not set)"
+set CONFIG_ICACHE_ALGORND 0
+set CONFIG_ICACHE_ALGOLRR 0
+set CONFIG_ICACHE_ALGOLRU 0
+set CONFIG_ICACHE_LOCK 0
+set CONFIG_ICACHE_LRAM 0
+set tmpvar_11 "(not set)"
+set CONFIG_ICACHE_LRAM_SZ1 0
+set CONFIG_ICACHE_LRAM_SZ2 0
+set CONFIG_ICACHE_LRAM_SZ4 0
+set CONFIG_ICACHE_LRAM_SZ8 0
+set CONFIG_ICACHE_LRAM_SZ16 0
+set CONFIG_ICACHE_LRAM_SZ32 0
+set CONFIG_ICACHE_LRAM_SZ64 0
+set CONFIG_ICACHE_LRAM_SZ128 0
+set CONFIG_ICACHE_LRAM_SZ256 0
+set CONFIG_ICACHE_LRSTART 8e
+set CONFIG_DCACHE_ENABLE 0
+set tmpvar_12 "(not set)"
+set CONFIG_DCACHE_ASSO1 0
+set CONFIG_DCACHE_ASSO2 0
+set CONFIG_DCACHE_ASSO3 0
+set CONFIG_DCACHE_ASSO4 0
+set tmpvar_13 "(not set)"
+set CONFIG_DCACHE_SZ1 0
+set CONFIG_DCACHE_SZ2 0
+set CONFIG_DCACHE_SZ4 0
+set CONFIG_DCACHE_SZ8 0
+set CONFIG_DCACHE_SZ16 0
+set CONFIG_DCACHE_SZ32 0
+set CONFIG_DCACHE_SZ64 0
+set CONFIG_DCACHE_SZ128 0
+set CONFIG_DCACHE_SZ256 0
+set tmpvar_14 "(not set)"
+set CONFIG_DCACHE_LZ16 0
+set CONFIG_DCACHE_LZ32 0
+set tmpvar_15 "(not set)"
+set CONFIG_DCACHE_ALGORND 0
+set CONFIG_DCACHE_ALGOLRR 0
+set CONFIG_DCACHE_ALGOLRU 0
+set CONFIG_DCACHE_LOCK 0
+set CONFIG_DCACHE_SNOOP 0
+set CONFIG_DCACHE_SNOOP_FAST 0
+set CONFIG_DCACHE_SNOOP_SEPTAG 0
+set CONFIG_CACHE_FIXED 0
+set CONFIG_DCACHE_LRAM 0
+set tmpvar_16 "(not set)"
+set CONFIG_DCACHE_LRAM_SZ1 0
+set CONFIG_DCACHE_LRAM_SZ2 0
+set CONFIG_DCACHE_LRAM_SZ4 0
+set CONFIG_DCACHE_LRAM_SZ8 0
+set CONFIG_DCACHE_LRAM_SZ16 0
+set CONFIG_DCACHE_LRAM_SZ32 0
+set CONFIG_DCACHE_LRAM_SZ64 0
+set CONFIG_DCACHE_LRAM_SZ128 0
+set CONFIG_DCACHE_LRAM_SZ256 0
+set CONFIG_DCACHE_LRSTART 8f
+set CONFIG_MMU_ENABLE 0
+set tmpvar_17 "(not set)"
+set CONFIG_MMU_COMBINED 0
+set CONFIG_MMU_SPLIT 0
+set tmpvar_18 "(not set)"
+set CONFIG_MMU_REPARRAY 0
+set CONFIG_MMU_REPINCREMENT 0
+set tmpvar_19 "(not set)"
+set CONFIG_MMU_I2 0
+set CONFIG_MMU_I4 0
+set CONFIG_MMU_I8 0
+set CONFIG_MMU_I16 0
+set CONFIG_MMU_I32 0
+set tmpvar_20 "(not set)"
+set CONFIG_MMU_D2 0
+set CONFIG_MMU_D4 0
+set CONFIG_MMU_D8 0
+set CONFIG_MMU_D16 0
+set CONFIG_MMU_D32 0
+set CONFIG_MMU_FASTWB 0
+set tmpvar_21 "(not set)"
+set CONFIG_MMU_PAGE_4K 0
+set CONFIG_MMU_PAGE_8K 0
+set CONFIG_MMU_PAGE_16K 0
+set CONFIG_MMU_PAGE_32K 0
+set CONFIG_MMU_PAGE_PROG 0
+set CONFIG_DSU_ENABLE 0
+set CONFIG_DSU_ITRACE 0
+set tmpvar_22 "(not set)"
+set CONFIG_DSU_ITRACESZ1 0
+set CONFIG_DSU_ITRACESZ2 0
+set CONFIG_DSU_ITRACESZ4 0
+set CONFIG_DSU_ITRACESZ8 0
+set CONFIG_DSU_ITRACESZ16 0
+set CONFIG_DSU_ATRACE 0
+set tmpvar_23 "(not set)"
+set CONFIG_DSU_ATRACESZ1 0
+set CONFIG_DSU_ATRACESZ2 0
+set CONFIG_DSU_ATRACESZ4 0
+set CONFIG_DSU_ATRACESZ8 0
+set CONFIG_DSU_ATRACESZ16 0
+set CONFIG_IU_DISAS 0
+set CONFIG_IU_DISAS_NET 0
+set CONFIG_DEBUG_PC32 0
+set CONFIG_AHB_DEFMST 0
+set CONFIG_AHB_RROBIN 0
+set CONFIG_AHB_SPLIT 0
+set CONFIG_AHB_IOADDR FFF
+set CONFIG_APB_HADDR 800
+set CONFIG_AHB_MON 0
+set CONFIG_AHB_MONERR 0
+set CONFIG_AHB_MONWAR 0
+set CONFIG_DSU_UART 0
+set CONFIG_DSU_JTAG 0
+set CONFIG_DSU_ETH 0
+set tmpvar_25 "(not set)"
+set CONFIG_DSU_ETHSZ1 0
+set CONFIG_DSU_ETHSZ2 0
+set CONFIG_DSU_ETHSZ4 0
+set CONFIG_DSU_ETHSZ8 0
+set CONFIG_DSU_ETHSZ16 0
+set CONFIG_DSU_IPMSB C0A8
+set CONFIG_DSU_IPLSB 0033
+set CONFIG_DSU_ETHMSB 020000
+set CONFIG_DSU_ETHLSB 000000
+set CONFIG_DSU_ETH_PROG 0
+set CONFIG_MCTRL_LEON2 0
+set CONFIG_MCTRL_8BIT 0
+set CONFIG_MCTRL_16BIT 0
+set CONFIG_MCTRL_5CS 0
+set CONFIG_MCTRL_SDRAM 0
+set CONFIG_MCTRL_SDRAM_SEPBUS 0
+set CONFIG_MCTRL_SDRAM_BUS64 0
+set CONFIG_MCTRL_SDRAM_INVCLK 0
+set CONFIG_MCTRL_PAGE 0
+set CONFIG_MCTRL_PROGPAGE 0
+set CONFIG_SSCTRL 0
+set CONFIG_SSCTRL_PROM16 0
+set CONFIG_DDRSP 0
+set CONFIG_DDRSP_INIT 0
+set CONFIG_DDRSP_FREQ 100
+set CONFIG_DDRSP_COL 9
+set CONFIG_DDRSP_MBYTE 16
+set CONFIG_DDRSP_RSKEW 0
+set CONFIG_SPIMCTRL 0
+set CONFIG_SPIMCTRL_SDCARD 0
+set CONFIG_SPIMCTRL_READCMD 0B
+set CONFIG_SPIMCTRL_DUMMYBYTE 0
+set CONFIG_SPIMCTRL_DUALOUTPUT 0
+set CONFIG_SPIMCTRL_SCALER 1
+set CONFIG_SPIMCTRL_ASCALER 8
+set CONFIG_SPIMCTRL_PWRUPCNT 0
+set CONFIG_AHBROM_ENABLE 0
+set CONFIG_AHBROM_START 000
+set CONFIG_AHBROM_PIPE 0
+set CONFIG_AHBRAM_ENABLE 0
+set tmpvar_26 "(not set)"
+set CONFIG_AHBRAM_SZ1 0
+set CONFIG_AHBRAM_SZ2 0
+set CONFIG_AHBRAM_SZ4 0
+set CONFIG_AHBRAM_SZ8 0
+set CONFIG_AHBRAM_SZ16 0
+set CONFIG_AHBRAM_SZ32 0
+set CONFIG_AHBRAM_SZ64 0
+set CONFIG_AHBRAM_START A00
+set CONFIG_GRETH_ENABLE 0
+set CONFIG_GRETH_GIGA 0
+set tmpvar_27 "(not set)"
+set CONFIG_GRETH_FIFO4 0
+set CONFIG_GRETH_FIFO8 0
+set CONFIG_GRETH_FIFO16 0
+set CONFIG_GRETH_FIFO32 0
+set CONFIG_GRETH_FIFO64 0
+set CONFIG_UART1_ENABLE 0
+set tmpvar_28 "(not set)"
+set CONFIG_UA1_FIFO1 0
+set CONFIG_UA1_FIFO2 0
+set CONFIG_UA1_FIFO4 0
+set CONFIG_UA1_FIFO8 0
+set CONFIG_UA1_FIFO16 0
+set CONFIG_UA1_FIFO32 0
+set CONFIG_IRQ3_ENABLE 0
+set CONFIG_IRQ3_SEC 0
+set CONFIG_IRQ3_NSEC 12
+set CONFIG_GPT_ENABLE 0
+set CONFIG_GPT_NTIM 2
+set CONFIG_GPT_SW 8
+set CONFIG_GPT_TW 32
+set CONFIG_GPT_IRQ 8
+set CONFIG_GPT_SEPIRQ 0
+set CONFIG_GPT_WDOGEN 0
+set CONFIG_GPT_WDOG FFFF
+set CONFIG_GRGPIO_ENABLE 0
+set CONFIG_GRGPIO_WIDTH 8
+set CONFIG_GRGPIO_IMASK 0000
+set CONFIG_I2C_ENABLE 0
+set CONFIG_PS2_ENABLE 0
+set CONFIG_SPICTRL_ENABLE 0
+set CONFIG_SPICTRL_SLVS 1
+set CONFIG_SPICTRL_FIFO 1
+set CONFIG_SPICTRL_SLVREG 0
+set CONFIG_SPICTRL_ASEL 0
+set CONFIG_SPICTRL_AM 0
+set CONFIG_SPICTRL_ODMODE 0
+set CONFIG_LCD_ENABLE 0
+set CONFIG_LCD3T_ENABLE 0
+set CONFIG_SVGA_ENABLE 0
+set CONFIG_DEBUG_UART 0
+set CONFIG_SYN_ARTISAN 4
+set CONFIG_PCI_ENABLE 4
+set CONFIG_HAS_SHARED_GRFPU 4
+set CONFIG_FPU_GRFPU_SH 4
+set CONFIG_LEON3FT_PRESENT 4
+set CONFIG_LEON3FT_EN 4
+set CONFIG_IUFT_NONE 4
+set CONFIG_IUFT_PAR 4
+set CONFIG_IUFT_DMR 4
+set CONFIG_IUFT_BCH 4
+set CONFIG_IUFT_TMR 4
+set CONFIG_FPUFT_EN 4
+set CONFIG_RF_ERRINJ 4
+set CONFIG_CACHE_FT_EN 4
+set CONFIG_CACHE_ERRINJ 4
+set CONFIG_LEON3_NETLIST 4
+set CONFIG_MODULES 4
+proc writeconfig {file1 file2} {
+ set cfg [open $file1 w]
+ set autocfg [open $file2 w]
+ set notmod 1
+ set notset 0
+ puts $cfg "#"
+ puts $cfg "# Automatically generated make config: don't edit"
+ puts $cfg "#"
+ puts $autocfg "/*"
+ puts $autocfg " * Automatically generated C config: don't edit"
+ puts $autocfg " */"
+ puts $autocfg "#define AUTOCONF_INCLUDED"
+ write_comment $cfg $autocfg "Synthesis "
+ global tmpvar_0
+
+ if { $tmpvar_0 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-Stratix" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-StratixII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-StratixIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-CycloneIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-Others" } then { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-Axcelerator" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-Axcelerator-DSP" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXDSP 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXDSP 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-Proasic" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-ProasicPlus" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-Proasic3/E/L" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-IGLOO/p/L" } then { write_tristate $cfg $autocfg CONFIG_SYN_IGLOO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IGLOO 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Aeroflex-UT025CRH" } then { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Atmel-ATC18" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Atmel-ATC18RHA" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "eASIC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "IHP25" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "IHP25RH" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Lattice-EC/ECP/XP" } then { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Quicklogic-Eclipse" } then { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Peregrine" } then { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "RH-LIB18T" } then { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "SMIC130" } then { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Spartan2" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Spartan3" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Spartan3E" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-VirtexE" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex2" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex4" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex5" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "UMC180" } then { write_tristate $cfg $autocfg CONFIG_SYN_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UMC 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "TSMC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 0 [list $notmod] 2 }
+ global tmpvar_1
+ global CONFIG_SYN_INFERRED
+ global CONFIG_SYN_CUSTOM1
+ global CONFIG_SYN_ATC18
+ global CONFIG_SYN_TSMC90
+ global CONFIG_SYN_UMC
+ global CONFIG_SYN_RHUMC
+ global CONFIG_SYN_ARTISAN
+ if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then {
+ if { $tmpvar_1 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "UMC18" } then { write_tristate $cfg $autocfg CONFIG_MEM_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_UMC 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "Artisan" } then { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "Virage" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "Virage-TSMC90" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 0 [list $notmod] 2 }}
+ global CONFIG_SYN_INFER_RAM
+ if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_RAM $CONFIG_SYN_INFER_RAM [list $notmod] 2 }
+ global CONFIG_SYN_INFER_PADS
+ if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_PADS $CONFIG_SYN_INFER_PADS [list $notmod] 2 }
+ global CONFIG_SYN_NO_ASYNC
+ write_tristate $cfg $autocfg CONFIG_SYN_NO_ASYNC $CONFIG_SYN_NO_ASYNC [list $notmod] 2
+ global CONFIG_SYN_SCAN
+ write_tristate $cfg $autocfg CONFIG_SYN_SCAN $CONFIG_SYN_SCAN [list $notmod] 2
+ write_comment $cfg $autocfg "Clock generation"
+ global tmpvar_2
+
+ if { $tmpvar_2 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "Actel-HCLKBUF" } then { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "Altera-ALTPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "Lattice-EXPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "Proasic3-PLLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "RH-LIB18T-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "DARE-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "Xilinx-CLKDLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "Xilinx-DCM" } then { write_tristate $cfg $autocfg CONFIG_CLK_DCM 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_DCM 0 [list $notmod] 2 }
+ global CONFIG_CLK_MUL
+ global CONFIG_CLK_DCM
+ global CONFIG_CLK_ALTDLL
+ global CONFIG_CLK_LATDLL
+ global CONFIG_CLK_PRO3PLL
+ global CONFIG_CLK_CLKDLL
+ global CONFIG_CLK_LIB18T
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_MUL $CONFIG_CLK_MUL $notmod }
+ global CONFIG_CLK_DIV
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_DIV $CONFIG_CLK_DIV $notmod }
+ global CONFIG_OCLK_DIV
+ if {($CONFIG_CLK_PRO3PLL == 1)} then {write_int $cfg $autocfg CONFIG_OCLK_DIV $CONFIG_OCLK_DIV $notmod }
+ global CONFIG_PCI_CLKDLL
+ if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_CLKDLL $CONFIG_PCI_CLKDLL [list $notmod] 2 }
+ global CONFIG_CLK_NOFB
+ if {($CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_CLK_NOFB $CONFIG_CLK_NOFB [list $notmod] 2 }
+ global CONFIG_PCI_SYSCLK
+ global CONFIG_PCI_ENABLE
+ if {($CONFIG_PCI_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SYSCLK $CONFIG_PCI_SYSCLK [list $notmod] 2 }
+ global CONFIG_LEON3
+ write_tristate $cfg $autocfg CONFIG_LEON3 $CONFIG_LEON3 [list $notmod] 2
+ global CONFIG_PROC_NUM
+ if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_PROC_NUM $CONFIG_PROC_NUM $notmod }
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Processor "}
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Integer unit "}
+ global CONFIG_IU_NWINDOWS
+ if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS $CONFIG_IU_NWINDOWS $notmod }
+ global CONFIG_IU_V8MULDIV
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONFIG_IU_V8MULDIV [list $notmod] 2 }
+ global tmpvar_3
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {
+ if { $tmpvar_3 == "2-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "4-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "5-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 0 [list $notmod] 2 }}
+ global CONFIG_IU_MUL_MAC
+ global CONFIG_IU_MUL_LATENCY_4
+ global CONFIG_IU_MUL_LATENCY_5
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_MAC $CONFIG_IU_MUL_MAC [list $notmod] 2 }
+ global CONFIG_IU_SVT
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONFIG_IU_SVT [list $notmod] 2 }
+ global CONFIG_IU_LDELAY
+ if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY $CONFIG_IU_LDELAY $notmod }
+ global CONFIG_IU_WATCHPOINTS
+ if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS $CONFIG_IU_WATCHPOINTS $notmod }
+ global CONFIG_PWD
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONFIG_PWD [list $notmod] 2 }
+ global CONFIG_IU_RSTADDR
+ if {($CONFIG_LEON3 == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR $CONFIG_IU_RSTADDR $notmod }
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Floating-point unit"}
+ global CONFIG_FPU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONFIG_FPU_ENABLE [list $notmod] 2 }
+ global tmpvar_4
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {
+ if { $tmpvar_4 == "GRFPU" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 0 [list $notmod] 2 }
+ if { $tmpvar_4 == "GRFPU-LITE" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 0 [list $notmod] 2 }
+ if { $tmpvar_4 == "Meiko" } then { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 0 [list $notmod] 2 }}
+ global tmpvar_5
+ global CONFIG_FPU_GRFPU
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then {
+ if { $tmpvar_5 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 0 [list $notmod] 2 }
+ if { $tmpvar_5 == "DW" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 0 [list $notmod] 2 }
+ if { $tmpvar_5 == "ModGen" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 0 [list $notmod] 2 }
+ if { $tmpvar_5 == "TechSpec" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_TECHSPEC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_TECHSPEC 0 [list $notmod] 2 }}
+ global tmpvar_6
+ global CONFIG_FPU_GRFPULITE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then {
+ if { $tmpvar_6 == "Simple" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 0 [list $notmod] 2 }
+ if { $tmpvar_6 == "Data-forwarding" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 0 [list $notmod] 2 }
+ if { $tmpvar_6 == "Non-blocking" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 0 [list $notmod] 2 }}
+ global CONFIG_FPU_NETLIST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_NETLIST $CONFIG_FPU_NETLIST [list $notmod] 2 }
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Cache system"}
+ global CONFIG_ICACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONFIG_ICACHE_ENABLE [list $notmod] 2 }
+ global tmpvar_7
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {
+ if { $tmpvar_7 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 0 [list $notmod] 2 }
+ if { $tmpvar_7 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 0 [list $notmod] 2 }
+ if { $tmpvar_7 == "3" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 0 [list $notmod] 2 }
+ if { $tmpvar_7 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 0 [list $notmod] 2 }}
+ global tmpvar_8
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {
+ if { $tmpvar_8 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 0 [list $notmod] 2 }}
+ global tmpvar_9
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {
+ if { $tmpvar_9 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 0 [list $notmod] 2 }}
+ global tmpvar_10
+ global CONFIG_ICACHE_ASSO1
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {
+ if { $tmpvar_10 == "Random" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 0 [list $notmod] 2 }
+ if { $tmpvar_10 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 0 [list $notmod] 2 }
+ if { $tmpvar_10 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 0 [list $notmod] 2 }}
+ global CONFIG_ICACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONFIG_ICACHE_LOCK [list $notmod] 2 }
+ global CONFIG_ICACHE_LRAM
+ global CONFIG_MMU_ENABLE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM $CONFIG_ICACHE_LRAM [list $notmod] 2 }
+ global tmpvar_11
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {
+ if { $tmpvar_11 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 0 [list $notmod] 2 }}
+ global CONFIG_ICACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_ICACHE_LRSTART $CONFIG_ICACHE_LRSTART $notmod }
+ global CONFIG_DCACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONFIG_DCACHE_ENABLE [list $notmod] 2 }
+ global tmpvar_12
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ if { $tmpvar_12 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "3" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 0 [list $notmod] 2 }}
+ global tmpvar_13
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ if { $tmpvar_13 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 0 [list $notmod] 2 }}
+ global tmpvar_14
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ if { $tmpvar_14 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 0 [list $notmod] 2 }}
+ global tmpvar_15
+ global CONFIG_DCACHE_ASSO1
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {
+ if { $tmpvar_15 == "Random" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 0 [list $notmod] 2 }
+ if { $tmpvar_15 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 0 [list $notmod] 2 }
+ if { $tmpvar_15 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }}
+ global CONFIG_DCACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 }
+ global CONFIG_DCACHE_SNOOP
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 }
+ global CONFIG_DCACHE_SNOOP_FAST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 }
+ global CONFIG_DCACHE_SNOOP_SEPTAG
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 }
+ global CONFIG_CACHE_FIXED
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod }
+ global CONFIG_DCACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 }
+ global tmpvar_16
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {
+ if { $tmpvar_16 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 0 [list $notmod] 2 }}
+ global CONFIG_DCACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_DCACHE_LRSTART $CONFIG_DCACHE_LRSTART $notmod }
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "MMU"}
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONFIG_MMU_ENABLE [list $notmod] 2 }
+ global tmpvar_17
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {
+ if { $tmpvar_17 == "combined" } then { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "split" } then { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 0 [list $notmod] 2 }}
+ global tmpvar_18
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {
+ if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 0 [list $notmod] 2 }
+ if { $tmpvar_18 == "Increment" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 0 [list $notmod] 2 }}
+ global tmpvar_19
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {
+ if { $tmpvar_19 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_I2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I2 0 [list $notmod] 2 }
+ if { $tmpvar_19 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_I4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I4 0 [list $notmod] 2 }
+ if { $tmpvar_19 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_I8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I8 0 [list $notmod] 2 }
+ if { $tmpvar_19 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_I16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I16 0 [list $notmod] 2 }
+ if { $tmpvar_19 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_I32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I32 0 [list $notmod] 2 }}
+ global tmpvar_20
+ global CONFIG_MMU_SPLIT
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {
+ if { $tmpvar_20 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_D2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D2 0 [list $notmod] 2 }
+ if { $tmpvar_20 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_D4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D4 0 [list $notmod] 2 }
+ if { $tmpvar_20 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_D8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D8 0 [list $notmod] 2 }
+ if { $tmpvar_20 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_D16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D16 0 [list $notmod] 2 }
+ if { $tmpvar_20 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_D32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D32 0 [list $notmod] 2 }}
+ global CONFIG_MMU_FASTWB
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_FASTWB $CONFIG_MMU_FASTWB [list $notmod] 2 }
+ global tmpvar_21
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {
+ if { $tmpvar_21 == "4K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 0 [list $notmod] 2 }
+ if { $tmpvar_21 == "8K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 0 [list $notmod] 2 }
+ if { $tmpvar_21 == "16K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 0 [list $notmod] 2 }
+ if { $tmpvar_21 == "32K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 0 [list $notmod] 2 }
+ if { $tmpvar_21 == "Programmable" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 0 [list $notmod] 2 }}
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Debug Support Unit "}
+ global CONFIG_DSU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONFIG_DSU_ENABLE [list $notmod] 2 }
+ global CONFIG_DSU_ITRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACE $CONFIG_DSU_ITRACE [list $notmod] 2 }
+ global tmpvar_22
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then {
+ if { $tmpvar_22 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 0 [list $notmod] 2 }
+ if { $tmpvar_22 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 0 [list $notmod] 2 }
+ if { $tmpvar_22 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 0 [list $notmod] 2 }
+ if { $tmpvar_22 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 0 [list $notmod] 2 }
+ if { $tmpvar_22 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 0 [list $notmod] 2 }}
+ global CONFIG_DSU_ATRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ATRACE $CONFIG_DSU_ATRACE [list $notmod] 2 }
+ global tmpvar_23
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then {
+ if { $tmpvar_23 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 0 [list $notmod] 2 }
+ if { $tmpvar_23 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 0 [list $notmod] 2 }
+ if { $tmpvar_23 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 0 [list $notmod] 2 }
+ if { $tmpvar_23 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 0 [list $notmod] 2 }
+ if { $tmpvar_23 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 0 [list $notmod] 2 }}
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Fault-tolerance "}
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "VHDL debug settings "}
+ global CONFIG_IU_DISAS
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS $CONFIG_IU_DISAS [list $notmod] 2 }
+ global CONFIG_IU_DISAS_NET
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS_NET $CONFIG_IU_DISAS_NET [list $notmod] 2 }
+ global CONFIG_DEBUG_PC32
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DEBUG_PC32 $CONFIG_DEBUG_PC32 [list $notmod] 2 }
+ write_comment $cfg $autocfg "AMBA configuration"
+ global CONFIG_AHB_DEFMST
+ write_int $cfg $autocfg CONFIG_AHB_DEFMST $CONFIG_AHB_DEFMST $notmod
+ global CONFIG_AHB_RROBIN
+ write_tristate $cfg $autocfg CONFIG_AHB_RROBIN $CONFIG_AHB_RROBIN [list $notmod] 2
+ global CONFIG_AHB_SPLIT
+ write_tristate $cfg $autocfg CONFIG_AHB_SPLIT $CONFIG_AHB_SPLIT [list $notmod] 2
+ global CONFIG_AHB_IOADDR
+ write_hex $cfg $autocfg CONFIG_AHB_IOADDR $CONFIG_AHB_IOADDR $notmod
+ global CONFIG_APB_HADDR
+ write_hex $cfg $autocfg CONFIG_APB_HADDR $CONFIG_APB_HADDR $notmod
+ global CONFIG_AHB_MON
+ write_tristate $cfg $autocfg CONFIG_AHB_MON $CONFIG_AHB_MON [list $notmod] 2
+ global CONFIG_AHB_MONERR
+ if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONERR $CONFIG_AHB_MONERR [list $notmod] 2 }
+ global CONFIG_AHB_MONWAR
+ if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONWAR $CONFIG_AHB_MONWAR [list $notmod] 2 }
+ write_comment $cfg $autocfg "Debug Link "
+ global CONFIG_DSU_UART
+ write_tristate $cfg $autocfg CONFIG_DSU_UART $CONFIG_DSU_UART [list $notmod] 2
+ global CONFIG_DSU_JTAG
+ write_tristate $cfg $autocfg CONFIG_DSU_JTAG $CONFIG_DSU_JTAG [list $notmod] 2
+ global CONFIG_DSU_ETH
+ global CONFIG_GRETH_ENABLE
+ if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH $CONFIG_DSU_ETH [list $notmod] 2 }
+ global tmpvar_25
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {
+ if { $tmpvar_25 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 0 [list $notmod] 2 }
+ if { $tmpvar_25 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 0 [list $notmod] 2 }
+ if { $tmpvar_25 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 0 [list $notmod] 2 }
+ if { $tmpvar_25 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 0 [list $notmod] 2 }
+ if { $tmpvar_25 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 0 [list $notmod] 2 }}
+ global CONFIG_DSU_IPMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPMSB $CONFIG_DSU_IPMSB $notmod }
+ global CONFIG_DSU_IPLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPLSB $CONFIG_DSU_IPLSB $notmod }
+ global CONFIG_DSU_ETHMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHMSB $CONFIG_DSU_ETHMSB $notmod }
+ global CONFIG_DSU_ETHLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod }
+ global CONFIG_DSU_ETH_PROG
+ global CONFIG_GRETH_GIGA
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 }
+ write_comment $cfg $autocfg "Peripherals "
+ write_comment $cfg $autocfg "Memory controllers "
+ write_comment $cfg $autocfg "Leon2 memory controller "
+ global CONFIG_MCTRL_LEON2
+ write_tristate $cfg $autocfg CONFIG_MCTRL_LEON2 $CONFIG_MCTRL_LEON2 [list $notmod] 2
+ global CONFIG_MCTRL_8BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_8BIT $CONFIG_MCTRL_8BIT [list $notmod] 2 }
+ global CONFIG_MCTRL_16BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_16BIT $CONFIG_MCTRL_16BIT [list $notmod] 2 }
+ global CONFIG_MCTRL_5CS
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_5CS $CONFIG_MCTRL_5CS [list $notmod] 2 }
+ global CONFIG_MCTRL_SDRAM
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM $CONFIG_MCTRL_SDRAM [list $notmod] 2 }
+ global CONFIG_MCTRL_SDRAM_SEPBUS
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_SEPBUS $CONFIG_MCTRL_SDRAM_SEPBUS [list $notmod] 2 }
+ global CONFIG_MCTRL_SDRAM_BUS64
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_BUS64 $CONFIG_MCTRL_SDRAM_BUS64 [list $notmod] 2 }
+ global CONFIG_MCTRL_SDRAM_INVCLK
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_INVCLK $CONFIG_MCTRL_SDRAM_INVCLK [list $notmod] 2 }
+ global CONFIG_MCTRL_PAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PAGE $CONFIG_MCTRL_PAGE [list $notmod] 2 }
+ global CONFIG_MCTRL_PROGPAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PROGPAGE $CONFIG_MCTRL_PROGPAGE [list $notmod] 2 }
+ write_comment $cfg $autocfg "Synchronous SRAM controller "
+ global CONFIG_SSCTRL
+ write_tristate $cfg $autocfg CONFIG_SSCTRL $CONFIG_SSCTRL [list $notmod] 2
+ global CONFIG_SSCTRL_PROM16
+ if {($CONFIG_SSCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SSCTRL_PROM16 $CONFIG_SSCTRL_PROM16 [list $notmod] 2 }
+ write_comment $cfg $autocfg "DDR266 SDRAM controller "
+ global CONFIG_DDRSP
+ write_tristate $cfg $autocfg CONFIG_DDRSP $CONFIG_DDRSP [list $notmod] 2
+ global CONFIG_DDRSP_INIT
+ if {($CONFIG_DDRSP == 1)} then {write_tristate $cfg $autocfg CONFIG_DDRSP_INIT $CONFIG_DDRSP_INIT [list $notmod] 2 }
+ global CONFIG_DDRSP_FREQ
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {write_int $cfg $autocfg CONFIG_DDRSP_FREQ $CONFIG_DDRSP_FREQ $notmod }
+ global CONFIG_DDRSP_COL
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {write_int $cfg $autocfg CONFIG_DDRSP_COL $CONFIG_DDRSP_COL $notmod }
+ global CONFIG_DDRSP_MBYTE
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_DDRSP_INIT == 1)} then {write_int $cfg $autocfg CONFIG_DDRSP_MBYTE $CONFIG_DDRSP_MBYTE $notmod }
+ global CONFIG_DDRSP_RSKEW
+ global CONFIG_SYN_VIRTEX2
+ global CONFIG_SYN_VIRTEX4
+ global CONFIG_SYN_SPARTAN3
+ global CONFIG_SYN_VIRTEX5
+ global CONFIG_SYN_SPARTAN3E
+ global CONFIG_SYN_CYCLONEIII
+ if {($CONFIG_DDRSP == 1) && ($CONFIG_SYN_VIRTEX2 == 1 || $CONFIG_SYN_VIRTEX4 == 1 || $CONFIG_SYN_SPARTAN3 == 1 || $CONFIG_SYN_VIRTEX5 == 1 || $CONFIG_SYN_SPARTAN3E == 1 || $CONFIG_SYN_CYCLONEIII == 1)} then {write_int $cfg $autocfg CONFIG_DDRSP_RSKEW $CONFIG_DDRSP_RSKEW $notmod }
+ write_comment $cfg $autocfg "SPI memory controller "
+ global CONFIG_SPIMCTRL
+ write_tristate $cfg $autocfg CONFIG_SPIMCTRL $CONFIG_SPIMCTRL [list $notmod] 2
+ global CONFIG_SPIMCTRL_SDCARD
+ if {($CONFIG_SPIMCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SPIMCTRL_SDCARD $CONFIG_SPIMCTRL_SDCARD [list $notmod] 2 }
+ global CONFIG_SPIMCTRL_READCMD
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {write_hex $cfg $autocfg CONFIG_SPIMCTRL_READCMD $CONFIG_SPIMCTRL_READCMD $notmod }
+ global CONFIG_SPIMCTRL_DUMMYBYTE
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {write_tristate $cfg $autocfg CONFIG_SPIMCTRL_DUMMYBYTE $CONFIG_SPIMCTRL_DUMMYBYTE [list $notmod] 2 }
+ global CONFIG_SPIMCTRL_DUALOUTPUT
+ if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {write_tristate $cfg $autocfg CONFIG_SPIMCTRL_DUALOUTPUT $CONFIG_SPIMCTRL_DUALOUTPUT [list $notmod] 2 }
+ global CONFIG_SPIMCTRL_SCALER
+ if {($CONFIG_SPIMCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SPIMCTRL_SCALER $CONFIG_SPIMCTRL_SCALER $notmod }
+ global CONFIG_SPIMCTRL_ASCALER
+ if {($CONFIG_SPIMCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SPIMCTRL_ASCALER $CONFIG_SPIMCTRL_ASCALER $notmod }
+ global CONFIG_SPIMCTRL_PWRUPCNT
+ if {($CONFIG_SPIMCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SPIMCTRL_PWRUPCNT $CONFIG_SPIMCTRL_PWRUPCNT $notmod }
+ write_comment $cfg $autocfg "On-chip RAM/ROM "
+ global CONFIG_AHBROM_ENABLE
+ write_tristate $cfg $autocfg CONFIG_AHBROM_ENABLE $CONFIG_AHBROM_ENABLE [list $notmod] 2
+ global CONFIG_AHBROM_START
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBROM_START $CONFIG_AHBROM_START $notmod }
+ global CONFIG_AHBROM_PIPE
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBROM_PIPE $CONFIG_AHBROM_PIPE [list $notmod] 2 }
+ global CONFIG_AHBRAM_ENABLE
+ write_tristate $cfg $autocfg CONFIG_AHBRAM_ENABLE $CONFIG_AHBRAM_ENABLE [list $notmod] 2
+ global tmpvar_26
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {
+ if { $tmpvar_26 == "1" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_26 == "2" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_26 == "4" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_26 == "8" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_26 == "16" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_26 == "32" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_26 == "64" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 0 [list $notmod] 2 }}
+ global CONFIG_AHBRAM_START
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBRAM_START $CONFIG_AHBRAM_START $notmod }
+ write_comment $cfg $autocfg "Ethernet "
+ write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2
+ if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 }
+ global tmpvar_27
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {
+ if { $tmpvar_27 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 0 [list $notmod] 2 }
+ if { $tmpvar_27 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 0 [list $notmod] 2 }
+ if { $tmpvar_27 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 0 [list $notmod] 2 }
+ if { $tmpvar_27 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 0 [list $notmod] 2 }
+ if { $tmpvar_27 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 0 [list $notmod] 2 }}
+ write_comment $cfg $autocfg "UARTs, timers and irq control "
+ global CONFIG_UART1_ENABLE
+ write_tristate $cfg $autocfg CONFIG_UART1_ENABLE $CONFIG_UART1_ENABLE [list $notmod] 2
+ global tmpvar_28
+ if {($CONFIG_UART1_ENABLE == 1)} then {
+ if { $tmpvar_28 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 0 [list $notmod] 2 }}
+ global CONFIG_IRQ3_ENABLE
+ write_tristate $cfg $autocfg CONFIG_IRQ3_ENABLE $CONFIG_IRQ3_ENABLE [list $notmod] 2
+ global CONFIG_IRQ3_SEC
+ if {($CONFIG_IRQ3_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_IRQ3_SEC $CONFIG_IRQ3_SEC [list $notmod] 2 }
+ global CONFIG_IRQ3_NSEC
+ if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {write_int $cfg $autocfg CONFIG_IRQ3_NSEC $CONFIG_IRQ3_NSEC $notmod }
+ global CONFIG_GPT_ENABLE
+ write_tristate $cfg $autocfg CONFIG_GPT_ENABLE $CONFIG_GPT_ENABLE [list $notmod] 2
+ global CONFIG_GPT_NTIM
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_NTIM $CONFIG_GPT_NTIM $notmod }
+ global CONFIG_GPT_SW
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_SW $CONFIG_GPT_SW $notmod }
+ global CONFIG_GPT_TW
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_TW $CONFIG_GPT_TW $notmod }
+ global CONFIG_GPT_IRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_IRQ $CONFIG_GPT_IRQ $notmod }
+ global CONFIG_GPT_SEPIRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_SEPIRQ $CONFIG_GPT_SEPIRQ [list $notmod] 2 }
+ global CONFIG_GPT_WDOGEN
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_WDOGEN $CONFIG_GPT_WDOGEN [list $notmod] 2 }
+ global CONFIG_GPT_WDOG
+ if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {write_hex $cfg $autocfg CONFIG_GPT_WDOG $CONFIG_GPT_WDOG $notmod }
+ global CONFIG_GRGPIO_ENABLE
+ write_tristate $cfg $autocfg CONFIG_GRGPIO_ENABLE $CONFIG_GRGPIO_ENABLE [list $notmod] 2
+ global CONFIG_GRGPIO_WIDTH
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRGPIO_WIDTH $CONFIG_GRGPIO_WIDTH $notmod }
+ global CONFIG_GRGPIO_IMASK
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_GRGPIO_IMASK $CONFIG_GRGPIO_IMASK $notmod }
+ write_comment $cfg $autocfg "Serial interfaces; I2C, PS/2 and SPI "
+ global CONFIG_I2C_ENABLE
+ write_tristate $cfg $autocfg CONFIG_I2C_ENABLE $CONFIG_I2C_ENABLE [list $notmod] 2
+ global CONFIG_PS2_ENABLE
+ write_tristate $cfg $autocfg CONFIG_PS2_ENABLE $CONFIG_PS2_ENABLE [list $notmod] 2
+ write_comment $cfg $autocfg "SPI controller "
+ global CONFIG_SPICTRL_ENABLE
+ write_tristate $cfg $autocfg CONFIG_SPICTRL_ENABLE $CONFIG_SPICTRL_ENABLE [list $notmod] 2
+ global CONFIG_SPICTRL_SLVS
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPICTRL_SLVS $CONFIG_SPICTRL_SLVS $notmod }
+ global CONFIG_SPICTRL_FIFO
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPICTRL_FIFO $CONFIG_SPICTRL_FIFO $notmod }
+ global CONFIG_SPICTRL_SLVREG
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_SLVREG $CONFIG_SPICTRL_SLVREG [list $notmod] 2 }
+ global CONFIG_SPICTRL_ASEL
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_ASEL $CONFIG_SPICTRL_ASEL [list $notmod] 2 }
+ global CONFIG_SPICTRL_AM
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_AM $CONFIG_SPICTRL_AM [list $notmod] 2 }
+ global CONFIG_SPICTRL_ODMODE
+ if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_ODMODE $CONFIG_SPICTRL_ODMODE [list $notmod] 2 }
+ write_comment $cfg $autocfg "LCD and VGA DAC "
+ global CONFIG_LCD_ENABLE
+ write_tristate $cfg $autocfg CONFIG_LCD_ENABLE $CONFIG_LCD_ENABLE [list $notmod] 2
+ global CONFIG_LCD3T_ENABLE
+ write_tristate $cfg $autocfg CONFIG_LCD3T_ENABLE $CONFIG_LCD3T_ENABLE [list $notmod] 2
+ global CONFIG_SVGA_ENABLE
+ write_tristate $cfg $autocfg CONFIG_SVGA_ENABLE $CONFIG_SVGA_ENABLE [list $notmod] 2
+ write_comment $cfg $autocfg "VHDL Debugging "
+ global CONFIG_DEBUG_UART
+ write_tristate $cfg $autocfg CONFIG_DEBUG_UART $CONFIG_DEBUG_UART [list $notmod] 2
+ close $cfg
+ close $autocfg
+}
+
+
+proc clear_choices { } {
+ global CONFIG_SYN_INFERRED; set CONFIG_SYN_INFERRED 0
+ global CONFIG_SYN_STRATIX; set CONFIG_SYN_STRATIX 0
+ global CONFIG_SYN_STRATIXII; set CONFIG_SYN_STRATIXII 0
+ global CONFIG_SYN_STRATIXIII; set CONFIG_SYN_STRATIXIII 0
+ global CONFIG_SYN_CYCLONEIII; set CONFIG_SYN_CYCLONEIII 0
+ global CONFIG_SYN_ALTERA; set CONFIG_SYN_ALTERA 0
+ global CONFIG_SYN_AXCEL; set CONFIG_SYN_AXCEL 0
+ global CONFIG_SYN_AXDSP; set CONFIG_SYN_AXDSP 0
+ global CONFIG_SYN_PROASIC; set CONFIG_SYN_PROASIC 0
+ global CONFIG_SYN_PROASICPLUS; set CONFIG_SYN_PROASICPLUS 0
+ global CONFIG_SYN_PROASIC3; set CONFIG_SYN_PROASIC3 0
+ global CONFIG_SYN_IGLOO; set CONFIG_SYN_IGLOO 0
+ global CONFIG_SYN_UT025CRH; set CONFIG_SYN_UT025CRH 0
+ global CONFIG_SYN_ATC18; set CONFIG_SYN_ATC18 0
+ global CONFIG_SYN_ATC18RHA; set CONFIG_SYN_ATC18RHA 0
+ global CONFIG_SYN_CUSTOM1; set CONFIG_SYN_CUSTOM1 0
+ global CONFIG_SYN_EASIC90; set CONFIG_SYN_EASIC90 0
+ global CONFIG_SYN_IHP25; set CONFIG_SYN_IHP25 0
+ global CONFIG_SYN_IHP25RH; set CONFIG_SYN_IHP25RH 0
+ global CONFIG_SYN_LATTICE; set CONFIG_SYN_LATTICE 0
+ global CONFIG_SYN_ECLIPSE; set CONFIG_SYN_ECLIPSE 0
+ global CONFIG_SYN_PEREGRINE; set CONFIG_SYN_PEREGRINE 0
+ global CONFIG_SYN_RH_LIB18T; set CONFIG_SYN_RH_LIB18T 0
+ global CONFIG_SYN_RHUMC; set CONFIG_SYN_RHUMC 0
+ global CONFIG_SYN_SMIC13; set CONFIG_SYN_SMIC13 0
+ global CONFIG_SYN_SPARTAN2; set CONFIG_SYN_SPARTAN2 0
+ global CONFIG_SYN_SPARTAN3; set CONFIG_SYN_SPARTAN3 0
+ global CONFIG_SYN_SPARTAN3E; set CONFIG_SYN_SPARTAN3E 0
+ global CONFIG_SYN_VIRTEX; set CONFIG_SYN_VIRTEX 0
+ global CONFIG_SYN_VIRTEXE; set CONFIG_SYN_VIRTEXE 0
+ global CONFIG_SYN_VIRTEX2; set CONFIG_SYN_VIRTEX2 0
+ global CONFIG_SYN_VIRTEX4; set CONFIG_SYN_VIRTEX4 0
+ global CONFIG_SYN_VIRTEX5; set CONFIG_SYN_VIRTEX5 0
+ global CONFIG_SYN_UMC; set CONFIG_SYN_UMC 0
+ global CONFIG_SYN_TSMC90; set CONFIG_SYN_TSMC90 0
+ global CONFIG_MEM_INFERRED; set CONFIG_MEM_INFERRED 0
+ global CONFIG_MEM_UMC; set CONFIG_MEM_UMC 0
+ global CONFIG_MEM_RHUMC; set CONFIG_MEM_RHUMC 0
+ global CONFIG_MEM_ARTISAN; set CONFIG_MEM_ARTISAN 0
+ global CONFIG_MEM_CUSTOM1; set CONFIG_MEM_CUSTOM1 0
+ global CONFIG_MEM_VIRAGE; set CONFIG_MEM_VIRAGE 0
+ global CONFIG_MEM_VIRAGE90; set CONFIG_MEM_VIRAGE90 0
+ global CONFIG_CLK_INFERRED; set CONFIG_CLK_INFERRED 0
+ global CONFIG_CLK_HCLKBUF; set CONFIG_CLK_HCLKBUF 0
+ global CONFIG_CLK_ALTDLL; set CONFIG_CLK_ALTDLL 0
+ global CONFIG_CLK_LATDLL; set CONFIG_CLK_LATDLL 0
+ global CONFIG_CLK_PRO3PLL; set CONFIG_CLK_PRO3PLL 0
+ global CONFIG_CLK_LIB18T; set CONFIG_CLK_LIB18T 0
+ global CONFIG_CLK_RHUMC; set CONFIG_CLK_RHUMC 0
+ global CONFIG_CLK_CLKDLL; set CONFIG_CLK_CLKDLL 0
+ global CONFIG_CLK_DCM; set CONFIG_CLK_DCM 0
+ global CONFIG_IU_MUL_LATENCY_2; set CONFIG_IU_MUL_LATENCY_2 0
+ global CONFIG_IU_MUL_LATENCY_4; set CONFIG_IU_MUL_LATENCY_4 0
+ global CONFIG_IU_MUL_LATENCY_5; set CONFIG_IU_MUL_LATENCY_5 0
+ global CONFIG_FPU_GRFPU; set CONFIG_FPU_GRFPU 0
+ global CONFIG_FPU_GRFPULITE; set CONFIG_FPU_GRFPULITE 0
+ global CONFIG_FPU_MEIKO; set CONFIG_FPU_MEIKO 0
+ global CONFIG_FPU_GRFPU_INFMUL; set CONFIG_FPU_GRFPU_INFMUL 0
+ global CONFIG_FPU_GRFPU_DWMUL; set CONFIG_FPU_GRFPU_DWMUL 0
+ global CONFIG_FPU_GRFPU_MODGEN; set CONFIG_FPU_GRFPU_MODGEN 0
+ global CONFIG_FPU_GRFPU_TECHSPEC; set CONFIG_FPU_GRFPU_TECHSPEC 0
+ global CONFIG_FPU_GRFPC0; set CONFIG_FPU_GRFPC0 0
+ global CONFIG_FPU_GRFPC1; set CONFIG_FPU_GRFPC1 0
+ global CONFIG_FPU_GRFPC2; set CONFIG_FPU_GRFPC2 0
+ global CONFIG_ICACHE_ASSO1; set CONFIG_ICACHE_ASSO1 0
+ global CONFIG_ICACHE_ASSO2; set CONFIG_ICACHE_ASSO2 0
+ global CONFIG_ICACHE_ASSO3; set CONFIG_ICACHE_ASSO3 0
+ global CONFIG_ICACHE_ASSO4; set CONFIG_ICACHE_ASSO4 0
+ global CONFIG_ICACHE_SZ1; set CONFIG_ICACHE_SZ1 0
+ global CONFIG_ICACHE_SZ2; set CONFIG_ICACHE_SZ2 0
+ global CONFIG_ICACHE_SZ4; set CONFIG_ICACHE_SZ4 0
+ global CONFIG_ICACHE_SZ8; set CONFIG_ICACHE_SZ8 0
+ global CONFIG_ICACHE_SZ16; set CONFIG_ICACHE_SZ16 0
+ global CONFIG_ICACHE_SZ32; set CONFIG_ICACHE_SZ32 0
+ global CONFIG_ICACHE_SZ64; set CONFIG_ICACHE_SZ64 0
+ global CONFIG_ICACHE_SZ128; set CONFIG_ICACHE_SZ128 0
+ global CONFIG_ICACHE_SZ256; set CONFIG_ICACHE_SZ256 0
+ global CONFIG_ICACHE_LZ16; set CONFIG_ICACHE_LZ16 0
+ global CONFIG_ICACHE_LZ32; set CONFIG_ICACHE_LZ32 0
+ global CONFIG_ICACHE_ALGORND; set CONFIG_ICACHE_ALGORND 0
+ global CONFIG_ICACHE_ALGOLRR; set CONFIG_ICACHE_ALGOLRR 0
+ global CONFIG_ICACHE_ALGOLRU; set CONFIG_ICACHE_ALGOLRU 0
+ global CONFIG_ICACHE_LRAM_SZ1; set CONFIG_ICACHE_LRAM_SZ1 0
+ global CONFIG_ICACHE_LRAM_SZ2; set CONFIG_ICACHE_LRAM_SZ2 0
+ global CONFIG_ICACHE_LRAM_SZ4; set CONFIG_ICACHE_LRAM_SZ4 0
+ global CONFIG_ICACHE_LRAM_SZ8; set CONFIG_ICACHE_LRAM_SZ8 0
+ global CONFIG_ICACHE_LRAM_SZ16; set CONFIG_ICACHE_LRAM_SZ16 0
+ global CONFIG_ICACHE_LRAM_SZ32; set CONFIG_ICACHE_LRAM_SZ32 0
+ global CONFIG_ICACHE_LRAM_SZ64; set CONFIG_ICACHE_LRAM_SZ64 0
+ global CONFIG_ICACHE_LRAM_SZ128; set CONFIG_ICACHE_LRAM_SZ128 0
+ global CONFIG_ICACHE_LRAM_SZ256; set CONFIG_ICACHE_LRAM_SZ256 0
+ global CONFIG_DCACHE_ASSO1; set CONFIG_DCACHE_ASSO1 0
+ global CONFIG_DCACHE_ASSO2; set CONFIG_DCACHE_ASSO2 0
+ global CONFIG_DCACHE_ASSO3; set CONFIG_DCACHE_ASSO3 0
+ global CONFIG_DCACHE_ASSO4; set CONFIG_DCACHE_ASSO4 0
+ global CONFIG_DCACHE_SZ1; set CONFIG_DCACHE_SZ1 0
+ global CONFIG_DCACHE_SZ2; set CONFIG_DCACHE_SZ2 0
+ global CONFIG_DCACHE_SZ4; set CONFIG_DCACHE_SZ4 0
+ global CONFIG_DCACHE_SZ8; set CONFIG_DCACHE_SZ8 0
+ global CONFIG_DCACHE_SZ16; set CONFIG_DCACHE_SZ16 0
+ global CONFIG_DCACHE_SZ32; set CONFIG_DCACHE_SZ32 0
+ global CONFIG_DCACHE_SZ64; set CONFIG_DCACHE_SZ64 0
+ global CONFIG_DCACHE_SZ128; set CONFIG_DCACHE_SZ128 0
+ global CONFIG_DCACHE_SZ256; set CONFIG_DCACHE_SZ256 0
+ global CONFIG_DCACHE_LZ16; set CONFIG_DCACHE_LZ16 0
+ global CONFIG_DCACHE_LZ32; set CONFIG_DCACHE_LZ32 0
+ global CONFIG_DCACHE_ALGORND; set CONFIG_DCACHE_ALGORND 0
+ global CONFIG_DCACHE_ALGOLRR; set CONFIG_DCACHE_ALGOLRR 0
+ global CONFIG_DCACHE_ALGOLRU; set CONFIG_DCACHE_ALGOLRU 0
+ global CONFIG_DCACHE_LRAM_SZ1; set CONFIG_DCACHE_LRAM_SZ1 0
+ global CONFIG_DCACHE_LRAM_SZ2; set CONFIG_DCACHE_LRAM_SZ2 0
+ global CONFIG_DCACHE_LRAM_SZ4; set CONFIG_DCACHE_LRAM_SZ4 0
+ global CONFIG_DCACHE_LRAM_SZ8; set CONFIG_DCACHE_LRAM_SZ8 0
+ global CONFIG_DCACHE_LRAM_SZ16; set CONFIG_DCACHE_LRAM_SZ16 0
+ global CONFIG_DCACHE_LRAM_SZ32; set CONFIG_DCACHE_LRAM_SZ32 0
+ global CONFIG_DCACHE_LRAM_SZ64; set CONFIG_DCACHE_LRAM_SZ64 0
+ global CONFIG_DCACHE_LRAM_SZ128; set CONFIG_DCACHE_LRAM_SZ128 0
+ global CONFIG_DCACHE_LRAM_SZ256; set CONFIG_DCACHE_LRAM_SZ256 0
+ global CONFIG_MMU_COMBINED; set CONFIG_MMU_COMBINED 0
+ global CONFIG_MMU_SPLIT; set CONFIG_MMU_SPLIT 0
+ global CONFIG_MMU_REPARRAY; set CONFIG_MMU_REPARRAY 0
+ global CONFIG_MMU_REPINCREMENT; set CONFIG_MMU_REPINCREMENT 0
+ global CONFIG_MMU_I2; set CONFIG_MMU_I2 0
+ global CONFIG_MMU_I4; set CONFIG_MMU_I4 0
+ global CONFIG_MMU_I8; set CONFIG_MMU_I8 0
+ global CONFIG_MMU_I16; set CONFIG_MMU_I16 0
+ global CONFIG_MMU_I32; set CONFIG_MMU_I32 0
+ global CONFIG_MMU_D2; set CONFIG_MMU_D2 0
+ global CONFIG_MMU_D4; set CONFIG_MMU_D4 0
+ global CONFIG_MMU_D8; set CONFIG_MMU_D8 0
+ global CONFIG_MMU_D16; set CONFIG_MMU_D16 0
+ global CONFIG_MMU_D32; set CONFIG_MMU_D32 0
+ global CONFIG_MMU_PAGE_4K; set CONFIG_MMU_PAGE_4K 0
+ global CONFIG_MMU_PAGE_8K; set CONFIG_MMU_PAGE_8K 0
+ global CONFIG_MMU_PAGE_16K; set CONFIG_MMU_PAGE_16K 0
+ global CONFIG_MMU_PAGE_32K; set CONFIG_MMU_PAGE_32K 0
+ global CONFIG_MMU_PAGE_PROG; set CONFIG_MMU_PAGE_PROG 0
+ global CONFIG_DSU_ITRACESZ1; set CONFIG_DSU_ITRACESZ1 0
+ global CONFIG_DSU_ITRACESZ2; set CONFIG_DSU_ITRACESZ2 0
+ global CONFIG_DSU_ITRACESZ4; set CONFIG_DSU_ITRACESZ4 0
+ global CONFIG_DSU_ITRACESZ8; set CONFIG_DSU_ITRACESZ8 0
+ global CONFIG_DSU_ITRACESZ16; set CONFIG_DSU_ITRACESZ16 0
+ global CONFIG_DSU_ATRACESZ1; set CONFIG_DSU_ATRACESZ1 0
+ global CONFIG_DSU_ATRACESZ2; set CONFIG_DSU_ATRACESZ2 0
+ global CONFIG_DSU_ATRACESZ4; set CONFIG_DSU_ATRACESZ4 0
+ global CONFIG_DSU_ATRACESZ8; set CONFIG_DSU_ATRACESZ8 0
+ global CONFIG_DSU_ATRACESZ16; set CONFIG_DSU_ATRACESZ16 0
+ global CONFIG_DSU_ETHSZ1; set CONFIG_DSU_ETHSZ1 0
+ global CONFIG_DSU_ETHSZ2; set CONFIG_DSU_ETHSZ2 0
+ global CONFIG_DSU_ETHSZ4; set CONFIG_DSU_ETHSZ4 0
+ global CONFIG_DSU_ETHSZ8; set CONFIG_DSU_ETHSZ8 0
+ global CONFIG_DSU_ETHSZ16; set CONFIG_DSU_ETHSZ16 0
+ global CONFIG_AHBRAM_SZ1; set CONFIG_AHBRAM_SZ1 0
+ global CONFIG_AHBRAM_SZ2; set CONFIG_AHBRAM_SZ2 0
+ global CONFIG_AHBRAM_SZ4; set CONFIG_AHBRAM_SZ4 0
+ global CONFIG_AHBRAM_SZ8; set CONFIG_AHBRAM_SZ8 0
+ global CONFIG_AHBRAM_SZ16; set CONFIG_AHBRAM_SZ16 0
+ global CONFIG_AHBRAM_SZ32; set CONFIG_AHBRAM_SZ32 0
+ global CONFIG_AHBRAM_SZ64; set CONFIG_AHBRAM_SZ64 0
+ global CONFIG_GRETH_FIFO4; set CONFIG_GRETH_FIFO4 0
+ global CONFIG_GRETH_FIFO8; set CONFIG_GRETH_FIFO8 0
+ global CONFIG_GRETH_FIFO16; set CONFIG_GRETH_FIFO16 0
+ global CONFIG_GRETH_FIFO32; set CONFIG_GRETH_FIFO32 0
+ global CONFIG_GRETH_FIFO64; set CONFIG_GRETH_FIFO64 0
+ global CONFIG_UA1_FIFO1; set CONFIG_UA1_FIFO1 0
+ global CONFIG_UA1_FIFO2; set CONFIG_UA1_FIFO2 0
+ global CONFIG_UA1_FIFO4; set CONFIG_UA1_FIFO4 0
+ global CONFIG_UA1_FIFO8; set CONFIG_UA1_FIFO8 0
+ global CONFIG_UA1_FIFO16; set CONFIG_UA1_FIFO16 0
+ global CONFIG_UA1_FIFO32; set CONFIG_UA1_FIFO32 0
+}
+
+
+proc update_choices { } {
+ global tmpvar_0
+ set tmpvar_0 "Inferred"
+ global CONFIG_SYN_INFERRED
+ if { $CONFIG_SYN_INFERRED == 1 } then { set tmpvar_0 "Inferred" }
+ global CONFIG_SYN_STRATIX
+ if { $CONFIG_SYN_STRATIX == 1 } then { set tmpvar_0 "Altera-Stratix" }
+ global CONFIG_SYN_STRATIXII
+ if { $CONFIG_SYN_STRATIXII == 1 } then { set tmpvar_0 "Altera-StratixII" }
+ global CONFIG_SYN_STRATIXIII
+ if { $CONFIG_SYN_STRATIXIII == 1 } then { set tmpvar_0 "Altera-StratixIII" }
+ global CONFIG_SYN_CYCLONEIII
+ if { $CONFIG_SYN_CYCLONEIII == 1 } then { set tmpvar_0 "Altera-CycloneIII" }
+ global CONFIG_SYN_ALTERA
+ if { $CONFIG_SYN_ALTERA == 1 } then { set tmpvar_0 "Altera-Others" }
+ global CONFIG_SYN_AXCEL
+ if { $CONFIG_SYN_AXCEL == 1 } then { set tmpvar_0 "Actel-Axcelerator" }
+ global CONFIG_SYN_AXDSP
+ if { $CONFIG_SYN_AXDSP == 1 } then { set tmpvar_0 "Actel-Axcelerator-DSP" }
+ global CONFIG_SYN_PROASIC
+ if { $CONFIG_SYN_PROASIC == 1 } then { set tmpvar_0 "Actel-Proasic" }
+ global CONFIG_SYN_PROASICPLUS
+ if { $CONFIG_SYN_PROASICPLUS == 1 } then { set tmpvar_0 "Actel-ProasicPlus" }
+ global CONFIG_SYN_PROASIC3
+ if { $CONFIG_SYN_PROASIC3 == 1 } then { set tmpvar_0 "Actel-Proasic3/E/L" }
+ global CONFIG_SYN_IGLOO
+ if { $CONFIG_SYN_IGLOO == 1 } then { set tmpvar_0 "Actel-IGLOO/p/L" }
+ global CONFIG_SYN_UT025CRH
+ if { $CONFIG_SYN_UT025CRH == 1 } then { set tmpvar_0 "Aeroflex-UT025CRH" }
+ global CONFIG_SYN_ATC18
+ if { $CONFIG_SYN_ATC18 == 1 } then { set tmpvar_0 "Atmel-ATC18" }
+ global CONFIG_SYN_ATC18RHA
+ if { $CONFIG_SYN_ATC18RHA == 1 } then { set tmpvar_0 "Atmel-ATC18RHA" }
+ global CONFIG_SYN_CUSTOM1
+ if { $CONFIG_SYN_CUSTOM1 == 1 } then { set tmpvar_0 "Custom1" }
+ global CONFIG_SYN_EASIC90
+ if { $CONFIG_SYN_EASIC90 == 1 } then { set tmpvar_0 "eASIC90" }
+ global CONFIG_SYN_IHP25
+ if { $CONFIG_SYN_IHP25 == 1 } then { set tmpvar_0 "IHP25" }
+ global CONFIG_SYN_IHP25RH
+ if { $CONFIG_SYN_IHP25RH == 1 } then { set tmpvar_0 "IHP25RH" }
+ global CONFIG_SYN_LATTICE
+ if { $CONFIG_SYN_LATTICE == 1 } then { set tmpvar_0 "Lattice-EC/ECP/XP" }
+ global CONFIG_SYN_ECLIPSE
+ if { $CONFIG_SYN_ECLIPSE == 1 } then { set tmpvar_0 "Quicklogic-Eclipse" }
+ global CONFIG_SYN_PEREGRINE
+ if { $CONFIG_SYN_PEREGRINE == 1 } then { set tmpvar_0 "Peregrine" }
+ global CONFIG_SYN_RH_LIB18T
+ if { $CONFIG_SYN_RH_LIB18T == 1 } then { set tmpvar_0 "RH-LIB18T" }
+ global CONFIG_SYN_RHUMC
+ if { $CONFIG_SYN_RHUMC == 1 } then { set tmpvar_0 "RH-UMC" }
+ global CONFIG_SYN_SMIC13
+ if { $CONFIG_SYN_SMIC13 == 1 } then { set tmpvar_0 "SMIC130" }
+ global CONFIG_SYN_SPARTAN2
+ if { $CONFIG_SYN_SPARTAN2 == 1 } then { set tmpvar_0 "Xilinx-Spartan2" }
+ global CONFIG_SYN_SPARTAN3
+ if { $CONFIG_SYN_SPARTAN3 == 1 } then { set tmpvar_0 "Xilinx-Spartan3" }
+ global CONFIG_SYN_SPARTAN3E
+ if { $CONFIG_SYN_SPARTAN3E == 1 } then { set tmpvar_0 "Xilinx-Spartan3E" }
+ global CONFIG_SYN_VIRTEX
+ if { $CONFIG_SYN_VIRTEX == 1 } then { set tmpvar_0 "Xilinx-Virtex" }
+ global CONFIG_SYN_VIRTEXE
+ if { $CONFIG_SYN_VIRTEXE == 1 } then { set tmpvar_0 "Xilinx-VirtexE" }
+ global CONFIG_SYN_VIRTEX2
+ if { $CONFIG_SYN_VIRTEX2 == 1 } then { set tmpvar_0 "Xilinx-Virtex2" }
+ global CONFIG_SYN_VIRTEX4
+ if { $CONFIG_SYN_VIRTEX4 == 1 } then { set tmpvar_0 "Xilinx-Virtex4" }
+ global CONFIG_SYN_VIRTEX5
+ if { $CONFIG_SYN_VIRTEX5 == 1 } then { set tmpvar_0 "Xilinx-Virtex5" }
+ global CONFIG_SYN_UMC
+ if { $CONFIG_SYN_UMC == 1 } then { set tmpvar_0 "UMC180" }
+ global CONFIG_SYN_TSMC90
+ if { $CONFIG_SYN_TSMC90 == 1 } then { set tmpvar_0 "TSMC90" }
+ global tmpvar_1
+ set tmpvar_1 "Inferred"
+ global CONFIG_MEM_INFERRED
+ if { $CONFIG_MEM_INFERRED == 1 } then { set tmpvar_1 "Inferred" }
+ global CONFIG_MEM_UMC
+ if { $CONFIG_MEM_UMC == 1 } then { set tmpvar_1 "UMC18" }
+ global CONFIG_MEM_RHUMC
+ if { $CONFIG_MEM_RHUMC == 1 } then { set tmpvar_1 "RH-UMC" }
+ global CONFIG_MEM_ARTISAN
+ if { $CONFIG_MEM_ARTISAN == 1 } then { set tmpvar_1 "Artisan" }
+ global CONFIG_MEM_CUSTOM1
+ if { $CONFIG_MEM_CUSTOM1 == 1 } then { set tmpvar_1 "Custom1" }
+ global CONFIG_MEM_VIRAGE
+ if { $CONFIG_MEM_VIRAGE == 1 } then { set tmpvar_1 "Virage" }
+ global CONFIG_MEM_VIRAGE90
+ if { $CONFIG_MEM_VIRAGE90 == 1 } then { set tmpvar_1 "Virage-TSMC90" }
+ global tmpvar_2
+ set tmpvar_2 "Inferred"
+ global CONFIG_CLK_INFERRED
+ if { $CONFIG_CLK_INFERRED == 1 } then { set tmpvar_2 "Inferred" }
+ global CONFIG_CLK_HCLKBUF
+ if { $CONFIG_CLK_HCLKBUF == 1 } then { set tmpvar_2 "Actel-HCLKBUF" }
+ global CONFIG_CLK_ALTDLL
+ if { $CONFIG_CLK_ALTDLL == 1 } then { set tmpvar_2 "Altera-ALTPLL" }
+ global CONFIG_CLK_LATDLL
+ if { $CONFIG_CLK_LATDLL == 1 } then { set tmpvar_2 "Lattice-EXPLL" }
+ global CONFIG_CLK_PRO3PLL
+ if { $CONFIG_CLK_PRO3PLL == 1 } then { set tmpvar_2 "Proasic3-PLLL" }
+ global CONFIG_CLK_LIB18T
+ if { $CONFIG_CLK_LIB18T == 1 } then { set tmpvar_2 "RH-LIB18T-PLL" }
+ global CONFIG_CLK_RHUMC
+ if { $CONFIG_CLK_RHUMC == 1 } then { set tmpvar_2 "DARE-PLL" }
+ global CONFIG_CLK_CLKDLL
+ if { $CONFIG_CLK_CLKDLL == 1 } then { set tmpvar_2 "Xilinx-CLKDLL" }
+ global CONFIG_CLK_DCM
+ if { $CONFIG_CLK_DCM == 1 } then { set tmpvar_2 "Xilinx-DCM" }
+ global tmpvar_3
+ set tmpvar_3 "5-cycles"
+ global CONFIG_IU_MUL_LATENCY_2
+ if { $CONFIG_IU_MUL_LATENCY_2 == 1 } then { set tmpvar_3 "2-cycles" }
+ global CONFIG_IU_MUL_LATENCY_4
+ if { $CONFIG_IU_MUL_LATENCY_4 == 1 } then { set tmpvar_3 "4-cycles" }
+ global CONFIG_IU_MUL_LATENCY_5
+ if { $CONFIG_IU_MUL_LATENCY_5 == 1 } then { set tmpvar_3 "5-cycles" }
+ global tmpvar_4
+ set tmpvar_4 "GRFPU"
+ global CONFIG_FPU_GRFPU
+ if { $CONFIG_FPU_GRFPU == 1 } then { set tmpvar_4 "GRFPU" }
+ global CONFIG_FPU_GRFPULITE
+ if { $CONFIG_FPU_GRFPULITE == 1 } then { set tmpvar_4 "GRFPU-LITE" }
+ global CONFIG_FPU_MEIKO
+ if { $CONFIG_FPU_MEIKO == 1 } then { set tmpvar_4 "Meiko" }
+ global tmpvar_5
+ set tmpvar_5 "Inferred"
+ global CONFIG_FPU_GRFPU_INFMUL
+ if { $CONFIG_FPU_GRFPU_INFMUL == 1 } then { set tmpvar_5 "Inferred" }
+ global CONFIG_FPU_GRFPU_DWMUL
+ if { $CONFIG_FPU_GRFPU_DWMUL == 1 } then { set tmpvar_5 "DW" }
+ global CONFIG_FPU_GRFPU_MODGEN
+ if { $CONFIG_FPU_GRFPU_MODGEN == 1 } then { set tmpvar_5 "ModGen" }
+ global CONFIG_FPU_GRFPU_TECHSPEC
+ if { $CONFIG_FPU_GRFPU_TECHSPEC == 1 } then { set tmpvar_5 "TechSpec" }
+ global tmpvar_6
+ set tmpvar_6 "Simple"
+ global CONFIG_FPU_GRFPC0
+ if { $CONFIG_FPU_GRFPC0 == 1 } then { set tmpvar_6 "Simple" }
+ global CONFIG_FPU_GRFPC1
+ if { $CONFIG_FPU_GRFPC1 == 1 } then { set tmpvar_6 "Data-forwarding" }
+ global CONFIG_FPU_GRFPC2
+ if { $CONFIG_FPU_GRFPC2 == 1 } then { set tmpvar_6 "Non-blocking" }
+ global tmpvar_7
+ set tmpvar_7 "1"
+ global CONFIG_ICACHE_ASSO1
+ if { $CONFIG_ICACHE_ASSO1 == 1 } then { set tmpvar_7 "1" }
+ global CONFIG_ICACHE_ASSO2
+ if { $CONFIG_ICACHE_ASSO2 == 1 } then { set tmpvar_7 "2" }
+ global CONFIG_ICACHE_ASSO3
+ if { $CONFIG_ICACHE_ASSO3 == 1 } then { set tmpvar_7 "3" }
+ global CONFIG_ICACHE_ASSO4
+ if { $CONFIG_ICACHE_ASSO4 == 1 } then { set tmpvar_7 "4" }
+ global tmpvar_8
+ set tmpvar_8 "4"
+ global CONFIG_ICACHE_SZ1
+ if { $CONFIG_ICACHE_SZ1 == 1 } then { set tmpvar_8 "1" }
+ global CONFIG_ICACHE_SZ2
+ if { $CONFIG_ICACHE_SZ2 == 1 } then { set tmpvar_8 "2" }
+ global CONFIG_ICACHE_SZ4
+ if { $CONFIG_ICACHE_SZ4 == 1 } then { set tmpvar_8 "4" }
+ global CONFIG_ICACHE_SZ8
+ if { $CONFIG_ICACHE_SZ8 == 1 } then { set tmpvar_8 "8" }
+ global CONFIG_ICACHE_SZ16
+ if { $CONFIG_ICACHE_SZ16 == 1 } then { set tmpvar_8 "16" }
+ global CONFIG_ICACHE_SZ32
+ if { $CONFIG_ICACHE_SZ32 == 1 } then { set tmpvar_8 "32" }
+ global CONFIG_ICACHE_SZ64
+ if { $CONFIG_ICACHE_SZ64 == 1 } then { set tmpvar_8 "64" }
+ global CONFIG_ICACHE_SZ128
+ if { $CONFIG_ICACHE_SZ128 == 1 } then { set tmpvar_8 "128" }
+ global CONFIG_ICACHE_SZ256
+ if { $CONFIG_ICACHE_SZ256 == 1 } then { set tmpvar_8 "256" }
+ global tmpvar_9
+ set tmpvar_9 "32"
+ global CONFIG_ICACHE_LZ16
+ if { $CONFIG_ICACHE_LZ16 == 1 } then { set tmpvar_9 "16" }
+ global CONFIG_ICACHE_LZ32
+ if { $CONFIG_ICACHE_LZ32 == 1 } then { set tmpvar_9 "32" }
+ global tmpvar_10
+ set tmpvar_10 "Random"
+ global CONFIG_ICACHE_ALGORND
+ if { $CONFIG_ICACHE_ALGORND == 1 } then { set tmpvar_10 "Random" }
+ global CONFIG_ICACHE_ALGOLRR
+ if { $CONFIG_ICACHE_ALGOLRR == 1 } then { set tmpvar_10 "LRR" }
+ global CONFIG_ICACHE_ALGOLRU
+ if { $CONFIG_ICACHE_ALGOLRU == 1 } then { set tmpvar_10 "LRU" }
+ global tmpvar_11
+ set tmpvar_11 "4"
+ global CONFIG_ICACHE_LRAM_SZ1
+ if { $CONFIG_ICACHE_LRAM_SZ1 == 1 } then { set tmpvar_11 "1" }
+ global CONFIG_ICACHE_LRAM_SZ2
+ if { $CONFIG_ICACHE_LRAM_SZ2 == 1 } then { set tmpvar_11 "2" }
+ global CONFIG_ICACHE_LRAM_SZ4
+ if { $CONFIG_ICACHE_LRAM_SZ4 == 1 } then { set tmpvar_11 "4" }
+ global CONFIG_ICACHE_LRAM_SZ8
+ if { $CONFIG_ICACHE_LRAM_SZ8 == 1 } then { set tmpvar_11 "8" }
+ global CONFIG_ICACHE_LRAM_SZ16
+ if { $CONFIG_ICACHE_LRAM_SZ16 == 1 } then { set tmpvar_11 "16" }
+ global CONFIG_ICACHE_LRAM_SZ32
+ if { $CONFIG_ICACHE_LRAM_SZ32 == 1 } then { set tmpvar_11 "32" }
+ global CONFIG_ICACHE_LRAM_SZ64
+ if { $CONFIG_ICACHE_LRAM_SZ64 == 1 } then { set tmpvar_11 "64" }
+ global CONFIG_ICACHE_LRAM_SZ128
+ if { $CONFIG_ICACHE_LRAM_SZ128 == 1 } then { set tmpvar_11 "128" }
+ global CONFIG_ICACHE_LRAM_SZ256
+ if { $CONFIG_ICACHE_LRAM_SZ256 == 1 } then { set tmpvar_11 "256" }
+ global tmpvar_12
+ set tmpvar_12 "1"
+ global CONFIG_DCACHE_ASSO1
+ if { $CONFIG_DCACHE_ASSO1 == 1 } then { set tmpvar_12 "1" }
+ global CONFIG_DCACHE_ASSO2
+ if { $CONFIG_DCACHE_ASSO2 == 1 } then { set tmpvar_12 "2" }
+ global CONFIG_DCACHE_ASSO3
+ if { $CONFIG_DCACHE_ASSO3 == 1 } then { set tmpvar_12 "3" }
+ global CONFIG_DCACHE_ASSO4
+ if { $CONFIG_DCACHE_ASSO4 == 1 } then { set tmpvar_12 "4" }
+ global tmpvar_13
+ set tmpvar_13 "4"
+ global CONFIG_DCACHE_SZ1
+ if { $CONFIG_DCACHE_SZ1 == 1 } then { set tmpvar_13 "1" }
+ global CONFIG_DCACHE_SZ2
+ if { $CONFIG_DCACHE_SZ2 == 1 } then { set tmpvar_13 "2" }
+ global CONFIG_DCACHE_SZ4
+ if { $CONFIG_DCACHE_SZ4 == 1 } then { set tmpvar_13 "4" }
+ global CONFIG_DCACHE_SZ8
+ if { $CONFIG_DCACHE_SZ8 == 1 } then { set tmpvar_13 "8" }
+ global CONFIG_DCACHE_SZ16
+ if { $CONFIG_DCACHE_SZ16 == 1 } then { set tmpvar_13 "16" }
+ global CONFIG_DCACHE_SZ32
+ if { $CONFIG_DCACHE_SZ32 == 1 } then { set tmpvar_13 "32" }
+ global CONFIG_DCACHE_SZ64
+ if { $CONFIG_DCACHE_SZ64 == 1 } then { set tmpvar_13 "64" }
+ global CONFIG_DCACHE_SZ128
+ if { $CONFIG_DCACHE_SZ128 == 1 } then { set tmpvar_13 "128" }
+ global CONFIG_DCACHE_SZ256
+ if { $CONFIG_DCACHE_SZ256 == 1 } then { set tmpvar_13 "256" }
+ global tmpvar_14
+ set tmpvar_14 "32"
+ global CONFIG_DCACHE_LZ16
+ if { $CONFIG_DCACHE_LZ16 == 1 } then { set tmpvar_14 "16" }
+ global CONFIG_DCACHE_LZ32
+ if { $CONFIG_DCACHE_LZ32 == 1 } then { set tmpvar_14 "32" }
+ global tmpvar_15
+ set tmpvar_15 "Random"
+ global CONFIG_DCACHE_ALGORND
+ if { $CONFIG_DCACHE_ALGORND == 1 } then { set tmpvar_15 "Random" }
+ global CONFIG_DCACHE_ALGOLRR
+ if { $CONFIG_DCACHE_ALGOLRR == 1 } then { set tmpvar_15 "LRR" }
+ global CONFIG_DCACHE_ALGOLRU
+ if { $CONFIG_DCACHE_ALGOLRU == 1 } then { set tmpvar_15 "LRU" }
+ global tmpvar_16
+ set tmpvar_16 "4"
+ global CONFIG_DCACHE_LRAM_SZ1
+ if { $CONFIG_DCACHE_LRAM_SZ1 == 1 } then { set tmpvar_16 "1" }
+ global CONFIG_DCACHE_LRAM_SZ2
+ if { $CONFIG_DCACHE_LRAM_SZ2 == 1 } then { set tmpvar_16 "2" }
+ global CONFIG_DCACHE_LRAM_SZ4
+ if { $CONFIG_DCACHE_LRAM_SZ4 == 1 } then { set tmpvar_16 "4" }
+ global CONFIG_DCACHE_LRAM_SZ8
+ if { $CONFIG_DCACHE_LRAM_SZ8 == 1 } then { set tmpvar_16 "8" }
+ global CONFIG_DCACHE_LRAM_SZ16
+ if { $CONFIG_DCACHE_LRAM_SZ16 == 1 } then { set tmpvar_16 "16" }
+ global CONFIG_DCACHE_LRAM_SZ32
+ if { $CONFIG_DCACHE_LRAM_SZ32 == 1 } then { set tmpvar_16 "32" }
+ global CONFIG_DCACHE_LRAM_SZ64
+ if { $CONFIG_DCACHE_LRAM_SZ64 == 1 } then { set tmpvar_16 "64" }
+ global CONFIG_DCACHE_LRAM_SZ128
+ if { $CONFIG_DCACHE_LRAM_SZ128 == 1 } then { set tmpvar_16 "128" }
+ global CONFIG_DCACHE_LRAM_SZ256
+ if { $CONFIG_DCACHE_LRAM_SZ256 == 1 } then { set tmpvar_16 "256" }
+ global tmpvar_17
+ set tmpvar_17 "combined"
+ global CONFIG_MMU_COMBINED
+ if { $CONFIG_MMU_COMBINED == 1 } then { set tmpvar_17 "combined" }
+ global CONFIG_MMU_SPLIT
+ if { $CONFIG_MMU_SPLIT == 1 } then { set tmpvar_17 "split" }
+ global tmpvar_18
+ set tmpvar_18 "Increment"
+ global CONFIG_MMU_REPARRAY
+ if { $CONFIG_MMU_REPARRAY == 1 } then { set tmpvar_18 "LRU" }
+ global CONFIG_MMU_REPINCREMENT
+ if { $CONFIG_MMU_REPINCREMENT == 1 } then { set tmpvar_18 "Increment" }
+ global tmpvar_19
+ set tmpvar_19 "8"
+ global CONFIG_MMU_I2
+ if { $CONFIG_MMU_I2 == 1 } then { set tmpvar_19 "2" }
+ global CONFIG_MMU_I4
+ if { $CONFIG_MMU_I4 == 1 } then { set tmpvar_19 "4" }
+ global CONFIG_MMU_I8
+ if { $CONFIG_MMU_I8 == 1 } then { set tmpvar_19 "8" }
+ global CONFIG_MMU_I16
+ if { $CONFIG_MMU_I16 == 1 } then { set tmpvar_19 "16" }
+ global CONFIG_MMU_I32
+ if { $CONFIG_MMU_I32 == 1 } then { set tmpvar_19 "32" }
+ global tmpvar_20
+ set tmpvar_20 "8"
+ global CONFIG_MMU_D2
+ if { $CONFIG_MMU_D2 == 1 } then { set tmpvar_20 "2" }
+ global CONFIG_MMU_D4
+ if { $CONFIG_MMU_D4 == 1 } then { set tmpvar_20 "4" }
+ global CONFIG_MMU_D8
+ if { $CONFIG_MMU_D8 == 1 } then { set tmpvar_20 "8" }
+ global CONFIG_MMU_D16
+ if { $CONFIG_MMU_D16 == 1 } then { set tmpvar_20 "16" }
+ global CONFIG_MMU_D32
+ if { $CONFIG_MMU_D32 == 1 } then { set tmpvar_20 "32" }
+ global tmpvar_21
+ set tmpvar_21 "4K"
+ global CONFIG_MMU_PAGE_4K
+ if { $CONFIG_MMU_PAGE_4K == 1 } then { set tmpvar_21 "4K" }
+ global CONFIG_MMU_PAGE_8K
+ if { $CONFIG_MMU_PAGE_8K == 1 } then { set tmpvar_21 "8K" }
+ global CONFIG_MMU_PAGE_16K
+ if { $CONFIG_MMU_PAGE_16K == 1 } then { set tmpvar_21 "16K" }
+ global CONFIG_MMU_PAGE_32K
+ if { $CONFIG_MMU_PAGE_32K == 1 } then { set tmpvar_21 "32K" }
+ global CONFIG_MMU_PAGE_PROG
+ if { $CONFIG_MMU_PAGE_PROG == 1 } then { set tmpvar_21 "Programmable" }
+ global tmpvar_22
+ set tmpvar_22 "1"
+ global CONFIG_DSU_ITRACESZ1
+ if { $CONFIG_DSU_ITRACESZ1 == 1 } then { set tmpvar_22 "1" }
+ global CONFIG_DSU_ITRACESZ2
+ if { $CONFIG_DSU_ITRACESZ2 == 1 } then { set tmpvar_22 "2" }
+ global CONFIG_DSU_ITRACESZ4
+ if { $CONFIG_DSU_ITRACESZ4 == 1 } then { set tmpvar_22 "4" }
+ global CONFIG_DSU_ITRACESZ8
+ if { $CONFIG_DSU_ITRACESZ8 == 1 } then { set tmpvar_22 "8" }
+ global CONFIG_DSU_ITRACESZ16
+ if { $CONFIG_DSU_ITRACESZ16 == 1 } then { set tmpvar_22 "16" }
+ global tmpvar_23
+ set tmpvar_23 "1"
+ global CONFIG_DSU_ATRACESZ1
+ if { $CONFIG_DSU_ATRACESZ1 == 1 } then { set tmpvar_23 "1" }
+ global CONFIG_DSU_ATRACESZ2
+ if { $CONFIG_DSU_ATRACESZ2 == 1 } then { set tmpvar_23 "2" }
+ global CONFIG_DSU_ATRACESZ4
+ if { $CONFIG_DSU_ATRACESZ4 == 1 } then { set tmpvar_23 "4" }
+ global CONFIG_DSU_ATRACESZ8
+ if { $CONFIG_DSU_ATRACESZ8 == 1 } then { set tmpvar_23 "8" }
+ global CONFIG_DSU_ATRACESZ16
+ if { $CONFIG_DSU_ATRACESZ16 == 1 } then { set tmpvar_23 "16" }
+ global tmpvar_25
+ set tmpvar_25 "2"
+ global CONFIG_DSU_ETHSZ1
+ if { $CONFIG_DSU_ETHSZ1 == 1 } then { set tmpvar_25 "1" }
+ global CONFIG_DSU_ETHSZ2
+ if { $CONFIG_DSU_ETHSZ2 == 1 } then { set tmpvar_25 "2" }
+ global CONFIG_DSU_ETHSZ4
+ if { $CONFIG_DSU_ETHSZ4 == 1 } then { set tmpvar_25 "4" }
+ global CONFIG_DSU_ETHSZ8
+ if { $CONFIG_DSU_ETHSZ8 == 1 } then { set tmpvar_25 "8" }
+ global CONFIG_DSU_ETHSZ16
+ if { $CONFIG_DSU_ETHSZ16 == 1 } then { set tmpvar_25 "16" }
+ global tmpvar_26
+ set tmpvar_26 "4"
+ global CONFIG_AHBRAM_SZ1
+ if { $CONFIG_AHBRAM_SZ1 == 1 } then { set tmpvar_26 "1" }
+ global CONFIG_AHBRAM_SZ2
+ if { $CONFIG_AHBRAM_SZ2 == 1 } then { set tmpvar_26 "2" }
+ global CONFIG_AHBRAM_SZ4
+ if { $CONFIG_AHBRAM_SZ4 == 1 } then { set tmpvar_26 "4" }
+ global CONFIG_AHBRAM_SZ8
+ if { $CONFIG_AHBRAM_SZ8 == 1 } then { set tmpvar_26 "8" }
+ global CONFIG_AHBRAM_SZ16
+ if { $CONFIG_AHBRAM_SZ16 == 1 } then { set tmpvar_26 "16" }
+ global CONFIG_AHBRAM_SZ32
+ if { $CONFIG_AHBRAM_SZ32 == 1 } then { set tmpvar_26 "32" }
+ global CONFIG_AHBRAM_SZ64
+ if { $CONFIG_AHBRAM_SZ64 == 1 } then { set tmpvar_26 "64" }
+ global tmpvar_27
+ set tmpvar_27 "8"
+ global CONFIG_GRETH_FIFO4
+ if { $CONFIG_GRETH_FIFO4 == 1 } then { set tmpvar_27 "4" }
+ global CONFIG_GRETH_FIFO8
+ if { $CONFIG_GRETH_FIFO8 == 1 } then { set tmpvar_27 "8" }
+ global CONFIG_GRETH_FIFO16
+ if { $CONFIG_GRETH_FIFO16 == 1 } then { set tmpvar_27 "16" }
+ global CONFIG_GRETH_FIFO32
+ if { $CONFIG_GRETH_FIFO32 == 1 } then { set tmpvar_27 "32" }
+ global CONFIG_GRETH_FIFO64
+ if { $CONFIG_GRETH_FIFO64 == 1 } then { set tmpvar_27 "64" }
+ global tmpvar_28
+ set tmpvar_28 "1"
+ global CONFIG_UA1_FIFO1
+ if { $CONFIG_UA1_FIFO1 == 1 } then { set tmpvar_28 "1" }
+ global CONFIG_UA1_FIFO2
+ if { $CONFIG_UA1_FIFO2 == 1 } then { set tmpvar_28 "2" }
+ global CONFIG_UA1_FIFO4
+ if { $CONFIG_UA1_FIFO4 == 1 } then { set tmpvar_28 "4" }
+ global CONFIG_UA1_FIFO8
+ if { $CONFIG_UA1_FIFO8 == 1 } then { set tmpvar_28 "8" }
+ global CONFIG_UA1_FIFO16
+ if { $CONFIG_UA1_FIFO16 == 1 } then { set tmpvar_28 "16" }
+ global CONFIG_UA1_FIFO32
+ if { $CONFIG_UA1_FIFO32 == 1 } then { set tmpvar_28 "32" }
+}
+
+
+proc update_define_mainmenu {} {
+ global CONFIG_MODULES
+}
+
+
+# FILE: tail.tk
+# This file is boilerplate TCL/TK function definitions for 'make xconfig'.
+#
+# CHANGES
+# =======
+#
+# 8 January 1998, Michael Elizabeth Chastain, <mec@shout.net>
+# Arrange buttons in three columns for better screen fitting.
+#
+
+#
+# Read the user's settings from .config. These will override whatever is
+# in config.in. Don't do this if the user specified a -D to force
+# the defaults.
+#
+
+set defaults defconfig
+
+if { [file readable .config] == 1} then {
+ if { $argc > 0 } then {
+ if { [lindex $argv 0] != "-D" } then {
+ read_config .config
+ }
+ else
+ {
+ read_config $defaults
+ }
+ } else {
+ read_config .config
+ }
+} else {
+ read_config $defaults
+}
+
+update_define 1 $total_menus 0
+update_mainmenu
+
+button .f0.right.save -anchor w -text "Save and Exit" -underline 0\
+ -command { catch {exec cp -f .config .config.old}; \
+ writeconfig .config config.h; wrapup .wrap }
+
+button .f0.right.quit -anchor w -text "Quit Without Saving" -underline 0\
+ -command { maybe_exit .maybe }
+
+button .f0.right.load -anchor w -text "Load Configuration from File" \
+ -command { load_configfile .load "Load Configuration from file" read_config_file
+}
+
+button .f0.right.store -anchor w -text "Store Configuration to File" \
+ -command { load_configfile .load "Store Configuration to file" write_config_file }
+
+#
+# Now pack everything.
+#
+
+pack .f0.right.store .f0.right.load .f0.right.quit .f0.right.save \
+ -padx 0 -pady 0 -side bottom -fill x
+pack .f0.left .f0.middle .f0.right -side left -padx 5 -pady 0 -fill y
+pack .f0 -padx 5 -pady 5
+
+update idletasks
+set winy [expr 10 + [winfo reqheight .f0]]
+set scry [lindex [wm maxsize .] 1]
+set winx [expr 10 + [winfo reqwidth .f0]]
+set scrx [lindex [wm maxsize .] 0]
+if {$winx < $scrx} then {set maxx -1} else {set maxx $winx}
+if {$winy < $scry} then {set maxy -1} else {set maxy $winy}
+.f0 configure -width $winx -height $winy
+wm maxsize . $maxx $maxy
+
+#
+# If we cannot write our config files, disable the write button.
+#
+if { [file exists .config] == 1 } then {
+ if { [file writable .config] == 0 } then {
+ .f0.right.save configure -state disabled
+ }
+ } else {
+ if { [file writable .] == 0 } then {
+ .f0.right.save configure -state disabled
+ }
+ }
+
+#if { [file exists include/linux/autoconf.h] == 1 } then {
+# if { [file writable include/linux/autoconf.h] == 0 } then {
+# .f0.right.save configure -state disabled
+# }
+# } else {
+# if { [file writable include/linux/] == 0 } then {
+# .f0.right.save configure -state disabled
+# }
+# }
--- /dev/null
+<sld_project_info>
+ <hub_info ir_width="8" node_count="1"/>
+ <node_info>
+ <node hpath="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" instance_id="0" mfg_id="110" node_id="8" sld_node_info="0x406E00" version="0">
+ <parameters>
+ <parameter name="sld_mfg_id" type="dec" value="110"/>
+ <parameter name="sld_type_id" type="dec" value="8"/>
+ <parameter name="sld_version" type="dec" value="0"/>
+ <parameter name="sld_instance_index" type="dec" value="0"/>
+ <parameter name="sld_auto_instance_index" type="string" value="NO"/>
+ <parameter name="sld_ir_width" type="dec" value="8"/>
+ <parameter name="SLD_NODE_INFO" type="dec" value="4222464"/>
+ </parameters>
+ <inputs>
+ <port name="usr_tdo" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|tdo"/>
+ <port name="usr_ir_out[0]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[0]"/>
+ <port name="usr_ir_out[1]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[1]"/>
+ <port name="usr_ir_out[2]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[2]"/>
+ <port name="usr_ir_out[3]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[3]"/>
+ <port name="usr_ir_out[4]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[4]"/>
+ <port name="usr_ir_out[5]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[5]"/>
+ <port name="usr_ir_out[6]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[6]"/>
+ <port name="usr_ir_out[7]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[7]"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_raw_tck" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_raw_tck"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_raw_tms" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_raw_tms"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_tdi" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_tdi"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_tlr" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_tlr"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_rti" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_rti"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_sdrs" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_sdrs"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_cdr" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_cdr"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_sdr" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_sdr"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_e1dr" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_e1dr"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_pdr" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_pdr"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_e2dr" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_e2dr"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_udr" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_udr"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_sirs" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_sirs"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_cir" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_cir"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_sir" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_sir"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_e1ir" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_e1ir"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_pir" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_pir"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_e2ir" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_e2ir"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_uir" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_jtag_state_uir"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_usr1" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_usr1"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_clr" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_clr"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ena" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ena"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_0_" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_0_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_1_" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_1_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_2_" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_2_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_3_" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_3_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_4_" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_4_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_5_" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_5_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_6_" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_6_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_7_" source="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_in_7_"/>
+ </inputs>
+ <outputs>
+ <port name="usr_tck"/>
+ <port name="usr_tdi"/>
+ <port name="usr_ir_in[0]"/>
+ <port name="usr_ir_in[1]"/>
+ <port name="usr_ir_in[2]"/>
+ <port name="usr_ir_in[3]"/>
+ <port name="usr_ir_in[4]"/>
+ <port name="usr_ir_in[5]"/>
+ <port name="usr_ir_in[6]"/>
+ <port name="usr_ir_in[7]"/>
+ <port name="usr_virtual_state_cdr"/>
+ <port name="usr_virtual_state_sdr"/>
+ <port name="usr_virtual_state_e1dr"/>
+ <port name="usr_virtual_state_pdr"/>
+ <port name="usr_virtual_state_e2dr"/>
+ <port name="usr_virtual_state_udr"/>
+ <port name="usr_virtual_state_cir"/>
+ <port name="usr_virtual_state_uir"/>
+ <port name="usr_tms"/>
+ <port name="usr_jtag_state_tlr"/>
+ <port name="usr_jtag_state_rti"/>
+ <port name="usr_jtag_state_sdrs"/>
+ <port name="usr_jtag_state_cdr"/>
+ <port name="usr_jtag_state_sdr"/>
+ <port name="usr_jtag_state_e1dr"/>
+ <port name="usr_jtag_state_pdr"/>
+ <port name="usr_jtag_state_e2dr"/>
+ <port name="usr_jtag_state_udr"/>
+ <port name="usr_jtag_state_sirs"/>
+ <port name="usr_jtag_state_cir"/>
+ <port name="usr_jtag_state_sir"/>
+ <port name="usr_jtag_state_e1ir"/>
+ <port name="usr_jtag_state_pir"/>
+ <port name="usr_jtag_state_e2ir"/>
+ <port name="usr_jtag_state_uir"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_tdo"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_out_0_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_out_1_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_out_2_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_out_3_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_out_4_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_out_5_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_out_6_"/>
+ <port name="jtag.bp._ahbjtaggen0_ahbjtag0_tap0__alt_u0_u0_sld_virtual_jtag_basic_inst_sld_virtual_jtag_impl_inst_ir_out_7_"/>
+ </outputs>
+ </node>
+ </node_info>
+</sld_project_info>
--- /dev/null
+------------------------------------------------------------------------------
+-- LEON3 Demonstration design
+-- Copyright (C) 2008 Jiri Gaisler, Gaisler Research
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+library techmap;
+use techmap.gencomp.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+use gaisler.net.all;
+use gaisler.ata.all;
+use gaisler.jtag.all;
+library esa;
+use esa.memoryctrl.all;
+
+library kuri;
+use kuri.mjpeg.all;
+
+use work.config.all;
+
+entity leon3mp is
+ generic (
+ fabtech : integer := CFG_FABTECH;
+ memtech : integer := CFG_MEMTECH;
+ padtech : integer := CFG_PADTECH;
+ clktech : integer := CFG_CLKTECH;
+ ncpu : integer := CFG_NCPU;
+ disas : integer := CFG_DISAS; -- Enable disassembly to console
+ dbguart : integer := CFG_DUART; -- Print UART on console
+ pclow : integer := CFG_PCLOW;
+ freq : integer := 50000 -- frequency of main clock (used for PLLs)
+ );
+ port (
+ resetn : in std_ulogic;
+ clk : in std_ulogic;
+ errorn : out std_ulogic;
+
+ -- flash/ssram bus
+ address : out std_logic_vector(25 downto 1);
+ data : inout std_logic_vector(31 downto 0);
+ romsn : out std_ulogic;
+ oen : out std_logic;
+ writen : out std_logic;
+ rstoutn : out std_ulogic;
+ ssram_cen : out std_logic;
+ ssram_wen : out std_logic;
+ ssram_bw : out std_logic_vector (0 to 3);
+ ssram_oen : out std_ulogic;
+ ssram_clk : out std_ulogic;
+ ssram_adscn : out std_ulogic;
+-- ssram_adsp_n : out std_ulogic;
+-- ssram_adv_n : out std_ulogic;
+
+-- pragma translate_off
+ iosn : out std_ulogic;
+-- pragma translate_on
+
+ -- DDR
+ ddr_clk : out std_logic;
+ ddr_clkn : out std_logic;
+ ddr_cke : out std_logic;
+ ddr_csb : out std_logic;
+ ddr_web : out std_ulogic; -- ddr write enable
+ ddr_rasb : out std_ulogic; -- ddr ras
+ ddr_casb : out std_ulogic; -- ddr cas
+ ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
+ ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
+ ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
+ ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
+ ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
+
+ -- debug support unit
+ dsubren : in std_ulogic;
+ dsuact : out std_ulogic;
+
+ -- I/O port
+ gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
+
+ -- Connections over HSMC connector
+ -- LCD touch panel display
+ hc_vd : out std_logic;
+ hc_hd : out std_logic;
+ hc_den : out std_logic;
+ hc_nclk : out std_logic;
+ hc_lcd_data : out std_logic_vector(7 downto 0);
+ hc_grest : out std_logic;
+ hc_scen : out std_logic;
+ hc_sda : inout std_logic;
+ hc_adc_penirq_n : in std_logic;
+ hc_adc_dout : in std_logic;
+ hc_adc_busy : in std_logic;
+ hc_adc_din : out std_logic;
+ hc_adc_dclk : out std_logic;
+ hc_adc_cs_n : out std_logic; -- Shared with video decoder
+
+ -- Shared by video decoder and audio codec
+ hc_i2c_sclk : out std_logic;
+ hc_i2c_sdat : inout std_logic;
+
+ -- Video decoder
+ hc_td_d : inout std_logic_vector(7 downto 0);
+ hc_td_hs : in std_logic;
+ hc_td_vs : in std_logic;
+ hc_td_27mhz : in std_logic;
+ hc_td_reset : out std_logic;
+
+ -- Audio codec
+ hc_aud_adclrck : out std_logic;
+ hc_aud_adcdat : in std_logic;
+ hc_aud_daclrck : out std_logic;
+ hc_aud_dacdat : out std_logic;
+ hc_aud_bclk : out std_logic;
+ hc_aud_xck : out std_logic;
+
+ -- SD card
+ hc_sd_dat : inout std_logic;
+ hc_sd_dat3 : inout std_logic;
+ hc_sd_cmd : inout std_logic;
+ hc_sd_clk : inout std_logic;
+
+ -- Ethernet PHY
+ hc_tx_d : out std_logic_vector(3 downto 0);
+ hc_rx_d : in std_logic_vector(3 downto 0);
+ hc_tx_clk : in std_logic;
+ hc_rx_clk : in std_logic;
+ hc_tx_en : out std_logic;
+ hc_rx_dv : in std_logic;
+ hc_rx_crs : in std_logic;
+ hc_rx_err : in std_logic;
+ hc_rx_col : in std_logic;
+ hc_mdio : inout std_logic;
+ hc_mdc : out std_logic;
+ hc_eth_reset_n : out std_logic;
+
+ -- RX232 (console/debug UART)
+ hc_uart_rxd : in std_logic;
+ hc_uart_txd : out std_logic;
+
+ -- PS/2
+ hc_ps2_dat : inout std_logic;
+ hc_ps2_clk : inout std_logic;
+
+ -- VGA/DAC
+ hc_vga_data : out std_logic_vector(9 downto 0);
+ hc_vga_clock : out std_ulogic;
+ hc_vga_hs : out std_ulogic;
+ hc_vga_vs : out std_ulogic;
+ hc_vga_blank : out std_ulogic;
+ hc_vga_sync : out std_ulogic;
+
+ -- I2C EEPROM
+ hc_id_i2cscl : out std_logic;
+ hc_id_i2cdat : inout std_logic
+ );
+end;
+
+architecture rtl of leon3mp is
+
+ component serializer
+ generic (
+ length : integer := 8 -- vector length
+ );
+ port (
+ clk : in std_ulogic;
+ sync : in std_ulogic;
+ ivec0 : in std_logic_vector((length-1) downto 0);
+ ivec1 : in std_logic_vector((length-1) downto 0);
+ ivec2 : in std_logic_vector((length-1) downto 0);
+ ovec : out std_logic_vector((length-1) downto 0)
+ );
+ end component;
+
+ component altera_eek_clkgen
+ generic (
+ clk0_mul : integer := 1;
+ clk0_div : integer := 1;
+ clk1_mul : integer := 1;
+ clk1_div : integer := 1;
+ clk_freq : integer := 25000);
+ port (
+ inclk0 : in std_ulogic;
+ clk0 : out std_ulogic;
+ clk0x3 : out std_ulogic;
+ clksel : in std_logic_vector(1 downto 0);
+ locked : out std_ulogic);
+ end component;
+
+ constant blength : integer := 12;
+ constant fifodepth : integer := 8;
+
+ constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+
+ CFG_SVGA_ENABLE+CFG_GRETH + 1;
+
+ signal vcc, gnd : std_logic_vector(7 downto 0);
+ signal memi, smemi : memory_in_type;
+ signal memo, smemo : memory_out_type;
+ signal wpo : wprot_out_type;
+
+ signal ddsi : ddrmem_in_type;
+ signal ddso : ddrmem_out_type;
+
+ signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
+ signal ddr_clkv : std_logic_vector(2 downto 0);
+ signal ddr_clkbv : std_logic_vector(2 downto 0);
+ signal ddr_ckev : std_logic_vector(1 downto 0);
+ signal ddr_csbv : std_logic_vector(1 downto 0);
+ signal ddr_adl : std_logic_vector (13 downto 0);
+ signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
+ signal tck, tckn, tms, tdi, tdo : std_ulogic;
+ signal ddrclk, ddrrst : std_ulogic;
+
+ signal apbi : apb_slv_in_type;
+ signal apbo : apb_slv_out_vector := (others => apb_none);
+ signal ahbsi : ahb_slv_in_type;
+ signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+ signal ahbmi : ahb_mst_in_type;
+ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+ signal clkm, rstn, rawrstn, ssram_clkl : std_ulogic;
+ signal cgi : clkgen_in_type;
+ signal cgo : clkgen_out_type;
+ signal u1i, dui : uart_in_type;
+ signal u1o, duo : uart_out_type;
+
+ signal irqi : irq_in_vector(0 to NCPU-1);
+ signal irqo : irq_out_vector(0 to NCPU-1);
+
+ signal dbgi : l3_debug_in_vector(0 to NCPU-1);
+ signal dbgo : l3_debug_out_vector(0 to NCPU-1);
+
+ signal dsui : dsu_in_type;
+ signal dsuo : dsu_out_type;
+
+ signal gpti : gptimer_in_type;
+ signal gpioi : gpio_in_type;
+ signal gpioo : gpio_out_type;
+
+ signal ps2i : ps2_in_type;
+ signal ps2o : ps2_out_type;
+
+ signal i2ci : i2c_in_type;
+ signal i2co : i2c_out_type;
+
+ signal spii : spi_in_type;
+ signal spio : spi_out_type;
+ signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
+
+ signal spmi : spimctrl_in_type;
+ signal spmo : spimctrl_out_type;
+
+ signal ethi : eth_in_type;
+ signal etho : eth_out_type;
+
+ signal lcdo : apbvga_out_type;
+ signal lcd_data : std_logic_vector(7 downto 0);
+ signal lcd_den : std_ulogic;
+ signal lcd_grest : std_ulogic;
+ signal lcdspii : spi_in_type;
+ signal lcdspio : spi_out_type;
+ signal lcdslvsel : std_logic_vector(1 downto 0);
+ signal lcdclksel : std_logic_vector(1 downto 0);
+ signal lcdclk : std_ulogic;
+ signal lcdclk3x : std_ulogic;
+ signal lcdclklck : std_ulogic;
+
+ signal vgao : apbvga_out_type;
+ signal vga_data : std_logic_vector(9 downto 0);
+ signal vgaclksel : std_logic_vector(1 downto 0);
+ signal vgaclk : std_ulogic;
+ signal vgaclk3x : std_ulogic;
+ signal vgaclklck : std_ulogic;
+
+ constant IOAEN : integer := 1;
+ constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
+ constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
+
+ signal lclk, lclkout : std_ulogic;
+
+ signal dsubre : std_ulogic;
+
+ attribute syn_keep : boolean;
+ attribute syn_keep of clkm : signal is true;
+ attribute syn_keep of clkml : signal is true;
+ attribute syn_keep of lcdclk : signal is true;
+ attribute syn_keep of lcdclk3x : signal is true;
+ attribute syn_keep of vgaclk : signal is true;
+ attribute syn_keep of vgaclk3x : signal is true;
+
+begin
+
+----------------------------------------------------------------------
+--- Reset and Clock generation -------------------------------------
+----------------------------------------------------------------------
+
+ vcc <= (others => '1'); gnd <= (others => '0');
+ cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
+
+ clklock <= cgo.clklock and lock and lcdclklck and vgaclklck;
+ clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
+
+ clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
+ generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
+ clk_div => CFG_CLKDIV, sdramen => 1,
+ freq => freq)
+ port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
+ clk2x => open, sdclk => ssram_clkl, pciclk => open,
+ cgi => cgi, cgo => cgo);
+
+ ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
+ port map (ssram_clk, ssram_clkl);
+
+ rst0 : rstgen -- reset generator
+ port map (resetn, clkm, clklock, rstn, rawrstn);
+
+ rstoutn <= resetn;
+
+----------------------------------------------------------------------
+--- AVOID BUS CONTENTION --------------------------------------------
+----------------------------------------------------------------------
+ -- This design uses the ethernet PHY and we must therefore disable the
+ -- video decoder and stay away from the touch panel.
+ -- Video coder
+ hc_td_reset <= '0'; -- Video Decoder Reset
+
+----------------------------------------------------------------------
+--- AHB CONTROLLER --------------------------------------------------
+----------------------------------------------------------------------
+
+ ahb0 : ahbctrl -- AHB arbiter/multiplexer
+ generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+ rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
+ ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
+ port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
+
+----------------------------------------------------------------------
+--- LEON3 processor and DSU -----------------------------------------
+----------------------------------------------------------------------
+
+ l3 : if CFG_LEON3 = 1 generate
+ cpu : for i in 0 to NCPU-1 generate
+ u0 : leon3s -- LEON3 processor
+ generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
+ 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
+ CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
+ CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
+ CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
+ CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
+ port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
+ irqi(i), irqo(i), dbgi(i), dbgo(i));
+ end generate;
+ errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
+
+ dsugen : if CFG_DSU = 1 generate
+ dsu0 : dsu3 -- LEON3 Debug Support Unit
+ generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
+ ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
+ port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
+
+ dsui.enable <= '1';
+
+ dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
+ dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
+ end generate;
+ end generate;
+ nodcom : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; end generate;
+
+ dcomgen : if CFG_AHB_UART = 1 generate
+ dcom0 : ahbuart -- Debug UART
+ generic map (hindex => NCPU, pindex => 7, paddr => 7)
+ port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
+ dsurx_pad : inpad generic map (tech => padtech) port map (hc_uart_rxd, dui.rxd);
+ dsutx_pad : outpad generic map (tech => padtech) port map (hc_uart_txd, duo.txd);
+ end generate;
+ nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
+
+ ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
+ ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
+ port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
+ open, open, open, open, open, open, open, gnd(0));
+ end generate;
+
+----------------------------------------------------------------------
+--- Memory controllers ----------------------------------------------
+----------------------------------------------------------------------
+
+ mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
+ sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
+ ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
+ sden => 0, ram16 => 1)
+ port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
+ end generate;
+
+ memi.brdyn <= '1'; memi.bexcn <= '1';
+ memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
+
+ ssr0 : if CFG_SSCTRL = 1 generate
+ ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
+ iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
+ bus16 => CFG_SSCTRLP16)
+ port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
+ end generate;
+
+ mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
+ apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
+ roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
+ end generate;
+
+ mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
+ addr_pad : outpadv generic map (width => 25, tech => padtech)
+ port map (address, memo.address(25 downto 1));
+ roms_pad : outpad generic map (tech => padtech)
+ port map (romsn, memo.romsn(0));
+ oen_pad : outpad generic map (tech => padtech)
+ port map (oen, memo.oen);
+ wri_pad : outpad generic map (tech => padtech)
+ port map (writen, memo.writen);
+-- pragma translate_off
+ iosn_pad : outpad generic map (tech => padtech)
+ port map (iosn, memo.iosn);
+-- pragma translate_on
+
+-- ssram_adv_n_pad : outpad generic map (tech => padtech)
+-- port map (ssram_adv_n, vcc(0));
+-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
+-- port map (ssram_adsp_n, gnd(0));
+ ssram_adscn_pad : outpad generic map (tech => padtech)
+ port map (ssram_adscn, gnd(0));
+ ssrams_pad : outpad generic map ( tech => padtech)
+ port map (ssram_cen, memo.ramsn(0));
+ ssram_oen_pad : outpad generic map (tech => padtech)
+ port map (ssram_oen, memo.oen);
+ ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
+ port map (ssram_bw, memo.wrn);
+ ssram_wri_pad : outpad generic map (tech => padtech)
+ port map (ssram_wen, memo.writen);
+ data_pad : iopadvv generic map (tech => padtech, width => 32)
+ port map (data(31 downto 0), memo.data(31 downto 0),
+ memo.vbdrive, memi.data(31 downto 0));
+ end generate;
+
+ ddrsp0 : if (CFG_DDRSP /= 0) generate
+ ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
+ hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
+ pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
+ clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
+ col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
+ port map (
+ resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
+ ddr_clkv, ddr_clkbv, open, gnd(0),
+ ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
+ ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
+ ddr_ad <= ddr_adl(12 downto 0);
+ ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
+ ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
+ end generate;
+
+ ddrsp1 : if (CFG_DDRSP = 0) generate
+ ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
+ end generate;
+
+ spimc: if CFG_SPIMCTRL = 1 generate -- SPI Memory Controller
+ spimctrl0 : spimctrl
+ generic map (hindex => 4,
+ hirq => 9,
+ faddr => 16#b00#,
+ fmask => 16#f00#,
+ ioaddr => 16#002#,
+ iomask => 16#fff#,
+ spliten => CFG_SPLIT,
+ oepol => 0,
+ sdcard => CFG_SPIMCTRL_SDCARD,
+ readcmd => CFG_SPIMCTRL_READCMD,
+ dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
+ dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
+ scaler => CFG_SPIMCTRL_SCALER,
+ altscaler => CFG_SPIMCTRL_ASCALER,
+ pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
+ port map (rstn, clkm, ahbsi, ahbso(4), spmi, spmo);
+
+ miso_pad : inpad generic map (tech => padtech)
+ port map (hc_sd_dat, spmi.miso);
+ mosi_pad : outpad generic map (tech => padtech)
+ port map (hc_sd_cmd, spmo.mosi);
+ sck_pad : outpad generic map (tech => padtech)
+ port map (hc_sd_clk, spmo.sck);
+ slvsel0_pad : iopad generic map (tech => padtech)
+ port map (hc_sd_dat3, spmo.csn, spmo.cdcsnoen, spmi.cd);
+ end generate;
+
+----------------------------------------------------------------------
+--- APB Bridge and various periherals -------------------------------
+----------------------------------------------------------------------
+
+ apb0 : apbctrl -- AHB/APB bridge
+ generic map (hindex => 1, haddr => CFG_APBADDR)
+ port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
+
+ ua1 : if CFG_UART1_ENABLE /= 0 generate
+ uart1 : apbuart -- UART 1
+ generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
+ fifosize => CFG_UART1_FIFO)
+ port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
+ u1i.ctsn <= '0'; u1i.extclk <= '0';
+ upads : if CFG_AHB_UART = 0 generate
+ u1i.rxd <= hc_uart_rxd; hc_uart_txd <= u1o.txd;
+ end generate;
+ end generate;
+ noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
+
+ irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
+ irqctrl0 : irqmp -- interrupt controller
+ generic map (pindex => 2, paddr => 2, ncpu => NCPU)
+ port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
+ end generate;
+ irq3 : if CFG_IRQ3_ENABLE = 0 generate
+ x : for i in 0 to NCPU-1 generate
+ irqi(i).irl <= "0000";
+ end generate;
+ apbo(2) <= apb_none;
+ end generate;
+
+ gpt : if CFG_GPT_ENABLE /= 0 generate
+ timer0 : gptimer -- Timer unit
+ generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
+ sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
+ nbits => CFG_GPT_TW)
+ port map (rstn, clkm, apbi, apbo(3), gpti, open);
+ gpti.dhalt <= dsuo.active; gpti.extclk <= '0';
+ end generate;
+ notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
+
+ gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
+ grgpio0: grgpio
+ generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
+ port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
+ gpioi => gpioi, gpioo => gpioo);
+ pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-3 generate
+ gpioi.din(i) <= gpio(i);
+ end generate;
+ gpioi.din(3) <= hc_adc_penirq_n;
+ gpioi.din(4) <= hc_adc_busy;
+ end generate;
+
+ ps2 : if CFG_PS2_ENABLE /= 0 generate -- PS/2 unit
+ ps20 : apbps2 generic map(pindex => 6, paddr => 6, pirq => 6)
+ port map(rstn, clkm, apbi, apbo(6), ps2i, ps2o);
+ end generate;
+ nops2 : if CFG_PS2_ENABLE = 0 generate
+ apbo(4) <= apb_none; ps2o <= ps2o_none;
+ end generate;
+ ps2clk_pad : iopad generic map (tech => padtech)
+ port map (hc_ps2_clk, ps2o.ps2_clk_o, ps2o.ps2_clk_oe, ps2i.ps2_clk_i);
+ ps2data_pad : iopad generic map (tech => padtech)
+ port map (hc_ps2_dat, ps2o.ps2_data_o, ps2o.ps2_data_oe, ps2i.ps2_data_i);
+
+ i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
+ i2c0 : i2cmst
+ generic map (pindex => 8, paddr => 8, pmask => 16#FFF#, pirq => 11)
+ port map (rstn, clkm, apbi, apbo(8), i2ci, i2co);
+ -- The EEK does not use a bi-directional line for the I2C clock
+ i2ci.scl <= i2co.scloen; -- No clock stretch possible
+ -- When SCL output enable is activated the line should go low
+ i2c_scl_pad : outpad generic map (tech => padtech)
+ port map (hc_id_i2cscl, i2co.scloen);
+ i2c_sda_pad : iopad generic map (tech => padtech)
+ port map (hc_id_i2cdat, i2co.sda, i2co.sdaoen, i2ci.sda);
+ end generate i2cm;
+
+ spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
+ spi1 : spictrl
+ generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 9,
+ fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
+ slvselsz => CFG_SPICTRL_SLVS, odmode => 1)
+ port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
+ miso_pad : iopad generic map (tech => padtech)
+ port map (hc_sd_dat, spio.miso, spio.misooen, spii.miso);
+ mosi_pad : iopad generic map (tech => padtech)
+ port map (hc_sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
+ sck_pad : iopad generic map (tech => padtech)
+ port map (hc_sd_clk, spio.sck, spio.sckoen, spii.sck);
+ slvsel_pad : outpad generic map (tech => padtech)
+ port map (hc_sd_dat3, slvsel(0));
+ spii.spisel <= '1'; -- Master only
+ end generate spic;
+
+-----------------------------------------------------------------------
+-- LCD touch panel ---------------------------------------------------
+-----------------------------------------------------------------------
+
+ lcd: if CFG_LCD_ENABLE /= 0 generate -- LCD
+ lcd0 : svgactrl generic map(memtech => memtech, pindex => 11, paddr => 11,
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
+ clk0 => 30120, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 4)
+ port map(rstn, clkm, lcdclk, apbi, apbo(11), lcdo, ahbmi,
+ ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
+
+ lcdser0: serializer generic map (length => 8)
+ port map (lcdclk3x, lcdo.hsync, lcdo.video_out_b, lcdo.video_out_g,
+ lcdo.video_out_r, lcd_data);
+
+ lcdclksel <= "00";
+
+ lcdclkgen : altera_eek_clkgen
+ generic map (clk0_mul => 166, clk0_div => 250, clk1_mul => 9,
+ clk1_div => 50, clk_freq => BOARD_FREQ)
+ port map (lclk, lcdclk, lcdclk3x, lcdclksel, lcdclklck);
+
+ lcd_vert_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_vd, lcdo.vsync);
+ lcd_horiz_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_hd, lcdo.hsync);
+ lcd_video_out_pad : outpadv generic map (width => 8, tech => padtech)
+ port map (hc_lcd_data, lcd_data);
+ lcd_video_clock_pad : outpad generic map (tech => padtech)
+ port map (hc_nclk, lcdclk3x);
+ lcd_den <= lcdo.blank;
+ end generate;
+
+ nolcd : if CFG_LCD_ENABLE = 0 generate
+ apbo(11) <= apb_none; lcdo <= vgao_none;
+ lcd_den <= '0'; -- LCD RGB Data Enable
+ lcdclk <= '0'; lcdclk3x <= '0'; lcdclklck <= '1';
+ end generate;
+
+ lcd_den_pad : outpad generic map (tech => padtech)
+ port map (hc_den, lcd_den);
+
+ lcdsysreset: if CFG_LCD_ENABLE /= 0 or CFG_LCD3T_ENABLE /= 0 generate
+ lcd_grest <= rstn;
+ end generate;
+
+ lcdalwaysreset: if CFG_LCD_ENABLE = 0 and CFG_LCD3T_ENABLE = 0 generate
+ lcd_grest <= '0';
+ end generate lcdalwaysreset;
+
+ lcd_reset_pad : outpad generic map (tech => padtech) -- LCD Global Reset, active low
+ port map (hc_grest, lcd_grest);
+
+ touch3wire: if CFG_LCD3T_ENABLE /= 0 generate -- LCD 3-wire and touch panel interface
+ -- TODO:
+ -- Interrupt and busy signals not connected
+ touch3spi1 : spictrl
+ generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
+ fdepth => 2, slvselen => 1, slvselsz => 2, odmode => 0)
+ port map (rstn, clkm, apbi, apbo(12), lcdspii, lcdspio, lcdslvsel);
+ adc_miso_pad : inpad generic map (tech => padtech)
+ port map (hc_adc_dout, lcdspii.miso);
+ adc_mosi_pad : outpad generic map (tech => padtech)
+ port map (hc_adc_din, lcdspio.mosi);
+ lcd_adc_dclk_pad : outpad generic map (tech => padtech)
+ port map (hc_adc_dclk, lcdspio.sck);
+ hcd_sda_pad : iopad generic map (tech => padtech)
+ port map (hc_sda, lcdspio.mosi, lcdspio.mosioen, lcdspii.mosi);
+
+ lcdspii.spisel <= '1'; -- Master only
+ end generate;
+
+ notouch3wire: if CFG_LCD3T_ENABLE = 0 generate
+ lcdslvsel <= (others => '1');
+ apbo(12) <= apb_none;
+ end generate;
+
+ hc_adc_cs_n_pad : outpad generic map (tech => padtech)
+ port map (hc_adc_cs_n, lcdslvsel(0));
+ hc_scen_pad : outpad generic map (tech => padtech)
+ port map (hc_scen, lcdslvsel(1));
+
+-----------------------------------------------------------------------
+-- SVGA controller ----------------------------------------------------
+-----------------------------------------------------------------------
+
+ svga : if CFG_SVGA_ENABLE /= 0 generate -- VGA DAC
+ svga0 : svgactrl generic map(memtech => memtech, pindex => 13, paddr => 13,
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE,
+ clk0 => 40000, clk1 => 25000, clk2 => 0, clk3 => 0, burstlen => 4)
+ port map(rstn, clkm, vgaclk, apbi, apbo(13), vgao, ahbmi,
+ ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE),
+ vgaclksel);
+
+ svgaser0: serializer generic map (length => 8)
+ port map (vgaclk3x, vgao.hsync, vgao.video_out_b, vgao.video_out_g,
+ vgao.video_out_r, vga_data(9 downto 2));
+ vga_data(1 downto 0) <= (others => '0');
+
+ vgaclkgen : altera_eek_clkgen
+ generic map (clk0_mul => 1, clk0_div => 2, clk1_mul => 4,
+ clk1_div => 5, clk_freq => BOARD_FREQ)
+ port map (lclk, vgaclk, vgaclk3x, vgaclksel, vgaclklck);
+
+ vga_blank_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_blank, vgao.blank);
+ vga_comp_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_sync, vgao.comp_sync);
+ vga_vert_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_vs, vgao.vsync);
+ vga_horiz_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_hs, vgao.hsync);
+ vga_video_out_pad : outpadv generic map (width => 10, tech => padtech)
+ port map (hc_vga_data, vga_data);
+ vga_video_clock_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_clock, vgaclk3x);
+ end generate svga;
+
+ nosvga : if CFG_SVGA_ENABLE = 0 generate
+ apbo(13) <= apb_none; vgao <= vgao_none;
+ vgaclk <= '0'; vgaclk3x <= '0'; vgaclklck <= '1';
+ end generate;
+
+-----------------------------------------------------------------------
+--- ETHERNET ---------------------------------------------------------
+-----------------------------------------------------------------------
+
+ eth0 : if CFG_GRETH /= 0 generate -- Gaisler ethernet MAC
+ e1 : grethm generic map(
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE,
+ pindex => 10, paddr => 10, pirq => 10, memtech => memtech,
+ mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
+ nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
+ macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
+ ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
+ port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
+ ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE),
+ apbi => apbi, apbo => apbo(10), ethi => ethi, etho => etho);
+
+ emdio_pad : iopad generic map (tech => padtech)
+ port map (hc_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
+ etxc_pad : clkpad generic map (tech => padtech, arch => 2)
+ port map (hc_tx_clk, ethi.tx_clk);
+ erxc_pad : clkpad generic map (tech => padtech, arch => 2)
+ port map (hc_rx_clk, ethi.rx_clk);
+ erxd_pad : inpadv generic map (tech => padtech, width => 4)
+ port map (hc_rx_d, ethi.rxd(3 downto 0));
+ erxdv_pad : inpad generic map (tech => padtech)
+ port map (hc_rx_dv, ethi.rx_dv);
+ erxer_pad : inpad generic map (tech => padtech)
+ port map (hc_rx_err, ethi.rx_er);
+ erxco_pad : inpad generic map (tech => padtech)
+ port map (hc_rx_col, ethi.rx_col);
+ erxcr_pad : inpad generic map (tech => padtech)
+ port map (hc_rx_crs, ethi.rx_crs);
+
+ etxd_pad : outpadv generic map (tech => padtech, width => 4)
+ port map (hc_tx_d, etho.txd(3 downto 0));
+ etxen_pad : outpad generic map (tech => padtech)
+ port map (hc_tx_en, etho.tx_en);
+ emdc_pad : outpad generic map (tech => padtech)
+ port map (hc_mdc, etho.mdc);
+ erst_pad : outpad generic map (tech => padtech)
+ port map (hc_eth_reset_n, rawrstn);
+ end generate;
+
+-----------------------------------------------------------------------
+--- AHB ROM ----------------------------------------------------------
+-----------------------------------------------------------------------
+
+ bpromgen : if CFG_AHBROMEN /= 0 generate
+ brom : entity work.ahbrom
+ generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
+ port map ( rstn, clkm, ahbsi, ahbso(6));
+ end generate;
+ nobpromgen : if CFG_AHBROMEN = 0 generate
+ ahbso(6) <= ahbs_none;
+ end generate;
+
+-----------------------------------------------------------------------
+--- AHB RAM ----------------------------------------------------------
+-----------------------------------------------------------------------
+
+ ahbramgen : if CFG_AHBRAMEN = 1 generate
+ ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
+ tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
+ port map (rstn, clkm, ahbsi, ahbso(7));
+ end generate;
+ nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
+
+
+-----------------------------------------------------------------------
+--- YCC-RGB translation module ------------------------------------
+-----------------------------------------------------------------------
+
+ jpgycc : yccrgbs
+ generic map(shindex => 5, haddr => 16#B00#, hirq => 13, pindex => 14,
+ paddr => 7, mhindex => 3 )
+ port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
+ ahbmo => ahbmo(3), ahbsi => ahbsi, ahbso => ahbso(5),
+ apbi => apbi, apbo => apbo(14)
+ );
+
+
+
+-----------------------------------------------------------------------
+--- Drive unused bus elements ---------------------------------------
+-----------------------------------------------------------------------
+
+ nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE+CFG_GRETH + 1) to NAHBMST-1 generate
+ ahbmo(i) <= ahbm_none;
+ end generate;
+
+ -- invert signal for input via a key
+ dsubre <= not dsubren;
+
+-----------------------------------------------------------------------
+--- Boot message ----------------------------------------------------
+-----------------------------------------------------------------------
+
+-- pragma translate_off
+ x : report_version
+ generic map (
+ msg1 => "LEON3 Altera Embedded Evaluation Kit Demonstration Design",
+ msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
+ & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
+ msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
+ mdel => 1
+ );
+-- pragma translate_on
+
+end;
--- /dev/null
+------------------------------------------------------------------------------
+-- LEON3 Demonstration design
+-- Copyright (C) 2008 Jiri Gaisler, Gaisler Research
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+library techmap;
+use techmap.gencomp.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+use gaisler.net.all;
+use gaisler.ata.all;
+use gaisler.jtag.all;
+library esa;
+use esa.memoryctrl.all;
+
+library kuri;
+use kuri.mjpeg.all;
+
+use work.config.all;
+
+entity leon3mp is
+ generic (
+ fabtech : integer := CFG_FABTECH;
+ memtech : integer := CFG_MEMTECH;
+ padtech : integer := CFG_PADTECH;
+ clktech : integer := CFG_CLKTECH;
+ ncpu : integer := CFG_NCPU;
+ disas : integer := CFG_DISAS; -- Enable disassembly to console
+ dbguart : integer := CFG_DUART; -- Print UART on console
+ pclow : integer := CFG_PCLOW;
+ freq : integer := 50000 -- frequency of main clock (used for PLLs)
+ );
+ port (
+ resetn : in std_ulogic;
+ clk : in std_ulogic;
+ errorn : out std_ulogic;
+
+ -- flash/ssram bus
+ address : out std_logic_vector(25 downto 1);
+ data : inout std_logic_vector(31 downto 0);
+ romsn : out std_ulogic;
+ oen : out std_logic;
+ writen : out std_logic;
+ rstoutn : out std_ulogic;
+ ssram_cen : out std_logic;
+ ssram_wen : out std_logic;
+ ssram_bw : out std_logic_vector (0 to 3);
+ ssram_oen : out std_ulogic;
+ ssram_clk : out std_ulogic;
+ ssram_adscn : out std_ulogic;
+-- ssram_adsp_n : out std_ulogic;
+-- ssram_adv_n : out std_ulogic;
+
+-- pragma translate_off
+ iosn : out std_ulogic;
+-- pragma translate_on
+
+ -- DDR
+ ddr_clk : out std_logic;
+ ddr_clkn : out std_logic;
+ ddr_cke : out std_logic;
+ ddr_csb : out std_logic;
+ ddr_web : out std_ulogic; -- ddr write enable
+ ddr_rasb : out std_ulogic; -- ddr ras
+ ddr_casb : out std_ulogic; -- ddr cas
+ ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
+ ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
+ ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
+ ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
+ ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
+
+ -- debug support unit
+ dsubren : in std_ulogic;
+ dsuact : out std_ulogic;
+
+ -- I/O port
+ gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
+
+ -- Connections over HSMC connector
+ -- LCD touch panel display
+ hc_vd : out std_logic;
+ hc_hd : out std_logic;
+ hc_den : out std_logic;
+ hc_nclk : out std_logic;
+ hc_lcd_data : out std_logic_vector(7 downto 0);
+ hc_grest : out std_logic;
+ hc_scen : out std_logic;
+ hc_sda : inout std_logic;
+ hc_adc_penirq_n : in std_logic;
+ hc_adc_dout : in std_logic;
+ hc_adc_busy : in std_logic;
+ hc_adc_din : out std_logic;
+ hc_adc_dclk : out std_logic;
+ hc_adc_cs_n : out std_logic; -- Shared with video decoder
+
+ -- Shared by video decoder and audio codec
+ hc_i2c_sclk : out std_logic;
+ hc_i2c_sdat : inout std_logic;
+
+ -- Video decoder
+ hc_td_d : inout std_logic_vector(7 downto 0);
+ hc_td_hs : in std_logic;
+ hc_td_vs : in std_logic;
+ hc_td_27mhz : in std_logic;
+ hc_td_reset : out std_logic;
+
+ -- Audio codec
+ hc_aud_adclrck : out std_logic;
+ hc_aud_adcdat : in std_logic;
+ hc_aud_daclrck : out std_logic;
+ hc_aud_dacdat : out std_logic;
+ hc_aud_bclk : out std_logic;
+ hc_aud_xck : out std_logic;
+
+ -- SD card
+ hc_sd_dat : inout std_logic;
+ hc_sd_dat3 : inout std_logic;
+ hc_sd_cmd : inout std_logic;
+ hc_sd_clk : inout std_logic;
+
+ -- Ethernet PHY
+ hc_tx_d : out std_logic_vector(3 downto 0);
+ hc_rx_d : in std_logic_vector(3 downto 0);
+ hc_tx_clk : in std_logic;
+ hc_rx_clk : in std_logic;
+ hc_tx_en : out std_logic;
+ hc_rx_dv : in std_logic;
+ hc_rx_crs : in std_logic;
+ hc_rx_err : in std_logic;
+ hc_rx_col : in std_logic;
+ hc_mdio : inout std_logic;
+ hc_mdc : out std_logic;
+ hc_eth_reset_n : out std_logic;
+
+ -- RX232 (console/debug UART)
+ hc_uart_rxd : in std_logic;
+ hc_uart_txd : out std_logic;
+
+ -- PS/2
+ hc_ps2_dat : inout std_logic;
+ hc_ps2_clk : inout std_logic;
+
+ -- VGA/DAC
+ hc_vga_data : out std_logic_vector(9 downto 0);
+ hc_vga_clock : out std_ulogic;
+ hc_vga_hs : out std_ulogic;
+ hc_vga_vs : out std_ulogic;
+ hc_vga_blank : out std_ulogic;
+ hc_vga_sync : out std_ulogic;
+
+ -- I2C EEPROM
+ hc_id_i2cscl : out std_logic;
+ hc_id_i2cdat : inout std_logic
+ );
+end;
+
+architecture rtl of leon3mp is
+
+ component serializer
+ generic (
+ length : integer := 8 -- vector length
+ );
+ port (
+ clk : in std_ulogic;
+ sync : in std_ulogic;
+ ivec0 : in std_logic_vector((length-1) downto 0);
+ ivec1 : in std_logic_vector((length-1) downto 0);
+ ivec2 : in std_logic_vector((length-1) downto 0);
+ ovec : out std_logic_vector((length-1) downto 0)
+ );
+ end component;
+
+ component altera_eek_clkgen
+ generic (
+ clk0_mul : integer := 1;
+ clk0_div : integer := 1;
+ clk1_mul : integer := 1;
+ clk1_div : integer := 1;
+ clk_freq : integer := 25000);
+ port (
+ inclk0 : in std_ulogic;
+ clk0 : out std_ulogic;
+ clk0x3 : out std_ulogic;
+ clksel : in std_logic_vector(1 downto 0);
+ locked : out std_ulogic);
+ end component;
+
+ constant blength : integer := 12;
+ constant fifodepth : integer := 8;
+
+ constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+
+ CFG_SVGA_ENABLE+CFG_GRETH;
+
+ signal vcc, gnd : std_logic_vector(7 downto 0);
+ signal memi, smemi : memory_in_type;
+ signal memo, smemo : memory_out_type;
+ signal wpo : wprot_out_type;
+
+ signal ddsi : ddrmem_in_type;
+ signal ddso : ddrmem_out_type;
+
+ signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
+ signal ddr_clkv : std_logic_vector(2 downto 0);
+ signal ddr_clkbv : std_logic_vector(2 downto 0);
+ signal ddr_ckev : std_logic_vector(1 downto 0);
+ signal ddr_csbv : std_logic_vector(1 downto 0);
+ signal ddr_adl : std_logic_vector (13 downto 0);
+ signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
+ signal tck, tckn, tms, tdi, tdo : std_ulogic;
+ signal ddrclk, ddrrst : std_ulogic;
+
+ signal apbi : apb_slv_in_type;
+ signal apbo : apb_slv_out_vector := (others => apb_none);
+ signal ahbsi : ahb_slv_in_type;
+ signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+ signal ahbmi : ahb_mst_in_type;
+ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+ signal clkm, rstn, rawrstn, ssram_clkl : std_ulogic;
+ signal cgi : clkgen_in_type;
+ signal cgo : clkgen_out_type;
+ signal u1i, dui : uart_in_type;
+ signal u1o, duo : uart_out_type;
+
+ signal irqi : irq_in_vector(0 to NCPU-1);
+ signal irqo : irq_out_vector(0 to NCPU-1);
+
+ signal dbgi : l3_debug_in_vector(0 to NCPU-1);
+ signal dbgo : l3_debug_out_vector(0 to NCPU-1);
+
+ signal dsui : dsu_in_type;
+ signal dsuo : dsu_out_type;
+
+ signal gpti : gptimer_in_type;
+ signal gpioi : gpio_in_type;
+ signal gpioo : gpio_out_type;
+
+ signal ps2i : ps2_in_type;
+ signal ps2o : ps2_out_type;
+
+ signal i2ci : i2c_in_type;
+ signal i2co : i2c_out_type;
+
+ signal spii : spi_in_type;
+ signal spio : spi_out_type;
+ signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
+
+ signal spmi : spimctrl_in_type;
+ signal spmo : spimctrl_out_type;
+
+ signal ethi : eth_in_type;
+ signal etho : eth_out_type;
+
+ signal lcdo : apbvga_out_type;
+ signal lcd_data : std_logic_vector(7 downto 0);
+ signal lcd_den : std_ulogic;
+ signal lcd_grest : std_ulogic;
+ signal lcdspii : spi_in_type;
+ signal lcdspio : spi_out_type;
+ signal lcdslvsel : std_logic_vector(1 downto 0);
+ signal lcdclksel : std_logic_vector(1 downto 0);
+ signal lcdclk : std_ulogic;
+ signal lcdclk3x : std_ulogic;
+ signal lcdclklck : std_ulogic;
+
+ signal vgao : apbvga_out_type;
+ signal vga_data : std_logic_vector(9 downto 0);
+ signal vgaclksel : std_logic_vector(1 downto 0);
+ signal vgaclk : std_ulogic;
+ signal vgaclk3x : std_ulogic;
+ signal vgaclklck : std_ulogic;
+
+ constant IOAEN : integer := 1;
+ constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
+ constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
+
+ signal lclk, lclkout : std_ulogic;
+
+ signal dsubre : std_ulogic;
+
+ attribute syn_keep : boolean;
+ attribute syn_keep of clkm : signal is true;
+ attribute syn_keep of clkml : signal is true;
+ attribute syn_keep of lcdclk : signal is true;
+ attribute syn_keep of lcdclk3x : signal is true;
+ attribute syn_keep of vgaclk : signal is true;
+ attribute syn_keep of vgaclk3x : signal is true;
+
+begin
+
+----------------------------------------------------------------------
+--- Reset and Clock generation -------------------------------------
+----------------------------------------------------------------------
+
+ vcc <= (others => '1'); gnd <= (others => '0');
+ cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
+
+ clklock <= cgo.clklock and lock and lcdclklck and vgaclklck;
+ clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
+
+ clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
+ generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
+ clk_div => CFG_CLKDIV, sdramen => 1,
+ freq => freq)
+ port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
+ clk2x => open, sdclk => ssram_clkl, pciclk => open,
+ cgi => cgi, cgo => cgo);
+
+ ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
+ port map (ssram_clk, ssram_clkl);
+
+ rst0 : rstgen -- reset generator
+ port map (resetn, clkm, clklock, rstn, rawrstn);
+
+ rstoutn <= resetn;
+
+----------------------------------------------------------------------
+--- AVOID BUS CONTENTION --------------------------------------------
+----------------------------------------------------------------------
+ -- This design uses the ethernet PHY and we must therefore disable the
+ -- video decoder and stay away from the touch panel.
+ -- Video coder
+ hc_td_reset <= '0'; -- Video Decoder Reset
+
+----------------------------------------------------------------------
+--- AHB CONTROLLER --------------------------------------------------
+----------------------------------------------------------------------
+
+ ahb0 : ahbctrl -- AHB arbiter/multiplexer
+ generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+ rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
+ ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
+ port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
+
+----------------------------------------------------------------------
+--- LEON3 processor and DSU -----------------------------------------
+----------------------------------------------------------------------
+
+ l3 : if CFG_LEON3 = 1 generate
+ cpu : for i in 0 to NCPU-1 generate
+ u0 : leon3s -- LEON3 processor
+ generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
+ 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
+ CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
+ CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
+ CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
+ CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
+ port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
+ irqi(i), irqo(i), dbgi(i), dbgo(i));
+ end generate;
+ errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
+
+ dsugen : if CFG_DSU = 1 generate
+ dsu0 : dsu3 -- LEON3 Debug Support Unit
+ generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
+ ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
+ port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
+
+ dsui.enable <= '1';
+
+ dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
+ dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
+ end generate;
+ end generate;
+ nodcom : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; end generate;
+
+ dcomgen : if CFG_AHB_UART = 1 generate
+ dcom0 : ahbuart -- Debug UART
+ generic map (hindex => NCPU, pindex => 7, paddr => 7)
+ port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
+ dsurx_pad : inpad generic map (tech => padtech) port map (hc_uart_rxd, dui.rxd);
+ dsutx_pad : outpad generic map (tech => padtech) port map (hc_uart_txd, duo.txd);
+ end generate;
+ nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
+
+ ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
+ ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
+ port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
+ open, open, open, open, open, open, open, gnd(0));
+ end generate;
+
+----------------------------------------------------------------------
+--- Memory controllers ----------------------------------------------
+----------------------------------------------------------------------
+
+ mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
+ sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
+ ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
+ sden => 0, ram16 => 1)
+ port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
+ end generate;
+
+ memi.brdyn <= '1'; memi.bexcn <= '1';
+ memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
+
+ ssr0 : if CFG_SSCTRL = 1 generate
+ ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
+ iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
+ bus16 => CFG_SSCTRLP16)
+ port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
+ end generate;
+
+ mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
+ apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
+ roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
+ end generate;
+
+ mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
+ addr_pad : outpadv generic map (width => 25, tech => padtech)
+ port map (address, memo.address(25 downto 1));
+ roms_pad : outpad generic map (tech => padtech)
+ port map (romsn, memo.romsn(0));
+ oen_pad : outpad generic map (tech => padtech)
+ port map (oen, memo.oen);
+ wri_pad : outpad generic map (tech => padtech)
+ port map (writen, memo.writen);
+-- pragma translate_off
+ iosn_pad : outpad generic map (tech => padtech)
+ port map (iosn, memo.iosn);
+-- pragma translate_on
+
+-- ssram_adv_n_pad : outpad generic map (tech => padtech)
+-- port map (ssram_adv_n, vcc(0));
+-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
+-- port map (ssram_adsp_n, gnd(0));
+ ssram_adscn_pad : outpad generic map (tech => padtech)
+ port map (ssram_adscn, gnd(0));
+ ssrams_pad : outpad generic map ( tech => padtech)
+ port map (ssram_cen, memo.ramsn(0));
+ ssram_oen_pad : outpad generic map (tech => padtech)
+ port map (ssram_oen, memo.oen);
+ ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
+ port map (ssram_bw, memo.wrn);
+ ssram_wri_pad : outpad generic map (tech => padtech)
+ port map (ssram_wen, memo.writen);
+ data_pad : iopadvv generic map (tech => padtech, width => 32)
+ port map (data(31 downto 0), memo.data(31 downto 0),
+ memo.vbdrive, memi.data(31 downto 0));
+ end generate;
+
+ ddrsp0 : if (CFG_DDRSP /= 0) generate
+ ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
+ hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
+ pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
+ clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
+ col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
+ port map (
+ resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
+ ddr_clkv, ddr_clkbv, open, gnd(0),
+ ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
+ ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
+ ddr_ad <= ddr_adl(12 downto 0);
+ ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
+ ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
+ end generate;
+
+ ddrsp1 : if (CFG_DDRSP = 0) generate
+ ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
+ end generate;
+
+ spimc: if CFG_SPIMCTRL = 1 generate -- SPI Memory Controller
+ spimctrl0 : spimctrl
+ generic map (hindex => 4,
+ hirq => 9,
+ faddr => 16#b00#,
+ fmask => 16#f00#,
+ ioaddr => 16#002#,
+ iomask => 16#fff#,
+ spliten => CFG_SPLIT,
+ oepol => 0,
+ sdcard => CFG_SPIMCTRL_SDCARD,
+ readcmd => CFG_SPIMCTRL_READCMD,
+ dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
+ dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
+ scaler => CFG_SPIMCTRL_SCALER,
+ altscaler => CFG_SPIMCTRL_ASCALER,
+ pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
+ port map (rstn, clkm, ahbsi, ahbso(4), spmi, spmo);
+
+ miso_pad : inpad generic map (tech => padtech)
+ port map (hc_sd_dat, spmi.miso);
+ mosi_pad : outpad generic map (tech => padtech)
+ port map (hc_sd_cmd, spmo.mosi);
+ sck_pad : outpad generic map (tech => padtech)
+ port map (hc_sd_clk, spmo.sck);
+ slvsel0_pad : iopad generic map (tech => padtech)
+ port map (hc_sd_dat3, spmo.csn, spmo.cdcsnoen, spmi.cd);
+ end generate;
+
+----------------------------------------------------------------------
+--- APB Bridge and various periherals -------------------------------
+----------------------------------------------------------------------
+
+ apb0 : apbctrl -- AHB/APB bridge
+ generic map (hindex => 1, haddr => CFG_APBADDR)
+ port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
+
+ ua1 : if CFG_UART1_ENABLE /= 0 generate
+ uart1 : apbuart -- UART 1
+ generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
+ fifosize => CFG_UART1_FIFO)
+ port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
+ u1i.ctsn <= '0'; u1i.extclk <= '0';
+ upads : if CFG_AHB_UART = 0 generate
+ u1i.rxd <= hc_uart_rxd; hc_uart_txd <= u1o.txd;
+ end generate;
+ end generate;
+ noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
+
+ irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
+ irqctrl0 : irqmp -- interrupt controller
+ generic map (pindex => 2, paddr => 2, ncpu => NCPU)
+ port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
+ end generate;
+ irq3 : if CFG_IRQ3_ENABLE = 0 generate
+ x : for i in 0 to NCPU-1 generate
+ irqi(i).irl <= "0000";
+ end generate;
+ apbo(2) <= apb_none;
+ end generate;
+
+ gpt : if CFG_GPT_ENABLE /= 0 generate
+ timer0 : gptimer -- Timer unit
+ generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
+ sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
+ nbits => CFG_GPT_TW)
+ port map (rstn, clkm, apbi, apbo(3), gpti, open);
+ gpti.dhalt <= dsuo.active; gpti.extclk <= '0';
+ end generate;
+ notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
+
+ gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
+ grgpio0: grgpio
+ generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
+ port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
+ gpioi => gpioi, gpioo => gpioo);
+ pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-3 generate
+ gpioi.din(i) <= gpio(i);
+ end generate;
+ gpioi.din(3) <= hc_adc_penirq_n;
+ gpioi.din(4) <= hc_adc_busy;
+ end generate;
+
+ ps2 : if CFG_PS2_ENABLE /= 0 generate -- PS/2 unit
+ ps20 : apbps2 generic map(pindex => 6, paddr => 6, pirq => 6)
+ port map(rstn, clkm, apbi, apbo(6), ps2i, ps2o);
+ end generate;
+ nops2 : if CFG_PS2_ENABLE = 0 generate
+ apbo(4) <= apb_none; ps2o <= ps2o_none;
+ end generate;
+ ps2clk_pad : iopad generic map (tech => padtech)
+ port map (hc_ps2_clk, ps2o.ps2_clk_o, ps2o.ps2_clk_oe, ps2i.ps2_clk_i);
+ ps2data_pad : iopad generic map (tech => padtech)
+ port map (hc_ps2_dat, ps2o.ps2_data_o, ps2o.ps2_data_oe, ps2i.ps2_data_i);
+
+ i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
+ i2c0 : i2cmst
+ generic map (pindex => 8, paddr => 8, pmask => 16#FFF#, pirq => 11)
+ port map (rstn, clkm, apbi, apbo(8), i2ci, i2co);
+ -- The EEK does not use a bi-directional line for the I2C clock
+ i2ci.scl <= i2co.scloen; -- No clock stretch possible
+ -- When SCL output enable is activated the line should go low
+ i2c_scl_pad : outpad generic map (tech => padtech)
+ port map (hc_id_i2cscl, i2co.scloen);
+ i2c_sda_pad : iopad generic map (tech => padtech)
+ port map (hc_id_i2cdat, i2co.sda, i2co.sdaoen, i2ci.sda);
+ end generate i2cm;
+
+ spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
+ spi1 : spictrl
+ generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 9,
+ fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
+ slvselsz => CFG_SPICTRL_SLVS, odmode => 1)
+ port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
+ miso_pad : iopad generic map (tech => padtech)
+ port map (hc_sd_dat, spio.miso, spio.misooen, spii.miso);
+ mosi_pad : iopad generic map (tech => padtech)
+ port map (hc_sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
+ sck_pad : iopad generic map (tech => padtech)
+ port map (hc_sd_clk, spio.sck, spio.sckoen, spii.sck);
+ slvsel_pad : outpad generic map (tech => padtech)
+ port map (hc_sd_dat3, slvsel(0));
+ spii.spisel <= '1'; -- Master only
+ end generate spic;
+
+-----------------------------------------------------------------------
+-- LCD touch panel ---------------------------------------------------
+-----------------------------------------------------------------------
+
+ lcd: if CFG_LCD_ENABLE /= 0 generate -- LCD
+ lcd0 : svgactrl generic map(memtech => memtech, pindex => 11, paddr => 11,
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
+ clk0 => 30120, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 4)
+ port map(rstn, clkm, lcdclk, apbi, apbo(11), lcdo, ahbmi,
+ ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
+
+ lcdser0: serializer generic map (length => 8)
+ port map (lcdclk3x, lcdo.hsync, lcdo.video_out_b, lcdo.video_out_g,
+ lcdo.video_out_r, lcd_data);
+
+ lcdclksel <= "00";
+
+ lcdclkgen : altera_eek_clkgen
+ generic map (clk0_mul => 166, clk0_div => 250, clk1_mul => 9,
+ clk1_div => 50, clk_freq => BOARD_FREQ)
+ port map (lclk, lcdclk, lcdclk3x, lcdclksel, lcdclklck);
+
+ lcd_vert_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_vd, lcdo.vsync);
+ lcd_horiz_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_hd, lcdo.hsync);
+ lcd_video_out_pad : outpadv generic map (width => 8, tech => padtech)
+ port map (hc_lcd_data, lcd_data);
+ lcd_video_clock_pad : outpad generic map (tech => padtech)
+ port map (hc_nclk, lcdclk3x);
+ lcd_den <= lcdo.blank;
+ end generate;
+
+ nolcd : if CFG_LCD_ENABLE = 0 generate
+ apbo(11) <= apb_none; lcdo <= vgao_none;
+ lcd_den <= '0'; -- LCD RGB Data Enable
+ lcdclk <= '0'; lcdclk3x <= '0'; lcdclklck <= '1';
+ end generate;
+
+ lcd_den_pad : outpad generic map (tech => padtech)
+ port map (hc_den, lcd_den);
+
+ lcdsysreset: if CFG_LCD_ENABLE /= 0 or CFG_LCD3T_ENABLE /= 0 generate
+ lcd_grest <= rstn;
+ end generate;
+
+ lcdalwaysreset: if CFG_LCD_ENABLE = 0 and CFG_LCD3T_ENABLE = 0 generate
+ lcd_grest <= '0';
+ end generate lcdalwaysreset;
+
+ lcd_reset_pad : outpad generic map (tech => padtech) -- LCD Global Reset, active low
+ port map (hc_grest, lcd_grest);
+
+ touch3wire: if CFG_LCD3T_ENABLE /= 0 generate -- LCD 3-wire and touch panel interface
+ -- TODO:
+ -- Interrupt and busy signals not connected
+ touch3spi1 : spictrl
+ generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
+ fdepth => 2, slvselen => 1, slvselsz => 2, odmode => 0)
+ port map (rstn, clkm, apbi, apbo(12), lcdspii, lcdspio, lcdslvsel);
+ adc_miso_pad : inpad generic map (tech => padtech)
+ port map (hc_adc_dout, lcdspii.miso);
+ adc_mosi_pad : outpad generic map (tech => padtech)
+ port map (hc_adc_din, lcdspio.mosi);
+ lcd_adc_dclk_pad : outpad generic map (tech => padtech)
+ port map (hc_adc_dclk, lcdspio.sck);
+ hcd_sda_pad : iopad generic map (tech => padtech)
+ port map (hc_sda, lcdspio.mosi, lcdspio.mosioen, lcdspii.mosi);
+
+ lcdspii.spisel <= '1'; -- Master only
+ end generate;
+
+ notouch3wire: if CFG_LCD3T_ENABLE = 0 generate
+ lcdslvsel <= (others => '1');
+ apbo(12) <= apb_none;
+ end generate;
+
+ hc_adc_cs_n_pad : outpad generic map (tech => padtech)
+ port map (hc_adc_cs_n, lcdslvsel(0));
+ hc_scen_pad : outpad generic map (tech => padtech)
+ port map (hc_scen, lcdslvsel(1));
+
+-----------------------------------------------------------------------
+-- SVGA controller ----------------------------------------------------
+-----------------------------------------------------------------------
+
+ svga : if CFG_SVGA_ENABLE /= 0 generate -- VGA DAC
+ svga0 : svgactrl generic map(memtech => memtech, pindex => 13, paddr => 13,
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE,
+ clk0 => 40000, clk1 => 25000, clk2 => 0, clk3 => 0, burstlen => 4)
+ port map(rstn, clkm, vgaclk, apbi, apbo(13), vgao, ahbmi,
+ ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE),
+ vgaclksel);
+
+ svgaser0: serializer generic map (length => 8)
+ port map (vgaclk3x, vgao.hsync, vgao.video_out_b, vgao.video_out_g,
+ vgao.video_out_r, vga_data(9 downto 2));
+ vga_data(1 downto 0) <= (others => '0');
+
+ vgaclkgen : altera_eek_clkgen
+ generic map (clk0_mul => 1, clk0_div => 2, clk1_mul => 4,
+ clk1_div => 5, clk_freq => BOARD_FREQ)
+ port map (lclk, vgaclk, vgaclk3x, vgaclksel, vgaclklck);
+
+ vga_blank_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_blank, vgao.blank);
+ vga_comp_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_sync, vgao.comp_sync);
+ vga_vert_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_vs, vgao.vsync);
+ vga_horiz_sync_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_hs, vgao.hsync);
+ vga_video_out_pad : outpadv generic map (width => 10, tech => padtech)
+ port map (hc_vga_data, vga_data);
+ vga_video_clock_pad : outpad generic map (tech => padtech)
+ port map (hc_vga_clock, vgaclk3x);
+ end generate svga;
+
+ nosvga : if CFG_SVGA_ENABLE = 0 generate
+ apbo(13) <= apb_none; vgao <= vgao_none;
+ vgaclk <= '0'; vgaclk3x <= '0'; vgaclklck <= '1';
+ end generate;
+
+-----------------------------------------------------------------------
+--- ETHERNET ---------------------------------------------------------
+-----------------------------------------------------------------------
+
+ eth0 : if CFG_GRETH /= 0 generate -- Gaisler ethernet MAC
+ e1 : grethm generic map(
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE,
+ pindex => 10, paddr => 10, pirq => 10, memtech => memtech,
+ mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
+ nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
+ macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
+ ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
+ port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
+ ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE),
+ apbi => apbi, apbo => apbo(10), ethi => ethi, etho => etho);
+
+ emdio_pad : iopad generic map (tech => padtech)
+ port map (hc_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
+ etxc_pad : clkpad generic map (tech => padtech, arch => 2)
+ port map (hc_tx_clk, ethi.tx_clk);
+ erxc_pad : clkpad generic map (tech => padtech, arch => 2)
+ port map (hc_rx_clk, ethi.rx_clk);
+ erxd_pad : inpadv generic map (tech => padtech, width => 4)
+ port map (hc_rx_d, ethi.rxd(3 downto 0));
+ erxdv_pad : inpad generic map (tech => padtech)
+ port map (hc_rx_dv, ethi.rx_dv);
+ erxer_pad : inpad generic map (tech => padtech)
+ port map (hc_rx_err, ethi.rx_er);
+ erxco_pad : inpad generic map (tech => padtech)
+ port map (hc_rx_col, ethi.rx_col);
+ erxcr_pad : inpad generic map (tech => padtech)
+ port map (hc_rx_crs, ethi.rx_crs);
+
+ etxd_pad : outpadv generic map (tech => padtech, width => 4)
+ port map (hc_tx_d, etho.txd(3 downto 0));
+ etxen_pad : outpad generic map (tech => padtech)
+ port map (hc_tx_en, etho.tx_en);
+ emdc_pad : outpad generic map (tech => padtech)
+ port map (hc_mdc, etho.mdc);
+ erst_pad : outpad generic map (tech => padtech)
+ port map (hc_eth_reset_n, rawrstn);
+ end generate;
+
+-----------------------------------------------------------------------
+--- AHB ROM ----------------------------------------------------------
+-----------------------------------------------------------------------
+
+ bpromgen : if CFG_AHBROMEN /= 0 generate
+ brom : entity work.ahbrom
+ generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
+ port map ( rstn, clkm, ahbsi, ahbso(6));
+ end generate;
+ nobpromgen : if CFG_AHBROMEN = 0 generate
+ ahbso(6) <= ahbs_none;
+ end generate;
+
+-----------------------------------------------------------------------
+--- AHB RAM ----------------------------------------------------------
+-----------------------------------------------------------------------
+
+ ahbramgen : if CFG_AHBRAMEN = 1 generate
+ ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
+ tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
+ port map (rstn, clkm, ahbsi, ahbso(7));
+ end generate;
+ nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
+
+
+-----------------------------------------------------------------------
+--- YCC-RGB translation module ------------------------------------
+-----------------------------------------------------------------------
+
+ jpgycc : yccrgbs
+ generic map(shindex => 5, haddr => 16#B00#, hirq => 13, pindex => 14,
+ paddr => 7, mhindex => 3 )
+ port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
+ ahbmo => ahbmo(3), ahbsi => ahbsi, ahbso => ahbso(5),
+ apbi => apbi, apbo => apbo(14)
+ );
+
+
+
+-----------------------------------------------------------------------
+--- Drive unused bus elements ---------------------------------------
+-----------------------------------------------------------------------
+
+ nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE+CFG_GRETH + 1) to NAHBMST-1 generate
+ ahbmo(i) <= ahbm_none;
+ end generate;
+
+ -- invert signal for input via a key
+ dsubre <= not dsubren;
+
+-----------------------------------------------------------------------
+--- Boot message ----------------------------------------------------
+-----------------------------------------------------------------------
+
+-- pragma translate_off
+ x : report_version
+ generic map (
+ msg1 => "LEON3 Altera Embedded Evaluation Kit Demonstration Design",
+ msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
+ & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
+ msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
+ mdel => 1
+ );
+-- pragma translate_on
+
+end;
--- /dev/null
+/* linkcmds
+ *
+ * $Id: linkcmds,v 1.8.2.1 2000/05/24 17:06:38 joel Exp $
+ */
+
+OUTPUT_ARCH(sparc)
+__DYNAMIC = 0;
+
+/*
+ * The memory map looks like this:
+ * +--------------------+ <- low memory
+ * | .text |
+ * | etext |
+ * | ctor list | the ctor and dtor lists are for
+ * | dtor list | C++ support
+ * | _endtext |
+ * +--------------------+
+ * | .data | initialized data goes here
+ * | _sdata |
+ * | _edata |
+ * +--------------------+
+ * | .bss |
+ * | __bss_start | start of bss, cleared by crt0
+ * | _end | start of heap, used by sbrk()
+ * +--------------------+
+ * | heap space |
+ * | _ENDHEAP |
+ * | stack space |
+ * | __stack | top of stack
+ * +--------------------+ <- high memory
+ */
+
+
+/* Default values, can be overridden */
+
+_PROM_SIZE = 2M;
+_RAM_SIZE = 4M;
+
+_RAM_START = 0x02000000;
+_RAM_END = _RAM_START + _RAM_SIZE;
+
+_PROM_START = 0x00000000;
+_PROM_END = _PROM_START + _PROM_SIZE;
+
+/*
+ * Alternate names without leading _.
+ */
+
+PROM_START = _PROM_START;
+PROM_SIZE = _PROM_SIZE;
+PROM_END = _PROM_END;
+
+RAM_START = _RAM_START;
+RAM_SIZE = _RAM_SIZE;
+RAM_END = _RAM_END;
+
+_LEON_REG = 0x80000000;
+LEON_REG = 0x80000000;
+
+/* these are the maximum values */
+
+MEMORY
+{
+ rom : ORIGIN = 0x00000000, LENGTH = 16M
+ ram : ORIGIN = 0x40000000, LENGTH = 1024M
+}
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ text_start = .;
+ _text_start = .;
+ *(.text)
+ . = ALIGN (16);
+
+ *(.eh_frame)
+ . = ALIGN (16);
+
+ *(.gnu.linkonce.t*)
+
+ /*
+ * C++ constructors
+ */
+ __CTOR_LIST__ = .;
+ LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+ *(.ctors)
+ LONG(0)
+ __CTOR_END__ = .;
+ __DTOR_LIST__ = .;
+ LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+ *(.dtors)
+ LONG(0)
+ __DTOR_END__ = .;
+
+ _rodata_start = . ;
+ *(.rodata*)
+ *(.gnu.linkonce.r*)
+ _erodata = ALIGN( 0x10 ) ;
+
+ etext = ALIGN(0x10);
+ _etext = .;
+ *(.init)
+ *(.fini)
+ *(.lit)
+ *(.shdata)
+ . = ALIGN (16);
+ _endtext = .;
+ } > rom
+ .dynamic : { *(.dynamic) } >ram
+ .got : { *(.got) } >ram
+ .plt : { *(.plt) } >ram
+ .hash : { *(.hash) } >ram
+ .dynrel : { *(.dynrel) } >ram
+ .dynsym : { *(.dynsym) } >ram
+ .dynstr : { *(.dynstr) } >ram
+ .hash : { *(.hash) } >ram
+ .data :
+ {
+ data_start = .;
+ _data_start = .;
+ _sdata = . ;
+ *(.data)
+ *(.gnu.linkonce.d*)
+ *(.gcc_except_table)
+ . = ALIGN(0x10);
+ edata = .;
+ _edata = .;
+ } > ram
+ .shbss :
+ {
+ *(.shbss)
+ } > ram
+ .bss :
+ {
+ __bss_start = ALIGN(0x8);
+ _bss_start = .;
+ bss_start = .;
+ *(.bss)
+ *(COMMON)
+ end = .;
+ _end = ALIGN(0x8);
+ __end = ALIGN(0x8);
+ } > ram
+ .jcr . (NOLOAD) : { *(.jcr) }
+ .stab . (NOLOAD) :
+ {
+ [ .stab ]
+ }
+ .stabstr . (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+#define MCFG1 0x10380133
+#define MCFG2 0xe6A00e61
+//#define MCFG2 0xe6A06e60
+#define MCFG3 0x000ff000
+#define ASDCFG 0xfff00100
+#define DSDCFG 0xe6A06e60
+#define L2MCTRLIO 0x80000000
+#define IRQCTRL 0x80000200
+#define RAMSTART 0x40000000
+#define RAMSIZE 0x00100000
+#define STACKSIZE 0x00002000
+
--- /dev/null
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--- /dev/null
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+------------------------------------------------------------------------------
+-- Entity: serializer
+-- File: serializer.vhd
+-- Author: Jan Andersson - Gaisler Research AB
+-- jan@gaisler.com
+--
+-- Description: Takes in three vectors and serializes them into one
+-- output vector. Intended to be used to serialize
+-- RGB VGA data.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity serializer is
+ generic (
+ length : integer := 8 -- vector length
+ );
+ port (
+ clk : in std_ulogic;
+ sync : in std_ulogic;
+ ivec0 : in std_logic_vector((length-1) downto 0);
+ ivec1 : in std_logic_vector((length-1) downto 0);
+ ivec2 : in std_logic_vector((length-1) downto 0);
+ ovec : out std_logic_vector((length-1) downto 0)
+ );
+end entity serializer;
+
+architecture rtl of serializer is
+
+ type state_type is (vec0, vec1, vec2);
+ type sreg_type is record
+ state : state_type;
+ sync : std_logic_vector(1 downto 0);
+ end record;
+
+ signal r, rin : sreg_type;
+
+begin -- rtl
+
+ comb: process (r, clk, sync, ivec0, ivec1, ivec2)
+ variable v : sreg_type;
+ begin -- process comb
+ v := r;
+
+ v.sync := r.sync(0) & sync;
+
+ case r.state is
+ when vec0 =>
+ ovec <= ivec0;
+ v.state := vec1;
+ when vec1 =>
+ ovec <= ivec1;
+ v.state := vec2;
+ when vec2 =>
+ ovec <= ivec2;
+ v.state := vec0;
+ end case;
+
+ if (r.sync(0) xor sync) = '1' then
+ v.state := vec1;
+ end if;
+
+ rin <= v;
+ end process comb;
+
+ reg: process (clk)
+ begin -- process reg
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+ end process reg;
+
+end rtl;
--- /dev/null
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--- /dev/null
+//#define NORMALTEST
+#define IP_CONNECT
+//#define BOARD_TEST
+
+main()
+{
+#ifdef NORMALTEST
+ report_start();
+ base_test();
+ greth_test(0x80000a00);
+ i2cmst_test(0x80000800);
+ spictrl_test(0x80000900);
+ report_end();
+#endif
+
+#ifdef IP_CONNECT
+ yccrgbs_connect_neek();
+#endif
+
+#ifdef BOARD_TEST
+ yccrgbs_pic_neek();
+#endif
+
+}
--- /dev/null
+
+main()
+
+{
+ report_start();
+
+ base_test();
+
+ greth_test(0x80000a00);
+
+ i2cmst_test(0x80000800);
+
+ spictrl_test(0x80000900);
+
+ report_end();
+}
--- /dev/null
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+------------------------------------------------------------------------------
+-- Altera Cyclone-III Embedded Evaluation Kit LEON3 Demonstration design test
+-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
+-- Adapted for EEK by Jan Andersson, Gaisler Research
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.sim.all;
+library techmap;
+use techmap.gencomp.all;
+library micron;
+use micron.components.all;
+library cypress;
+use cypress.components.all;
+
+use work.debug.all;
+
+use work.config.all; -- configuration
+
+entity testbench is
+ generic (
+ fabtech : integer := CFG_FABTECH;
+ memtech : integer := CFG_MEMTECH;
+ padtech : integer := CFG_PADTECH;
+ clktech : integer := CFG_CLKTECH;
+ ncpu : integer := CFG_NCPU;
+ disas : integer := CFG_DISAS; -- Enable disassembly to console
+ dbguart : integer := CFG_DUART; -- Print UART on console
+ pclow : integer := CFG_PCLOW;
+
+ clkperiod : integer := 20; -- system clock period
+ romwidth : integer := 8; -- rom data width (8/32)
+ romdepth : integer := 23; -- rom address depth
+ sramwidth : integer := 32; -- ram data width (8/16/32)
+ sramdepth : integer := 20; -- ram address depth
+ srambanks : integer := 1 -- number of ram banks
+ );
+end;
+
+architecture behav of testbench is
+
+ constant promfile : string := "prom.srec"; -- rom contents
+ constant sramfile : string := "sram.srec"; -- ram contents
+ constant sdramfile : string := "sdram.srec"; -- sdram contents
+
+ signal clk : std_logic := '0';
+ signal clkout, pllref : std_ulogic;
+ signal rst : std_logic := '0'; -- Reset
+ constant ct : integer := clkperiod/2;
+
+ signal address : std_logic_vector(25 downto 0);
+ signal data : std_logic_vector(31 downto 0);
+ signal romsn : std_ulogic;
+ signal iosn : std_ulogic;
+ signal oen : std_ulogic;
+ signal writen : std_ulogic;
+ signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
+ signal dsurst : std_ulogic;
+ signal test : std_ulogic;
+ signal error : std_logic;
+ signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
+ signal GND : std_ulogic := '0';
+ signal VCC : std_ulogic := '1';
+ signal NC : std_ulogic := 'Z';
+ signal clk2 : std_ulogic := '1';
+
+ signal ssram_cen : std_logic;
+ signal ssram_wen : std_logic;
+ signal ssram_bw : std_logic_vector (0 to 3);
+ signal ssram_oen : std_ulogic;
+ signal ssram_clk : std_ulogic;
+ signal ssram_adscn : std_ulogic;
+ signal ssram_adsp_n : std_ulogic;
+ signal ssram_adv_n : std_ulogic;
+ signal datazz : std_logic_vector(3 downto 0);
+
+ -- ddr memory
+ signal ddr_clk : std_logic;
+ signal ddr_clkb : std_logic;
+ signal ddr_clkin : std_logic;
+ signal ddr_cke : std_logic;
+ signal ddr_csb : std_logic;
+ signal ddr_web : std_ulogic; -- ddr write enable
+ signal ddr_rasb : std_ulogic; -- ddr ras
+ signal ddr_casb : std_ulogic; -- ddr cas
+ signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
+ signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
+ signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
+ signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
+ signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
+
+ -- Connections over HSMC connector
+ -- LCD touch panel display
+ signal hc_vd : std_logic;
+ signal hc_hd : std_logic;
+ signal hc_den : std_logic;
+ signal hc_nclk : std_logic;
+ signal hc_lcd_data : std_logic_vector(7 downto 0);
+ signal hc_grest : std_logic;
+ signal hc_scen : std_logic;
+ signal hc_sda : std_logic;
+ signal hc_adc_penirq_n : std_logic;
+ signal hc_adc_dout : std_logic;
+ signal hc_adc_busy : std_logic;
+ signal hc_adc_din : std_logic;
+ signal hc_adc_dclk : std_logic;
+ signal hc_adc_cs_n : std_logic;
+
+ -- Shared by video decoder and audio codec
+ signal hc_i2c_sclk : std_logic;
+ signal hc_i2c_sdat : std_logic;
+
+ -- Video decoder
+ signal hc_td_d : std_logic_vector(7 downto 0);
+ signal hc_td_hs : std_logic;
+ signal hc_td_vs : std_logic;
+ signal hc_td_27mhz : std_logic;
+ signal hc_td_reset : std_logic;
+
+ -- Audio codec
+ signal hc_aud_adclrck : std_logic;
+ signal hc_aud_adcdat : std_logic;
+ signal hc_aud_daclrck : std_logic;
+ signal hc_aud_dacdat : std_logic;
+ signal hc_aud_bclk : std_logic;
+ signal hc_aud_xck : std_logic;
+
+ -- SD card
+ signal hc_sd_dat : std_logic;
+ signal hc_sd_dat3 : std_logic;
+ signal hc_sd_cmd : std_logic;
+ signal hc_sd_clk : std_logic;
+
+ -- Ethernet PHY
+ signal hc_tx_d : std_logic_vector(3 downto 0);
+ signal hc_rx_d : std_logic_vector(3 downto 0);
+ signal hc_tx_clk : std_logic;
+ signal hc_rx_clk : std_logic;
+ signal hc_tx_en : std_logic;
+ signal hc_rx_dv : std_logic;
+ signal hc_rx_crs : std_logic;
+ signal hc_rx_err : std_logic;
+ signal hc_rx_col : std_logic;
+ signal hc_mdio : std_logic;
+ signal hc_mdc : std_logic;
+ signal hc_eth_reset_n : std_logic;
+
+ -- RX232 (console/debug UART)
+ signal hc_uart_rxd : std_logic;
+ signal hc_uart_txd : std_logic;
+
+ -- PS/2
+ signal hc_ps2_dat : std_logic;
+ signal hc_ps2_clk : std_logic;
+
+ -- VGA/DAC
+ signal hc_vga_data : std_logic_vector(9 downto 0);
+ signal hc_vga_clock : std_ulogic;
+ signal hc_vga_hs : std_ulogic;
+ signal hc_vga_vs : std_ulogic;
+ signal hc_vga_blank : std_ulogic;
+ signal hc_vga_sync : std_ulogic;
+
+ -- I2C EEPROM
+ signal hc_id_i2cscl : std_logic;
+ signal hc_id_i2cdat : std_logic;
+
+ -- Ethernet PHY sim model
+ signal phy_tx_er : std_ulogic;
+ signal phy_gtx_clk : std_ulogic;
+ signal hc_tx_dt : std_logic_vector(7 downto 0) := (others => '0');
+ signal hc_rx_dt : std_logic_vector(7 downto 0) := (others => '0');
+
+ constant lresp : boolean := false;
+
+begin
+
+-- clock and reset
+
+ clk <= not clk after ct * 1 ns;
+ ddr_clkin <= not clk after ct * 1 ns;
+ rst <= dsurst;
+ dsubren <= '1'; hc_uart_rxd <= '1';
+ address(0) <= '0';
+
+-- ddr_dqs <= (others => 'L');
+ d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
+ ncpu, disas, dbguart, pclow )
+ port map (rst, clk, error,
+ address(25 downto 1), data, romsn, oen, writen, open,
+ ssram_cen, ssram_wen, ssram_bw, ssram_oen,
+ ssram_clk, ssram_adscn, iosn,
+ -- DDR
+ ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
+ ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
+ -- DSU
+ dsubren, dsuact,
+ -- I/O port
+ gpio,
+ -- LCD
+ hc_vd, hc_hd, hc_den, hc_nclk, hc_lcd_data, hc_grest, hc_scen,
+ hc_sda, hc_adc_penirq_n, hc_adc_dout, hc_adc_busy, hc_adc_din,
+ hc_adc_dclk, hc_adc_cs_n,
+ -- Shared by video decoder and audio codec
+ hc_i2c_sclk, hc_i2c_sdat,
+ -- Video decoder
+ hc_td_d, hc_td_hs, hc_td_vs, hc_td_27mhz, hc_td_reset,
+ -- Audio codec
+ hc_aud_adclrck, hc_aud_adcdat, hc_aud_daclrck, hc_aud_dacdat,
+ hc_aud_bclk, hc_aud_xck,
+ -- SD card
+ hc_sd_dat, hc_sd_dat3, hc_sd_cmd, hc_sd_clk,
+ -- Ethernet PHY
+ hc_tx_d, hc_rx_d, hc_tx_clk, hc_rx_clk, hc_tx_en, hc_rx_dv, hc_rx_crs,
+ hc_rx_err, hc_rx_col, hc_mdio, hc_mdc, hc_eth_reset_n,
+ -- RX232 (console/debug UART)
+ hc_uart_rxd, hc_uart_txd,
+ -- PS/2
+ hc_ps2_dat, hc_ps2_clk,
+ -- VGA/DAC
+ hc_vga_data, hc_vga_clock, hc_vga_hs, hc_vga_vs, hc_vga_blank, hc_vga_sync,
+ -- I2C EEPROM
+ hc_id_i2cscl, hc_id_i2cdat
+ );
+
+ -- I2C bus pull-ups
+ hc_i2c_sclk <= 'H'; hc_i2c_sdat <= 'H';
+ hc_id_i2cscl <= 'H'; hc_id_i2cdat <= 'H';
+
+ -- SD card signals
+ hc_sd_dat <= 'L'; hc_sd_cmd <= 'Z';
+
+ ddr0 : mt46v16m16
+ generic map (index => -1, fname => sdramfile)
+ port map(
+ Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
+ Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
+ Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
+ Dm => ddr_dm(1 downto 0));
+
+ datazz <= "HHHH";
+
+ ssram_adsp_n <= '1'; ssram_adv_n <= '1';
+ ssram0 : cy7c1380d generic map (fname => sramfile)
+ port map(
+ ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => data,
+ iAddr => address(20 downto 2), iMode => gnd,
+ inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
+ inADSP => ssram_adsp_n, inADSC => ssram_adscn,
+ iClk => ssram_clk,
+ inBwa => ssram_bw(3), inBwb => ssram_bw(2),
+ inBwc => ssram_bw(1), inBwd => ssram_bw(0),
+ inOE => ssram_oen, inCE1 => ssram_cen,
+ iCE2 => vcc, inCE3 => gnd, iZz => gnd);
+
+ -- 16 bit prom
+ prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
+ port map (address(romdepth downto 1), data(31 downto 16),
+ gnd, gnd, romsn, writen, oen);
+
+ -- Ethernet PHY
+ hc_mdio <= 'H';
+ phy_tx_er <= '0';
+ phy_gtx_clk <= '0';
+ hc_tx_dt(3 downto 0) <= hc_tx_d;
+ hc_rx_d <= hc_rx_dt(3 downto 0);
+ p0: phy
+ generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
+ port map(hc_eth_reset_n, hc_mdio, hc_tx_clk, hc_rx_clk, hc_rx_dt, hc_rx_dv,
+ hc_rx_err, hc_rx_col, hc_rx_crs, hc_tx_dt, hc_tx_en, phy_tx_er, hc_mdc, phy_gtx_clk);
+
+ -- I2C memory
+ i0: i2c_slave_model
+ port map (hc_id_i2cscl, hc_id_i2cdat);
+
+ error <= 'H'; -- ERROR pull-up
+
+ iuerr : process
+ begin
+ wait for 2500 ns;
+ if to_x01(error) = '1' then wait on error; end if;
+ assert (to_x01(error) = '1')
+ report "*** IU in error mode, simulation halted ***"
+ severity failure ;
+ end process;
+
+ data <= buskeep(data), (others => 'H') after 250 ns;
+
+ test0 : grtestmod
+ port map ( rst, clk, error, address(21 downto 2), data,
+ iosn, oen, writen, open);
+
+ dsucom : process
+ procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
+ variable w32 : std_logic_vector(31 downto 0);
+ variable c8 : std_logic_vector(7 downto 0);
+ constant txp : time := 160 * 1 ns;
+ begin
+ dsutx <= '1';
+ dsurst <= '0';
+ wait for 500 ns;
+ dsurst <= '1';
+ wait;
+ wait for 5000 ns;
+ txc(dsutx, 16#55#, txp); -- sync uart
+
+-- txc(dsutx, 16#c0#, txp);
+-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
+-- txc(dsutx, 16#c0#, txp);
+-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
+-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
+-- txc(dsutx, 16#c0#, txp);
+-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
+-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
+-- txc(dsutx, 16#c0#, txp);
+-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
+ txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
+
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
+
+ txc(dsutx, 16#80#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+ rxi(dsurx, w32, txp, lresp);
+
+ txc(dsutx, 16#a0#, txp);
+ txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
+ rxi(dsurx, w32, txp, lresp);
+
+ end;
+
+ begin
+
+ dsucfg(dsutx, dsurx);
+
+ wait;
+ end process;
+end ;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+------------------------------------------------------------------------------
+-- Altera Cyclone-III Embedded Evaluation Kit LEON3 Demonstration design test
+-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
+-- Adapted for EEK by Jan Andersson, Gaisler Research
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.sim.all;
+library techmap;
+use techmap.gencomp.all;
+library micron;
+use micron.components.all;
+library cypress;
+use cypress.components.all;
+
+use work.debug.all;
+
+use work.config.all; -- configuration
+
+entity testbench is
+ generic (
+ fabtech : integer := CFG_FABTECH;
+ memtech : integer := CFG_MEMTECH;
+ padtech : integer := CFG_PADTECH;
+ clktech : integer := CFG_CLKTECH;
+ ncpu : integer := CFG_NCPU;
+ disas : integer := CFG_DISAS; -- Enable disassembly to console
+ dbguart : integer := CFG_DUART; -- Print UART on console
+ pclow : integer := CFG_PCLOW;
+
+ clkperiod : integer := 20; -- system clock period
+ romwidth : integer := 8; -- rom data width (8/32)
+ romdepth : integer := 23; -- rom address depth
+ sramwidth : integer := 32; -- ram data width (8/16/32)
+ sramdepth : integer := 20; -- ram address depth
+ srambanks : integer := 1 -- number of ram banks
+ );
+end;
+
+architecture behav of testbench is
+
+ constant promfile : string := "prom.srec"; -- rom contents
+ constant sramfile : string := "sram.srec"; -- ram contents
+ constant sdramfile : string := "sdram.srec"; -- sdram contents
+
+ signal clk : std_logic := '0';
+ signal clkout, pllref : std_ulogic;
+ signal rst : std_logic := '0'; -- Reset
+ constant ct : integer := clkperiod/2;
+
+ signal address : std_logic_vector(25 downto 0);
+ signal data : std_logic_vector(31 downto 0);
+ signal romsn : std_ulogic;
+ signal iosn : std_ulogic;
+ signal oen : std_ulogic;
+ signal writen : std_ulogic;
+ signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
+ signal dsurst : std_ulogic;
+ signal test : std_ulogic;
+ signal error : std_logic;
+ signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
+ signal GND : std_ulogic := '0';
+ signal VCC : std_ulogic := '1';
+ signal NC : std_ulogic := 'Z';
+ signal clk2 : std_ulogic := '1';
+
+ signal ssram_cen : std_logic;
+ signal ssram_wen : std_logic;
+ signal ssram_bw : std_logic_vector (0 to 3);
+ signal ssram_oen : std_ulogic;
+ signal ssram_clk : std_ulogic;
+ signal ssram_adscn : std_ulogic;
+ signal ssram_adsp_n : std_ulogic;
+ signal ssram_adv_n : std_ulogic;
+ signal datazz : std_logic_vector(3 downto 0);
+
+ -- ddr memory
+ signal ddr_clk : std_logic;
+ signal ddr_clkb : std_logic;
+ signal ddr_clkin : std_logic;
+ signal ddr_cke : std_logic;
+ signal ddr_csb : std_logic;
+ signal ddr_web : std_ulogic; -- ddr write enable
+ signal ddr_rasb : std_ulogic; -- ddr ras
+ signal ddr_casb : std_ulogic; -- ddr cas
+ signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
+ signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
+ signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
+ signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
+ signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
+
+ -- Connections over HSMC connector
+ -- LCD touch panel display
+ signal hc_vd : std_logic;
+ signal hc_hd : std_logic;
+ signal hc_den : std_logic;
+ signal hc_nclk : std_logic;
+ signal hc_lcd_data : std_logic_vector(7 downto 0);
+ signal hc_grest : std_logic;
+ signal hc_scen : std_logic;
+ signal hc_sda : std_logic;
+ signal hc_adc_penirq_n : std_logic;
+ signal hc_adc_dout : std_logic;
+ signal hc_adc_busy : std_logic;
+ signal hc_adc_din : std_logic;
+ signal hc_adc_dclk : std_logic;
+ signal hc_adc_cs_n : std_logic;
+
+ -- Shared by video decoder and audio codec
+ signal hc_i2c_sclk : std_logic;
+ signal hc_i2c_sdat : std_logic;
+
+ -- Video decoder
+ signal hc_td_d : std_logic_vector(7 downto 0);
+ signal hc_td_hs : std_logic;
+ signal hc_td_vs : std_logic;
+ signal hc_td_27mhz : std_logic;
+ signal hc_td_reset : std_logic;
+
+ -- Audio codec
+ signal hc_aud_adclrck : std_logic;
+ signal hc_aud_adcdat : std_logic;
+ signal hc_aud_daclrck : std_logic;
+ signal hc_aud_dacdat : std_logic;
+ signal hc_aud_bclk : std_logic;
+ signal hc_aud_xck : std_logic;
+
+ -- SD card
+ signal hc_sd_dat : std_logic;
+ signal hc_sd_dat3 : std_logic;
+ signal hc_sd_cmd : std_logic;
+ signal hc_sd_clk : std_logic;
+
+ -- Ethernet PHY
+ signal hc_tx_d : std_logic_vector(3 downto 0);
+ signal hc_rx_d : std_logic_vector(3 downto 0);
+ signal hc_tx_clk : std_logic;
+ signal hc_rx_clk : std_logic;
+ signal hc_tx_en : std_logic;
+ signal hc_rx_dv : std_logic;
+ signal hc_rx_crs : std_logic;
+ signal hc_rx_err : std_logic;
+ signal hc_rx_col : std_logic;
+ signal hc_mdio : std_logic;
+ signal hc_mdc : std_logic;
+ signal hc_eth_reset_n : std_logic;
+
+ -- RX232 (console/debug UART)
+ signal hc_uart_rxd : std_logic;
+ signal hc_uart_txd : std_logic;
+
+ -- PS/2
+ signal hc_ps2_dat : std_logic;
+ signal hc_ps2_clk : std_logic;
+
+ -- VGA/DAC
+ signal hc_vga_data : std_logic_vector(9 downto 0);
+ signal hc_vga_clock : std_ulogic;
+ signal hc_vga_hs : std_ulogic;
+ signal hc_vga_vs : std_ulogic;
+ signal hc_vga_blank : std_ulogic;
+ signal hc_vga_sync : std_ulogic;
+
+ -- I2C EEPROM
+ signal hc_id_i2cscl : std_logic;
+ signal hc_id_i2cdat : std_logic;
+
+ -- Ethernet PHY sim model
+ signal phy_tx_er : std_ulogic;
+ signal phy_gtx_clk : std_ulogic;
+ signal hc_tx_dt : std_logic_vector(7 downto 0) := (others => '0');
+ signal hc_rx_dt : std_logic_vector(7 downto 0) := (others => '0');
+
+ constant lresp : boolean := false;
+
+begin
+
+-- clock and reset
+
+ clk <= not clk after ct * 1 ns;
+ ddr_clkin <= not clk after ct * 1 ns;
+ rst <= dsurst;
+ dsubren <= '1'; hc_uart_rxd <= '1';
+ address(0) <= '0';
+
+-- ddr_dqs <= (others => 'L');
+ d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
+ ncpu, disas, dbguart, pclow )
+ port map (rst, clk, error,
+ address(25 downto 1), data, romsn, oen, writen, open,
+ ssram_cen, ssram_wen, ssram_bw, ssram_oen,
+ ssram_clk, ssram_adscn, iosn,
+ -- DDR
+ ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
+ ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
+ -- DSU
+ dsubren, dsuact,
+ -- I/O port
+ gpio,
+ -- LCD
+ hc_vd, hc_hd, hc_den, hc_nclk, hc_lcd_data, hc_grest, hc_scen,
+ hc_sda, hc_adc_penirq_n, hc_adc_dout, hc_adc_busy, hc_adc_din,
+ hc_adc_dclk, hc_adc_cs_n,
+ -- Shared by video decoder and audio codec
+ hc_i2c_sclk, hc_i2c_sdat,
+ -- Video decoder
+ hc_td_d, hc_td_hs, hc_td_vs, hc_td_27mhz, hc_td_reset,
+ -- Audio codec
+ hc_aud_adclrck, hc_aud_adcdat, hc_aud_daclrck, hc_aud_dacdat,
+ hc_aud_bclk, hc_aud_xck,
+ -- SD card
+ hc_sd_dat, hc_sd_dat3, hc_sd_cmd, hc_sd_clk,
+ -- Ethernet PHY
+ hc_tx_d, hc_rx_d, hc_tx_clk, hc_rx_clk, hc_tx_en, hc_rx_dv, hc_rx_crs,
+ hc_rx_err, hc_rx_col, hc_mdio, hc_mdc, hc_eth_reset_n,
+ -- RX232 (console/debug UART)
+ hc_uart_rxd, hc_uart_txd,
+ -- PS/2
+ hc_ps2_dat, hc_ps2_clk,
+ -- VGA/DAC
+ hc_vga_data, hc_vga_clock, hc_vga_hs, hc_vga_vs, hc_vga_blank, hc_vga_sync,
+ -- I2C EEPROM
+ hc_id_i2cscl, hc_id_i2cdat
+ );
+
+ -- I2C bus pull-ups
+ hc_i2c_sclk <= 'H'; hc_i2c_sdat <= 'H';
+ hc_id_i2cscl <= 'H'; hc_id_i2cdat <= 'H';
+
+ -- SD card signals
+ hc_sd_dat <= 'L'; hc_sd_cmd <= 'Z';
+
+ ddr0 : mt46v16m16
+ generic map (index => -1, fname => sdramfile)
+ port map(
+ Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
+ Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
+ Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
+ Dm => ddr_dm(1 downto 0));
+
+ datazz <= "HHHH";
+
+ ssram_adsp_n <= '1'; ssram_adv_n <= '1';
+ ssram0 : cy7c1380d generic map (fname => sramfile)
+ port map(
+ ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => data,
+ iAddr => address(20 downto 2), iMode => gnd,
+ inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
+ inADSP => ssram_adsp_n, inADSC => ssram_adscn,
+ iClk => ssram_clk,
+ inBwa => ssram_bw(3), inBwb => ssram_bw(2),
+ inBwc => ssram_bw(1), inBwd => ssram_bw(0),
+ inOE => ssram_oen, inCE1 => ssram_cen,
+ iCE2 => vcc, inCE3 => gnd, iZz => gnd);
+
+ -- 16 bit prom
+ prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
+ port map (address(romdepth downto 1), data(31 downto 16),
+ gnd, gnd, romsn, writen, oen);
+
+ -- Ethernet PHY
+ hc_mdio <= 'H';
+ phy_tx_er <= '0';
+ phy_gtx_clk <= '0';
+ hc_tx_dt(3 downto 0) <= hc_tx_d;
+ hc_rx_d <= hc_rx_dt(3 downto 0);
+ p0: phy
+ generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
+ port map(hc_eth_reset_n, hc_mdio, hc_tx_clk, hc_rx_clk, hc_rx_dt, hc_rx_dv,
+ hc_rx_err, hc_rx_col, hc_rx_crs, hc_tx_dt, hc_tx_en, phy_tx_er, hc_mdc, phy_gtx_clk);
+
+ -- I2C memory
+-- i0: i2c_slave_model
+-- port map (hc_id_i2cscl, hc_id_i2cdat);
+
+ error <= 'H'; -- ERROR pull-up
+
+ iuerr : process
+ begin
+ wait for 2500 ns;
+ if to_x01(error) = '1' then wait on error; end if;
+ assert (to_x01(error) = '1')
+ report "*** IU in error mode, simulation halted ***"
+ severity failure ;
+ end process;
+
+ data <= buskeep(data), (others => 'H') after 250 ns;
+
+ test0 : grtestmod
+ port map ( rst, clk, error, address(21 downto 2), data,
+ iosn, oen, writen, open);
+
+ dsucom : process
+ procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
+ variable w32 : std_logic_vector(31 downto 0);
+ variable c8 : std_logic_vector(7 downto 0);
+ constant txp : time := 160 * 1 ns;
+ begin
+ dsutx <= '1';
+ dsurst <= '0';
+ wait for 500 ns;
+ dsurst <= '1';
+ wait;
+ wait for 5000 ns;
+ txc(dsutx, 16#55#, txp); -- sync uart
+
+-- txc(dsutx, 16#c0#, txp);
+-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
+-- txc(dsutx, 16#c0#, txp);
+-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
+-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
+-- txc(dsutx, 16#c0#, txp);
+-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
+-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
+-- txc(dsutx, 16#c0#, txp);
+-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
+ txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
+
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
+
+ txc(dsutx, 16#80#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+ rxi(dsurx, w32, txp, lresp);
+
+ txc(dsutx, 16#a0#, txp);
+ txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
+ rxi(dsurx, w32, txp, lresp);
+
+ end;
+
+ begin
+
+ dsucfg(dsutx, dsurx);
+
+ wait;
+ end process;
+end ;
+
--- /dev/null
+#if defined CONFIG_SYN_INFERRED
+#define CONFIG_SYN_TECH inferred
+#elif defined CONFIG_SYN_UMC
+#define CONFIG_SYN_TECH umc
+#elif defined CONFIG_SYN_RHUMC
+#define CONFIG_SYN_TECH rhumc
+#elif defined CONFIG_SYN_ATC18
+#define CONFIG_SYN_TECH atc18s
+#elif defined CONFIG_SYN_ATC18RHA
+#define CONFIG_SYN_TECH atc18rha
+#elif defined CONFIG_SYN_AXCEL
+#define CONFIG_SYN_TECH axcel
+#elif defined CONFIG_SYN_AXDSP
+#define CONFIG_SYN_TECH axdsp
+#elif defined CONFIG_SYN_PROASICPLUS
+#define CONFIG_SYN_TECH proasic
+#elif defined CONFIG_SYN_ALTERA
+#define CONFIG_SYN_TECH altera
+#elif defined CONFIG_SYN_STRATIX
+#define CONFIG_SYN_TECH stratix1
+#elif defined CONFIG_SYN_STRATIXII
+#define CONFIG_SYN_TECH stratix2
+#elif defined CONFIG_SYN_STRATIXIII
+#define CONFIG_SYN_TECH stratix3
+#elif defined CONFIG_SYN_CYCLONEIII
+#define CONFIG_SYN_TECH cyclone3
+#elif defined CONFIG_SYN_EASIC90
+#define CONFIG_SYN_TECH easic90
+#elif defined CONFIG_SYN_IHP25
+#define CONFIG_SYN_TECH ihp25
+#elif defined CONFIG_SYN_IHP25RH
+#define CONFIG_SYN_TECH ihp25rh
+#elif defined CONFIG_SYN_LATTICE
+#define CONFIG_SYN_TECH lattice
+#elif defined CONFIG_SYN_ECLIPSE
+#define CONFIG_SYN_TECH eclipse
+#elif defined CONFIG_SYN_PEREGRINE
+#define CONFIG_SYN_TECH peregrine
+#elif defined CONFIG_SYN_PROASIC
+#define CONFIG_SYN_TECH proasic
+#elif defined CONFIG_SYN_PROASIC3
+#define CONFIG_SYN_TECH apa3
+#elif defined CONFIG_SYN_IGLOO
+#define CONFIG_SYN_TECH apa3
+#elif defined CONFIG_SYN_SPARTAN2
+#define CONFIG_SYN_TECH virtex
+#elif defined CONFIG_SYN_VIRTEX
+#define CONFIG_SYN_TECH virtex
+#elif defined CONFIG_SYN_VIRTEXE
+#define CONFIG_SYN_TECH virtex
+#elif defined CONFIG_SYN_SPARTAN3
+#define CONFIG_SYN_TECH spartan3
+#elif defined CONFIG_SYN_SPARTAN3E
+#define CONFIG_SYN_TECH spartan3e
+#elif defined CONFIG_SYN_VIRTEX2
+#define CONFIG_SYN_TECH virtex2
+#elif defined CONFIG_SYN_VIRTEX4
+#define CONFIG_SYN_TECH virtex4
+#elif defined CONFIG_SYN_VIRTEX5
+#define CONFIG_SYN_TECH virtex5
+#elif defined CONFIG_SYN_RH_LIB18T
+#define CONFIG_SYN_TECH rhlib18t
+#elif defined CONFIG_SYN_SMIC13
+#define CONFIG_SYN_TECH smic013
+#elif defined CONFIG_SYN_UT025CRH
+#define CONFIG_SYN_TECH ut25
+#elif defined CONFIG_SYN_TSMC90
+#define CONFIG_SYN_TECH tsmc90
+#elif defined CONFIG_SYN_CUSTOM1
+#define CONFIG_SYN_TECH custom1
+#else
+#error "unknown target technology"
+#endif
+
+#if defined CONFIG_SYN_INFER_RAM
+#define CFG_RAM_TECH inferred
+#elif defined CONFIG_MEM_UMC
+#define CFG_RAM_TECH umc
+#elif defined CONFIG_MEM_RHUMC
+#define CFG_RAM_TECH rhumc
+#elif defined CONFIG_MEM_VIRAGE
+#define CFG_RAM_TECH memvirage
+#elif defined CONFIG_MEM_ARTISAN
+#define CFG_RAM_TECH memartisan
+#elif defined CONFIG_MEM_CUSTOM1
+#define CFG_RAM_TECH custom1
+#elif defined CONFIG_MEM_VIRAGE90
+#define CFG_RAM_TECH memvirage90
+#elif defined CONFIG_MEM_INFERRED
+#define CFG_RAM_TECH inferred
+#else
+#define CFG_RAM_TECH CONFIG_SYN_TECH
+#endif
+
+#if defined CONFIG_SYN_INFER_PADS
+#define CFG_PAD_TECH inferred
+#else
+#define CFG_PAD_TECH CONFIG_SYN_TECH
+#endif
+
+#ifndef CONFIG_SYN_NO_ASYNC
+#define CONFIG_SYN_NO_ASYNC 0
+#endif
+
+#ifndef CONFIG_SYN_SCAN
+#define CONFIG_SYN_SCAN 0
+#endif
+
+
+#if defined CONFIG_CLK_ALTDLL
+#define CFG_CLK_TECH CONFIG_SYN_TECH
+#elif defined CONFIG_CLK_HCLKBUF
+#define CFG_CLK_TECH axcel
+#elif defined CONFIG_CLK_LATDLL
+#define CFG_CLK_TECH lattice
+#elif defined CONFIG_CLK_PRO3PLL
+#define CFG_CLK_TECH apa3
+#elif defined CONFIG_CLK_CLKDLL
+#define CFG_CLK_TECH virtex
+#elif defined CONFIG_CLK_DCM
+#define CFG_CLK_TECH CONFIG_SYN_TECH
+#elif defined CONFIG_CLK_LIB18T
+#define CFG_CLK_TECH rhlib18t
+#elif defined CONFIG_CLK_RHUMC
+#define CFG_CLK_TECH rhumc
+#else
+#define CFG_CLK_TECH inferred
+#endif
+
+#ifndef CONFIG_CLK_MUL
+#define CONFIG_CLK_MUL 2
+#endif
+
+#ifndef CONFIG_CLK_DIV
+#define CONFIG_CLK_DIV 2
+#endif
+
+#ifndef CONFIG_OCLK_DIV
+#define CONFIG_OCLK_DIV 2
+#endif
+
+#ifndef CONFIG_PCI_CLKDLL
+#define CONFIG_PCI_CLKDLL 0
+#endif
+
+#ifndef CONFIG_PCI_SYSCLK
+#define CONFIG_PCI_SYSCLK 0
+#endif
+
+#ifndef CONFIG_CLK_NOFB
+#define CONFIG_CLK_NOFB 0
+#endif
+#ifndef CONFIG_LEON3
+#define CONFIG_LEON3 0
+#endif
+
+#ifndef CONFIG_PROC_NUM
+#define CONFIG_PROC_NUM 1
+#endif
+
+#ifndef CONFIG_IU_NWINDOWS
+#define CONFIG_IU_NWINDOWS 8
+#endif
+
+#ifndef CONFIG_IU_RSTADDR
+#define CONFIG_IU_RSTADDR 8
+#endif
+
+#ifndef CONFIG_IU_LDELAY
+#define CONFIG_IU_LDELAY 1
+#endif
+
+#ifndef CONFIG_IU_WATCHPOINTS
+#define CONFIG_IU_WATCHPOINTS 0
+#endif
+
+#ifdef CONFIG_IU_V8MULDIV
+#ifdef CONFIG_IU_MUL_LATENCY_4
+#define CFG_IU_V8 1
+#elif defined CONFIG_IU_MUL_LATENCY_5
+#define CFG_IU_V8 2
+#elif defined CONFIG_IU_MUL_LATENCY_2
+#define CFG_IU_V8 16#32#
+#endif
+#else
+#define CFG_IU_V8 0
+#endif
+
+#ifndef CONFIG_PWD
+#define CONFIG_PWD 0
+#endif
+
+#ifndef CONFIG_IU_MUL_MAC
+#define CONFIG_IU_MUL_MAC 0
+#endif
+
+#ifndef CONFIG_IU_SVT
+#define CONFIG_IU_SVT 0
+#endif
+
+#if defined CONFIG_FPU_GRFPC1
+#define CONFIG_FPU_GRFPC 1
+#elif defined CONFIG_FPU_GRFPC2
+#define CONFIG_FPU_GRFPC 2
+#else
+#define CONFIG_FPU_GRFPC 0
+#endif
+
+#if defined CONFIG_FPU_GRFPU_INFMUL
+#define CONFIG_FPU_GRFPU_MUL 0
+#elif defined CONFIG_FPU_GRFPU_DWMUL
+#define CONFIG_FPU_GRFPU_MUL 1
+#elif defined CONFIG_FPU_GRFPU_MODGEN
+#define CONFIG_FPU_GRFPU_MUL 2
+#elif defined CONFIG_FPU_GRFPU_TECHSPEC
+#define CONFIG_FPU_GRFPU_MUL 3
+#else
+#define CONFIG_FPU_GRFPU_MUL 0
+#endif
+
+#if defined CONFIG_FPU_GRFPU_SH
+#define CONFIG_FPU_GRFPU_SHARED 1
+#else
+#define CONFIG_FPU_GRFPU_SHARED 0
+#endif
+
+#if defined CONFIG_FPU_GRFPU
+#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
+#elif defined CONFIG_FPU_MEIKO
+#define CONFIG_FPU 15
+#elif defined CONFIG_FPU_GRFPULITE
+#define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
+#else
+#define CONFIG_FPU 0
+#endif
+
+#ifndef CONFIG_FPU_NETLIST
+#define CONFIG_FPU_NETLIST 0
+#endif
+
+#ifndef CONFIG_ICACHE_ENABLE
+#define CONFIG_ICACHE_ENABLE 0
+#endif
+
+#if defined CONFIG_ICACHE_ASSO1
+#define CFG_IU_ISETS 1
+#elif defined CONFIG_ICACHE_ASSO2
+#define CFG_IU_ISETS 2
+#elif defined CONFIG_ICACHE_ASSO3
+#define CFG_IU_ISETS 3
+#elif defined CONFIG_ICACHE_ASSO4
+#define CFG_IU_ISETS 4
+#else
+#define CFG_IU_ISETS 1
+#endif
+
+#if defined CONFIG_ICACHE_SZ1
+#define CFG_ICACHE_SZ 1
+#elif defined CONFIG_ICACHE_SZ2
+#define CFG_ICACHE_SZ 2
+#elif defined CONFIG_ICACHE_SZ4
+#define CFG_ICACHE_SZ 4
+#elif defined CONFIG_ICACHE_SZ8
+#define CFG_ICACHE_SZ 8
+#elif defined CONFIG_ICACHE_SZ16
+#define CFG_ICACHE_SZ 16
+#elif defined CONFIG_ICACHE_SZ32
+#define CFG_ICACHE_SZ 32
+#elif defined CONFIG_ICACHE_SZ64
+#define CFG_ICACHE_SZ 64
+#elif defined CONFIG_ICACHE_SZ128
+#define CFG_ICACHE_SZ 128
+#elif defined CONFIG_ICACHE_SZ256
+#define CFG_ICACHE_SZ 256
+#else
+#define CFG_ICACHE_SZ 1
+#endif
+
+#ifdef CONFIG_ICACHE_LZ16
+#define CFG_ILINE_SZ 4
+#else
+#define CFG_ILINE_SZ 8
+#endif
+
+#if defined CONFIG_ICACHE_ALGORND
+#define CFG_ICACHE_ALGORND 2
+#elif defined CONFIG_ICACHE_ALGOLRR
+#define CFG_ICACHE_ALGORND 1
+#else
+#define CFG_ICACHE_ALGORND 0
+#endif
+
+#ifndef CONFIG_ICACHE_LOCK
+#define CONFIG_ICACHE_LOCK 0
+#endif
+
+#ifndef CONFIG_ICACHE_LRAM
+#define CONFIG_ICACHE_LRAM 0
+#endif
+
+#ifndef CONFIG_ICACHE_LRSTART
+#define CONFIG_ICACHE_LRSTART 8E
+#endif
+
+#if defined CONFIG_ICACHE_LRAM_SZ2
+#define CFG_ILRAM_SIZE 2
+#elif defined CONFIG_ICACHE_LRAM_SZ4
+#define CFG_ILRAM_SIZE 4
+#elif defined CONFIG_ICACHE_LRAM_SZ8
+#define CFG_ILRAM_SIZE 8
+#elif defined CONFIG_ICACHE_LRAM_SZ16
+#define CFG_ILRAM_SIZE 16
+#elif defined CONFIG_ICACHE_LRAM_SZ32
+#define CFG_ILRAM_SIZE 32
+#elif defined CONFIG_ICACHE_LRAM_SZ64
+#define CFG_ILRAM_SIZE 64
+#elif defined CONFIG_ICACHE_LRAM_SZ128
+#define CFG_ILRAM_SIZE 128
+#elif defined CONFIG_ICACHE_LRAM_SZ256
+#define CFG_ILRAM_SIZE 256
+#else
+#define CFG_ILRAM_SIZE 1
+#endif
+
+
+#ifndef CONFIG_DCACHE_ENABLE
+#define CONFIG_DCACHE_ENABLE 0
+#endif
+
+#if defined CONFIG_DCACHE_ASSO1
+#define CFG_IU_DSETS 1
+#elif defined CONFIG_DCACHE_ASSO2
+#define CFG_IU_DSETS 2
+#elif defined CONFIG_DCACHE_ASSO3
+#define CFG_IU_DSETS 3
+#elif defined CONFIG_DCACHE_ASSO4
+#define CFG_IU_DSETS 4
+#else
+#define CFG_IU_DSETS 1
+#endif
+
+#if defined CONFIG_DCACHE_SZ1
+#define CFG_DCACHE_SZ 1
+#elif defined CONFIG_DCACHE_SZ2
+#define CFG_DCACHE_SZ 2
+#elif defined CONFIG_DCACHE_SZ4
+#define CFG_DCACHE_SZ 4
+#elif defined CONFIG_DCACHE_SZ8
+#define CFG_DCACHE_SZ 8
+#elif defined CONFIG_DCACHE_SZ16
+#define CFG_DCACHE_SZ 16
+#elif defined CONFIG_DCACHE_SZ32
+#define CFG_DCACHE_SZ 32
+#elif defined CONFIG_DCACHE_SZ64
+#define CFG_DCACHE_SZ 64
+#elif defined CONFIG_DCACHE_SZ128
+#define CFG_DCACHE_SZ 128
+#elif defined CONFIG_DCACHE_SZ256
+#define CFG_DCACHE_SZ 256
+#else
+#define CFG_DCACHE_SZ 1
+#endif
+
+#ifdef CONFIG_DCACHE_LZ16
+#define CFG_DLINE_SZ 4
+#else
+#define CFG_DLINE_SZ 8
+#endif
+
+#if defined CONFIG_DCACHE_ALGORND
+#define CFG_DCACHE_ALGORND 2
+#elif defined CONFIG_DCACHE_ALGOLRR
+#define CFG_DCACHE_ALGORND 1
+#else
+#define CFG_DCACHE_ALGORND 0
+#endif
+
+#ifndef CONFIG_DCACHE_LOCK
+#define CONFIG_DCACHE_LOCK 0
+#endif
+
+#ifndef CONFIG_DCACHE_SNOOP
+#define CONFIG_DCACHE_SNOOP 0
+#endif
+
+#ifndef CONFIG_DCACHE_SNOOP_FAST
+#define CONFIG_DCACHE_SNOOP_FAST 0
+#endif
+
+#ifndef CONFIG_DCACHE_SNOOP_SEPTAG
+#define CONFIG_DCACHE_SNOOP_SEPTAG 0
+#endif
+
+#ifndef CONFIG_CACHE_FIXED
+#define CONFIG_CACHE_FIXED 0
+#endif
+
+#ifndef CONFIG_DCACHE_LRAM
+#define CONFIG_DCACHE_LRAM 0
+#endif
+
+#ifndef CONFIG_DCACHE_LRSTART
+#define CONFIG_DCACHE_LRSTART 8F
+#endif
+
+#if defined CONFIG_DCACHE_LRAM_SZ2
+#define CFG_DLRAM_SIZE 2
+#elif defined CONFIG_DCACHE_LRAM_SZ4
+#define CFG_DLRAM_SIZE 4
+#elif defined CONFIG_DCACHE_LRAM_SZ8
+#define CFG_DLRAM_SIZE 8
+#elif defined CONFIG_DCACHE_LRAM_SZ16
+#define CFG_DLRAM_SIZE 16
+#elif defined CONFIG_DCACHE_LRAM_SZ32
+#define CFG_DLRAM_SIZE 32
+#elif defined CONFIG_DCACHE_LRAM_SZ64
+#define CFG_DLRAM_SIZE 64
+#elif defined CONFIG_DCACHE_LRAM_SZ128
+#define CFG_DLRAM_SIZE 128
+#elif defined CONFIG_DCACHE_LRAM_SZ256
+#define CFG_DLRAM_SIZE 256
+#else
+#define CFG_DLRAM_SIZE 1
+#endif
+
+#if defined CONFIG_MMU_PAGE_4K
+#define CONFIG_MMU_PAGE 0
+#elif defined CONFIG_MMU_PAGE_8K
+#define CONFIG_MMU_PAGE 1
+#elif defined CONFIG_MMU_PAGE_16K
+#define CONFIG_MMU_PAGE 2
+#elif defined CONFIG_MMU_PAGE_32K
+#define CONFIG_MMU_PAGE 3
+#elif defined CONFIG_MMU_PAGE_PROG
+#define CONFIG_MMU_PAGE 4
+#else
+#define CONFIG_MMU_PAGE 0
+#endif
+
+#ifdef CONFIG_MMU_ENABLE
+#define CONFIG_MMUEN 1
+
+#ifdef CONFIG_MMU_SPLIT
+#define CONFIG_TLB_TYPE 0
+#endif
+#ifdef CONFIG_MMU_COMBINED
+#define CONFIG_TLB_TYPE 1
+#endif
+
+#ifdef CONFIG_MMU_REPARRAY
+#define CONFIG_TLB_REP 0
+#endif
+#ifdef CONFIG_MMU_REPINCREMENT
+#define CONFIG_TLB_REP 1
+#endif
+
+#ifdef CONFIG_MMU_I2
+#define CONFIG_ITLBNUM 2
+#endif
+#ifdef CONFIG_MMU_I4
+#define CONFIG_ITLBNUM 4
+#endif
+#ifdef CONFIG_MMU_I8
+#define CONFIG_ITLBNUM 8
+#endif
+#ifdef CONFIG_MMU_I16
+#define CONFIG_ITLBNUM 16
+#endif
+#ifdef CONFIG_MMU_I32
+#define CONFIG_ITLBNUM 32
+#endif
+
+#define CONFIG_DTLBNUM 2
+#ifdef CONFIG_MMU_D2
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 2
+#endif
+#ifdef CONFIG_MMU_D4
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 4
+#endif
+#ifdef CONFIG_MMU_D8
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 8
+#endif
+#ifdef CONFIG_MMU_D16
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 16
+#endif
+#ifdef CONFIG_MMU_D32
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 32
+#endif
+#ifdef CONFIG_MMU_FASTWB
+#define CFG_MMU_FASTWB 1
+#else
+#define CFG_MMU_FASTWB 0
+#endif
+
+#else
+#define CONFIG_MMUEN 0
+#define CONFIG_ITLBNUM 2
+#define CONFIG_DTLBNUM 2
+#define CONFIG_TLB_TYPE 1
+#define CONFIG_TLB_REP 1
+#define CFG_MMU_FASTWB 0
+#endif
+
+#ifndef CONFIG_DSU_ENABLE
+#define CONFIG_DSU_ENABLE 0
+#endif
+
+#if defined CONFIG_DSU_ITRACESZ1
+#define CFG_DSU_ITB 1
+#elif CONFIG_DSU_ITRACESZ2
+#define CFG_DSU_ITB 2
+#elif CONFIG_DSU_ITRACESZ4
+#define CFG_DSU_ITB 4
+#elif CONFIG_DSU_ITRACESZ8
+#define CFG_DSU_ITB 8
+#elif CONFIG_DSU_ITRACESZ16
+#define CFG_DSU_ITB 16
+#else
+#define CFG_DSU_ITB 0
+#endif
+
+#if defined CONFIG_DSU_ATRACESZ1
+#define CFG_DSU_ATB 1
+#elif CONFIG_DSU_ATRACESZ2
+#define CFG_DSU_ATB 2
+#elif CONFIG_DSU_ATRACESZ4
+#define CFG_DSU_ATB 4
+#elif CONFIG_DSU_ATRACESZ8
+#define CFG_DSU_ATB 8
+#elif CONFIG_DSU_ATRACESZ16
+#define CFG_DSU_ATB 16
+#else
+#define CFG_DSU_ATB 0
+#endif
+
+#ifndef CONFIG_LEON3FT_EN
+#define CONFIG_LEON3FT_EN 0
+#endif
+
+#if defined CONFIG_IUFT_PAR
+#define CONFIG_IUFT_EN 1
+#elif defined CONFIG_IUFT_DMR
+#define CONFIG_IUFT_EN 2
+#elif defined CONFIG_IUFT_BCH
+#define CONFIG_IUFT_EN 3
+#elif defined CONFIG_IUFT_TMR
+#define CONFIG_IUFT_EN 4
+#else
+#define CONFIG_IUFT_EN 0
+#endif
+#ifndef CONFIG_RF_ERRINJ
+#define CONFIG_RF_ERRINJ 0
+#endif
+
+#ifndef CONFIG_FPUFT_EN
+#define CONFIG_FPUFT 0
+#else
+#ifdef CONFIG_FPU_GRFPU
+#define CONFIG_FPUFT 2
+#else
+#define CONFIG_FPUFT 1
+#endif
+#endif
+
+#ifndef CONFIG_CACHE_FT_EN
+#define CONFIG_CACHE_FT_EN 0
+#endif
+#ifndef CONFIG_CACHE_ERRINJ
+#define CONFIG_CACHE_ERRINJ 0
+#endif
+
+#ifndef CONFIG_LEON3_NETLIST
+#define CONFIG_LEON3_NETLIST 0
+#endif
+
+#ifdef CONFIG_DEBUG_PC32
+#define CFG_DEBUG_PC32 0
+#else
+#define CFG_DEBUG_PC32 2
+#endif
+#ifndef CONFIG_IU_DISAS
+#define CONFIG_IU_DISAS 0
+#endif
+#ifndef CONFIG_IU_DISAS_NET
+#define CONFIG_IU_DISAS_NET 0
+#endif
+
+
+#ifndef CONFIG_AHB_SPLIT
+#define CONFIG_AHB_SPLIT 0
+#endif
+
+#ifndef CONFIG_AHB_RROBIN
+#define CONFIG_AHB_RROBIN 0
+#endif
+
+#ifndef CONFIG_AHB_IOADDR
+#define CONFIG_AHB_IOADDR FFF
+#endif
+
+#ifndef CONFIG_APB_HADDR
+#define CONFIG_APB_HADDR 800
+#endif
+
+#ifndef CONFIG_AHB_MON
+#define CONFIG_AHB_MON 0
+#endif
+
+#ifndef CONFIG_AHB_MONERR
+#define CONFIG_AHB_MONERR 0
+#endif
+
+#ifndef CONFIG_AHB_MONWAR
+#define CONFIG_AHB_MONWAR 0
+#endif
+
+#ifndef CONFIG_DSU_UART
+#define CONFIG_DSU_UART 0
+#endif
+
+
+#ifndef CONFIG_DSU_JTAG
+#define CONFIG_DSU_JTAG 0
+#endif
+
+#ifndef CONFIG_DSU_ETH
+#define CONFIG_DSU_ETH 0
+#endif
+
+#ifndef CONFIG_DSU_IPMSB
+#define CONFIG_DSU_IPMSB C0A8
+#endif
+
+#ifndef CONFIG_DSU_IPLSB
+#define CONFIG_DSU_IPLSB 0033
+#endif
+
+#ifndef CONFIG_DSU_ETHMSB
+#define CONFIG_DSU_ETHMSB 020000
+#endif
+
+#ifndef CONFIG_DSU_ETHLSB
+#define CONFIG_DSU_ETHLSB 000009
+#endif
+
+#if defined CONFIG_DSU_ETHSZ1
+#define CFG_DSU_ETHB 1
+#elif CONFIG_DSU_ETHSZ2
+#define CFG_DSU_ETHB 2
+#elif CONFIG_DSU_ETHSZ4
+#define CFG_DSU_ETHB 4
+#elif CONFIG_DSU_ETHSZ8
+#define CFG_DSU_ETHB 8
+#elif CONFIG_DSU_ETHSZ16
+#define CFG_DSU_ETHB 16
+#elif CONFIG_DSU_ETHSZ32
+#define CFG_DSU_ETHB 32
+#else
+#define CFG_DSU_ETHB 1
+#endif
+
+#ifndef CONFIG_DSU_ETH_PROG
+#define CONFIG_DSU_ETH_PROG 0
+#endif
+
+#ifndef CONFIG_MCTRL_LEON2
+#define CONFIG_MCTRL_LEON2 0
+#endif
+
+#ifndef CONFIG_MCTRL_SDRAM
+#define CONFIG_MCTRL_SDRAM 0
+#endif
+
+#ifndef CONFIG_MCTRL_SDRAM_SEPBUS
+#define CONFIG_MCTRL_SDRAM_SEPBUS 0
+#endif
+
+#ifndef CONFIG_MCTRL_SDRAM_INVCLK
+#define CONFIG_MCTRL_SDRAM_INVCLK 0
+#endif
+
+#ifndef CONFIG_MCTRL_SDRAM_BUS64
+#define CONFIG_MCTRL_SDRAM_BUS64 0
+#endif
+
+#ifndef CONFIG_MCTRL_8BIT
+#define CONFIG_MCTRL_8BIT 0
+#endif
+
+#ifndef CONFIG_MCTRL_16BIT
+#define CONFIG_MCTRL_16BIT 0
+#endif
+
+#ifndef CONFIG_MCTRL_5CS
+#define CONFIG_MCTRL_5CS 0
+#endif
+
+#ifndef CONFIG_MCTRL_EDAC
+#define CONFIG_MCTRL_EDAC 0
+#endif
+
+#ifndef CONFIG_MCTRL_PAGE
+#define CONFIG_MCTRL_PAGE 0
+#endif
+
+#ifndef CONFIG_MCTRL_PROGPAGE
+#define CONFIG_MCTRL_PROGPAGE 0
+#endif
+
+#ifndef CONFIG_SSCTRL
+#define CONFIG_SSCTRL 0
+#endif
+
+#ifndef CONFIG_SSCTRL_PROM16
+#define CONFIG_SSCTRL_PROM16 0
+#endif
+
+#ifndef CONFIG_DDRSP
+#define CONFIG_DDRSP 0
+#endif
+
+#ifndef CONFIG_DDRSP_INIT
+#define CONFIG_DDRSP_INIT 0
+#endif
+
+#ifndef CONFIG_DDRSP_FREQ
+#define CONFIG_DDRSP_FREQ 100
+#endif
+
+#ifndef CONFIG_DDRSP_COL
+#define CONFIG_DDRSP_COL 9
+#endif
+
+#ifndef CONFIG_DDRSP_MBYTE
+#define CONFIG_DDRSP_MBYTE 8
+#endif
+
+#ifndef CONFIG_DDRSP_RSKEW
+#define CONFIG_DDRSP_RSKEW 0
+#endif
+
+#ifndef CONFIG_SPIMCTRL
+#define CONFIG_SPIMCTRL 0
+#endif
+
+#ifndef CONFIG_SPIMCTRL_SDCARD
+#define CONFIG_SPIMCTRL_SDCARD 0
+#endif
+
+#ifndef CONFIG_SPIMCTRL_READCMD
+#define CONFIG_SPIMCTRL_READCMD 0
+#endif
+
+#ifndef CONFIG_SPIMCTRL_DUMMYBYTE
+#define CONFIG_SPIMCTRL_DUMMYBYTE 0
+#endif
+
+#ifndef CONFIG_SPIMCTRL_DUALOUTPUT
+#define CONFIG_SPIMCTRL_DUALOUTPUT 0
+#endif
+
+#ifndef CONFIG_SPIMCTRL_SCALER
+#define CONFIG_SPIMCTRL_SCALER 1
+#endif
+
+#ifndef CONFIG_SPIMCTRL_ASCALER
+#define CONFIG_SPIMCTRL_ASCALER 1
+#endif
+
+#ifndef CONFIG_SPIMCTRL_PWRUPCNT
+#define CONFIG_SPIMCTRL_PWRUPCNT 0
+#endif
+#ifndef CONFIG_AHBROM_ENABLE
+#define CONFIG_AHBROM_ENABLE 0
+#endif
+
+#ifndef CONFIG_AHBROM_START
+#define CONFIG_AHBROM_START 000
+#endif
+
+#ifndef CONFIG_AHBROM_PIPE
+#define CONFIG_AHBROM_PIPE 0
+#endif
+
+#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
+#define CONFIG_ROM_START 100
+#else
+#define CONFIG_ROM_START 000
+#endif
+
+
+#ifndef CONFIG_AHBRAM_ENABLE
+#define CONFIG_AHBRAM_ENABLE 0
+#endif
+
+#ifndef CONFIG_AHBRAM_START
+#define CONFIG_AHBRAM_START A00
+#endif
+
+#if defined CONFIG_AHBRAM_SZ1
+#define CFG_AHBRAMSZ 1
+#elif CONFIG_AHBRAM_SZ2
+#define CFG_AHBRAMSZ 2
+#elif CONFIG_AHBRAM_SZ4
+#define CFG_AHBRAMSZ 4
+#elif CONFIG_AHBRAM_SZ8
+#define CFG_AHBRAMSZ 8
+#elif CONFIG_AHBRAM_SZ16
+#define CFG_AHBRAMSZ 16
+#elif CONFIG_AHBRAM_SZ32
+#define CFG_AHBRAMSZ 32
+#elif CONFIG_AHBRAM_SZ64
+#define CFG_AHBRAMSZ 64
+#else
+#define CFG_AHBRAMSZ 1
+#endif
+
+#ifndef CONFIG_GRETH_ENABLE
+#define CONFIG_GRETH_ENABLE 0
+#endif
+
+#ifndef CONFIG_GRETH_GIGA
+#define CONFIG_GRETH_GIGA 0
+#endif
+
+#if defined CONFIG_GRETH_FIFO4
+#define CFG_GRETH_FIFO 4
+#elif defined CONFIG_GRETH_FIFO8
+#define CFG_GRETH_FIFO 8
+#elif defined CONFIG_GRETH_FIFO16
+#define CFG_GRETH_FIFO 16
+#elif defined CONFIG_GRETH_FIFO32
+#define CFG_GRETH_FIFO 32
+#elif defined CONFIG_GRETH_FIFO64
+#define CFG_GRETH_FIFO 64
+#else
+#define CFG_GRETH_FIFO 8
+#endif
+
+#ifndef CONFIG_UART1_ENABLE
+#define CONFIG_UART1_ENABLE 0
+#endif
+
+#if defined CONFIG_UA1_FIFO1
+#define CFG_UA1_FIFO 1
+#elif defined CONFIG_UA1_FIFO2
+#define CFG_UA1_FIFO 2
+#elif defined CONFIG_UA1_FIFO4
+#define CFG_UA1_FIFO 4
+#elif defined CONFIG_UA1_FIFO8
+#define CFG_UA1_FIFO 8
+#elif defined CONFIG_UA1_FIFO16
+#define CFG_UA1_FIFO 16
+#elif defined CONFIG_UA1_FIFO32
+#define CFG_UA1_FIFO 32
+#else
+#define CFG_UA1_FIFO 1
+#endif
+
+#ifndef CONFIG_IRQ3_ENABLE
+#define CONFIG_IRQ3_ENABLE 0
+#endif
+#ifndef CONFIG_IRQ3_NSEC
+#define CONFIG_IRQ3_NSEC 0
+#endif
+#ifndef CONFIG_GPT_ENABLE
+#define CONFIG_GPT_ENABLE 0
+#endif
+
+#ifndef CONFIG_GPT_NTIM
+#define CONFIG_GPT_NTIM 1
+#endif
+
+#ifndef CONFIG_GPT_SW
+#define CONFIG_GPT_SW 8
+#endif
+
+#ifndef CONFIG_GPT_TW
+#define CONFIG_GPT_TW 8
+#endif
+
+#ifndef CONFIG_GPT_IRQ
+#define CONFIG_GPT_IRQ 8
+#endif
+
+#ifndef CONFIG_GPT_SEPIRQ
+#define CONFIG_GPT_SEPIRQ 0
+#endif
+#ifndef CONFIG_GPT_ENABLE
+#define CONFIG_GPT_ENABLE 0
+#endif
+
+#ifndef CONFIG_GPT_NTIM
+#define CONFIG_GPT_NTIM 1
+#endif
+
+#ifndef CONFIG_GPT_SW
+#define CONFIG_GPT_SW 8
+#endif
+
+#ifndef CONFIG_GPT_TW
+#define CONFIG_GPT_TW 8
+#endif
+
+#ifndef CONFIG_GPT_IRQ
+#define CONFIG_GPT_IRQ 8
+#endif
+
+#ifndef CONFIG_GPT_SEPIRQ
+#define CONFIG_GPT_SEPIRQ 0
+#endif
+
+#ifndef CONFIG_GPT_WDOGEN
+#define CONFIG_GPT_WDOGEN 0
+#endif
+
+#ifndef CONFIG_GPT_WDOG
+#define CONFIG_GPT_WDOG 0
+#endif
+
+#ifndef CONFIG_GRGPIO_ENABLE
+#define CONFIG_GRGPIO_ENABLE 0
+#endif
+#ifndef CONFIG_GRGPIO_IMASK
+#define CONFIG_GRGPIO_IMASK 0000
+#endif
+#ifndef CONFIG_GRGPIO_WIDTH
+#define CONFIG_GRGPIO_WIDTH 1
+#endif
+
+#ifndef CONFIG_I2C_ENABLE
+#define CONFIG_I2C_ENABLE 0
+#endif
+#ifndef CONFIG_PS2_ENABLE
+#define CONFIG_PS2_ENABLE 0
+#endif
+
+#ifndef CONFIG_SPICTRL_ENABLE
+#define CONFIG_SPICTRL_ENABLE 0
+#endif
+#ifndef CONFIG_SPICTRL_SLVS
+#define CONFIG_SPICTRL_SLVS 1
+#endif
+#ifndef CONFIG_SPICTRL_FIFO
+#define CONFIG_SPICTRL_FIFO 1
+#endif
+#ifndef CONFIG_SPICTRL_SLVREG
+#define CONFIG_SPICTRL_SLVREG 0
+#endif
+#ifndef CONFIG_SPICTRL_ODMODE
+#define CONFIG_SPICTRL_ODMODE 0
+#endif
+#ifndef CONFIG_SPICTRL_AM
+#define CONFIG_SPICTRL_AM 0
+#endif
+#ifndef CONFIG_SPICTRL_ASEL
+#define CONFIG_SPICTRL_ASEL 0
+#endif
+#ifndef CONFIG_LCD_ENABLE
+#define CONFIG_LCD_ENABLE 0
+#endif
+#ifndef CONFIG_LCD3T_ENABLE
+#define CONFIG_LCD3T_ENABLE 0
+#endif
+
+#ifndef CONFIG_SVGA_ENABLE
+#define CONFIG_SVGA_ENABLE 0
+#endif
+
+
+#ifndef CONFIG_DEBUG_UART
+#define CONFIG_DEBUG_UART 0
+#endif
--- /dev/null
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Testbench top-level}
+add wave -noupdate -format Logic /testbench/clk
+add wave -noupdate -format Logic /testbench/clkout
+add wave -noupdate -format Logic /testbench/pllref
+add wave -noupdate -format Logic /testbench/rst
+add wave -noupdate -format Literal /testbench/address
+add wave -noupdate -format Literal /testbench/data
+add wave -noupdate -format Logic /testbench/romsn
+add wave -noupdate -format Logic /testbench/iosn
+add wave -noupdate -format Logic /testbench/oen
+add wave -noupdate -format Logic /testbench/writen
+add wave -noupdate -format Logic /testbench/dsuen
+add wave -noupdate -format Logic /testbench/dsutx
+add wave -noupdate -format Logic /testbench/dsurx
+add wave -noupdate -format Logic /testbench/dsubren
+add wave -noupdate -format Logic /testbench/dsuact
+add wave -noupdate -format Logic /testbench/dsurst
+add wave -noupdate -format Logic /testbench/test
+add wave -noupdate -format Logic /testbench/error
+add wave -noupdate -format Literal /testbench/gpio
+add wave -noupdate -format Logic /testbench/gnd
+add wave -noupdate -format Logic /testbench/vcc
+add wave -noupdate -format Logic /testbench/nc
+add wave -noupdate -format Logic /testbench/clk2
+add wave -noupdate -format Logic /testbench/ssram_cen
+add wave -noupdate -format Logic /testbench/ssram_wen
+add wave -noupdate -format Literal /testbench/ssram_bw
+add wave -noupdate -format Logic /testbench/ssram_oen
+add wave -noupdate -format Logic /testbench/ssram_clk
+add wave -noupdate -format Logic /testbench/ssram_adscn
+add wave -noupdate -format Logic /testbench/ssram_adsp_n
+add wave -noupdate -format Logic /testbench/ssram_adv_n
+add wave -noupdate -format Literal /testbench/datazz
+add wave -noupdate -format Logic /testbench/ddr_clk
+add wave -noupdate -format Logic /testbench/ddr_clkb
+add wave -noupdate -format Logic /testbench/ddr_clkin
+add wave -noupdate -format Logic /testbench/ddr_cke
+add wave -noupdate -format Logic /testbench/ddr_csb
+add wave -noupdate -format Logic /testbench/ddr_web
+add wave -noupdate -format Logic /testbench/ddr_rasb
+add wave -noupdate -format Logic /testbench/ddr_casb
+add wave -noupdate -format Literal /testbench/ddr_dm
+add wave -noupdate -format Literal /testbench/ddr_dqs
+add wave -noupdate -format Literal /testbench/ddr_ad
+add wave -noupdate -format Literal /testbench/ddr_ba
+add wave -noupdate -format Literal /testbench/ddr_dq
+add wave -noupdate -format Logic /testbench/hc_vd
+add wave -noupdate -format Logic /testbench/hc_hd
+add wave -noupdate -format Logic /testbench/hc_den
+add wave -noupdate -format Logic /testbench/hc_nclk
+add wave -noupdate -format Literal /testbench/hc_lcd_data
+add wave -noupdate -format Logic /testbench/hc_grest
+add wave -noupdate -format Logic /testbench/hc_scen
+add wave -noupdate -format Logic /testbench/hc_sda
+add wave -noupdate -format Logic /testbench/hc_adc_penirq_n
+add wave -noupdate -format Logic /testbench/hc_adc_dout
+add wave -noupdate -format Logic /testbench/hc_adc_busy
+add wave -noupdate -format Logic /testbench/hc_adc_din
+add wave -noupdate -format Logic /testbench/hc_adc_dclk
+add wave -noupdate -format Logic /testbench/hc_adc_cs_n
+add wave -noupdate -format Logic /testbench/hc_i2c_sclk
+add wave -noupdate -format Logic /testbench/hc_i2c_sdat
+add wave -noupdate -format Literal /testbench/hc_td_d
+add wave -noupdate -format Logic /testbench/hc_td_hs
+add wave -noupdate -format Logic /testbench/hc_td_vs
+add wave -noupdate -format Logic /testbench/hc_td_27mhz
+add wave -noupdate -format Logic /testbench/hc_td_reset
+add wave -noupdate -format Logic /testbench/hc_aud_adclrck
+add wave -noupdate -format Logic /testbench/hc_aud_adcdat
+add wave -noupdate -format Logic /testbench/hc_aud_daclrck
+add wave -noupdate -format Logic /testbench/hc_aud_dacdat
+add wave -noupdate -format Logic /testbench/hc_aud_bclk
+add wave -noupdate -format Logic /testbench/hc_aud_xck
+add wave -noupdate -format Logic /testbench/hc_sd_dat
+add wave -noupdate -format Logic /testbench/hc_sd_dat3
+add wave -noupdate -format Logic /testbench/hc_sd_cmd
+add wave -noupdate -format Logic /testbench/hc_sd_clk
+add wave -noupdate -format Literal /testbench/hc_tx_d
+add wave -noupdate -format Literal /testbench/hc_rx_d
+add wave -noupdate -format Logic /testbench/hc_tx_clk
+add wave -noupdate -format Logic /testbench/hc_rx_clk
+add wave -noupdate -format Logic /testbench/hc_tx_en
+add wave -noupdate -format Logic /testbench/hc_rx_dv
+add wave -noupdate -format Logic /testbench/hc_rx_crs
+add wave -noupdate -format Logic /testbench/hc_rx_err
+add wave -noupdate -format Logic /testbench/hc_rx_col
+add wave -noupdate -format Logic /testbench/hc_mdio
+add wave -noupdate -format Logic /testbench/hc_mdc
+add wave -noupdate -format Logic /testbench/hc_eth_reset_n
+add wave -noupdate -format Logic /testbench/hc_uart_rxd
+add wave -noupdate -format Logic /testbench/hc_uart_txd
+add wave -noupdate -format Logic /testbench/hc_ps2_dat
+add wave -noupdate -format Logic /testbench/hc_ps2_clk
+add wave -noupdate -format Literal /testbench/hc_vga_data
+add wave -noupdate -format Logic /testbench/hc_vga_clock
+add wave -noupdate -format Logic /testbench/hc_vga_hs
+add wave -noupdate -format Logic /testbench/hc_vga_vs
+add wave -noupdate -format Logic /testbench/hc_vga_blank
+add wave -noupdate -format Logic /testbench/hc_vga_sync
+add wave -noupdate -format Logic /testbench/hc_id_i2cscl
+add wave -noupdate -format Logic /testbench/hc_id_i2cdat
+add wave -noupdate -format Logic /testbench/phy_tx_er
+add wave -noupdate -format Logic /testbench/phy_gtx_clk
+add wave -noupdate -format Literal /testbench/hc_tx_dt
+add wave -noupdate -format Literal /testbench/hc_rx_dt
+add wave -noupdate -divider {CPU 1}
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ici
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ico
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dci
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dco
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/rfi
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/rfo
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/irqi
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/irqo
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dbgi
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dbgo
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/r
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/wpr
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dsur
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ir
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/cmem0/crami
+add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/cmem0/cramo
+add wave -noupdate -divider {New Divider}
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {119390198 ps} 0}
+configure wave -namecolwidth 314
+configure wave -valuecolwidth 136
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {120003641 ps} {122684879 ps}
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Synthesis
+#
+# CONFIG_SYN_INFERRED is not set
+# CONFIG_SYN_STRATIX is not set
+# CONFIG_SYN_STRATIXII is not set
+# CONFIG_SYN_STRATIXIII is not set
+# CONFIG_SYN_CYCLONEIII is not set
+# CONFIG_SYN_ALTERA is not set
+# CONFIG_SYN_AXCEL is not set
+# CONFIG_SYN_AXDSP is not set
+# CONFIG_SYN_PROASIC is not set
+# CONFIG_SYN_PROASICPLUS is not set
+# CONFIG_SYN_PROASIC3 is not set
+# CONFIG_SYN_IGLOO is not set
+# CONFIG_SYN_UT025CRH is not set
+# CONFIG_SYN_ATC18 is not set
+# CONFIG_SYN_ATC18RHA is not set
+# CONFIG_SYN_CUSTOM1 is not set
+# CONFIG_SYN_EASIC90 is not set
+# CONFIG_SYN_IHP25 is not set
+# CONFIG_SYN_IHP25RH is not set
+# CONFIG_SYN_LATTICE is not set
+# CONFIG_SYN_ECLIPSE is not set
+# CONFIG_SYN_PEREGRINE is not set
+# CONFIG_SYN_RH_LIB18T is not set
+# CONFIG_SYN_RHUMC is not set
+# CONFIG_SYN_SMIC13 is not set
+# CONFIG_SYN_SPARTAN2 is not set
+CONFIG_SYN_SPARTAN3=y
+# CONFIG_SYN_SPARTAN3E is not set
+# CONFIG_SYN_SPARTAN6 is not set
+# CONFIG_SYN_VIRTEX is not set
+# CONFIG_SYN_VIRTEXE is not set
+# CONFIG_SYN_VIRTEX2 is not set
+# CONFIG_SYN_VIRTEX4 is not set
+# CONFIG_SYN_VIRTEX5 is not set
+# CONFIG_SYN_VIRTEX6 is not set
+# CONFIG_SYN_UMC is not set
+# CONFIG_SYN_TSMC90 is not set
+# CONFIG_SYN_INFER_RAM is not set
+# CONFIG_SYN_INFER_PADS is not set
+# CONFIG_SYN_NO_ASYNC is not set
+# CONFIG_SYN_SCAN is not set
+CONFIG_FPGA_1500=y
+# CONFIG_FPGA_2000 is not set
+
+#
+# Clock generation
+#
+# CONFIG_CLK_INFERRED is not set
+# CONFIG_CLK_HCLKBUF is not set
+# CONFIG_CLK_ALTDLL is not set
+# CONFIG_CLK_LATDLL is not set
+# CONFIG_CLK_PRO3PLL is not set
+# CONFIG_CLK_LIB18T is not set
+# CONFIG_CLK_RHUMC is not set
+# CONFIG_CLK_CLKDLL is not set
+CONFIG_CLK_DCM=y
+CONFIG_CLK_MUL=4
+CONFIG_CLK_DIV=5
+# CONFIG_PCI_CLKDLL is not set
+# CONFIG_CLK_NOFB is not set
+# CONFIG_PCI_SYSCLK is not set
+CONFIG_LEON3=y
+CONFIG_PROC_NUM=1
+
+#
+# Processor
+#
+
+#
+# Integer unit
+#
+CONFIG_IU_NWINDOWS=8
+CONFIG_IU_V8MULDIV=y
+CONFIG_IU_MUL_LATENCY_2=y
+# CONFIG_IU_MUL_LATENCY_4 is not set
+# CONFIG_IU_MUL_LATENCY_5 is not set
+# CONFIG_IU_BP is not set
+# CONFIG_IU_SVT is not set
+CONFIG_IU_LDELAY=1
+CONFIG_IU_WATCHPOINTS=4
+# CONFIG_PWD is not set
+CONFIG_IU_RSTADDR=00000
+
+#
+# Floating-point unit
+#
+# CONFIG_FPU_ENABLE is not set
+
+#
+# Cache system
+#
+CONFIG_ICACHE_ENABLE=y
+# CONFIG_ICACHE_ASSO1 is not set
+CONFIG_ICACHE_ASSO2=y
+# CONFIG_ICACHE_ASSO3 is not set
+# CONFIG_ICACHE_ASSO4 is not set
+# CONFIG_ICACHE_SZ1 is not set
+# CONFIG_ICACHE_SZ2 is not set
+CONFIG_ICACHE_SZ4=y
+# CONFIG_ICACHE_SZ8 is not set
+# CONFIG_ICACHE_SZ16 is not set
+# CONFIG_ICACHE_SZ32 is not set
+# CONFIG_ICACHE_SZ64 is not set
+# CONFIG_ICACHE_SZ128 is not set
+# CONFIG_ICACHE_SZ256 is not set
+# CONFIG_ICACHE_LZ16 is not set
+CONFIG_ICACHE_LZ32=y
+# CONFIG_ICACHE_ALGORND is not set
+# CONFIG_ICACHE_ALGOLRR is not set
+CONFIG_ICACHE_ALGOLRU=y
+# CONFIG_ICACHE_LOCK is not set
+CONFIG_DCACHE_ENABLE=y
+CONFIG_DCACHE_ASSO1=y
+# CONFIG_DCACHE_ASSO2 is not set
+# CONFIG_DCACHE_ASSO3 is not set
+# CONFIG_DCACHE_ASSO4 is not set
+# CONFIG_DCACHE_SZ1 is not set
+# CONFIG_DCACHE_SZ2 is not set
+CONFIG_DCACHE_SZ4=y
+# CONFIG_DCACHE_SZ8 is not set
+# CONFIG_DCACHE_SZ16 is not set
+# CONFIG_DCACHE_SZ32 is not set
+# CONFIG_DCACHE_SZ64 is not set
+# CONFIG_DCACHE_SZ128 is not set
+# CONFIG_DCACHE_SZ256 is not set
+CONFIG_DCACHE_LZ16=y
+# CONFIG_DCACHE_LZ32 is not set
+CONFIG_DCACHE_SNOOP=y
+# CONFIG_DCACHE_SNOOP_FAST is not set
+# CONFIG_DCACHE_SNOOP_SEPTAG is not set
+CONFIG_CACHE_FIXED=0
+
+#
+# MMU
+#
+CONFIG_MMU_ENABLE=y
+# CONFIG_MMU_COMBINED is not set
+CONFIG_MMU_SPLIT=y
+CONFIG_MMU_REPARRAY=y
+# CONFIG_MMU_REPINCREMENT is not set
+# CONFIG_MMU_I2 is not set
+# CONFIG_MMU_I4 is not set
+CONFIG_MMU_I8=y
+# CONFIG_MMU_I16 is not set
+# CONFIG_MMU_I32 is not set
+# CONFIG_MMU_D2 is not set
+# CONFIG_MMU_D4 is not set
+CONFIG_MMU_D8=y
+# CONFIG_MMU_D16 is not set
+# CONFIG_MMU_D32 is not set
+CONFIG_MMU_FASTWB=y
+# CONFIG_MMU_PAGE_4K is not set
+# CONFIG_MMU_PAGE_8K is not set
+# CONFIG_MMU_PAGE_16K is not set
+# CONFIG_MMU_PAGE_32K is not set
+CONFIG_MMU_PAGE_PROG=y
+
+#
+# Debug Support Unit
+#
+CONFIG_DSU_ENABLE=y
+CONFIG_DSU_ITRACE=y
+# CONFIG_DSU_ITRACESZ1 is not set
+CONFIG_DSU_ITRACESZ2=y
+# CONFIG_DSU_ITRACESZ4 is not set
+# CONFIG_DSU_ITRACESZ8 is not set
+# CONFIG_DSU_ITRACESZ16 is not set
+CONFIG_DSU_ATRACE=y
+# CONFIG_DSU_ATRACESZ1 is not set
+CONFIG_DSU_ATRACESZ2=y
+# CONFIG_DSU_ATRACESZ4 is not set
+# CONFIG_DSU_ATRACESZ8 is not set
+# CONFIG_DSU_ATRACESZ16 is not set
+
+#
+# Fault-tolerance
+#
+
+#
+# VHDL debug settings
+#
+# CONFIG_IU_DISAS is not set
+# CONFIG_DEBUG_PC32 is not set
+
+#
+# AMBA configuration
+#
+CONFIG_AHB_DEFMST=0
+CONFIG_AHB_RROBIN=y
+# CONFIG_AHB_SPLIT is not set
+CONFIG_AHB_IOADDR=FFF
+CONFIG_APB_HADDR=800
+# CONFIG_AHB_MON is not set
+
+#
+# Debug Link
+#
+CONFIG_DSU_UART=y
+CONFIG_DSU_JTAG=y
+# CONFIG_GRUSB_DCL is not set
+CONFIG_DSU_ETH=y
+# CONFIG_DSU_ETHSZ1 is not set
+CONFIG_DSU_ETHSZ2=y
+# CONFIG_DSU_ETHSZ4 is not set
+# CONFIG_DSU_ETHSZ8 is not set
+# CONFIG_DSU_ETHSZ16 is not set
+CONFIG_DSU_IPMSB=C0A8
+CONFIG_DSU_IPLSB=180A
+CONFIG_DSU_ETHMSB=020000
+CONFIG_DSU_ETHLSB=000008
+# CONFIG_DSU_ETH_PROG is not set
+
+#
+# Peripherals
+#
+
+#
+# Memory controller
+#
+
+#
+# Leon2 memory controller
+#
+CONFIG_MCTRL_LEON2=y
+CONFIG_MCTRL_8BIT=y
+# CONFIG_MCTRL_16BIT is not set
+# CONFIG_MCTRL_5CS is not set
+CONFIG_MCTRL_SDRAM=y
+# CONFIG_MCTRL_SDRAM_SEPBUS is not set
+CONFIG_MCTRL_PAGE=y
+# CONFIG_MCTRL_PROGPAGE is not set
+# CONFIG_AHBSTAT_ENABLE is not set
+
+#
+# On-chip RAM/ROM
+#
+# CONFIG_AHBROM_ENABLE is not set
+# CONFIG_AHBRAM_ENABLE is not set
+
+#
+# Ethernet
+#
+CONFIG_GRETH_ENABLE=y
+# CONFIG_GRETH_GIGA is not set
+# CONFIG_GRETH_FIFO4 is not set
+# CONFIG_GRETH_FIFO8 is not set
+CONFIG_GRETH_FIFO16=y
+# CONFIG_GRETH_FIFO32 is not set
+# CONFIG_GRETH_FIFO64 is not set
+
+#
+# IDE Disk controller
+#
+# CONFIG_ATA_ENABLE is not set
+
+#
+# CAN
+#
+# CONFIG_CAN_ENABLE is not set
+
+#
+# USB 2.0 Device Controller
+#
+# CONFIG_GRUSBDC_ENABLE is not set
+
+#
+# UART, timer, I/O port and interrupt controller
+#
+CONFIG_UART1_ENABLE=y
+# CONFIG_UA1_FIFO1 is not set
+# CONFIG_UA1_FIFO2 is not set
+CONFIG_UA1_FIFO4=y
+# CONFIG_UA1_FIFO8 is not set
+# CONFIG_UA1_FIFO16 is not set
+# CONFIG_UA1_FIFO32 is not set
+CONFIG_IRQ3_ENABLE=y
+# CONFIG_IRQ3_SEC is not set
+CONFIG_GPT_ENABLE=y
+CONFIG_GPT_NTIM=2
+CONFIG_GPT_SW=8
+CONFIG_GPT_TW=32
+CONFIG_GPT_IRQ=8
+CONFIG_GPT_SEPIRQ=y
+# CONFIG_GPT_WDOGEN is not set
+CONFIG_GRGPIO_ENABLE=y
+CONFIG_GRGPIO_WIDTH=8
+CONFIG_GRGPIO_IMASK=0000
+
+#
+# Spacewire
+#
+# CONFIG_SPW_ENABLE is not set
+
+#
+# Keybord and VGA interface
+#
+CONFIG_KBD_ENABLE=y
+# CONFIG_VGA_ENABLE is not set
+CONFIG_SVGA_ENABLE=y
+
+#
+# VHDL Debugging
+#
+# CONFIG_DEBUG_UART is not set
--- /dev/null
+include .config
+
+GRLIB=../..
+TOP=leon3mp
+BOARD=gr-xc3s-1500
+include $(GRLIB)/boards/$(BOARD)/Makefile.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+#UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
+UCF=leon3mp.ucf
+QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
+EFFORT=high
+ISEMAPOPT=-timing
+XSTOPT=
+SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
+VHDLSYNFILES=config.vhd ahbrom.vhd vga_clkgen.vhd leon3mp.vhd
+VHDLSIMFILES=testbench.vhd
+SIMTOP=testbench
+#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
+SDCFILE=default.sdc
+BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
+CLEAN=soft-clean
+VCOMOPT=-explicit
+TECHLIBS = unisim
+
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+ tmtc openchip hynix cypress ihp gleichmann gsi fmf spansion
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest ddr \
+ haps ascs slink coremp7
+FILESKIP = grcan.vhd
+
+include $(GRLIB)/bin/Makefile
+include $(GRLIB)/software/leon3/Makefile
+
+
+################## project specific targets ##########################
+
--- /dev/null
+
+----------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2009 Aeroflex Gaisler
+----------------------------------------------------------------------------
+-- Entity: ahbrom
+-- File: ahbrom.vhd
+-- Author: Jiri Gaisler - Gaisler Research
+-- Description: AHB rom. 0/1-waitstate read
+----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+entity ahbrom is
+ generic (
+ hindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ pipe : integer := 0;
+ tech : integer := 0;
+ kbytes : integer := 1);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type
+ );
+end;
+
+architecture rtl of ahbrom is
+constant abits : integer := 10;
+constant bytes : integer := 560;
+
+constant hconfig : ahb_config_type := (
+ 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
+ 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
+
+signal romdata : std_logic_vector(31 downto 0);
+signal addr : std_logic_vector(abits-1 downto 2);
+signal hsel, hready : std_ulogic;
+
+begin
+
+ ahbso.hresp <= "00";
+ ahbso.hsplit <= (others => '0');
+ ahbso.hirq <= (others => '0');
+ ahbso.hcache <= '1';
+ ahbso.hconfig <= hconfig;
+ ahbso.hindex <= hindex;
+
+ reg : process (clk)
+ begin
+ if rising_edge(clk) then
+ addr <= ahbsi.haddr(abits-1 downto 2);
+ end if;
+ end process;
+
+ p0 : if pipe = 0 generate
+ ahbso.hrdata <= romdata;
+ ahbso.hready <= '1';
+ end generate;
+
+ p1 : if pipe = 1 generate
+ reg2 : process (clk)
+ begin
+ if rising_edge(clk) then
+ hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
+ hready <= ahbsi.hready;
+ ahbso.hready <= (not rst) or (hsel and hready) or
+ (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
+ ahbso.hrdata <= romdata;
+ end if;
+ end process;
+ end generate;
+
+ comb : process (addr)
+ begin
+ case conv_integer(addr) is
+ when 16#00000# => romdata <= X"81D82000";
+ when 16#00001# => romdata <= X"03000004";
+ when 16#00002# => romdata <= X"821060E0";
+ when 16#00003# => romdata <= X"81884000";
+ when 16#00004# => romdata <= X"81900000";
+ when 16#00005# => romdata <= X"81980000";
+ when 16#00006# => romdata <= X"81800000";
+ when 16#00007# => romdata <= X"A1800000";
+ when 16#00008# => romdata <= X"01000000";
+ when 16#00009# => romdata <= X"03002040";
+ when 16#0000A# => romdata <= X"8210600F";
+ when 16#0000B# => romdata <= X"C2A00040";
+ when 16#0000C# => romdata <= X"84100000";
+ when 16#0000D# => romdata <= X"01000000";
+ when 16#0000E# => romdata <= X"01000000";
+ when 16#0000F# => romdata <= X"01000000";
+ when 16#00010# => romdata <= X"01000000";
+ when 16#00011# => romdata <= X"01000000";
+ when 16#00012# => romdata <= X"80108002";
+ when 16#00013# => romdata <= X"01000000";
+ when 16#00014# => romdata <= X"01000000";
+ when 16#00015# => romdata <= X"01000000";
+ when 16#00016# => romdata <= X"01000000";
+ when 16#00017# => romdata <= X"01000000";
+ when 16#00018# => romdata <= X"87444000";
+ when 16#00019# => romdata <= X"8608E01F";
+ when 16#0001A# => romdata <= X"88100000";
+ when 16#0001B# => romdata <= X"8A100000";
+ when 16#0001C# => romdata <= X"8C100000";
+ when 16#0001D# => romdata <= X"8E100000";
+ when 16#0001E# => romdata <= X"A0100000";
+ when 16#0001F# => romdata <= X"A2100000";
+ when 16#00020# => romdata <= X"A4100000";
+ when 16#00021# => romdata <= X"A6100000";
+ when 16#00022# => romdata <= X"A8100000";
+ when 16#00023# => romdata <= X"AA100000";
+ when 16#00024# => romdata <= X"AC100000";
+ when 16#00025# => romdata <= X"AE100000";
+ when 16#00026# => romdata <= X"90100000";
+ when 16#00027# => romdata <= X"92100000";
+ when 16#00028# => romdata <= X"94100000";
+ when 16#00029# => romdata <= X"96100000";
+ when 16#0002A# => romdata <= X"98100000";
+ when 16#0002B# => romdata <= X"9A100000";
+ when 16#0002C# => romdata <= X"9C100000";
+ when 16#0002D# => romdata <= X"9E100000";
+ when 16#0002E# => romdata <= X"86A0E001";
+ when 16#0002F# => romdata <= X"16BFFFEF";
+ when 16#00030# => romdata <= X"81E00000";
+ when 16#00031# => romdata <= X"82102002";
+ when 16#00032# => romdata <= X"81904000";
+ when 16#00033# => romdata <= X"03000004";
+ when 16#00034# => romdata <= X"821060E0";
+ when 16#00035# => romdata <= X"81884000";
+ when 16#00036# => romdata <= X"01000000";
+ when 16#00037# => romdata <= X"01000000";
+ when 16#00038# => romdata <= X"01000000";
+ when 16#00039# => romdata <= X"83480000";
+ when 16#0003A# => romdata <= X"8330600C";
+ when 16#0003B# => romdata <= X"80886001";
+ when 16#0003C# => romdata <= X"02800024";
+ when 16#0003D# => romdata <= X"01000000";
+ when 16#0003E# => romdata <= X"07000000";
+ when 16#0003F# => romdata <= X"8610E178";
+ when 16#00040# => romdata <= X"C108C000";
+ when 16#00041# => romdata <= X"C118C000";
+ when 16#00042# => romdata <= X"C518C000";
+ when 16#00043# => romdata <= X"C918C000";
+ when 16#00044# => romdata <= X"CD18C000";
+ when 16#00045# => romdata <= X"D118C000";
+ when 16#00046# => romdata <= X"D518C000";
+ when 16#00047# => romdata <= X"D918C000";
+ when 16#00048# => romdata <= X"DD18C000";
+ when 16#00049# => romdata <= X"E118C000";
+ when 16#0004A# => romdata <= X"E518C000";
+ when 16#0004B# => romdata <= X"E918C000";
+ when 16#0004C# => romdata <= X"ED18C000";
+ when 16#0004D# => romdata <= X"F118C000";
+ when 16#0004E# => romdata <= X"F518C000";
+ when 16#0004F# => romdata <= X"F918C000";
+ when 16#00050# => romdata <= X"FD18C000";
+ when 16#00051# => romdata <= X"01000000";
+ when 16#00052# => romdata <= X"01000000";
+ when 16#00053# => romdata <= X"01000000";
+ when 16#00054# => romdata <= X"01000000";
+ when 16#00055# => romdata <= X"01000000";
+ when 16#00056# => romdata <= X"89A00842";
+ when 16#00057# => romdata <= X"01000000";
+ when 16#00058# => romdata <= X"01000000";
+ when 16#00059# => romdata <= X"01000000";
+ when 16#0005A# => romdata <= X"01000000";
+ when 16#0005B# => romdata <= X"10800005";
+ when 16#0005C# => romdata <= X"01000000";
+ when 16#0005D# => romdata <= X"01000000";
+ when 16#0005E# => romdata <= X"00000000";
+ when 16#0005F# => romdata <= X"00000000";
+ when 16#00060# => romdata <= X"87444000";
+ when 16#00061# => romdata <= X"8730E01C";
+ when 16#00062# => romdata <= X"8688E00F";
+ when 16#00063# => romdata <= X"12800015";
+ when 16#00064# => romdata <= X"03200000";
+ when 16#00065# => romdata <= X"05040E00";
+ when 16#00066# => romdata <= X"8410A033";
+ when 16#00067# => romdata <= X"C4204000";
+ when 16#00068# => romdata <= X"0539AE1B";
+ when 16#00069# => romdata <= X"8410A260";
+ when 16#0006A# => romdata <= X"C4206004";
+ when 16#0006B# => romdata <= X"050003FC";
+ when 16#0006C# => romdata <= X"C4206008";
+ when 16#0006D# => romdata <= X"82103860";
+ when 16#0006E# => romdata <= X"C4004000";
+ when 16#0006F# => romdata <= X"8530A00C";
+ when 16#00070# => romdata <= X"03000004";
+ when 16#00071# => romdata <= X"82106009";
+ when 16#00072# => romdata <= X"80A04002";
+ when 16#00073# => romdata <= X"12800005";
+ when 16#00074# => romdata <= X"03200000";
+ when 16#00075# => romdata <= X"0539A81B";
+ when 16#00076# => romdata <= X"8410A260";
+ when 16#00077# => romdata <= X"C4204000";
+ when 16#00078# => romdata <= X"05000080";
+ when 16#00079# => romdata <= X"82100000";
+ when 16#0007A# => romdata <= X"80A0E000";
+ when 16#0007B# => romdata <= X"02800005";
+ when 16#0007C# => romdata <= X"01000000";
+ when 16#0007D# => romdata <= X"82004002";
+ when 16#0007E# => romdata <= X"10BFFFFC";
+ when 16#0007F# => romdata <= X"8620E001";
+ when 16#00080# => romdata <= X"3D1003FF";
+ when 16#00081# => romdata <= X"BC17A3E0";
+ when 16#00082# => romdata <= X"BC278001";
+ when 16#00083# => romdata <= X"9C27A060";
+ when 16#00084# => romdata <= X"03100000";
+ when 16#00085# => romdata <= X"81C04000";
+ when 16#00086# => romdata <= X"01000000";
+ when 16#00087# => romdata <= X"01000000";
+ when 16#00088# => romdata <= X"00000000";
+ when 16#00089# => romdata <= X"00000000";
+ when 16#0008A# => romdata <= X"00000000";
+ when 16#0008B# => romdata <= X"00000000";
+ when 16#0008C# => romdata <= X"00000000";
+ when others => romdata <= (others => '-');
+ end case;
+ end process;
+ -- pragma translate_off
+ bootmsg : report_version
+ generic map ("ahbrom" & tost(hindex) &
+ ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
+ -- pragma translate_on
+ end;
--- /dev/null
+
+
+Prompt for target technology
+CONFIG_SYN_INFERRED
+ Selects the target technology for memory and pads.
+ The following are available:
+
+ - Inferred: Generic FPGA or ASIC targets if your synthesis tool
+ is capable of inferring RAMs and pads automatically.
+
+ - Actel ProAsic/P/3, IGLOO and Axcelerator FPGAs
+ - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS
+ - Altera: Most Altera FPGA families
+ - Altera-Stratix: Altera Stratix FPGA family
+ - Altera-StratixII: Altera Stratix-II FPGA family
+ - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
+ - IHP25: IHP 0.25 um CMOS
+ - IHP25RH: IHP Rad-Hard 0.25 um CMOS
+ - Lattice : EC/ECP/XP FPGAs
+ - Quicklogic : Eclipse/E/II FPGAs
+ - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
+ - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries
+ - Xilinx-Spartan3E: Xilinx Spartan3E libraries
+ - Xilinx-Virtex/E: Xilinx Virtex/E libraries
+ - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries
+
+
+Ram library
+CONFIG_MEM_VIRAGE
+ Select RAM generators for ASIC targets.
+
+Infer ram
+CONFIG_SYN_INFER_RAM
+ Say Y here if you want the synthesis tool to infer your
+ RAM automatically. Say N to directly instantiate technology-
+ specific RAM cells for the selected target technology package.
+
+Infer pads
+CONFIG_SYN_INFER_PADS
+ Say Y here if you want the synthesis tool to infer pads.
+ Say N to directly instantiate technology-specific pads from
+ the selected target technology package.
+
+No async reset
+CONFIG_SYN_NO_ASYNC
+ Say Y here if you disable asynchronous reset in some of the IP cores.
+ Might be necessary if the target library does not have cells with
+ asynchronous set/reset.
+
+Scan support
+CONFIG_SYN_SCAN
+ Say Y here to enable scan support in some cores. This will enable
+ the scan support generics where available and add logic to make
+ the design testable using full-scan.
+
+Use Virtex CLKDLL for clock synchronisation
+CONFIG_CLK_INFERRED
+ Certain target technologies include clock generators to scale or
+ phase-adjust the system and SDRAM clocks. This is currently supported
+ for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you
+ can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2),
+ the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL
+ (Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred'
+ option to skip a clock generator.
+
+Clock multiplier
+CONFIG_CLK_MUL
+ When using the Xilinx DCM or Altera ALTPLL, the system clock can
+ be multiplied with a factor of 2 - 32, and divided by a factor of
+ 1 - 32. This makes it possible to generate almost any desired
+ processor frequency. When using the Xilinx CLKDLL generator,
+ the resulting frequency scale factor (mul/div) must be one of
+ 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
+
+ WARNING: The resulting clock must be within the limits specified
+ by the target FPGA family.
+
+Clock divider
+CONFIG_CLK_DIV
+ When using the Xilinx DCM or Altera ALTPLL, the system clock can
+ be multiplied with a factor of 2 - 32, and divided by a factor of
+ 1 - 32. This makes it possible to generate almost any desired
+ processor frequency. When using the Xilinx CLKDLL generator,
+ the resulting frequency scale factor (mul/div) must be one of
+ 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
+
+ WARNING: The resulting clock must be within the limits specified
+ by the target FPGA family.
+
+Output clock divider
+CONFIG_OCLK_DIV
+ When using the Proasic3 PLL, the system clock is generated by three
+ parameters: input clock multiplication, input clock division and
+ output clock division. Only certain values of these parameters
+ are allowed, but unfortunately this is not documented by Actel.
+ To find the correct values, run the Libero Smartgen tool and
+ insert you desired input and output clock frequencies in the
+ Static PLL configurator. The mul/div factors can then be read
+ out from tool.
+
+System clock multiplier
+CONFIG_CLKDLL_1_2
+ The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0,
+ or 2.0. Useful when the target board has an oscillator with a too high
+ (or low) frequency for your design. The divided clock will be used as the
+ main clock for the whole processor (except PCI and ethernet clocks).
+
+System clock multiplier
+CONFIG_DCM_2_3
+ The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
+ range of factors. Useful when the target board has an oscillator with a
+ too high (or low) frequency for your design. The divided clock will
+ be used as the main clock for the whole processor (except PCI and
+ ethernet clocks). NOTE: the resulting frequency must be at least
+ 24 MHz or the DCM and ALTDLL might not work.
+
+Enable CLKDLL for PCI clock
+CONFIG_PCI_CLKDLL
+ Say Y here to re-synchronize the PCI clock using a
+ Virtex BUFGDLL macro. Will improve PCI clock-to-output
+ delays on the expense of input-setup requirements.
+
+Use PCI clock system clock
+CONFIG_PCI_SYSCLK
+ Say Y here to the PCI clock to generate the system clock.
+ The PCI clock can be scaled using the DCM or CLKDLL to
+ generate a suitable processor clock.
+
+External SDRAM clock feedback
+CONFIG_CLK_NOFB
+ Say Y here to disable the external clock feedback to synchronize the
+ SDRAM clock. This option is necessary if your board or design does not
+ have an external clock feedback that is connected to the pllref input
+ of the clock generator.
+
+Number of processors
+CONFIG_PROC_NUM
+ The number of processor cores. The LEON3MP design can accomodate
+ up to 4 LEON3 processor cores. Use 1 unless you know what you are
+ doing ...
+
+Number of SPARC register windows
+CONFIG_IU_NWINDOWS
+ The SPARC architecture (and LEON) allows 2 - 32 register windows.
+ However, any number except 8 will require that you modify and
+ recompile your run-time system or kernel. Unless you know what
+ you are doing, use 8.
+
+SPARC V8 multiply and divide instruction
+CONFIG_IU_V8MULDIV
+ If you say Y here, the SPARC V8 multiply and divide instructions
+ will be implemented. The instructions are: UMUL, UMULCC, SMUL,
+ SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
+ integer multiplications and divisions, significant performance
+ increase can be achieved. Emulated floating-point operations will
+ also benefit from this option.
+
+ By default, the gcc compiler does not emit multiply or divide
+ instructions and your code must be compiled with -mv8 to see any
+ performance increase. On the other hand, code compiled with -mv8
+ will generate an illegal instruction trap when executed on processors
+ with this option disabled.
+
+ The divider consumes approximately 2 kgates, the multiplier 6 kgates.
+
+Multiplier latency
+CONFIG_IU_MUL_LATENCY_2
+ Implementation options for the integer multiplier.
+
+ Type Implementation issue-rate/latency
+ 2-clocks 32x32 pipelined multiplier 1/2
+ 4-clocks 16x16 standard multiplier 4/4
+ 5-clocks 16x16 pipelined multiplier 4/5
+
+Multiplier latency
+CONFIG_IU_MUL_MAC
+ If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
+ instructions will be enabled. The instructions implement a
+ single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
+ The details of these instructions can be found in the LEON manual,
+ This option is only available when 16x16 multiplier is used.
+
+Branch prediction
+CONFIG_IU_BP
+ Enabling branch prediction will improve performance with
+ up to 20%, depending on application. The timing and area
+ overhead are minor, so it is recommended to always enable
+ this option.
+
+Single vector trapping
+CONFIG_IU_SVT
+ Single-vector trapping is a SPARC V8e option to reduce code-size
+ in small applications. If enabled, the processor will jump to
+ the address of trap 0 (tt = 0x00) for all traps. No trap table
+ is then needed. The trap type is present in %psr.tt and must
+ be decoded by the O/S. Saves 4 Kbyte of code, but increases
+ trap and interrupt overhead. Currently, the only O/S supporting
+ this option is eCos. To enable SVT, the O/S must also set bit 13
+ in %asr17.
+
+Load latency
+CONFIG_IU_LDELAY
+ Defines the pipeline load delay (= pipeline cycles before the data
+ from a load instruction is available for the next instruction).
+ One cycle gives best performance, but might create a critical path
+ on targets with slow (data) cache memories. A 2-cycle delay can
+ improve timing but will reduce performance with about 5%.
+
+Reset address
+CONFIG_IU_RSTADDR
+ By default, a SPARC processor starts execution at address 0.
+ With this option, any 4-kbyte aligned reset start address can be
+ choosen. Keep at 0 unless you really know what you are doing.
+
+Power-down
+CONFIG_PWD
+ Say Y here to enable the power-down feature of the processor.
+ Might reduce the maximum frequency slightly on FPGA targets.
+ For details on the power-down operation, see the LEON3 manual.
+
+Hardware watchpoints
+CONFIG_IU_WATCHPOINTS
+ The processor can have up to 4 hardware watchpoints, allowing to
+ create both data and instruction breakpoints at any memory location,
+ also in PROM. Each watchpoint will use approximately 500 gates.
+ Use 0 to disable the watchpoint function.
+
+Floating-point enable
+CONFIG_FPU_ENABLE
+ Say Y here to enable the floating-point interface for the MEIKO
+ or GRFPU. Note that no FPU's are provided with the GPL version
+ of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial
+ cores and must be obtained separately.
+
+FPU selection
+CONFIG_FPU_GRFPU
+ Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun
+ Meiko FPU core. All cores are fully IEEE-754 compatible and support
+ all SPARC FPU instructions.
+
+GRFPU Multiplier
+CONFIG_FPU_GRFPU_INFMUL
+ On FPGA targets choose inferred multiplier. For ASIC implementations
+ choose between Synopsys Design Ware (DW) multiplier or Module
+ Generator (ModGen) multiplier. The DW multiplier gives better results
+ (smaller area and better timing) but requires a DW license.
+ The ModGen multiplier is part of GRLIB and does not require a license.
+ The Technology Specific multiplier option selects a pre-designed
+ multiplier using technology specific macrocells when available, else
+ an inferred multiplier is used.
+
+Shared GRFPU
+CONFIG_FPU_GRFPU_SH
+ If enabled multiple CPU cores will share one GRFPU.
+
+GRFPC Configuration
+CONFIG_FPU_GRFPC0
+ Configures the GRFPU-LITE controller.
+
+ In simple configuration controller executes FP instructions
+ in parallel with integer instructions. FP operands are fetched
+ in the register file stage and the result is written in the write
+ stage. This option uses least area resources.
+
+ Data forwarding configuration gives ~ 10 % higher FP performance than
+ the simple configuration by adding data forwarding between the pipeline
+ stages.
+
+ Non-blocking controller allows FP load and store instructions to
+ execute in parallel with FP instructions. The performance increase is
+ ~ 20 % for FP applications. This option uses most logic resources and
+ is suitable for ASIC implementations.
+
+Floating-point netlist
+CONFIG_FPU_NETLIST
+ Say Y here to use a VHDL netlist of the GRFPU-Lite. This is
+ only available in certain versions of grlib.
+
+Enable Instruction cache
+CONFIG_ICACHE_ENABLE
+ The instruction cache should always be enabled to allow
+ maximum performance. Some low-end system might want to
+ save area and disable the cache, but this will reduce
+ the performance with a factor of 2 - 3.
+
+Enable Data cache
+CONFIG_DCACHE_ENABLE
+ The data cache should always be enabled to allow
+ maximum performance. Some low-end system might want to
+ save area and disable the cache, but this will reduce
+ the performance with a factor of 2 at least.
+
+Instruction cache associativity
+CONFIG_ICACHE_ASSO1
+ The instruction cache can be implemented as a multi-set cache with
+ 1 - 4 sets. Higher associativity usually increases the cache hit
+ rate and thereby the performance. The downside is higher power
+ consumption and increased gate-count for tag comparators.
+
+ Note that a 1-set cache is effectively a direct-mapped cache.
+
+Instruction cache set size
+CONFIG_ICACHE_SZ1
+ The size of each set in the instuction cache (kbytes). Valid values
+ are 1 - 64 in binary steps. Note that the full range is only supported
+ by the generic and virtex2 targets. Most target packages are limited
+ to 2 - 16 kbyte. Large set size gives higher performance but might
+ affect the maximum frequency (on ASIC targets). The total instruction
+ cache size is the number of set multiplied with the set size.
+
+Instruction cache line size
+CONFIG_ICACHE_LZ16
+ The instruction cache line size. Can be set to either 16 or 32
+ bytes per line. Instruction caches typically benefit from larger
+ line sizes, but on small caches it migh be better with 16 bytes/line
+ to limit eviction miss rate.
+
+Instruction cache replacement algorithm
+CONFIG_ICACHE_ALGORND
+ Cache replacement algorithm for caches with 2 - 4 sets. The 'random'
+ algorithm selects the set to evict randomly. The least-recently-replaced
+ (LRR) algorithm evicts the set least recently replaced. The least-
+ recently-used (LRU) algorithm evicts the set least recently accessed.
+ The random algorithm uses a simple 1- or 2-bit counter to select
+ the eviction set and has low area overhead. The LRR scheme uses one
+ extra bit in the tag ram and has therefore also low area overhead.
+ However, the LRR scheme can only be used with 2-set caches. The LRU
+ scheme has typically the best performance but also highest area overhead.
+ A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops
+ per line, and a 4-set LRU uses 5 flip-flops per line to store the access
+ history.
+
+Instruction cache locking
+CONFIG_ICACHE_LOCK
+ Say Y here to enable cache locking in the instruction cache.
+ Locking can be done on cache-line level, but will increase the
+ width of the tag ram with one bit. If you don't know what
+ locking is good for, it is safe to say N.
+
+Data cache associativity
+CONFIG_DCACHE_ASSO1
+ The data cache can be implemented as a multi-set cache with
+ 1 - 4 sets. Higher associativity usually increases the cache hit
+ rate and thereby the performance. The downside is higher power
+ consumption and increased gate-count for tag comparators.
+
+ Note that a 1-set cache is effectively a direct-mapped cache.
+
+Data cache set size
+CONFIG_DCACHE_SZ1
+ The size of each set in the data cache (kbytes). Valid values are
+ 1 - 64 in binary steps. Note that the full range is only supported
+ by the generic and virtex2 targets. Most target packages are limited
+ to 2 - 16 kbyte. A large cache gives higher performance but the
+ data cache is timing critical an a too large setting might affect
+ the maximum frequency (on ASIC targets). The total data cache size
+ is the number of set multiplied with the set size.
+
+Data cache line size
+CONFIG_DCACHE_LZ16
+ The data cache line size. Can be set to either 16 or 32 bytes per
+ line. A smaller line size gives better associativity and higher
+ cache hit rate, but requires a larger tag memory.
+
+Data cache replacement algorithm
+CONFIG_DCACHE_ALGORND
+ See the explanation for instruction cache replacement algorithm.
+
+Data cache locking
+CONFIG_DCACHE_LOCK
+ Say Y here to enable cache locking in the data cache.
+ Locking can be done on cache-line level, but will increase the
+ width of the tag ram with one bit. If you don't know what
+ locking is good for, it is safe to say N.
+
+Data cache snooping
+CONFIG_DCACHE_SNOOP
+ Say Y here to enable data cache snooping on the AHB bus. Is only
+ useful if you have additional AHB masters such as the DSU or a
+ target PCI interface. Note that the target technology must support
+ dual-port RAMs for this option to be enabled. Dual-port RAMS are
+ currently supported on Virtex/2, Virage and Actel targets.
+
+Data cache snooping implementation
+CONFIG_DCACHE_SNOOP_FAST
+ The default snooping implementation is 'slow', which works if you
+ don't have AHB slaves in cacheable areas capable of zero-waitstates
+ non-sequential write accesses. Otherwise use 'fast' and suffer a
+ few kgates extra area. This option is currently only needed in
+ multi-master systems with the SSRAM or DDR memory controllers.
+
+Separate snoop tags
+CONFIG_DCACHE_SNOOP_SEPTAG
+ Enable a separate memory to store the data tags used for snooping.
+ This is necessary when snooping support is wanted in systems
+ with MMU, typically for SMP systems. In this case, the snoop
+ tags will contain the physical tag address while the normal
+ tags contain the virtual tag address. This option can also be
+ together with the 'fast snooping' option to enable snooping
+ support on technologies without dual-port RAMs. In such case,
+ the snoop tag RAM will be implemented using a two-port RAM.
+
+Fixed cacheability map
+CONFIG_CACHE_FIXED
+ If this variable is 0, the cacheable memory regions are defined
+ by the AHB plug&play information (default). To overriden the
+ plug&play settings, this variable can be set to indicate which
+ areas should be cached. The value is treated as a 16-bit hex value
+ with each bit defining if a 256 Mbyte segment should be cached or not.
+ The right-most (LSB) bit defines the cacheability of AHB address
+ 0 - 256 MByte, while the left-most bit (MSB) defines AHB address
+ 3840 - 4096 MByte. If the bit is set, the corresponding area is
+ cacheable. A value of 00F3 defines address 0 - 0x20000000 and
+ 0x40000000 - 0x80000000 as cacheable.
+
+Local data ram
+CONFIG_DCACHE_LRAM
+ Say Y here to add a local ram to the data cache controller.
+ Accesses to the ram (load/store) will be performed at 0 waitstates
+ and store data will never be written back to the AHB bus.
+
+Size of local data ram
+CONFIG_DCACHE_LRAM_SZ1
+ Defines the size of the local data ram in Kbytes. Note that most
+ technology libraries do not support larger rams than 16 Kbyte.
+
+Start address of local data ram
+CONFIG_DCACHE_LRSTART
+ Defines the 8 MSB bits of start address of the local data ram.
+ By default set to 8f (start address = 0x8f000000), but any value
+ (except 0) is possible. Note that the local data ram 'shadows'
+ a 16 Mbyte block of the address space.
+
+MMU enable
+CONFIG_MMU_ENABLE
+ Say Y here to enable the Memory Management Unit.
+
+MMU split icache/dcache table lookaside buffer
+CONFIG_MMU_COMBINED
+ Select "combined" for a combined icache/dcache table lookaside buffer,
+ "split" for a split icache/dcache table lookaside buffer
+
+MMU tlb replacement scheme
+CONFIG_MMU_REPARRAY
+ Select "LRU" to use the "least recently used" algorithm for TLB
+ replacement, or "Increment" for a simple incremental replacement
+ scheme.
+
+Combined i/dcache tlb
+CONFIG_MMU_I2
+ Select the number of entries for the instruction TLB, or the
+ combined icache/dcache TLB if such is used.
+
+Split tlb, dcache
+CONFIG_MMU_D2
+ Select the number of entries for the dcache TLB.
+
+Fast writebuffer
+CONFIG_MMU_FASTWB
+ Only selectable if split tlb is enabled. In case fast writebuffer is
+ enabled the tlb hit will be made concurrent to the cache hit. This
+ leads to higher store performance, but increased power and area.
+
+MMU pagesize
+CONFIG_MMU_PAGE_4K
+ The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the
+ cache way size to 4 Kbyte, and total data cache size to 16 Kbyte,
+ when the MMU is used. To increase the maximum data cache size,
+ the MMU pages size can be increased to up 32 Kbyte. This will
+ give a maximum data cache size of 128 Kbyte.
+
+ Note that an MMU page size different than 4 Kbyte will require
+ a special linux tool-chain if glibc is used. If you don't know
+ what you are doing, stay with 4 Kbyte ...
+
+DSU enable
+CONFIG_DSU_ENABLE
+ The debug support unit (DSU) allows non-intrusive debugging and tracing
+ of both executed instructions and AHB transfers. If you want to enable
+ the DSU, say Y here and select the configuration below.
+
+Trace buffer enable
+CONFIG_DSU_TRACEBUF
+ Say Y to enable the trace buffer. The buffer is not necessary for
+ debugging, only for tracing instructions and data transfers.
+
+Enable instruction tracing
+CONFIG_DSU_ITRACE
+ If you say Y here, an instruction trace buffer will be implemented
+ in each processor. The trace buffer will trace executed instructions
+ and their results, and place them in a circular buffer. The buffer
+ can be read out by any AHB master, and in particular by the debug
+ communication link.
+
+Size of trace buffer
+CONFIG_DSU_ITRACESZ1
+ Select the buffer size (in kbytes) for the instruction trace buffer.
+ Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
+ need 2 kbyte.
+
+Enable AHB tracing
+CONFIG_DSU_ATRACE
+ If you say Y here, an AHB trace buffer will be implemented in the
+ debug support unit processor. The AHB buffer will trace all transfers
+ on the AHB bus and save them in a circular buffer. The trace buffer
+ can be read out by any AHB master, and in particular by the debug
+ communication link.
+
+Size of trace buffer
+CONFIG_DSU_ATRACESZ1
+ Select the buffer size (in kbytes) for the AHB trace buffer.
+ Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
+ need 2 kbyte.
+
+
+LEON3FT enable
+CONFIG_LEON3FT_EN
+ Say Y here to use the fault-tolerant LEON3FT core instead of the
+ standard non-FT LEON3.
+
+IU Register file protection
+CONFIG_IUFT_NONE
+ Select the FT implementation in the LEON3FT integer unit
+ register file. The options include parity, parity with
+ sparing, 7-bit BCH and TMR.
+
+FPU Register file protection
+CONFIG_FPUFT_EN
+ Say Y to enable SEU protection of the FPU register file.
+ The GRFPU will be protected using 8-bit parity without restart, while
+ the GRFPU-Lite will be protected with 4-bit parity with restart. If
+ disabled the FPU register file will be implemented using flip-flops.
+
+Cache memory error injection
+CONFIG_RF_ERRINJ
+ Say Y here to enable error injection in to the IU/FPU regfiles.
+ Affects only simulation.
+
+Cache memory protection
+CONFIG_CACHE_FT_EN
+ Enable SEU error-correction in the cache memories.
+
+Cache memory error injection
+CONFIG_CACHE_ERRINJ
+ Say Y here to enable error injection in to the cache memories.
+ Affects only simulation.
+
+Leon3ft netlist
+CONFIG_LEON3_NETLIST
+ Say Y here to use a VHDL netlist of the LEON3FT. This is
+ only available in certain versions of grlib.
+
+IU assembly printing
+CONFIG_IU_DISAS
+ Enable printing of executed instructions to the console.
+
+IU assembly printing in netlist
+CONFIG_IU_DISAS_NET
+ Enable printing of executed instructions to the console also
+ when simulating a netlist. NOTE: with this option enabled, it
+ will not be possible to pass place&route.
+
+32-bit program counters
+CONFIG_DEBUG_PC32
+ Since the LSB 2 bits of the program counters always are zero, they are
+ normally not implemented. If you say Y here, the program counters will
+ be implemented with full 32 bits, making debugging of the VHDL model
+ much easier. Turn of this option for synthesis or you will be wasting
+ area.
+CONFIG_AHB_DEFMST
+ Sets the default AHB master (see AMBA 2.0 specification for definition).
+ Should not be set to a value larger than the number of AHB masters - 1.
+ For highest processor performance, leave it at 0.
+
+Default AHB master
+CONFIG_AHB_RROBIN
+ Say Y here to enable round-robin arbitration of the AHB bus. A N will
+ select fixed priority, with the master with the highest bus index having
+ the highest priority.
+
+Support AHB split-transactions
+CONFIG_AHB_SPLIT
+ Say Y here to enable AHB split-transaction support in the AHB arbiter.
+ Unless you actually have an AHB slave that can generate AHB split
+ responses, say N and save some gates.
+
+Default AHB master
+CONFIG_AHB_IOADDR
+ Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined
+ in the plug&play extentions of the AMBA bus. Should be kept to FFF
+ unless you really know what you are doing.
+
+APB bridge address
+CONFIG_APB_HADDR
+ Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
+ kept at 800 for software compatibility.
+
+AHB monitor
+CONFIG_AHB_MON
+ Say Y to enable the AHB bus monitor. The monitor will check for
+ illegal AHB transactions during simulation. It has no impact on
+ synthesis.
+
+Report AHB errors
+CONFIG_AHB_MONERR
+ Print out detected AHB violations on console.
+
+Report AHB warnings
+CONFIG_AHB_MONWAR
+ Print out detected AHB warnings on console.
+
+
+DSU enable
+CONFIG_DSU_UART
+ Say Y to enable the AHB uart (serial-to-AHB). This is the most
+ commonly used debug communication link.
+
+JTAG Enable
+CONFIG_DSU_JTAG
+ Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done
+ with GRMON through the boards JTAG chain at speeds of up to 800 kbits/s.
+ Supported JTAG cables are Xilinx Parallel Cable III and IV,
+ Xilinx Platform cables (USB), and Altera parallel and USB cables.
+
+USB DSU enable
+CONFIG_GRUSB_DCL
+ Say Y to enable the USB Debug Communication Link
+
+CONFIG_GRUSB_DCL_ULPI
+ Select the interface of the USB transceiver that the USBDCL will be
+ connected to.
+Ethernet DSU enable
+CONFIG_DSU_ETH
+ Say Y to enable the Ethernet Debug Communication Link (EDCL). The link
+ provides a DSU gateway between ethernet and the AHB bus. Debugging is
+ done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must
+ enable the GRETH Ethernet MAC for this option to become active.
+
+Size of EDCL trace buffer
+CONFIG_DSU_ETHSZ1
+ Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is
+ usually enough, while a larger buffer will increase the transfer rate.
+ When operating at 100 Mbit, use a buffer size of at least 8 kbyte for
+ maximum throughput.
+
+MSB IP address
+CONFIG_DSU_IPMSB
+ Set the MSB 16 bits of the IP address of the EDCL.
+
+LSB IP address
+CONFIG_DSU_IPLSB
+ Set the LSB 16 bits of the IP address of the EDCL.
+
+MSB ethernet address
+CONFIG_DSU_ETHMSB
+ Set the MSB 24 bits of the ethernet address of the EDCL.
+
+LSB ethernet address
+CONFIG_DSU_ETHLSB
+ Set the LSB 24 bits of the ethernet address of the EDCL.
+
+Programmable MAC/IP address
+CONFIG_DSU_ETH_PROG
+ Say Y to make the LSB 4 bits of the EDCL MAC and IP address
+ configurable using the ethi.edcladdr inputs.
+Leon2 memory controller
+CONFIG_MCTRL_LEON2
+ Say Y here to enable the LEON2 memory controller. The controller
+ can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
+ and SRAM is programmable to 8-, 16- or 32-bits.
+
+8-bit memory support
+CONFIG_MCTRL_8BIT
+ If you say Y here, the PROM/SRAM memory controller will support
+ 8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
+ Say N to save a few hundred gates.
+
+16-bit memory support
+CONFIG_MCTRL_16BIT
+ If you say Y here, the PROM/SRAM memory controller will support
+ 16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
+ Say N to save a few hundred gates.
+
+Write strobe feedback
+CONFIG_MCTRL_WFB
+ If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
+ be used to enable the data bus drivers during write cycles. This
+ will guarantee that the data is still valid on the rising edge of
+ the write strobe. If you say N, the write strobes and the data bus
+ drivers will be clocked on the rising edge, potentially creating
+ a hold time problem in external memory or I/O. However, in all
+ practical cases, there is enough capacitance in the data bus lines
+ to keep the value stable for a few (many?) nano-seconds after the
+ buffers have been disabled, making it safe to say N and remove a
+ combinational path in the netlist that might be difficult to
+ analyze.
+
+Write strobe feedback
+CONFIG_MCTRL_5CS
+ If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
+ be enabled. If you don't intend to use it, say N and save some gates.
+
+SDRAM controller enable
+CONFIG_MCTRL_SDRAM
+ Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
+ intend to use SDRAM, say N and save about 1 kgates.
+
+SDRAM controller inverted clock
+CONFIG_MCTRL_SDRAM_INVCLK
+ If you say Y here, the SDRAM controller output signals will be delayed
+ with 1/2 clock in respect to the SDRAM clock. This will allow the used
+ of an SDRAM clock which in not strictly in phase with the internal
+ clock. This option will limit the SDRAM frequency to 40 - 50 MHz.
+
+ On FPGA targets without SDRAM clock synchronizations through PLL/DLL,
+ say Y. On ASIC targets, say N and tell your foundry to balance the
+ SDRAM clock output.
+
+SDRAM separate address buses
+CONFIG_MCTRL_SDRAM_SEPBUS
+ Say Y here if your SDRAM is connected through separate address
+ and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
+ board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.
+
+64-bit data bus
+CONFIG_MCTRL_SDRAM_BUS64
+ Say Y here to enable 64-bit SDRAM data bus.
+
+Page burst enable
+CONFIG_MCTRL_PAGE
+ Say Y here to enable SDRAM page burst operation. This will implement
+ read operations using page bursts rather than 8-word bursts and save
+ about 500 gates (100 LUTs). Note that not all SDRAM supports page
+ burst, so use this option with care.
+
+Programmable page burst enable
+CONFIG_MCTRL_PROGPAGE
+ Say Y here to enable programmable SDRAM page burst operation. This
+ will allow to dynamically enable/disable page burst by setting
+ bit 17 in MCFG2.
+
+AHB status register
+CONFIG_AHBSTAT_ENABLE
+ Say Y here to enable the AHB status register (AHBSTAT IP).
+ The register will latch the AHB address and master index when
+ an error response is returned by any AHB slave.
+
+SDRAM separate address buses
+CONFIG_AHBSTAT_NFTSLV
+ The AHB status register can also latch the AHB address on an external
+ input. Select here how many of such inputs are required.
+
+On-chip rom
+CONFIG_AHBROM_ENABLE
+ Say Y here to add a block on on-chip rom to the AHB bus. The ram
+ provides 0-waitstates read access, burst support, and 8-, 16-
+ and 32-bit data size. The rom will be syntheised into block rams
+ on Xilinx and Altera FPGA devices, and into gates on ASIC
+ technologies. GRLIB includes a utility to automatically create
+ the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
+ documentation for details.
+
+On-chip rom address
+CONFIG_AHBROM_START
+ Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
+ a 1 Mbyte slot at the selected address. Default is 000, corresponding
+ to AHB address 0x00000000. When address 0x0 is selected, the rom area
+ of any other memory controller is set to 0x10000000 to avoid conflicts.
+
+Enable pipeline register for on-chip rom
+CONFIG_AHBROM_PIPE
+ Say Y here to add a data pipeline register to the on-chip rom.
+ This should be done when the rom is implemenented in (ASIC) gates,
+ or in logic cells on FPGAs. Do not use this option when the rom is
+ implemented in block rams. If enabled, the rom will operate with
+ one waitstate.
+
+On-chip ram
+CONFIG_AHBRAM_ENABLE
+ Say Y here to add a block on on-chip ram to the AHB bus. The ram
+ provides 0-waitstates read access and 0/1 waitstates write access.
+ All AHB burst types are supported, as well as 8-, 16- and 32-bit
+ data size.
+
+On-chip ram size
+CONFIG_AHBRAM_SZ1
+ Set the size of the on-chip AHB ram. The ram is infered/instantiated
+ as four byte-wide ram slices to allow byte and half-word write
+ accesses. It is therefore essential that the target package can
+ infer byte-wide rams. This is currently supported on the generic,
+ virtex, virtex2, proasic and axellerator targets.
+
+On-chip ram address
+CONFIG_AHBRAM_START
+ Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
+ a 1 Mbyte slot at the selected address. Default is A00, corresponding
+ to AHB address 0xA0000000.
+
+Gaisler Ethernet MAC enable
+CONFIG_GRETH_ENABLE
+ Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has
+ one AHB master interface to read and write packets to memory, and one
+ APB slave interface for accessing the control registers.
+
+Gaisler Ethernet 1G MAC enable
+CONFIG_GRETH_GIGA
+ Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC .
+ The 1G MAC is only available in the commercial version of GRLIB,
+ so do NOT enable it if you are using the GPL version.
+
+CONFIG_GRETH_FIFO4
+ Set the depth of the receive and transmit FIFOs in the MAC core.
+ The MAC core will perform AHB burst read/writes with half the
+ size of the FIFO depth.
+
+
+ATA interface enable
+CONFIG_ATA_ENABLE
+ Say Y here to enable the ATA interace from OpenCores. The core has one
+ AHB slave interface for accessing all control registers.
+
+ATA register address
+CONFIG_ATAIO
+ The control registers of the ATA core occupy 256 byte, and are
+ mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting
+ defines at which address in the I/O area the registers appear (HADDR[19:8]).
+
+ATA interrupt
+CONFIG_ATAIRQ
+ Defines which interrupt number the ATA core will generate.
+
+ATA DMA support
+CONFIG_ATA_MWDMA
+ Say yes here to enable IDE multi-word DMA support (MWDMA).
+ This will increase transfer rate compared to the PIO mode,
+ but increase area with approxiamtely 5,000 gates. Note that
+ DMA is not supported by legacy CF cards, so it makes no sense
+ to enable it on CF card sockets.
+
+ATA DMA FIFO depth
+CONFIG_ATA_FIFO
+ Defines the DMA FIFO depth. Choose 8 or 16.
+CAN interface enable
+CONFIG_CAN_ENABLE
+ Say Y here to enable one or more CAN cores. The cores has one
+ AHB slave interface for accessing the control registers. The CAN core
+ is register-compatible with the SAJ1000 core from Philips, with a
+ few exceptions. See the GRLIP IP manual for details.
+
+CONFIG_CAN_NUM
+ Number of CAN cores. The module allows up to 8 independent
+ CAN cores to be implemented.
+
+CAN register address
+CONFIG_CANIO
+ The control registers of each CAN core occupies 256 bytes, and
+ address space needed for the full module is thus 2 Kbyte. The cores
+ are mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000).
+ This setting defines at which address in the I/O area the registers
+ appear (HADDR[19:8]).
+
+CAN interrupt
+CONFIG_CANIRQ
+ Defines which interrupt number the CAN core will generate.
+
+CAN interrupt
+CONFIG_CANSEPIRQ
+ Say Y here to assign an individual interrupt to each CAN core,
+ starting from the base interrupt number. If set to N, all
+ CAN cores will generate the same interrupt.
+
+CAN FT memories
+CONFIG_CAN_FT
+ If you say Y here, the CAN FIFOs will be implemented using
+ SEU protected RAM blocks. Only applicable to the FT version
+ of grlib.
+
+CAN Synchronous reset
+CONFIG_CAN_SYNCRST
+ If you say Y here, the CAN core will be implemented with
+ synchronous reset rather than asynchronous. This is needed
+ when the target library does not implement registers with
+ async reset. Unless you know what you are doing, say N.
+
+Gaisler Research USB 2.0 Device Controller enable
+CONFIG_GRUSBDC_ENABLE
+ Say Y here to enable the Gaisler Research USB 2.0 Device Controller.
+ The core can be configured with 1-16 IN endpoints and 1-16 OUT
+ endpoints (including endpoint zero). The core use an AHB slave
+ interface for configuration. For data transfers the the user have the
+ option of adding an AHB master interface for DMA, or to use the slave
+ interface. The core supports 8-bit and 16-bit UTMI/UTMI+ and
+ ULPI interfaces towards the USB transceiver.
+
+CONFIG_GRUSBDC_AHBMST
+ Say Y here to enable the AHB master interface and DMA. When master
+ interface is disabled all data transfers are handled with the AHB
+ slave interface.
+
+CONFIG_GRUSBDC_ULPI
+ Select the interface of the USB transceiver that the core will be
+ connected to.
+
+CONFIG_GRUSBDC_NEPI
+ Select number of IN endpoints (including endpoint zero).
+ Valid range is 1 - 16.
+
+CONFIG_GRUSBDC_NEPO
+ Select number of OUT endpoints (including endpoint zero).
+ Valid range is 1 - 16.
+
+CONFIG_GRUSBDC_I0
+ Select buffer size (in bytes) for IN endpoint 0.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O0
+ Select buffer size (in bytes) for OUT endpoint 0.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I1
+ Select buffer size (in bytes) for IN endpoint 1.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O1
+ Select buffer size (in bytes) for OUT endpoint 1.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I2
+ Select buffer size (in bytes) for IN endpoint 2.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O2
+ Select buffer size (in bytes) for OUT endpoint 2.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I3
+ Select buffer size (in bytes) for IN endpoint 3.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O3
+ Select buffer size (in bytes) for OUT endpoint 3.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I4
+ Select buffer size (in bytes) for IN endpoint 4.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O4
+ Select buffer size (in bytes) for OUT endpoint 4.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I5
+ Select buffer size (in bytes) for IN endpoint 5.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O5
+ Select buffer size (in bytes) for OUT endpoint 5.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I6
+ Select buffer size (in bytes) for IN endpoint 6.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O6
+ Select buffer size (in bytes) for OUT endpoint 6.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I7
+ Select buffer size (in bytes) for IN endpoint 7.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O7
+ Select buffer size (in bytes) for OUT endpoint 7.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I8
+ Select buffer size (in bytes) for IN endpoint 8.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O8
+ Select buffer size (in bytes) for OUT endpoint 8.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I9
+ Select buffer size (in bytes) for IN endpoint 9.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O9
+ Select buffer size (in bytes) for OUT endpoint 9.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I10
+ Select buffer size (in bytes) for IN endpoint 10.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O10
+ Select buffer size (in bytes) for OUT endpoint 10.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I11
+ Select buffer size (in bytes) for IN endpoint 11.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O11
+ Select buffer size (in bytes) for OUT endpoint 11.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I12
+ Select buffer size (in bytes) for IN endpoint 12.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O12
+ Select buffer size (in bytes) for OUT endpoint 12.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I13
+ Select buffer size (in bytes) for IN endpoint 13.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O13
+ Select buffer size (in bytes) for OUT endpoint 13.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I14
+ Select buffer size (in bytes) for IN endpoint 14.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O14
+ Select buffer size (in bytes) for OUT endpoint 14.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_I15
+ Select buffer size (in bytes) for IN endpoint 15.
+ Valid range is 8 - 3072.
+
+CONFIG_GRUSBDC_O15
+ Select buffer size (in bytes) for OUT endpoint 15.
+ Valid range is 8 - 3072.
+
+UART1 enable
+CONFIG_UART1_ENABLE
+ Say Y here to enable UART1, or the console UART. This is needed to
+ get any print-out from LEON3 systems regardless of operating system.
+
+UART1 FIFO
+CONFIG_UA1_FIFO1
+ The UART has configurable transmitt and receive FIFO's, which can
+ be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
+ maximum throughput.
+
+
+UART2 enable
+CONFIG_UART2_ENABLE
+ Say Y here to enable UART2, or the secondary UART. This UART can be
+ used to connect a second console (uClinux) or to control external
+ equipment.
+
+UART2 FIFO
+CONFIG_UA2_FIFO1
+ The UART has configurable transmitt and receive FIFO's, which can
+ be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
+ maximum throughput.
+
+LEON3 interrupt controller
+CONFIG_IRQ3_ENABLE
+ Say Y here to enable the LEON3 interrupt controller. This is needed
+ if you want to be able to receive interrupts. Operating systems like
+ Linux, RTEMS and eCos needs this option to be enabled. If you intend
+ to use the Bare-C run-time and not use interrupts, you could disable
+ the interrupt controller and save about 500 gates.
+
+LEON3 interrupt controller broadcast
+CONFIG_IRQ3_BROADCAST_ENABLE
+ If enabled the broadcast register is used to determine which
+ interrupt should be sent to all cpus instead of just the first
+ one that consumes it.
+
+Secondary interrupts
+CONFIG_IRQ3_SEC
+ The interrupt controller handles 15 interrupts by default (1 - 15).
+ These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F),
+ and AMBA interrupts 1 - 15. This option will enable 16 additional
+ (secondary) interrupts, corresponding to AMBA interrupts 16 - 31.
+ The secondary interrupts will be multiplexed onto one of the first
+ 15 interrupts. The total number of handled interrupts can then
+ be up to 30 (14 primary and 16 secondary).
+
+Number of interrupts
+CONFIG_IRQ3_NSEC
+ Defines which of the first 15 interrupts should be used for the
+ secondary (16 - 31) interrupts. Interrupt 15 should be avoided
+ since it is not maskable by the processor.
+Timer module enable
+CONFIG_GPT_ENABLE
+ Say Y here to enable the Modular Timer Unit. The timer unit consists
+ of one common scaler and up to 7 independent timers. The timer unit
+ is needed for Linux, RTEMS, eCos and the Bare-C run-times.
+
+Timer module enable
+CONFIG_GPT_NTIM
+ Set the number of timers in the timer unit (1 - 7).
+
+Scaler width
+CONFIG_GPT_SW
+ Set the width if the common pre-scaler (2 - 16 bits). The scaler
+ is used to divide the system clock down to 1 MHz, so 8 bits should
+ be sufficient for most implementations (allows clocks up to 256 MHz).
+
+Timer width
+CONFIG_GPT_TW
+ Set the width if the timers (2 - 32 bits). 32 bits is recommended
+ for the Bare-C run-time, lower values (e.g. 16 bits) can work with
+ RTEMS and Linux.
+
+Timer Interrupt
+CONFIG_GPT_IRQ
+ Set the interrupt number for the first timer. Remaining timers will
+ have incrementing interrupts, unless the separate-interrupts option
+ below is disabled.
+
+Watchdog enable
+CONFIG_GPT_WDOGEN
+ Say Y here to enable the watchdog functionality in the timer unit.
+
+Watchdog time-out value
+CONFIG_GPT_WDOG
+ This value will be loaded in the watchdog timer at reset.
+
+GPIO port
+CONFIG_GRGPIO_ENABLE
+ Say Y here to enable a general purpose I/O port. The port can be
+ configured from 1 - 32 bits, whith each port signal individually
+ programmable as input or output. The port signals can also serve
+ as interrupt inputs.
+
+GPIO port witdth
+CONFIG_GRGPIO_WIDTH
+ Number of bits in the I/O port. Must be in the range of 1 - 32.
+
+GPIO interrupt mask
+CONFIG_GRGPIO_IMASK
+ The I/O port interrupt mask defines which bits in the I/O port
+ should be able to create an interrupt.
+
+Spacewire link
+CONFIG_SPW_ENABLE
+ Say Y here to enable one or more Spacewire serial links. The links
+ are based on the GRSPW core from Gaisler Research.
+
+Number of spacewire links
+CONFIG_SPW_NUM
+ Select the number of links to implement. Each link will be a
+ separate AHB master and APB slave for configuration.
+
+AHB FIFO depth
+CONFIG_SPW_AHBFIFO4
+ Select the AHB FIFO depth (in 32-bit words).
+
+RX FIFO depth
+CONFIG_SPW_RXFIFO16
+ Select the receiver FIFO depth (in bytes).
+
+RMAP protocol
+CONFIG_SPW_RMAP
+ Enable hardware target support for the RMAP protocol (
+ draft C for GRSPW1 and ECSS-E-ST-50-11C Draft V1.3
+ for GRSPW2).
+
+RMAP Buffer depth
+CONFIG_SPW_RMAPBUF2
+ Select the size of the RMAP buffer (in bytes).
+
+RMAP CRC
+CONFIG_SPW_RMAPCRC
+ Enable hardware calculation of the RMAP CRC checksum. RMAP CRC
+ is always enabled when the RMAP hardware target is enabled so this
+ parameter will have no effect in that case.
+
+Rx unaligned
+CONFIG_SPW_RXUNAL
+ Enable support for byte writes used for non word-aligned
+ receiver buffer addresses. Without this enabled data will
+ still be written at the correct location but complete words
+ will always be written so data outside the intended boundaries
+ might be overwritten.
+
+Netlists
+CONFIG_SPW_NETLIST
+ Use the netlist version of GRSPW. This option is required if
+ you have not licensed the source code of the Spacewire core.
+ Currently only supported for Xilinx and Actel FPGAs.
+ The AHB/RX FIFO sizes should be set to 16 word/byte. If the
+ RMAP is enabled, set the buffer size to 128 bytes. Other netlist
+ configurations can be requested from Gaisler Research.
+
+Spacewire FT
+CONFIG_SPW_FT
+ Say Y here to implement the Spacewire block rams with fault-tolerance
+ against SEU errors.
+
+Spacewire core
+CONFIG_SPW_GRSPW1
+ Select to use GRSPW1 core or GRSPW2 core.
+
+DMA channels
+CONFIG_SPW_DMACHAN
+ Set the number of DMA channels for the GRSPW2 core.
+ Set to 1 for now ...
+
+Ports
+CONFIG_SPW_PORTS
+ Set the number of SpaceWire ports for the GRSPW2 core
+
+Same clock for SpaceWire receiver and transmitter
+CONFIG_SPW_RTSAME
+ Say Y here if the same clock is connected to both the receiver
+ and transmitter in the GRSPW2 core. This will remove two
+ asynchronous resets and some synchronization logic. This is only
+ applicable for the SDR and DDR inputs modes.
+
+
+Receiver clock type
+CONFIG_SPW_RX_SDR
+ Selects the input clocking scheme for the GRSPW2. SDR means that the
+ core samples data and strobe using single data rate registers at the
+ receiver clock frequency. DDR is the same except DDR registers are used.
+ Xor selects the traditional self clocking scheme using a xor gate.
+ Aeroflex sets the receiver in a mode compatible with the Aeroflex
+ SpaceWire transceiver.
+
+Receiver clock type
+CONFIG_SPW_TX_SDR
+ Selects the output clocking scheme for the GRSPW2. SDR means that the
+ core transmits data and strobe using single data rate registers at the
+ transmitter clock frequency. DDR is the same except DDR registers are used.
+ Aeroflex sets the transmitter in a mode compatible with the Aeroflex
+ SpaceWire transceiver.
+Text-mode VGA
+CONFIG_VGA_ENABLE
+ Say Y here to enable a simple text-mode VGA controller. The controller
+ generate 48x36 characters on a 640x480 pixel screen. The pixel clock
+ is 25 MHz.
+
+SVGA frame buffer
+CONFIG_SVGA_ENABLE
+ Say Y here to enable a graphical frame buffer. The frame buffer
+ can be configured up to 1024x768 pixels and 8-, 16- or 32-bit
+ colour depth.
+
+PS2 KBD interface
+CONFIG_KBD_ENABLE
+ Say Y here to enable a PS/2 keyboard or mouse interface.
+
+UART debugging
+CONFIG_DEBUG_UART
+ During simulation, the output from the UARTs is printed on the
+ simulator console. Since the ratio between the system clock and
+ UART baud-rate is quite high, simulating UART output will be very
+ slow. If you say Y here, the UARTs will print a character as soon
+ as it is stored in the transmitter data register. The transmitter
+ ready flag will be permanently set, speeding up simulation. However,
+ the output on the UART tx line will be garbled. Has not impact on
+ synthesis, but will cause the LEON test bench to fail.
+
+FPU register tracing
+CONFIG_DEBUG_FPURF
+ If you say Y here, all writes to the floating-point unit register file
+ will be printed on the simulator console.
+
--- /dev/null
+
+# LEON3 configuration written in linux configuration language
+#
+# Written by Jiri Gaisler, Gaisler Research
+#
+# Comments and bug reports to jiri@gaisler.com
+#
+#
+
+#define_bool CONFIG_MCTRL_RMW y
+
+mainmenu_name "LEON3MP Design Configuration"
+
+mainmenu_option next_comment
+ comment 'Synthesis '
+ source lib/techmap/gencomp/tech.in
+ choice 'FPGA type ' \
+ "XC3S-1500 CONFIG_FPGA_1500 \
+ XC3S-2000 CONFIG_FPGA_2000" XC3S-1500
+
+endmenu
+
+mainmenu_option next_comment
+ comment 'Clock generation'
+ source lib/techmap/clocks/clkgen.in
+endmenu
+
+source lib/gaisler/leon3/leon3.in
+source lib/grlib/amba/amba.in
+
+mainmenu_option next_comment
+ comment 'Debug Link '
+ source lib/gaisler/uart/dcom.in
+ source lib/gaisler/jtag/jtag.in
+ source lib/gaisler/usb/grusb_dcl.in
+ source lib/gaisler/net/edcl.in
+endmenu
+
+mainmenu_option next_comment
+comment 'Peripherals '
+
+ mainmenu_option next_comment
+ comment 'Memory controller '
+ source lib/esa/memoryctrl/mctrl.in
+ source lib/gaisler/misc/ahbstat.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'On-chip RAM/ROM '
+ source lib/gaisler/misc/ahbrom.in
+ source lib/gaisler/misc/ahbram.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'Ethernet '
+ source lib/gaisler/greth/greth.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'IDE Disk controller '
+ source lib/gaisler/ata/ata.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'CAN '
+ source lib/gaisler/can/can_mc.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'USB 2.0 Device Controller '
+ source lib/gaisler/usb/grusbdc.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'UART, timer, I/O port and interrupt controller'
+ source lib/gaisler/uart/uart1.in
+ if [ "$CONFIG_DSU_UART" != "y" ]; then
+ source lib/gaisler/uart/uart2.in
+ fi
+ source lib/gaisler/leon3/irqmp.in
+ source lib/gaisler/misc/gptimer.in
+ source lib/gaisler/misc/grgpio.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'Spacewire '
+ source lib/gaisler/spacewire/spacewire.in
+ endmenu
+
+ mainmenu_option next_comment
+ comment 'Keybord and VGA interface'
+ source lib/gaisler/misc/ps2vga.in
+ endmenu
+endmenu
+
+mainmenu_option next_comment
+comment 'VHDL Debugging '
+ source lib/grlib/util/debug.in
+endmenu
--- /dev/null
+
+
+
+
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench configuration
+-- Copyright (C) 2009 Aeroflex Gaisler
+------------------------------------------------------------------------------
+
+
+library techmap;
+use techmap.gencomp.all;
+
+package config is
+-- Technology and synthesis options
+ constant CFG_FABTECH : integer := spartan3;
+ constant CFG_MEMTECH : integer := spartan3;
+ constant CFG_PADTECH : integer := spartan3;
+ constant CFG_NOASYNC : integer := 0;
+ constant CFG_SCAN : integer := 0;
+-- Clock generator
+ constant CFG_CLKTECH : integer := spartan3;
+ constant CFG_CLKMUL : integer := (4);
+ constant CFG_CLKDIV : integer := (5);
+ constant CFG_OCLKDIV : integer := 2;
+ constant CFG_PCIDLL : integer := 0;
+ constant CFG_PCISYSCLK: integer := 0;
+ constant CFG_CLK_NOFB : integer := 0;
+-- LEON3 processor core
+ constant CFG_LEON3 : integer := 1;
+ constant CFG_NCPU : integer := (1);
+ constant CFG_NWIN : integer := (8);
+ constant CFG_V8 : integer := 16#32#;
+ constant CFG_MAC : integer := 0;
+ constant CFG_BP : integer := 0;
+ constant CFG_SVT : integer := 0;
+ constant CFG_RSTADDR : integer := 16#00000#;
+ constant CFG_LDDEL : integer := (1);
+ constant CFG_NWP : integer := (4);
+ constant CFG_PWD : integer := 0*2;
+ constant CFG_FPU : integer := 0 + 16*0;
+ constant CFG_GRFPUSH : integer := 0;
+ constant CFG_ICEN : integer := 1;
+ constant CFG_ISETS : integer := 2;
+ constant CFG_ISETSZ : integer := 4;
+ constant CFG_ILINE : integer := 8;
+ constant CFG_IREPL : integer := 0;
+ constant CFG_ILOCK : integer := 0;
+ constant CFG_ILRAMEN : integer := 0;
+ constant CFG_ILRAMADDR: integer := 16#8E#;
+ constant CFG_ILRAMSZ : integer := 1;
+ constant CFG_DCEN : integer := 1;
+ constant CFG_DSETS : integer := 1;
+ constant CFG_DSETSZ : integer := 4;
+ constant CFG_DLINE : integer := 4;
+ constant CFG_DREPL : integer := 0;
+ constant CFG_DLOCK : integer := 0;
+ constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
+ constant CFG_DFIXED : integer := 16#0#;
+ constant CFG_DLRAMEN : integer := 0;
+ constant CFG_DLRAMADDR: integer := 16#8F#;
+ constant CFG_DLRAMSZ : integer := 1;
+ constant CFG_MMUEN : integer := 1;
+ constant CFG_ITLBNUM : integer := 8;
+ constant CFG_DTLBNUM : integer := 8;
+ constant CFG_TLB_TYPE : integer := 0 + 1*2;
+ constant CFG_TLB_REP : integer := 0;
+ constant CFG_MMU_PAGE : integer := 4;
+ constant CFG_DSU : integer := 1;
+ constant CFG_ITBSZ : integer := 2;
+ constant CFG_ATBSZ : integer := 2;
+ constant CFG_LEON3FT_EN : integer := 0;
+ constant CFG_IUFT_EN : integer := 0;
+ constant CFG_FPUFT_EN : integer := 0;
+ constant CFG_RF_ERRINJ : integer := 0;
+ constant CFG_CACHE_FT_EN : integer := 0;
+ constant CFG_CACHE_ERRINJ : integer := 0;
+ constant CFG_LEON3_NETLIST: integer := 0;
+ constant CFG_DISAS : integer := 0 + 0;
+ constant CFG_PCLOW : integer := 2;
+-- AMBA settings
+ constant CFG_DEFMST : integer := (0);
+ constant CFG_RROBIN : integer := 1;
+ constant CFG_SPLIT : integer := 0;
+ constant CFG_AHBIO : integer := 16#FFF#;
+ constant CFG_APBADDR : integer := 16#800#;
+ constant CFG_AHB_MON : integer := 0;
+ constant CFG_AHB_MONERR : integer := 0;
+ constant CFG_AHB_MONWAR : integer := 0;
+-- DSU UART
+ constant CFG_AHB_UART : integer := 1;
+-- JTAG based DSU interface
+ constant CFG_AHB_JTAG : integer := 1;
+-- USB DSU
+ constant CFG_GRUSB_DCL : integer := 0;
+ constant CFG_GRUSB_DCL_UIFACE : integer := 1;
+ constant CFG_GRUSB_DCL_DW : integer := 8;
+-- Ethernet DSU
+ constant CFG_DSU_ETH : integer := 1 + 0;
+ constant CFG_ETH_BUF : integer := 2;
+ constant CFG_ETH_IPM : integer := 16#C0A8#;
+ constant CFG_ETH_IPL : integer := 16#180A#;
+ constant CFG_ETH_ENM : integer := 16#020000#;
+ constant CFG_ETH_ENL : integer := 16#000008#;
+-- LEON2 memory controller
+ constant CFG_MCTRL_LEON2 : integer := 1;
+ constant CFG_MCTRL_RAM8BIT : integer := 1;
+ constant CFG_MCTRL_RAM16BIT : integer := 0;
+ constant CFG_MCTRL_5CS : integer := 0;
+ constant CFG_MCTRL_SDEN : integer := 1;
+ constant CFG_MCTRL_SEPBUS : integer := 0;
+ constant CFG_MCTRL_INVCLK : integer := 0;
+ constant CFG_MCTRL_SD64 : integer := 0;
+ constant CFG_MCTRL_PAGE : integer := 1 + 0;
+-- AHB status register
+ constant CFG_AHBSTAT : integer := 0;
+ constant CFG_AHBSTATN : integer := 1;
+-- AHB ROM
+ constant CFG_AHBROMEN : integer := 0;
+ constant CFG_AHBROPIP : integer := 0;
+ constant CFG_AHBRODDR : integer := 16#000#;
+ constant CFG_ROMADDR : integer := 16#000#;
+ constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
+-- AHB RAM
+ constant CFG_AHBRAMEN : integer := 0;
+ constant CFG_AHBRSZ : integer := 1;
+ constant CFG_AHBRADDR : integer := 16#A00#;
+-- Gaisler Ethernet core
+ constant CFG_GRETH : integer := 1;
+ constant CFG_GRETH1G : integer := 0;
+ constant CFG_ETH_FIFO : integer := 16;
+
+-- ATA interface
+ constant CFG_ATA : integer := 0;
+ constant CFG_ATAIO : integer := 16#0#;
+ constant CFG_ATAIRQ : integer := 0;
+ constant CFG_ATADMA : integer := 0;
+ constant CFG_ATAFIFO : integer := 8;
+
+-- CAN 2.0 interface
+ constant CFG_CAN : integer := 0;
+ constant CFG_CAN_NUM : integer := 1;
+ constant CFG_CANIO : integer := 16#0#;
+ constant CFG_CANIRQ : integer := 0;
+ constant CFG_CANSEPIRQ: integer := 0;
+ constant CFG_CAN_SYNCRST : integer := 0;
+ constant CFG_CANFT : integer := 0;
+
+-- GR USB 2.0 Device Controller
+ constant CFG_GRUSBDC : integer := 0;
+ constant CFG_GRUSBDC_AIFACE : integer := 0;
+ constant CFG_GRUSBDC_UIFACE : integer := 1;
+ constant CFG_GRUSBDC_DW : integer := 8;
+ constant CFG_GRUSBDC_NEPI : integer := 1;
+ constant CFG_GRUSBDC_NEPO : integer := 1;
+ constant CFG_GRUSBDC_I0 : integer := 1024;
+ constant CFG_GRUSBDC_I1 : integer := 1024;
+ constant CFG_GRUSBDC_I2 : integer := 1024;
+ constant CFG_GRUSBDC_I3 : integer := 1024;
+ constant CFG_GRUSBDC_I4 : integer := 1024;
+ constant CFG_GRUSBDC_I5 : integer := 1024;
+ constant CFG_GRUSBDC_I6 : integer := 1024;
+ constant CFG_GRUSBDC_I7 : integer := 1024;
+ constant CFG_GRUSBDC_I8 : integer := 1024;
+ constant CFG_GRUSBDC_I9 : integer := 1024;
+ constant CFG_GRUSBDC_I10 : integer := 1024;
+ constant CFG_GRUSBDC_I11 : integer := 1024;
+ constant CFG_GRUSBDC_I12 : integer := 1024;
+ constant CFG_GRUSBDC_I13 : integer := 1024;
+ constant CFG_GRUSBDC_I14 : integer := 1024;
+ constant CFG_GRUSBDC_I15 : integer := 1024;
+ constant CFG_GRUSBDC_O0 : integer := 1024;
+ constant CFG_GRUSBDC_O1 : integer := 1024;
+ constant CFG_GRUSBDC_O2 : integer := 1024;
+ constant CFG_GRUSBDC_O3 : integer := 1024;
+ constant CFG_GRUSBDC_O4 : integer := 1024;
+ constant CFG_GRUSBDC_O5 : integer := 1024;
+ constant CFG_GRUSBDC_O6 : integer := 1024;
+ constant CFG_GRUSBDC_O7 : integer := 1024;
+ constant CFG_GRUSBDC_O8 : integer := 1024;
+ constant CFG_GRUSBDC_O9 : integer := 1024;
+ constant CFG_GRUSBDC_O10 : integer := 1024;
+ constant CFG_GRUSBDC_O11 : integer := 1024;
+ constant CFG_GRUSBDC_O12 : integer := 1024;
+ constant CFG_GRUSBDC_O13 : integer := 1024;
+ constant CFG_GRUSBDC_O14 : integer := 1024;
+ constant CFG_GRUSBDC_O15 : integer := 1024;
+-- UART 1
+ constant CFG_UART1_ENABLE : integer := 1;
+ constant CFG_UART1_FIFO : integer := 4;
+
+-- UART 2
+ constant CFG_UART2_ENABLE : integer := 0;
+ constant CFG_UART2_FIFO : integer := 1;
+
+-- LEON3 interrupt controller
+ constant CFG_IRQ3_ENABLE : integer := 1;
+ constant CFG_IRQ3_NSEC : integer := 0;
+
+-- Modular timer
+ constant CFG_GPT_ENABLE : integer := 1;
+ constant CFG_GPT_NTIM : integer := (2);
+ constant CFG_GPT_SW : integer := (8);
+ constant CFG_GPT_TW : integer := (32);
+ constant CFG_GPT_IRQ : integer := (8);
+ constant CFG_GPT_SEPIRQ : integer := 1;
+ constant CFG_GPT_WDOGEN : integer := 0;
+ constant CFG_GPT_WDOG : integer := 16#0#;
+
+-- GPIO port
+ constant CFG_GRGPIO_ENABLE : integer := 1;
+ constant CFG_GRGPIO_IMASK : integer := 16#0000#;
+ constant CFG_GRGPIO_WIDTH : integer := (8);
+
+-- Spacewire interface
+ constant CFG_SPW_EN : integer := 0;
+ constant CFG_SPW_NUM : integer := 1;
+ constant CFG_SPW_AHBFIFO : integer := 4;
+ constant CFG_SPW_RXFIFO : integer := 16;
+ constant CFG_SPW_RMAP : integer := 0;
+ constant CFG_SPW_RMAPBUF : integer := 4;
+ constant CFG_SPW_RMAPCRC : integer := 0;
+ constant CFG_SPW_NETLIST : integer := 0;
+ constant CFG_SPW_FT : integer := 0;
+ constant CFG_SPW_GRSPW : integer := 2;
+ constant CFG_SPW_RXUNAL : integer := 0;
+ constant CFG_SPW_DMACHAN : integer := 1;
+ constant CFG_SPW_PORTS : integer := 1;
+ constant CFG_SPW_INPUT : integer := 2;
+ constant CFG_SPW_OUTPUT : integer := 0;
+ constant CFG_SPW_RTSAME : integer := 0;
+-- VGA and PS2/ interface
+ constant CFG_KBD_ENABLE : integer := 1;
+ constant CFG_VGA_ENABLE : integer := 0;
+ constant CFG_SVGA_ENABLE : integer := 1;
+
+-- GRLIB debugging
+ constant CFG_DUART : integer := 0;
+end;
--- /dev/null
+-- Technology and synthesis options
+ constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
+ constant CFG_MEMTECH : integer := CFG_RAM_TECH;
+ constant CFG_PADTECH : integer := CFG_PAD_TECH;
+ constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
+ constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
+
+-- Clock generator
+ constant CFG_CLKTECH : integer := CFG_CLK_TECH;
+ constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
+ constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
+ constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
+ constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
+ constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
+ constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
+
+-- LEON3 processor core
+ constant CFG_LEON3 : integer := CONFIG_LEON3;
+ constant CFG_NCPU : integer := CONFIG_PROC_NUM;
+ constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
+ constant CFG_V8 : integer := CFG_IU_V8;
+ constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
+ constant CFG_BP : integer := CONFIG_IU_BP;
+ constant CFG_SVT : integer := CONFIG_IU_SVT;
+ constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
+ constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
+ constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
+ constant CFG_PWD : integer := CONFIG_PWD*2;
+ constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
+ constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
+ constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
+ constant CFG_ISETS : integer := CFG_IU_ISETS;
+ constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
+ constant CFG_ILINE : integer := CFG_ILINE_SZ;
+ constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
+ constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
+ constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
+ constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
+ constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
+ constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
+ constant CFG_DSETS : integer := CFG_IU_DSETS;
+ constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
+ constant CFG_DLINE : integer := CFG_DLINE_SZ;
+ constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
+ constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
+ constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
+ constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
+ constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
+ constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
+ constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
+ constant CFG_MMUEN : integer := CONFIG_MMUEN;
+ constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
+ constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
+ constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
+ constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
+ constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
+ constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
+ constant CFG_ITBSZ : integer := CFG_DSU_ITB;
+ constant CFG_ATBSZ : integer := CFG_DSU_ATB;
+ constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
+ constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
+ constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
+ constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
+ constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
+ constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
+ constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
+ constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
+ constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
+
+-- AMBA settings
+ constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
+ constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
+ constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
+ constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
+ constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
+ constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
+ constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
+ constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
+
+-- DSU UART
+ constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
+
+-- JTAG based DSU interface
+ constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
+
+-- USB DSU
+ constant CFG_GRUSB_DCL : integer := CONFIG_GRUSB_DCL;
+ constant CFG_GRUSB_DCL_UIFACE : integer := CONFIG_GRUSB_DCL_UIFACE;
+ constant CFG_GRUSB_DCL_DW : integer := CONFIG_GRUSB_DCL_DW;
+
+-- Ethernet DSU
+ constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
+ constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
+ constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
+ constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
+ constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
+ constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
+
+-- LEON2 memory controller
+ constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
+ constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
+ constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
+ constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
+ constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
+ constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
+ constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
+ constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
+ constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
+
+-- AHB status register
+ constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
+ constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
+
+-- AHB ROM
+ constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
+ constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
+ constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
+ constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
+ constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
+
+-- AHB RAM
+ constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
+ constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
+ constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
+
+-- Gaisler Ethernet core
+ constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
+ constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
+ constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
+
+-- ATA interface
+ constant CFG_ATA : integer := CONFIG_ATA_ENABLE;
+ constant CFG_ATAIO : integer := 16#CONFIG_ATAIO#;
+ constant CFG_ATAIRQ : integer := CONFIG_ATAIRQ;
+ constant CFG_ATADMA : integer := CONFIG_ATA_MWDMA;
+ constant CFG_ATAFIFO : integer := CONFIG_ATA_FIFO;
+
+-- CAN 2.0 interface
+ constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
+ constant CFG_CAN_NUM : integer := CONFIG_CAN_NUM;
+ constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
+ constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
+ constant CFG_CANSEPIRQ: integer := CONFIG_CANSEPIRQ;
+ constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
+ constant CFG_CANFT : integer := CONFIG_CAN_FT;
+
+-- GR USB 2.0 Device Controller
+ constant CFG_GRUSBDC : integer := CONFIG_GRUSBDC_ENABLE;
+ constant CFG_GRUSBDC_AIFACE : integer := CONFIG_GRUSBDC_AIFACE;
+ constant CFG_GRUSBDC_UIFACE : integer := CONFIG_GRUSBDC_UIFACE;
+ constant CFG_GRUSBDC_DW : integer := CONFIG_GRUSBDC_DW;
+ constant CFG_GRUSBDC_NEPI : integer := CONFIG_GRUSBDC_NEPI;
+ constant CFG_GRUSBDC_NEPO : integer := CONFIG_GRUSBDC_NEPO;
+ constant CFG_GRUSBDC_I0 : integer := CONFIG_GRUSBDC_I0;
+ constant CFG_GRUSBDC_I1 : integer := CONFIG_GRUSBDC_I1;
+ constant CFG_GRUSBDC_I2 : integer := CONFIG_GRUSBDC_I2;
+ constant CFG_GRUSBDC_I3 : integer := CONFIG_GRUSBDC_I3;
+ constant CFG_GRUSBDC_I4 : integer := CONFIG_GRUSBDC_I4;
+ constant CFG_GRUSBDC_I5 : integer := CONFIG_GRUSBDC_I5;
+ constant CFG_GRUSBDC_I6 : integer := CONFIG_GRUSBDC_I6;
+ constant CFG_GRUSBDC_I7 : integer := CONFIG_GRUSBDC_I7;
+ constant CFG_GRUSBDC_I8 : integer := CONFIG_GRUSBDC_I8;
+ constant CFG_GRUSBDC_I9 : integer := CONFIG_GRUSBDC_I9;
+ constant CFG_GRUSBDC_I10 : integer := CONFIG_GRUSBDC_I10;
+ constant CFG_GRUSBDC_I11 : integer := CONFIG_GRUSBDC_I11;
+ constant CFG_GRUSBDC_I12 : integer := CONFIG_GRUSBDC_I12;
+ constant CFG_GRUSBDC_I13 : integer := CONFIG_GRUSBDC_I13;
+ constant CFG_GRUSBDC_I14 : integer := CONFIG_GRUSBDC_I14;
+ constant CFG_GRUSBDC_I15 : integer := CONFIG_GRUSBDC_I15;
+ constant CFG_GRUSBDC_O0 : integer := CONFIG_GRUSBDC_O0;
+ constant CFG_GRUSBDC_O1 : integer := CONFIG_GRUSBDC_O1;
+ constant CFG_GRUSBDC_O2 : integer := CONFIG_GRUSBDC_O2;
+ constant CFG_GRUSBDC_O3 : integer := CONFIG_GRUSBDC_O3;
+ constant CFG_GRUSBDC_O4 : integer := CONFIG_GRUSBDC_O4;
+ constant CFG_GRUSBDC_O5 : integer := CONFIG_GRUSBDC_O5;
+ constant CFG_GRUSBDC_O6 : integer := CONFIG_GRUSBDC_O6;
+ constant CFG_GRUSBDC_O7 : integer := CONFIG_GRUSBDC_O7;
+ constant CFG_GRUSBDC_O8 : integer := CONFIG_GRUSBDC_O8;
+ constant CFG_GRUSBDC_O9 : integer := CONFIG_GRUSBDC_O9;
+ constant CFG_GRUSBDC_O10 : integer := CONFIG_GRUSBDC_O10;
+ constant CFG_GRUSBDC_O11 : integer := CONFIG_GRUSBDC_O11;
+ constant CFG_GRUSBDC_O12 : integer := CONFIG_GRUSBDC_O12;
+ constant CFG_GRUSBDC_O13 : integer := CONFIG_GRUSBDC_O13;
+ constant CFG_GRUSBDC_O14 : integer := CONFIG_GRUSBDC_O14;
+ constant CFG_GRUSBDC_O15 : integer := CONFIG_GRUSBDC_O15;
+-- UART 1
+ constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
+ constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
+
+-- UART 2
+ constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE;
+ constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO;
+
+-- LEON3 interrupt controller
+ constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
+ constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
+
+-- Modular timer
+ constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
+ constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
+ constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
+ constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
+ constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
+ constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
+ constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
+ constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
+
+-- GPIO port
+ constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
+ constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
+ constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
+
+-- Spacewire interface
+ constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE;
+ constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM;
+ constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO;
+ constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO;
+ constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP;
+ constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF;
+ constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC;
+ constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST;
+ constant CFG_SPW_FT : integer := CONFIG_SPW_FT;
+ constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW;
+ constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL;
+ constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN;
+ constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS;
+ constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT;
+ constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT;
+ constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME;
+-- VGA and PS2/ interface
+ constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
+ constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
+ constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
+
+-- GRLIB debugging
+ constant CFG_DUART : integer := CONFIG_DEBUG_UART;
+
--- /dev/null
+#include "config.h"
+#include "tkconfig.h"
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench configuration
+-- Copyright (C) 2009 Aeroflex Gaisler
+------------------------------------------------------------------------------
+
+
+library techmap;
+use techmap.gencomp.all;
+
+package config is
+
+#include "config.vhd.h"
+
+end;
--- /dev/null
+# Synplicity, Inc. constraint file
+# /home/jiri/ibm/vhdl/grlib/boards/gr-xc3s-1500/default.sdc
+# Written on Thu May 11 15:07:16 2006
+# by Synplify Pro, 7.1.1 Scope Editor
+
+#
+# Clocks
+#
+#define_clock -name {clk} -freq 50.000 -route 5.0 -clockgroup default_clkgroup
+define_clock -name {rxclki} -freq 100.000 -route 2.0 -clockgroup rxclki_clkgroup
+define_clock -name {txclk} -freq 100.000 -route 2.0 -clockgroup txclk_clkgroup
+define_clock -name {erx_clk} -freq 25.000 -route 5.0 -clockgroup erx_clkgroup
+define_clock -name {etx_clk} -freq 25.000 -route 5.0 -clockgroup etx_clkgroup
+define_clock -name {usb_clkout} -freq 60.000 -route 4.0 -clockgroup usb_clkgroup
+define_clock -name {clk50} -freq 50.000 -route 4.0 -clockgroup vga_clkgroup
+define_clock -name {ethclk} -freq 25.000 -route 4.0 -clockgroup eth_clkgroup
+define_clock -name {clk3} -freq 25.000 -route 2.0 -clockgroup eth_clkgroup
+define_clock -name {leon3mp|video_clk} -freq 50.000 -route 2.0 -clockgroup video_clkgroup
+
+#
+# Inputs/Outputs
+#
+define_clock_delay -rise {clk3} -rise {vga_clkgen|clkgen65.clk0B_derived_clock} -false
+define_clock_delay -rise {vga_clkgen|clkgen65.clk0B_derived_clock} -rise {clk3} -false
+define_clock_delay -rise {leon3mp|clkgen0.xc3s_v.clk0B_derived_clock} -rise {leon3mp|clk50} -false
+define_clock_delay -rise {leon3mp|clk50} -rise {leon3mp|clkgen0.xc3s_v.clk0B_derived_clock} -false
+
+define_output_delay -disable -default 10.00 -improve 0.00 -route 0.00 -ref clk:r
+define_input_delay -disable -default 10.00 -improve 0.00 -route 0.00 -ref clk:r
+define_output_delay 8.00 -improve 0.00 -route 0.00 -ref {usb_clkout:r}
+define_input_delay 8.00 -improve 0.00 -route 0.00 -ref {usb_clkout:r}
+
+#
+# Registers
+#
+
+#
+# Multicycle Path
+#
+
+#
+# False Path
+#
+
+#
+# Attributes
+#
+define_global_attribute syn_useioff {1}
+
+#
+# Other Constraints
+#
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Synthesis
+#
+# CONFIG_SYN_INFERRED is not set
+# CONFIG_SYN_ALTERA is not set
+# CONFIG_SYN_AXCEL is not set
+# CONFIG_SYN_PROASIC is not set
+# CONFIG_SYN_PROASICPLUS is not set
+# CONFIG_SYN_PROASIC3 is not set
+# CONFIG_SYN_ATC18 is not set
+# CONFIG_SYN_IHP25 is not set
+# CONFIG_SYN_LATTICE is not set
+# CONFIG_SYN_RH_LIB18T is not set
+# CONFIG_SYN_RHUMC is not set
+# CONFIG_SYN_SPARTAN2 is not set
+CONFIG_SYN_SPARTAN3=y
+# CONFIG_SYN_VIRTEX is not set
+# CONFIG_SYN_VIRTEXE is not set
+# CONFIG_SYN_VIRTEX2 is not set
+# CONFIG_SYN_VIRTEX4 is not set
+# CONFIG_SYN_INFER_RAM is not set
+# CONFIG_SYN_INFER_PADS is not set
+# CONFIG_SYN_NO_ASYNC is not set
+
+#
+# Clock generation
+#
+# CONFIG_CLK_INFERRED is not set
+# CONFIG_CLK_HCLKBUF is not set
+# CONFIG_CLK_ALTDLL is not set
+# CONFIG_CLK_LATDLL is not set
+# CONFIG_CLK_LIB18T is not set
+# CONFIG_CLK_CLKDLL is not set
+CONFIG_CLK_DCM=y
+CONFIG_CLK_MUL=4
+CONFIG_CLK_DIV=5
+# CONFIG_PCI_CLKDLL is not set
+# CONFIG_CLK_NOFB is not set
+# CONFIG_PCI_SYSCLK is not set
+CONFIG_LEON3=y
+CONFIG_PROC_NUM=1
+
+#
+# Processor
+#
+
+#
+# Integer unit
+#
+CONFIG_IU_NWINDOWS=8
+CONFIG_IU_V8MULDIV=y
+# CONFIG_IU_MUL_LATENCY_4 is not set
+CONFIG_IU_MUL_LATENCY_5=y
+CONFIG_IU_MUL_MAC=y
+CONFIG_IU_SVT=y
+CONFIG_IU_LDELAY=1
+CONFIG_IU_WATCHPOINTS=2
+CONFIG_PWD=y
+CONFIG_IU_RSTADDR=00000
+
+#
+# Floating-point unit
+#
+# CONFIG_FPU_ENABLE is not set
+
+#
+# Cache system
+#
+CONFIG_ICACHE_ENABLE=y
+CONFIG_ICACHE_ASSO1=y
+# CONFIG_ICACHE_ASSO2 is not set
+# CONFIG_ICACHE_ASSO3 is not set
+# CONFIG_ICACHE_ASSO4 is not set
+# CONFIG_ICACHE_SZ1 is not set
+# CONFIG_ICACHE_SZ2 is not set
+# CONFIG_ICACHE_SZ4 is not set
+CONFIG_ICACHE_SZ8=y
+# CONFIG_ICACHE_SZ16 is not set
+# CONFIG_ICACHE_SZ32 is not set
+# CONFIG_ICACHE_SZ64 is not set
+# CONFIG_ICACHE_SZ128 is not set
+# CONFIG_ICACHE_SZ256 is not set
+# CONFIG_ICACHE_LZ16 is not set
+CONFIG_ICACHE_LZ32=y
+CONFIG_DCACHE_ENABLE=y
+CONFIG_DCACHE_ASSO1=y
+# CONFIG_DCACHE_ASSO2 is not set
+# CONFIG_DCACHE_ASSO3 is not set
+# CONFIG_DCACHE_ASSO4 is not set
+# CONFIG_DCACHE_SZ1 is not set
+# CONFIG_DCACHE_SZ2 is not set
+CONFIG_DCACHE_SZ4=y
+# CONFIG_DCACHE_SZ8 is not set
+# CONFIG_DCACHE_SZ16 is not set
+# CONFIG_DCACHE_SZ32 is not set
+# CONFIG_DCACHE_SZ64 is not set
+# CONFIG_DCACHE_SZ128 is not set
+# CONFIG_DCACHE_SZ256 is not set
+# CONFIG_DCACHE_LZ16 is not set
+CONFIG_DCACHE_LZ32=y
+CONFIG_DCACHE_SNOOP=y
+# CONFIG_DCACHE_SNOOP_FAST is not set
+CONFIG_CACHE_FIXED=00F3
+
+#
+# MMU
+#
+CONFIG_MMU_ENABLE=y
+# CONFIG_MMU_COMBINED is not set
+CONFIG_MMU_SPLIT=y
+CONFIG_MMU_REPARRAY=y
+# CONFIG_MMU_REPINCREMENT is not set
+# CONFIG_MMU_I2 is not set
+# CONFIG_MMU_I4 is not set
+CONFIG_MMU_I8=y
+# CONFIG_MMU_I16 is not set
+# CONFIG_MMU_I32 is not set
+# CONFIG_MMU_D2 is not set
+# CONFIG_MMU_D4 is not set
+CONFIG_MMU_D8=y
+# CONFIG_MMU_D16 is not set
+# CONFIG_MMU_D32 is not set
+
+#
+# Debug Support Unit
+#
+CONFIG_DSU_ENABLE=y
+CONFIG_DSU_ITRACE=y
+# CONFIG_DSU_ITRACESZ1 is not set
+CONFIG_DSU_ITRACESZ2=y
+# CONFIG_DSU_ITRACESZ4 is not set
+# CONFIG_DSU_ITRACESZ8 is not set
+# CONFIG_DSU_ITRACESZ16 is not set
+CONFIG_DSU_ATRACE=y
+# CONFIG_DSU_ATRACESZ1 is not set
+CONFIG_DSU_ATRACESZ2=y
+# CONFIG_DSU_ATRACESZ4 is not set
+# CONFIG_DSU_ATRACESZ8 is not set
+# CONFIG_DSU_ATRACESZ16 is not set
+
+#
+# VHDL debug settings
+#
+# CONFIG_IU_DISAS is not set
+# CONFIG_DEBUG_PC32 is not set
+
+#
+# AMBA configuration
+#
+CONFIG_AHB_DEFMST=0
+CONFIG_AHB_RROBIN=y
+# CONFIG_AHB_SPLIT is not set
+CONFIG_AHB_IOADDR=FFF
+CONFIG_APB_HADDR=800
+
+#
+# Debug Link
+#
+CONFIG_DSU_UART=y
+CONFIG_DSU_JTAG=y
+# CONFIG_USBDCL is not set
+# CONFIG_DSU_ETH is not set
+
+#
+# Peripherals
+#
+
+#
+# Memory controller
+#
+
+#
+# Leon2 memory controller
+#
+CONFIG_MCTRL_LEON2=y
+CONFIG_MCTRL_8BIT=y
+# CONFIG_MCTRL_16BIT is not set
+# CONFIG_MCTRL_5CS is not set
+CONFIG_MCTRL_SDRAM=y
+# CONFIG_MCTRL_SDRAM_SEPBUS is not set
+CONFIG_AHBSTAT_ENABLE=y
+CONFIG_AHBSTAT_NFTSLV=1
+
+#
+# On-chip RAM/ROM
+#
+# CONFIG_AHBROM_ENABLE is not set
+# CONFIG_AHBRAM_ENABLE is not set
+
+#
+# Ethernet
+#
+CONFIG_GRETH_ENABLE=y
+# CONFIG_GRETH_FIFO4 is not set
+# CONFIG_GRETH_FIFO8 is not set
+# CONFIG_GRETH_FIFO16 is not set
+CONFIG_GRETH_FIFO32=y
+# CONFIG_GRETH_FIFO64 is not set
+
+#
+# IDE Disk controller
+#
+CONFIG_ATA_ENABLE=y
+CONFIG_ATAIO=A00
+CONFIG_ATAIRQ=10
+
+#
+# CAN
+#
+# CONFIG_CAN_ENABLE is not set
+
+#
+# UART, timer, I/O port and interrupt controller
+#
+CONFIG_UART1_ENABLE=y
+# CONFIG_UA1_FIFO1 is not set
+# CONFIG_UA1_FIFO2 is not set
+# CONFIG_UA1_FIFO4 is not set
+CONFIG_UA1_FIFO8=y
+# CONFIG_UA1_FIFO16 is not set
+# CONFIG_UA1_FIFO32 is not set
+CONFIG_IRQ3_ENABLE=y
+CONFIG_GPT_ENABLE=y
+CONFIG_GPT_NTIM=2
+CONFIG_GPT_SW=8
+CONFIG_GPT_TW=32
+CONFIG_GPT_IRQ=8
+CONFIG_GPT_SEPIRQ=y
+# CONFIG_GPT_WDOGEN is not set
+CONFIG_GRGPIO_ENABLE=y
+CONFIG_GRGPIO_WIDTH=18
+CONFIG_GRGPIO_IMASK=FFF0
+
+#
+# Spacewire
+#
+# CONFIG_SPW_ENABLE is not set
+
+#
+# Keybord and VGA interface
+#
+CONFIG_KBD_ENABLE=y
+CONFIG_VGA_ENABLE=y
+
+#
+# VHDL Debugging
+#
+# CONFIG_DEBUG_UART is not set
--- /dev/null
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(G17.1142451)\r/Parent 9839 0 R \r/Prev 9853 0 R \r/Next 9851 0 R \r>> \rendobj\r9853 0 obj\r<< \r/Title (20.5.7 Arbitration lost capture register)\r/Dest (G17.1142418)\r/Parent 9839 0 R \r/Prev 9854 0 R \r/Next 9852 0 R \r>> \rendobj\r9854 0 obj\r<< \r/Title (20.5.6 Interrupt enable register)\r/Dest (G17.1142329)\r/Parent 9839 0 R \r/Prev 9855 0 R \r/Next 9853 0 R \r>> \rendobj\r9855 0 obj\r<< \r/Title (20.5.5 Interrupt register)\r/Dest (G17.1142264)\r/Parent 9839 0 R \r/Prev 9856 0 R \r/Next 9854 0 R \r>> \rendobj\r9856 0 obj\r<< \r/Title (20.5.4 Status register)\r/Dest (G17.1142197)\r/Parent 9839 0 R \r/Prev 9857 0 R \r/Next 9855 0 R \r>> \rendobj\r9857 0 obj\r<< \r/Title (20.5.3 Command register)\r/Dest (G17.1142128)\r/Parent 9839 0 R \r/Prev 9858 0 R \r/Next 9856 0 R \r>> \rendobj\r9858 0 obj\r<< \r/Title (20.5.2 Mode register)\r/Dest (G17.1142124)\r/Parent 9839 0 R \r/Prev 9844 0 R \r/Next 9857 0 R \r>> \rendobj\r9859 0 obj\r<< \r/Title (20.3 AHB interface)\r/Dest (G17.1140671)\r/Parent 9829 0 R \r/Prev 9868 0 R \r/Next 9843 0 R \r>> \rendobj\r9860 0 obj\r<< \r/Title (20.4.1 BasicCAN register map)\r/Dest (G17.1145601)\r/Parent 9843 0 R \r/Next 9867 0 R \r>> \rendobj\r9861 0 obj\r<< \r/Title (20.4.8 Acceptance filter)\r/Dest (G17.1141565)\r/Parent 9843 0 R \r/Prev 9862 0 R \r>> \rendobj\r9862 0 obj\r<< \r/Title (20.4.7 Receive buffer)\r/Dest (G17.1141563)\r/Parent 9843 0 R \r/Prev 9863 0 R \r/Next 9861 0 R \r>> \rendobj\r9863 0 obj\r<< \r/Title (20.4.6 Transmit buffer)\r/Dest (G17.1141298)\r/Parent 9843 0 R \r/Prev 9864 0 R \r/Next 9862 0 R \r>> \rendobj\r9864 0 obj\r<< \r/Title (20.4.5 Interrupt register)\r/Dest (G17.1141230)\r/Parent 9843 0 R \r/Prev 9865 0 R \r/Next 9863 0 R \r>> \rendobj\r9865 0 obj\r<< \r/Title (20.4.4 Status register)\r/Dest (G17.1141162)\r/Parent 9843 0 R \r/Prev 9866 0 R \r/Next 9864 0 R \r>> \rendobj\r9866 0 obj\r<< \r/Title (20.4.3 Command register)\r/Dest (G17.1141095)\r/Parent 9843 0 R \r/Prev 9867 0 R \r/Next 9865 0 R \r>> \rendobj\r9867 0 obj\r<< \r/Title (20.4.2 Control register)\r/Dest (G17.1145603)\r/Parent 9843 0 R \r/Prev 9860 0 R \r/Next 9866 0 R \r>> \rendobj\r9868 0 obj\r<< \r/Title (20.2 Opencores CAN controller overview)\r/Dest (G17.1140667)\r/Parent 9829 0 R \r/Prev 9831 0 R \r/Next 9859 0 R \r>> \rendobj\r9869 0 obj\r<< \r/Title (18 AHBJTAG - JTAG Debug Link with AHB Master Interface)\r/Dest (G15.966345)\r/Parent 9827 0 R \r/Prev 9897 0 R \r/Next 9830 0 R \r/First 9898 0 R \r/Last 9899 0 R \r/Count -8 \r>> \rendobj\r9870 0 obj\r<< \r/Title (19.1 Overview)\r/Dest (G16.1011047)\r/Parent 9830 0 R \r/Next 9889 0 R \r>> \rendobj\r9871 0 obj\r<< \r/Title (19.14 Instantiation)\r/Dest (G16.1017661)\r/Parent 9830 0 R \r/Prev 9872 0 R \r>> \rendobj\r9872 0 obj\r<< \r/Title (19.13 Library dependencies)\r/Dest (G16.1017799)\r/Parent 9830 0 R \r/Prev 9873 0 R \r/Next 9871 0 R \r>> \rendobj\r9873 0 obj\r<< \r/Title (19.12 Signal descriptions)\r/Dest (G16.1024974)\r/Parent 9830 0 R \r/Prev 9874 0 R \r/Next 9872 0 R \r>> \rendobj\r9874 0 obj\r<< \r/Title (19.11 Configuration options)\r/Dest (G16.1018226)\r/Parent 9830 0 R \r/Prev 9875 0 R \r/Next 9873 0 R \r>> \rendobj\r9875 0 obj\r<< \r/Title (19.10 Vendor and device identifiers)\r/Dest (G16.1026285)\r/Parent 9830 0 R \r/Prev 9876 0 R \r/Next 9874 0 R \r>> \rendobj\r9876 0 obj\r<< \r/Title (19.9 Registers)\r/Dest (G16.1026001)\r/Parent 9830 0 R \r/Prev 9877 0 R \r/Next 9875 0 R \r>> \rendobj\r9877 0 obj\r<< \r/Title (19.8 Software drivers)\r/Dest (G16.1026462)\r/Parent 9830 0 R \r/Prev 9878 0 R \r/Next 9876 0 R \r>> \rendobj\r9878 0 obj\r<< \r/Title (19.7 Media Independent Interfaces)\r/Dest (G16.1025066)\r/Parent 9830 0 R \r/Prev 9879 0 R \r/Next 9877 0 R \r>> \rendobj\r9879 0 obj\r<< \r/Title (19.6 Ethernet Debug Communication Link \(EDCL\))\r/Dest (G16.1022973)\r/Parent 9830 0 R \r/Prev 9880 0 R \r/Next 9878 0 R \r/First 9881 0 R \r/Last 9882 0 R \r/Count -2 \r>> \rendobj\r9880 0 obj\r<< \r/Title (19.5 MDIO Interface)\r/Dest (G16.1023731)\r/Parent 9830 0 R \r/Prev 9883 0 R \r/Next 9879 0 R \r>> \rendobj\r9881 0 obj\r<< \r/Title (19.6.1 Operation)\r/Dest (G16.1023827)\r/Parent 9879 0 R \r/Next 9882 0 R \r>> \rendobj\r9882 0 obj\r<< \r/Title (19.6.2 EDCL protocols)\r/Dest (G16.1023843)\r/Parent 9879 0 R \r/Prev 9881 0 R \r>> \rendobj\r9883 0 obj\r<< \r/Title (19.4 Rx DMA interface)\r/Dest (G16.1023510)\r/Parent 9830 0 R \r/Prev 9884 0 R \r/Next 9880 0 R \r/First 9885 0 R \r/Last 9886 0 R \r/Count -4 \r>> \rendobj\r9884 0 obj\r<< \r/Title (19.3 Tx DMA interface)\r/Dest (G16.1022971)\r/Parent 9830 0 R \r/Prev 9889 0 R \r/Next 9883 0 R \r/First 9890 0 R \r/Last 9891 0 R \r/Count -4 \r>> \rendobj\r9885 0 obj\r<< \r/Title (19.4.1 Setting up descriptors)\r/Dest (G16.1023706)\r/Parent 9883 0 R \r/Next 9888 0 R \r>> \rendobj\r9886 0 obj\r<< \r/Title (19.4.4 Reception with AHB errors)\r/Dest (G16.1023783)\r/Parent 9883 0 R \r/Prev 9887 0 R \r>> \rendobj\r9887 0 obj\r<< \r/Title (19.4.3 Descriptor handling after reception)\r/Dest (G16.1023752)\r/Parent 9883 0 R \r/Prev 9888 0 R \r/Next 9886 0 R \r>> \rendobj\r9888 0 obj\r<< \r/Title (19.4.2 Starting reception)\r/Dest (G16.1023728)\r/Parent 9883 0 R \r/Prev 9885 0 R \r/Next 9887 0 R \r>> \rendobj\r9889 0 obj\r<< \r/Title (19.2 Operation)\r/Dest (G16.1022970)\r/Parent 9830 0 R \r/Prev 9870 0 R \r/Next 9884 0 R \r/First 9894 0 R \r/Last 9895 0 R \r/Count -3 \r>> \rendobj\r9890 0 obj\r<< \r/Title (19.3.1 Setting up a descriptor.)\r/Dest (G16.1023518)\r/Parent 9884 0 R \r/Next 9893 0 R \r>> \rendobj\r9891 0 obj\r<< \r/Title (19.3.4 Setting up the data for transmission)\r/Dest (G16.1023721)\r/Parent 9884 0 R \r/Prev 9892 0 R \r>> \rendobj\r9892 0 obj\r<< \r/Title (19.3.3 Descriptor handling after transmission)\r/Dest (G16.1023670)\r/Parent 9884 0 R \r/Prev 9893 0 R \r/Next 9891 0 R \r>> \rendobj\r9893 0 obj\r<< \r/Title (19.3.2 Starting transmissions)\r/Dest (G16.1023593)\r/Parent 9884 0 R \r/Prev 9890 0 R \r/Next 9892 0 R \r>> \rendobj\r9894 0 obj\r<< \r/Title (19.2.1 System overview)\r/Dest (G16.1018225)\r/Parent 9889 0 R \r/Next 9896 0 R \r>> \rendobj\r9895 0 obj\r<< \r/Title (19.2.3 Hardware requirements)\r/Dest (G16.1023288)\r/Parent 9889 0 R \r/Prev 9896 0 R \r>> \rendobj\r9896 0 obj\r<< \r/Title (19.2.2 Protocol support)\r/Dest (G16.1023386)\r/Parent 9889 0 R \r/Prev 9894 0 R \r/Next 9895 0 R \r>> \rendobj\r9897 0 obj\r<< \r/Title (17 AHBUART- AMBA AHB Serial Debug Interface)\r/Dest (G14.1026426)\r/Parent 9827 0 R \r/Prev 9907 0 R \r/Next 9869 0 R \r/First 9908 0 R \r/Last 9909 0 R \r/Count -8 \r>> \rendobj\r9898 0 obj\r<< \r/Title (18.1 Overview)\r/Dest (G15.1032167)\r/Parent 9869 0 R \r/Next 9905 0 R \r>> \rendobj\r9899 0 obj\r<< \r/Title (18.8 Instantiation)\r/Dest (G15.1056390)\r/Parent 9869 0 R \r/Prev 9900 0 R \r>> \rendobj\r9900 0 obj\r<< \r/Title (18.7 Library dependencies)\r/Dest (G15.1056351)\r/Parent 9869 0 R \r/Prev 9901 0 R \r/Next 9899 0 R \r>> \rendobj\r9901 0 obj\r<< \r/Title (18.6 Signal descriptions)\r/Dest (G15.1057067)\r/Parent 9869 0 R \r/Prev 9902 0 R \r/Next 9900 0 R \r>> \rendobj\r9902 0 obj\r<< \r/Title (18.5 Configuration options)\r/Dest (G15.1055627)\r/Parent 9869 0 R \r/Prev 9903 0 R \r/Next 9901 0 R \r>> \rendobj\r9903 0 obj\r<< \r/Title (18.4 Vendor and device identifiers)\r/Dest (G15.1055625)\r/Parent 9869 0 R \r/Prev 9904 0 R \r/Next 9902 0 R \r>> \rendobj\r9904 0 obj\r<< \r/Title (18.3 Registers)\r/Dest (G15.1055623)\r/Parent 9869 0 R \r/Prev 9905 0 R \r/Next 9903 0 R \r>> \rendobj\r9905 0 obj\r<< \r/Title (18.2 Operation)\r/Dest (G15.1055582)\r/Parent 9869 0 R \r/Prev 9898 0 R \r/Next 9904 0 R \r/First 9906 0 R \r/Last 9906 0 R \r/Count -1 \r>> \rendobj\r9906 0 obj\r<< \r/Title (18.2.1 Transmission protocol)\r/Dest (G15.1055583)\r/Parent 9905 0 R \r>> \rendobj\r9907 0 obj\r<< \r/Title (16 APBVGA - VGA controller with APB interface)\r/Dest (G13.1080710)\r/Parent 9827 0 R \r/Prev 9918 0 R \r/Next 9897 0 R \r/First 9919 0 R \r/Last 9920 0 R \r/Count -8 \r>> \rendobj\r9908 0 obj\r<< \r/Title (17.1 Overview)\r/Dest (G14.1026404)\r/Parent 9897 0 R \r/Next 9915 0 R \r>> \rendobj\r9909 0 obj\r<< \r/Title (17.8 Instantiation)\r/Dest (G14.1063689)\r/Parent 9897 0 R \r/Prev 9910 0 R \r>> \rendobj\r9910 0 obj\r<< \r/Title (17.7 Library dependencies)\r/Dest (G14.1063650)\r/Parent 9897 0 R \r/Prev 9911 0 R \r/Next 9909 0 R \r>> \rendobj\r9911 0 obj\r<< \r/Title (17.6 Signal descriptions)\r/Dest (G14.1063499)\r/Parent 9897 0 R \r/Prev 9912 0 R \r/Next 9910 0 R \r>> \rendobj\r9912 0 obj\r<< \r/Title (17.5 Configuration options)\r/Dest (G14.1063444)\r/Parent 9897 0 R \r/Prev 9913 0 R \r/Next 9911 0 R \r>> \rendobj\r9913 0 obj\r<< \r/Title (17.4 Vendor and device identifiers)\r/Dest (G14.1063442)\r/Parent 9897 0 R \r/Prev 9914 0 R \r/Next 9912 0 R \r>> \rendobj\r9914 0 obj\r<< \r/Title (17.3 Registers)\r/Dest (G14.1063353)\r/Parent 9897 0 R \r/Prev 9915 0 R \r/Next 9913 0 R \r>> \rendobj\r9915 0 obj\r<< \r/Title (17.2 Operation)\r/Dest (G14.1063225)\r/Parent 9897 0 R \r/Prev 9908 0 R \r/Next 9914 0 R \r/First 9916 0 R \r/Last 9917 0 R \r/Count -2 \r>> \rendobj\r9916 0 obj\r<< \r/Title (17.2.1 Transmission protocol)\r/Dest (G14.1063226)\r/Parent 9915 0 R \r/Next 9917 0 R \r>> \rendobj\r9917 0 obj\r<< \r/Title (17.2.2 Baud rate generation)\r/Dest (G14.1063348)\r/Parent 9915 0 R \r/Prev 9916 0 R \r>> \rendobj\r9918 0 obj\r<< \r/Title (15 APBPS2 - PS/2 keyboard with APB interface)\r/Dest (G12.1078908)\r/Parent 9827 0 R \r/Prev 9930 0 R \r/Next 9907 0 R \r/First 9931 0 R \r/Last 9932 0 R \r/Count -12 \r>> \rendobj\r9919 0 obj\r<< \r/Title (16.1 Introduction)\r/Dest (G13.1059227)\r/Parent 9907 0 R \r/Next 9926 0 R \r>> \rendobj\r9920 0 obj\r<< \r/Title (16.8 Instantiation)\r/Dest (G13.1080507)\r/Parent 9907 0 R \r/Prev 9921 0 R \r>> \rendobj\r9921 0 obj\r<< \r/Title (16.7 Library dependencies)\r/Dest (G13.1080451)\r/Parent 9907 0 R \r/Prev 9922 0 R \r/Next 9920 0 R \r>> \rendobj\r9922 0 obj\r<< \r/Title (16.6 Signal descriptions)\r/Dest (G13.1080696)\r/Parent 9907 0 R \r/Prev 9923 0 R \r/Next 9921 0 R \r>> \rendobj\r9923 0 obj\r<< \r/Title (16.5 Configuration options)\r/Dest (G13.1082729)\r/Parent 9907 0 R \r/Prev 9924 0 R \r/Next 9922 0 R \r>> \rendobj\r9924 0 obj\r<< \r/Title (16.4 Vendor and device identifiers)\r/Dest (G13.1082949)\r/Parent 9907 0 R \r/Prev 9925 0 R \r/Next 9923 0 R \r>> \rendobj\r9925 0 obj\r<< \r/Title (16.3 Registers)\r/Dest (G13.1082731)\r/Parent 9907 0 R \r/Prev 9926 0 R \r/Next 9924 0 R \r/First 9927 0 R \r/Last 9928 0 R \r/Count -3 \r>> \rendobj\r9926 0 obj\r<< \r/Title (16.2 Operation)\r/Dest (G13.1080556)\r/Parent 9907 0 R \r/Prev 9919 0 R \r/Next 9925 0 R \r>> \rendobj\r9927 0 obj\r<< \r/Title (16.3.1 VGA Data Register)\r/Dest (G13.1082773)\r/Parent 9925 0 R \r/Next 9929 0 R \r>> \rendobj\r9928 0 obj\r<< \r/Title (16.3.3 VGA Foreground Color)\r/Dest (G13.1082944)\r/Parent 9925 0 R \r/Prev 9929 0 R \r>> \rendobj\r9929 0 obj\r<< \r/Title (16.3.2 VGA Background Color)\r/Dest (G13.1082858)\r/Parent 9925 0 R \r/Prev 9927 0 R \r/Next 9928 0 R \r>> \rendobj\r9930 0 obj\r<< \r/Title (14 GRGPIO - General Purpose I/O Port)\r/Dest (G11.966345)\r/Parent 9827 0 R \r/Prev 9947 0 R \r/Next 9918 0 R \r/First 9948 0 R \r/Last 9949 0 R \r/Count -9 \r>> \rendobj\r9931 0 obj\r<< \r/Title (15.1 Introduction)\r/Dest (G12.1082804)\r/Parent 9918 0 R \r/Next 9946 0 R \r>> \rendobj\r9932 0 obj\r<< \r/Title (15.12 Keyboard commands)\r/Dest (G12.1082205)\r/Parent 9918 0 R \r/Prev 9933 0 R \r>> \rendobj\r9933 0 obj\r<< \r/Title (15.11 Keboard scan codes)\r/Dest (G12.1081994)\r/Parent 9918 0 R \r/Prev 9934 0 R \r/Next 9932 0 R \r>> \rendobj\r9934 0 obj\r<< \r/Title (15.10 Instantiation)\r/Dest (G12.1079974)\r/Parent 9918 0 R \r/Prev 9935 0 R \r/Next 9933 0 R \r>> \rendobj\r9935 0 obj\r<< \r/Title (15.9 Library dependencies)\r/Dest (G12.1080572)\r/Parent 9918 0 R \r/Prev 9936 0 R \r/Next 9934 0 R \r>> \rendobj\r9936 0 obj\r<< \r/Title (15.8 Signal descriptions)\r/Dest (G12.1084732)\r/Parent 9918 0 R \r/Prev 9937 0 R \r/Next 9935 0 R \r>> \rendobj\r9937 0 obj\r<< \r/Title (15.7 Configuration options)\r/Dest (G12.1084817)\r/Parent 9918 0 R \r/Prev 9938 0 R \r/Next 9936 0 R \r>> \rendobj\r9938 0 obj\r<< \r/Title (15.6 Vendor and device identifiers)\r/Dest (G12.1084819)\r/Parent 9918 0 R \r/Prev 9939 0 R \r/Next 9937 0 R \r>> \rendobj\r9939 0 obj\r<< \r/Title (15.5 Registers)\r/Dest (G12.1079763)\r/Parent 9918 0 R \r/Prev 9940 0 R \r/Next 9938 0 R \r/First 9941 0 R \r/Last 9942 0 R \r/Count -4 \r>> \rendobj\r9940 0 obj\r<< \r/Title (15.4 Clock generation)\r/Dest (G12.1083662)\r/Parent 9918 0 R \r/Prev 9945 0 R \r/Next 9939 0 R \r>> \rendobj\r9941 0 obj\r<< \r/Title (15.5.1 PS/2 Data Register)\r/Dest (G12.1080697)\r/Parent 9939 0 R \r/Next 9944 0 R \r>> \rendobj\r9942 0 obj\r<< \r/Title (15.5.4 PS/2 Timer Reload Register)\r/Dest (G12.1083476)\r/Parent 9939 0 R \r/Prev 9943 0 R \r>> \rendobj\r9943 0 obj\r<< \r/Title (15.5.3 PS/2 Control Register)\r/Dest (G12.1079765)\r/Parent 9939 0 R \r/Prev 9944 0 R \r/Next 9942 0 R \r>> \rendobj\r9944 0 obj\r<< \r/Title (15.5.2 PS/2 Status Register)\r/Dest (G12.1080557)\r/Parent 9939 0 R \r/Prev 9941 0 R \r/Next 9943 0 R \r>> \rendobj\r9945 0 obj\r<< \r/Title (15.3 Transmitter operations)\r/Dest (G12.1079978)\r/Parent 9918 0 R \r/Prev 9946 0 R \r/Next 9940 0 R \r>> \rendobj\r9946 0 obj\r<< \r/Title (15.2 Receiver operation)\r/Dest (G12.1078909)\r/Parent 9918 0 R \r/Prev 9931 0 R \r/Next 9945 0 R \r>> \rendobj\r9947 0 obj\r<< \r/Title (13 GPTIMER - General Purpose Timer Unit)\r/Dest (G10.1016816)\r/Parent 9827 0 R \r/Prev 9957 0 R \r/Next 9930 0 R \r/First 9958 0 R \r/Last 9959 0 R \r/Count -8 \r>> \rendobj\r9948 0 obj\r<< \r/Title (14.1 Overview)\r/Dest (G11.1011047)\r/Parent 9930 0 R \r/Next 9956 0 R \r>> \rendobj\r9949 0 obj\r<< \r/Title (14.9 Instantiation)\r/Dest (G11.1041089)\r/Parent 9930 0 R \r/Prev 9950 0 R \r>> \rendobj\r9950 0 obj\r<< \r/Title (14.8 Component declaration)\r/Dest (G11.1041063)\r/Parent 9930 0 R \r/Prev 9951 0 R \r/Next 9949 0 R \r>> \rendobj\r9951 0 obj\r<< \r/Title (14.7 Library dependencies)\r/Dest (G11.1041024)\r/Parent 9930 0 R \r/Prev 9952 0 R \r/Next 9950 0 R \r>> \rendobj\r9952 0 obj\r<< \r/Title (14.6 Signal descriptions)\r/Dest (G11.1040652)\r/Parent 9930 0 R \r/Prev 9953 0 R \r/Next 9951 0 R \r>> \rendobj\r9953 0 obj\r<< \r/Title (14.5 Configuration options)\r/Dest (G11.1040581)\r/Parent 9930 0 R \r/Prev 9954 0 R \r/Next 9952 0 R \r>> \rendobj\r9954 0 obj\r<< \r/Title (14.4 Vendor and device identifiers)\r/Dest (G11.1040579)\r/Parent 9930 0 R \r/Prev 9955 0 R \r/Next 9953 0 R \r>> \rendobj\r9955 0 obj\r<< \r/Title (14.3 Registers)\r/Dest (G11.1040443)\r/Parent 9930 0 R \r/Prev 9956 0 R \r/Next 9954 0 R \r>> \rendobj\r9956 0 obj\r<< \r/Title (14.2 Operation)\r/Dest (G11.1040440)\r/Parent 9930 0 R \r/Prev 9948 0 R \r/Next 9955 0 R \r>> \rendobj\r9957 0 obj\r<< \r/Title (12 APBUART - AMBA APB UART Serial Interface)\r/Dest (G9.966345)\r/Parent 9827 0 R \r/Prev 9966 0 R \r/Next 9947 0 R \r/First 9967 0 R \r/Last 9968 0 R \r/Count -9 \r>> \rendobj\r9958 0 obj\r<< \r/Title (13.1 Overview)\r/Dest (G10.1016817)\r/Parent 9947 0 R \r/Next 9965 0 R \r>> \rendobj\r9959 0 obj\r<< \r/Title (13.8 Instantiation)\r/Dest (G10.1056183)\r/Parent 9947 0 R \r/Prev 9960 0 R \r>> \rendobj\r9960 0 obj\r<< \r/Title (13.7 Library dependencies)\r/Dest (G10.1056144)\r/Parent 9947 0 R \r/Prev 9961 0 R \r/Next 9959 0 R \r>> \rendobj\r9961 0 obj\r<< \r/Title (13.6 Signal descriptions)\r/Dest (G10.1055826)\r/Parent 9947 0 R \r/Prev 9962 0 R \r/Next 9960 0 R \r>> \rendobj\r9962 0 obj\r<< \r/Title (13.5 Configuration options)\r/Dest (G10.1055730)\r/Parent 9947 0 R \r/Prev 9963 0 R \r/Next 9961 0 R \r>> \rendobj\r9963 0 obj\r<< \r/Title (13.4 Vendor and device identifiers)\r/Dest (G10.1055728)\r/Parent 9947 0 R \r/Prev 9964 0 R \r/Next 9962 0 R \r>> \rendobj\r9964 0 obj\r<< \r/Title (13.3 Registers)\r/Dest (G10.1055530)\r/Parent 9947 0 R \r/Prev 9965 0 R \r/Next 9963 0 R \r>> \rendobj\r9965 0 obj\r<< \r/Title (13.2 Operation)\r/Dest (G10.1055523)\r/Parent 9947 0 R \r/Prev 9958 0 R \r/Next 9964 0 R \r>> \rendobj\r9966 0 obj\r<< \r/Title (11 AHBSTAT - AHB Status Registers)\r/Dest (G8.966345)\r/Parent 9827 0 R \r/Prev 9984 0 R \r/Next 9957 0 R \r/First 9985 0 R \r/Last 9986 0 R \r/Count -8 \r>> \rendobj\r9967 0 obj\r<< \r/Title (12.1 Overview)\r/Dest (G9.1018126)\r/Parent 9957 0 R \r/Next 9979 0 R \r>> \rendobj\r9968 0 obj\r<< \r/Title (12.9 Instantiation)\r/Dest (G9.1090173)\r/Parent 9957 0 R \r/Prev 9969 0 R \r>> \rendobj\r9969 0 obj\r<< \r/Title (12.8 Library dependencies)\r/Dest (G9.1090134)\r/Parent 9957 0 R \r/Prev 9970 0 R \r/Next 9968 0 R \r>> \rendobj\r9970 0 obj\r<< \r/Title (12.7 Signal descriptions)\r/Dest (G9.1090003)\r/Parent 9957 0 R \r/Prev 9971 0 R \r/Next 9969 0 R \r>> \rendobj\r9971 0 obj\r<< \r/Title (12.6 Configuration options)\r/Dest (G9.1089916)\r/Parent 9957 0 R \r/Prev 9972 0 R \r/Next 9970 0 R \r>> \rendobj\r9972 0 obj\r<< \r/Title (12.5 Vendor and device identifiers)\r/Dest (G9.1089914)\r/Parent 9957 0 R \r/Prev 9973 0 R \r/Next 9971 0 R \r>> \rendobj\r9973 0 obj\r<< \r/Title (12.4 Registers)\r/Dest (G9.1089736)\r/Parent 9957 0 R \r/Prev 9974 0 R \r/Next 9972 0 R \r/First 9975 0 R \r/Last 9976 0 R \r/Count -4 \r>> \rendobj\r9974 0 obj\r<< \r/Title (12.3 Baud-rate generation)\r/Dest (G9.1089729)\r/Parent 9957 0 R \r/Prev 9979 0 R \r/Next 9973 0 R \r/First 9980 0 R \r/Last 9981 0 R \r/Count -2 \r>> \rendobj\r9975 0 obj\r<< \r/Title (12.4.1 UART Data Register)\r/Dest (G9.1089777)\r/Parent 9973 0 R \r/Next 9978 0 R \r>> \rendobj\r9976 0 obj\r<< \r/Title (12.4.4 UART Scaler Register)\r/Dest (G9.1089913)\r/Parent 9973 0 R \r/Prev 9977 0 R \r>> \rendobj\r9977 0 obj\r<< \r/Title (12.4.3 UART Control Register)\r/Dest (G9.1089887)\r/Parent 9973 0 R \r/Prev 9978 0 R \r/Next 9976 0 R \r>> \rendobj\r9978 0 obj\r<< \r/Title (12.4.2 UART Status Register)\r/Dest (G9.1089831)\r/Parent 9973 0 R \r/Prev 9975 0 R \r/Next 9977 0 R \r>> \rendobj\r9979 0 obj\r<< \r/Title (12.2 Operation)\r/Dest (G9.1089639)\r/Parent 9957 0 R \r/Prev 9967 0 R \r/Next 9974 0 R \r/First 9982 0 R \r/Last 9983 0 R \r/Count -2 \r>> \rendobj\r9980 0 obj\r<< \r/Title (12.3.1 Loop back mode)\r/Dest (G9.1089731)\r/Parent 9974 0 R \r/Next 9981 0 R \r>> \rendobj\r9981 0 obj\r<< \r/Title (12.3.2 Interrupt generation)\r/Dest (G9.1089733)\r/Parent 9974 0 R \r/Prev 9980 0 R \r>> \rendobj\r9982 0 obj\r<< \r/Title (12.2.1 Transmitter operation)\r/Dest (G9.1089640)\r/Parent 9979 0 R \r/Next 9983 0 R \r>> \rendobj\r9983 0 obj\r<< \r/Title (12.2.2 Receiver operation)\r/Dest (G9.1089724)\r/Parent 9979 0 R \r/Prev 9982 0 R \r>> \rendobj\r9984 0 obj\r<< \r/Title (10 MCTRL - Combined PROM/IO/SRAM/SDRAM Memory Controller)\r/Dest (G7.966345)\r/Parent 9827 0 R \r/Prev 9993 0 R \r/Next 9966 0 R \r/First 9994 0 R \r/Last 9995 0 R \r/Count -18 \r>> \rendobj\r9985 0 obj\r<< \r/Title (11.1 Overview)\r/Dest (G8.1011047)\r/Parent 9966 0 R \r/Next 9992 0 R \r>> \rendobj\r9986 0 obj\r<< \r/Title (11.8 Instantiation)\r/Dest (G8.1030704)\r/Parent 9966 0 R \r/Prev 9987 0 R \r>> \rendobj\r9987 0 obj\r<< \r/Title (11.7 Library dependencies)\r/Dest (G8.1031127)\r/Parent 9966 0 R \r/Prev 9988 0 R \r/Next 9986 0 R \r>> \rendobj\r9988 0 obj\r<< \r/Title (11.6 Signal descriptions)\r/Dest (G8.1031021)\r/Parent 9966 0 R \r/Prev 9989 0 R \r/Next 9987 0 R \r>> \rendobj\r9989 0 obj\r<< \r/Title (11.5 Configuration options)\r/Dest (G8.1031136)\r/Parent 9966 0 R \r/Prev 9990 0 R \r/Next 9988 0 R \r>> \rendobj\r9990 0 obj\r<< \r/Title (11.4 Vendor and device identifiers)\r/Dest (G8.1033491)\r/Parent 9966 0 R \r/Prev 9991 0 R \r/Next 9989 0 R \r>> \rendobj\r9991 0 obj\r<< \r/Title (11.3 Registers)\r/Dest (G8.1030406)\r/Parent 9966 0 R \r/Prev 9992 0 R \r/Next 9990 0 R \r>> \rendobj\r9992 0 obj\r<< \r/Title (11.2 Operation)\r/Dest (G8.1030400)\r/Parent 9966 0 R \r/Prev 9985 0 R \r/Next 9991 0 R \r>> \rendobj\r9993 0 obj\r<< \r/Title (9 IRQMP - Multiprocessor Interrupt Controller)\r/Dest (G6.966345)\r/Parent 9827 0 R \r/Prev 10025 0 R \r/Next 9984 0 R \r/First 10026 0 R \r/Last 10027 0 R \r/Count -8 \r>> \rendobj\r9994 0 obj\r<< \r/Title (10.1 Overview)\r/Dest (G7.1011047)\r/Parent 9984 0 R \r/Next 10024 0 R \r>> \rendobj\r9995 0 obj\r<< \r/Title (10.18 Instantiation)\r/Dest (G7.1016199)\r/Parent 9984 0 R \r/Prev 9996 0 R \r>> \rendobj\r9996 0 obj\r<< \r/Title (10.17 Library dependencies)\r/Dest (G7.1016041)\r/Parent 9984 0 R \r/Prev 9997 0 R \r/Next 9995 0 R \r>> \rendobj\r9997 0 obj\r<< \r/Title (10.16 Signal descriptions)\r/Dest (G7.1019363)\r/Parent 9984 0 R \r/Prev 9998 0 R \r/Next 9996 0 R \r>> \rendobj\r9998 0 obj\r<< \r/Title (10.15 Configuration options)\r/Dest (G7.1020654)\r/Parent 9984 0 R \r/Prev 9999 0 R \r/Next 9997 0 R \r>> \rendobj\r9999 0 obj\r<< \r/Title (10.14 Vendor and device identifiers)\r/Dest (G7.1020656)\r/Parent 9984 0 R \r/Prev 10000 0 R \r/Next 9998 0 R \r>> \rendobj\r10000 0 obj\r<< \r/Title (10.13 Registers)\r/Dest (G7.1014682)\r/Parent 9984 0 R \r/Prev 10001 0 R \r/Next 9999 0 R \r/First 10002 0 R \r/Last 10003 0 R \r/Count -3 \r>> \rendobj\r10001 0 obj\r<< \r/Title (10.12 Attaching an external DRAM controller)\r/Dest (G7.1020760)\r/Parent 9984 0 R \r/Prev 10005 0 R \r/Next 10000 0 R \r>> \rendobj\r10002 0 obj\r<< \r/Title (10.13.1 Memory configuration register 1 \(MCFG1\))\r/Dest (G7.1014476)\r/Parent 10000 0 R \r/Next 10004 0 R \r>> \rendobj\r10003 0 obj\r<< \r/Title (10.13.3 Memory configuration register 3 \(MCFG3\))\r/Dest (G7.1014650)\r/Parent 10000 0 R \r/Prev 10004 0 R \r>> \rendobj\r10004 0 obj\r<< \r/Title (10.13.2 Memory configuration register 2 \(MCFG2\))\r/Dest (G7.1014555)\r/Parent 10000 0 R \r/Prev 10002 0 R \r/Next 10003 0 R \r>> \rendobj\r10005 0 obj\r<< \r/Title (10.11 Access errors)\r/Dest (G7.1020594)\r/Parent 9984 0 R \r/Prev 10006 0 R \r/Next 10001 0 R \r>> \rendobj\r10006 0 obj\r<< \r/Title (10.10 Using bus ready signalling)\r/Dest (G7.1020540)\r/Parent 9984 0 R \r/Prev 10007 0 R \r/Next 10005 0 R \r>> \rendobj\r10007 0 obj\r<< \r/Title (10.9 Refresh)\r/Dest (G7.1014394)\r/Parent 9984 0 R \r/Prev 10008 0 R \r/Next 10006 0 R \r/First 10009 0 R \r/Last 10010 0 R \r/Count -6 \r>> \rendobj\r10008 0 obj\r<< \r/Title (10.8 SDRAM access)\r/Dest (G7.1014331)\r/Parent 9984 0 R \r/Prev 10015 0 R \r/Next 10007 0 R \r/First 10016 0 R \r/Last 10017 0 R \r/Count -4 \r>> \rendobj\r10009 0 obj\r<< \r/Title (10.9.1 SDRAM commands)\r/Dest (G7.1014396)\r/Parent 10007 0 R \r/Next 10014 0 R \r>> \rendobj\r10010 0 obj\r<< \r/Title (10.9.6 Clocking)\r/Dest (G7.1014404)\r/Parent 10007 0 R \r/Prev 10011 0 R \r>> \rendobj\r10011 0 obj\r<< \r/Title (10.9.5 Data bus)\r/Dest (G7.1017082)\r/Parent 10007 0 R \r/Prev 10012 0 R \r/Next 10010 0 R \r>> \rendobj\r10012 0 obj\r<< \r/Title (10.9.4 Address bus connection)\r/Dest (G7.1014402)\r/Parent 10007 0 R \r/Prev 10013 0 R \r/Next 10011 0 R \r>> \rendobj\r10013 0 obj\r<< \r/Title (10.9.3 Write cycles)\r/Dest (G7.1014400)\r/Parent 10007 0 R \r/Prev 10014 0 R \r/Next 10012 0 R \r>> \rendobj\r10014 0 obj\r<< \r/Title (10.9.2 Read cycles)\r/Dest (G7.1014398)\r/Parent 10007 0 R \r/Prev 10009 0 R \r/Next 10013 0 R \r>> \rendobj\r10015 0 obj\r<< \r/Title (10.7 8- and 16-bit I/O access)\r/Dest (G7.1019331)\r/Parent 9984 0 R \r/Prev 10020 0 R \r/Next 10008 0 R \r>> \rendobj\r10016 0 obj\r<< \r/Title (10.8.1 General)\r/Dest (G7.1014332)\r/Parent 10008 0 R \r/Next 10019 0 R \r>> \rendobj\r10017 0 obj\r<< \r/Title (10.8.4 Configurable SDRAM timing parameters)\r/Dest (G7.1014338)\r/Parent 10008 0 R \r/Prev 10018 0 R \r>> \rendobj\r10018 0 obj\r<< \r/Title (10.8.3 Initialisation)\r/Dest (G7.1014336)\r/Parent 10008 0 R \r/Prev 10019 0 R \r/Next 10017 0 R \r>> \rendobj\r10019 0 obj\r<< \r/Title (10.8.2 Address mapping)\r/Dest (G7.1014334)\r/Parent 10008 0 R \r/Prev 10016 0 R \r/Next 10018 0 R \r>> \rendobj\r10020 0 obj\r<< \r/Title (10.6 Burst cycles)\r/Dest (G7.1019333)\r/Parent 9984 0 R \r/Prev 10021 0 R \r/Next 10015 0 R \r>> \rendobj\r10021 0 obj\r<< \r/Title (10.5 8-bit and 16-bit PROM and SRAM access)\r/Dest (G7.1014197)\r/Parent 9984 0 R \r/Prev 10022 0 R \r/Next 10020 0 R \r>> \rendobj\r10022 0 obj\r<< \r/Title (10.4 SRAM access)\r/Dest (G7.1014093)\r/Parent 9984 0 R \r/Prev 10023 0 R \r/Next 10021 0 R \r>> \rendobj\r10023 0 obj\r<< \r/Title (10.3 Memory mapped I/O)\r/Dest (G7.1014440)\r/Parent 9984 0 R \r/Prev 10024 0 R \r/Next 10022 0 R \r>> \rendobj\r10024 0 obj\r<< \r/Title (10.2 PROM access)\r/Dest (G7.1016977)\r/Parent 9984 0 R \r/Prev 9994 0 R \r/Next 10023 0 R \r>> \rendobj\r10025 0 obj\r<< \r/Title (8 DSU3 - LEON3 Hardware Debug Support Unit)\r/Dest (G5.1014921)\r/Parent 9827 0 R \r/Prev 10043 0 R \r/Next 9993 0 R \r/First 10044 0 R \r/Last 10045 0 R \r/Count -12 \r>> \rendobj\r10026 0 obj\r<< \r/Title (9.1 Overview)\r/Dest (G6.1011047)\r/Parent 9993 0 R \r/Next 10033 0 R \r>> \rendobj\r10027 0 obj\r<< \r/Title (9.8 Instantiation)\r/Dest (G6.1135056)\r/Parent 9993 0 R \r/Prev 10028 0 R \r>> \rendobj\r10028 0 obj\r<< \r/Title (9.7 Library dependencies)\r/Dest (G6.1135017)\r/Parent 9993 0 R \r/Prev 10029 0 R \r/Next 10027 0 R \r>> \rendobj\r10029 0 obj\r<< \r/Title (9.6 Signal descriptions)\r/Dest (G6.1134890)\r/Parent 9993 0 R \r/Prev 10030 0 R \r/Next 10028 0 R \r>> \rendobj\r10030 0 obj\r<< \r/Title (9.5 Configuration options)\r/Dest (G6.1134839)\r/Parent 9993 0 R \r/Prev 10031 0 R \r/Next 10029 0 R \r>> \rendobj\r10031 0 obj\r<< \r/Title (9.4 Vendor and device identifiers)\r/Dest (G6.1134837)\r/Parent 9993 0 R \r/Prev 10032 0 R \r/Next 10030 0 R \r>> \rendobj\r10032 0 obj\r<< \r/Title (9.3 Registers)\r/Dest (G6.1134559)\r/Parent 9993 0 R \r/Prev 10033 0 R \r/Next 10031 0 R \r/First 10034 0 R \r/Last 10035 0 R \r/Count -7 \r>> \rendobj\r10033 0 obj\r<< \r/Title (9.2 Operation)\r/Dest (G6.1134465)\r/Parent 9993 0 R \r/Prev 10026 0 R \r/Next 10032 0 R \r/First 10041 0 R \r/Last 10042 0 R \r/Count -2 \r>> \rendobj\r10034 0 obj\r<< \r/Title (9.3.1 Interrupt level register)\r/Dest (G6.1134633)\r/Parent 10032 0 R \r/Next 10040 0 R \r>> \rendobj\r10035 0 obj\r<< \r/Title (9.3.7 Processor interrupt force register \(NCPU > 0\))\r/Dest (G6.1134764)\r/Parent 10032 0 R \r/Prev 10036 0 R \r>> \rendobj\r10036 0 obj\r<< \r/Title (9.3.6 Processor interrupt mask register)\r/Dest (G6.1134740)\r/Parent 10032 0 R \r/Prev 10037 0 R \r/Next 10035 0 R \r>> \rendobj\r10037 0 obj\r<< \r/Title (9.3.5 Multiprocessor status register)\r/Dest (G6.1134719)\r/Parent 10032 0 R \r/Prev 10038 0 R \r/Next 10036 0 R \r>> \rendobj\r10038 0 obj\r<< \r/Title (9.3.4 Interrupt clear register)\r/Dest (G6.1134698)\r/Parent 10032 0 R \r/Prev 10039 0 R \r/Next 10037 0 R \r>> \rendobj\r10039 0 obj\r<< \r/Title (9.3.3 Interrupt force register \(NCPU = 0\))\r/Dest (G6.1134676)\r/Parent 10032 0 R \r/Prev 10040 0 R \r/Next 10038 0 R \r>> \rendobj\r10040 0 obj\r<< \r/Title (9.3.2 Interrupt pending register)\r/Dest (G6.1134655)\r/Parent 10032 0 R \r/Prev 10034 0 R \r/Next 10039 0 R \r>> \rendobj\r10041 0 obj\r<< \r/Title (9.2.1 Interrupt prioritization)\r/Dest (G6.1134466)\r/Parent 10033 0 R \r/Next 10042 0 R \r>> \rendobj\r10042 0 obj\r<< \r/Title (9.2.2 Processor status monitoring)\r/Dest (G6.1134557)\r/Parent 10033 0 R \r/Prev 10041 0 R \r>> \rendobj\r10043 0 obj\r<< \r/Title (7 GRFPC - GRFPU Control Unit)\r/Dest (G4.1007208)\r/Parent 9827 0 R \r/Prev 10066 0 R \r/Next 10025 0 R \r/First 10067 0 R \r/Last 10068 0 R \r/Count -3 \r>> \rendobj\r10044 0 obj\r<< \r/Title (8.1 Overview)\r/Dest (G5.1015708)\r/Parent 10025 0 R \r/Next 10065 0 R \r>> \rendobj\r10045 0 obj\r<< \r/Title (8.12 Instantiation)\r/Dest (G5.1066649)\r/Parent 10025 0 R \r/Prev 10046 0 R \r>> \rendobj\r10046 0 obj\r<< \r/Title (8.11 Component declaration)\r/Dest (G5.1066622)\r/Parent 10025 0 R \r/Prev 10047 0 R \r/Next 10045 0 R \r>> \rendobj\r10047 0 obj\r<< \r/Title (8.10 Library dependencies)\r/Dest (G5.1066583)\r/Parent 10025 0 R \r/Prev 10048 0 R \r/Next 10046 0 R \r>> \rendobj\r10048 0 obj\r<< \r/Title (8.9 Signal descriptions)\r/Dest (G5.1066207)\r/Parent 10025 0 R \r/Prev 10049 0 R \r/Next 10047 0 R \r>> \rendobj\r10049 0 obj\r<< \r/Title (8.8 Configuration options)\r/Dest (G5.1066128)\r/Parent 10025 0 R \r/Prev 10050 0 R \r/Next 10048 0 R \r>> \rendobj\r10050 0 obj\r<< \r/Title (8.7 Vendor and device identifiers)\r/Dest (G5.1066126)\r/Parent 10025 0 R \r/Prev 10051 0 R \r/Next 10049 0 R \r>> \rendobj\r10051 0 obj\r<< \r/Title (8.6 DSU registers)\r/Dest (G5.1065834)\r/Parent 10025 0 R \r/Prev 10052 0 R \r/Next 10050 0 R \r/First 10053 0 R \r/Last 10054 0 R \r/Count -10 \r>> \rendobj\r10052 0 obj\r<< \r/Title (8.5 DSU memory map)\r/Dest (G5.1065693)\r/Parent 10025 0 R \r/Prev 10063 0 R \r/Next 10051 0 R \r>> \rendobj\r10053 0 obj\r<< \r/Title (8.6.1 DSU control register)\r/Dest (G5.1065835)\r/Parent 10051 0 R \r/Next 10062 0 R \r>> \rendobj\r10054 0 obj\r<< \r/Title (8.6.10 Instruction trace control register)\r/Dest (G5.1066110)\r/Parent 10051 0 R \r/Prev 10055 0 R \r>> \rendobj\r10055 0 obj\r<< \r/Title (8.6.9 AHB trace buffer breakpoint registers)\r/Dest (G5.1066075)\r/Parent 10051 0 R \r/Prev 10056 0 R \r/Next 10054 0 R \r>> \rendobj\r10056 0 obj\r<< \r/Title (8.6.8 AHB trace buffer index register)\r/Dest (G5.1066058)\r/Parent 10051 0 R \r/Prev 10057 0 R \r/Next 10055 0 R \r>> \rendobj\r10057 0 obj\r<< \r/Title (8.6.7 AHB Trace buffer control register)\r/Dest (G5.1066035)\r/Parent 10051 0 R \r/Prev 10058 0 R \r/Next 10056 0 R \r>> \rendobj\r10058 0 obj\r<< \r/Title (8.6.6 DSU ASI register)\r/Dest (G5.1066019)\r/Parent 10051 0 R \r/Prev 10059 0 R \r/Next 10057 0 R \r>> \rendobj\r10059 0 obj\r<< \r/Title (8.6.5 Trace buffer time tag counter)\r/Dest (G5.1066003)\r/Parent 10051 0 R \r/Prev 10060 0 R \r/Next 10058 0 R \r>> \rendobj\r10060 0 obj\r<< \r/Title (8.6.4 DSU trap register)\r/Dest (G5.1065978)\r/Parent 10051 0 R \r/Prev 10061 0 R \r/Next 10059 0 R \r>> \rendobj\r10061 0 obj\r<< \r/Title (8.6.3 DSU Debug Mode Mask Register)\r/Dest (G5.1065938)\r/Parent 10051 0 R \r/Prev 10062 0 R \r/Next 10060 0 R \r>> \rendobj\r10062 0 obj\r<< \r/Title (8.6.2 DSU Break and Single Step register)\r/Dest (G5.1065898)\r/Parent 10051 0 R \r/Prev 10053 0 R \r/Next 10061 0 R \r>> \rendobj\r10063 0 obj\r<< \r/Title (8.4 Instruction trace buffer)\r/Dest (G5.1065626)\r/Parent 10025 0 R \r/Prev 10064 0 R \r/Next 10052 0 R \r>> \rendobj\r10064 0 obj\r<< \r/Title (8.3 AHB Trace Buffer)\r/Dest (G5.1065522)\r/Parent 10025 0 R \r/Prev 10065 0 R \r/Next 10063 0 R \r>> \rendobj\r10065 0 obj\r<< \r/Title (8.2 Operation)\r/Dest (G5.1065500)\r/Parent 10025 0 R \r/Prev 10044 0 R \r/Next 10064 0 R \r>> \rendobj\r10066 0 obj\r<< \r/Title (6 GRFPU - High-performance IEEE-754 Floating-point unit)\r/Dest (G4.998206)\r/Parent 9827 0 R \r/Prev 10070 0 R \r/Next 10043 0 R \r/First 10071 0 R \r/Last 10072 0 R \r/Count -4 \r>> \rendobj\r10067 0 obj\r<< \r/Title (7.1 Floating-Point register file)\r/Dest (G4.1002404)\r/Parent 10043 0 R \r/Next 10069 0 R \r>> \rendobj\r10068 0 obj\r<< \r/Title (7.3 Floating-Point Exceptions and Floating-Point Deferred-Queue)\r/Dest (G4.1002440)\r/Parent 10043 0 R \r/Prev 10069 0 R \r>> \rendobj\r10069 0 obj\r<< \r/Title (7.2 Floating-Point State Register \(FSR\))\r/Dest (G4.1002410)\r/Parent 10043 0 R \r/Prev 10067 0 R \r/Next 10068 0 R \r>> \rendobj\r10070 0 obj\r<< \r/Title (5 LEON3 - High-performance SPARC V8 32-bit Processor)\r/Dest (G3.1015710)\r/Parent 9827 0 R \r/Prev 10082 0 R \r/Next 10066 0 R \r/First 10083 0 R \r/Last 10084 0 R \r/Count -13 \r>> \rendobj\r10071 0 obj\r<< \r/Title (6.1 Overview)\r/Dest (G4.1009186)\r/Parent 10066 0 R \r/Next 10074 0 R \r>> \rendobj\r10072 0 obj\r<< \r/Title (6.4 Timing)\r/Dest (G4.1002164)\r/Parent 10066 0 R \r/Prev 10073 0 R \r>> \rendobj\r10073 0 obj\r<< \r/Title (6.3 Signal descriptions)\r/Dest (G4.1007132)\r/Parent 10066 0 R \r/Prev 10074 0 R \r/Next 10072 0 R \r>> \rendobj\r10074 0 obj\r<< \r/Title (6.2 Functional description)\r/Dest (G4.1006300)\r/Parent 10066 0 R \r/Prev 10071 0 R \r/Next 10073 0 R \r/First 10075 0 R \r/Last 10076 0 R \r/Count -7 \r>> \rendobj\r10075 0 obj\r<< \r/Title (6.2.1 Floating-point number formats)\r/Dest (G4.1001332)\r/Parent 10074 0 R \r/Next 10081 0 R \r>> \rendobj\r10076 0 obj\r<< \r/Title (6.2.7 NaNs)\r/Dest (G4.999330)\r/Parent 10074 0 R \r/Prev 10077 0 R \r>> \rendobj\r10077 0 obj\r<< \r/Title (6.2.6 Non-standard Mode)\r/Dest (G4.998616)\r/Parent 10074 0 R \r/Prev 10078 0 R \r/Next 10076 0 R \r>> \rendobj\r10078 0 obj\r<< \r/Title (6.2.5 Denormalized numbers)\r/Dest (G4.1006900)\r/Parent 10074 0 R \r/Prev 10079 0 R \r/Next 10077 0 R \r>> \rendobj\r10079 0 obj\r<< \r/Title (6.2.4 Rounding)\r/Dest (G4.1002307)\r/Parent 10074 0 R \r/Prev 10080 0 R \r/Next 10078 0 R \r>> \rendobj\r10080 0 obj\r<< \r/Title (6.2.3 Exceptions)\r/Dest (G4.1001917)\r/Parent 10074 0 R \r/Prev 10081 0 R \r/Next 10079 0 R \r>> \rendobj\r10081 0 obj\r<< \r/Title (6.2.2 FP operations)\r/Dest (G4.1002006)\r/Parent 10074 0 R \r/Prev 10075 0 R \r/Next 10080 0 R \r>> \rendobj\r10082 0 obj\r<< \r/Title (4 Software development)\r/Dest (G2.1024474)\r/Parent 9827 0 R \r/Prev 10146 0 R \r/Next 10070 0 R \r/First 10147 0 R \r/Last 10148 0 R \r/Count -4 \r>> \rendobj\r10083 0 obj\r<< \r/Title (5.1 Overview)\r/Dest (G3.985683)\r/Parent 10070 0 R \r/Next 10117 0 R \r/First 10136 0 R \r/Last 10137 0 R \r/Count -10 \r>> \rendobj\r10084 0 obj\r<< \r/Title (5.13 Component declaration)\r/Dest (G3.1061871)\r/Parent 10070 0 R \r/Prev 10085 0 R \r>> \rendobj\r10085 0 obj\r<< \r/Title (5.12 Library dependencies)\r/Dest (G3.1061836)\r/Parent 10070 0 R \r/Prev 10086 0 R \r/Next 10084 0 R \r>> \rendobj\r10086 0 obj\r<< \r/Title (5.11 Signal descriptions)\r/Dest (G3.1061002)\r/Parent 10070 0 R \r/Prev 10087 0 R \r/Next 10085 0 R \r>> \rendobj\r10087 0 obj\r<< \r/Title (5.10 Configuration options)\r/Dest (G3.1060312)\r/Parent 10070 0 R \r/Prev 10088 0 R \r/Next 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92 612 null ] \r>> \rendobj\r1430 0 obj\r<< \r/D [ 37 0 R /XYZ 197 612 null ] \r>> \rendobj\r1431 0 obj\r<< \r/D [ 37 0 R /XYZ 424 612 null ] \r>> \rendobj\r1432 0 obj\r<< \r/D [ 37 0 R /XYZ 481 612 null ] \r>> \rendobj\r1433 0 obj\r<< \r/D [ 37 0 R /XYZ 92 597 null ] \r>> \rendobj\r1434 0 obj\r<< \r/D [ 37 0 R /XYZ 197 597 null ] \r>> \rendobj\r1435 0 obj\r<< \r/D [ 37 0 R /XYZ 424 597 null ] \r>> \rendobj\r1436 0 obj\r<< \r/D [ 37 0 R /XYZ 481 597 null ] \r>> \rendobj\r1437 0 obj\r<< \r/D [ 37 0 R /XYZ 92 582 null ] \r>> \rendobj\r1438 0 obj\r<< \r/D [ 37 0 R /XYZ 197 582 null ] \r>> \rendobj\r1439 0 obj\r<< \r/D [ 37 0 R /XYZ 424 582 null ] \r>> \rendobj\r1440 0 obj\r<< \r/D [ 37 0 R /XYZ 481 582 null ] \r>> \rendobj\r1441 0 obj\r<< \r/D [ 37 0 R /XYZ 92 567 null ] \r>> \rendobj\r1442 0 obj\r<< \r/D [ 37 0 R /XYZ 197 567 null ] \r>> \rendobj\r1443 0 obj\r<< \r/D [ 37 0 R /XYZ 424 567 null ] \r>> \rendobj\r1444 0 obj\r<< \r/D [ 37 0 R /XYZ 481 567 null ] \r>> \rendobj\r1445 0 obj\r<< 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null ] \r>> \rendobj\r1618 0 obj\r<< \r/D [ 47 0 R /XYZ 56 752 null ] \r>> \rendobj\r1619 0 obj\r<< \r/D [ 47 0 R /XYZ 56 695 null ] \r>> \rendobj\r1620 0 obj\r<< \r/D [ 47 0 R /XYZ 56 676 null ] \r>> \rendobj\r1621 0 obj\r<< \r/D [ 47 0 R /XYZ 56 666 null ] \r>> \rendobj\r1622 0 obj\r<< \r/D [ 47 0 R /XYZ 56 657 null ] \r>> \rendobj\r1623 0 obj\r<< \r/D [ 47 0 R /XYZ 56 639 null ] \r>> \rendobj\r1624 0 obj\r<< \r/D [ 47 0 R /XYZ 56 620 null ] \r>> \rendobj\r1625 0 obj\r<< \r/D [ 47 0 R /XYZ 56 610 null ] \r>> \rendobj\r1626 0 obj\r<< \r/D [ 47 0 R /XYZ 56 600 null ] \r>> \rendobj\r1627 0 obj\r<< \r/D [ 47 0 R /XYZ 56 590 null ] \r>> \rendobj\r1628 0 obj\r<< \r/D [ 47 0 R /XYZ 56 580 null ] \r>> \rendobj\r1629 0 obj\r<< \r/D [ 47 0 R /XYZ 56 570 null ] \r>> \rendobj\r1630 0 obj\r<< \r/D [ 47 0 R /XYZ 56 560 null ] \r>> \rendobj\r1631 0 obj\r<< \r/D [ 47 0 R /XYZ 56 550 null ] \r>> \rendobj\r1632 0 obj\r<< \r/D [ 47 0 R /XYZ 56 540 null ] \r>> \rendobj\r1633 0 obj\r<< \r/D [ 47 0 R /XYZ 56 530 null ] \r>> \rendobj\r1634 0 obj\r<< \r/D [ 47 0 R /XYZ 56 520 null ] \r>> \rendobj\r1635 0 obj\r<< \r/D [ 47 0 R /XYZ 56 510 null ] \r>> \rendobj\r1636 0 obj\r<< \r/D [ 47 0 R /XYZ 56 500 null ] \r>> \rendobj\r1637 0 obj\r<< \r/D [ 47 0 R /XYZ 56 490 null ] \r>> \rendobj\r1638 0 obj\r<< \r/D [ 47 0 R /XYZ 56 480 null ] \r>> \rendobj\r1639 0 obj\r<< \r/D [ 47 0 R /XYZ 56 470 null ] \r>> \rendobj\r1640 0 obj\r<< \r/D [ 47 0 R /XYZ 56 460 null ] \r>> \rendobj\r1641 0 obj\r<< \r/D [ 47 0 R /XYZ 56 450 null ] \r>> \rendobj\r1642 0 obj\r<< \r/D [ 47 0 R /XYZ 56 440 null ] \r>> \rendobj\r1643 0 obj\r<< \r/D [ 47 0 R /XYZ 56 430 null ] \r>> \rendobj\r1644 0 obj\r<< \r/D [ 47 0 R /XYZ 56 420 null ] \r>> \rendobj\r1645 0 obj\r<< \r/D [ 47 0 R /XYZ 56 410 null ] \r>> \rendobj\r1646 0 obj\r<< \r/D [ 47 0 R /XYZ 56 400 null ] \r>> \rendobj\r1647 0 obj\r<< \r/D [ 47 0 R /XYZ 56 390 null ] \r>> \rendobj\r1648 0 obj\r<< \r/D [ 47 0 R /XYZ 56 380 null ] \r>> \rendobj\r1649 0 obj\r<< \r/D [ 47 0 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] \r>> \rendobj\r1713 0 obj\r<< \r/D [ 50 0 R /XYZ 56 217 null ] \r>> \rendobj\r1714 0 obj\r<< \r/D [ 50 0 R /XYZ 56 185 null ] \r>> \rendobj\r1715 0 obj\r<< \r/D [ 50 0 R /XYZ 56 176 null ] \r>> \rendobj\r1716 0 obj\r<< \r/D [ 50 0 R /XYZ 56 158 null ] \r>> \rendobj\r1717 0 obj\r<< \r/D [ 50 0 R /XYZ 56 127 null ] \r>> \rendobj\r1718 0 obj\r<< \r/D [ 50 0 R /XYZ 56 95 null ] \r>> \rendobj\r1719 0 obj\r<< \r/D [ 53 0 R /XYZ null null null ] \r>> \rendobj\r1720 0 obj\r<< \r/D [ 53 0 R /XYZ null null null ] \r>> \rendobj\r1721 0 obj\r<< \r/D [ 53 0 R /XYZ 56 775 null ] \r>> \rendobj\r1722 0 obj\r<< \r/D [ 53 0 R /XYZ 56 745 null ] \r>> \rendobj\r1723 0 obj\r<< \r/D [ 53 0 R /XYZ 56 722 null ] \r>> \rendobj\r1724 0 obj\r<< \r/D [ 53 0 R /XYZ 56 704 null ] \r>> \rendobj\r1725 0 obj\r<< \r/D [ 53 0 R /XYZ 56 686 null ] \r>> \rendobj\r1726 0 obj\r<< \r/D [ 53 0 R /XYZ 56 668 null ] \r>> \rendobj\r1727 0 obj\r<< \r/D [ 53 0 R /XYZ 56 650 null ] \r>> \rendobj\r1728 0 obj\r<< \r/D [ 53 0 R /XYZ 56 632 null ] \r>> \rendobj\r1729 0 obj\r<< \r/D [ 53 0 R /XYZ 56 614 null ] \r>> \rendobj\r1730 0 obj\r<< \r/D [ 53 0 R /XYZ 56 588 null ] \r>> \rendobj\r1731 0 obj\r<< \r/D [ 53 0 R /XYZ 56 565 null ] \r>> \rendobj\r1732 0 obj\r<< \r/D [ 53 0 R /XYZ 56 495 null ] \r>> \rendobj\r1733 0 obj\r<< \r/D [ 53 0 R /XYZ 56 469 null ] \r>> \rendobj\r1734 0 obj\r<< \r/D [ 53 0 R /XYZ 56 446 null ] \r>> \rendobj\r1735 0 obj\r<< \r/D [ 53 0 R /XYZ 56 401 null ] \r>> \rendobj\r1736 0 obj\r<< \r/D [ 53 0 R /XYZ 56 391 null ] \r>> \rendobj\r1737 0 obj\r<< \r/D [ 53 0 R /XYZ 56 382 null ] \r>> \rendobj\r1738 0 obj\r<< \r/D [ 53 0 R /XYZ 56 351 null ] \r>> \rendobj\r1739 0 obj\r<< \r/D [ 53 0 R /XYZ 56 306 null ] \r>> \rendobj\r1740 0 obj\r<< \r/D [ 53 0 R /XYZ 56 296 null ] \r>> \rendobj\r1741 0 obj\r<< \r/D [ 53 0 R /XYZ 56 287 null ] \r>> \rendobj\r1742 0 obj\r<< \r/D [ 53 0 R /XYZ 56 261 null ] \r>> \rendobj\r1743 0 obj\r<< \r/D [ 53 0 R /XYZ 56 238 null ] \r>> \rendobj\r1744 0 obj\r<< \r/D [ 53 0 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null ] \r>> \rendobj\r1792 0 obj\r<< \r/D [ 62 0 R /XYZ 56 592 null ] \r>> \rendobj\r1793 0 obj\r<< \r/D [ 62 0 R /XYZ 56 574 null ] \r>> \rendobj\r1794 0 obj\r<< \r/D [ 62 0 R /XYZ 56 556 null ] \r>> \rendobj\r1795 0 obj\r<< \r/D [ 62 0 R /XYZ 160 141 null ] \r>> \rendobj\r1796 0 obj\r<< \r/D [ 66 0 R /XYZ null null null ] \r>> \rendobj\r1797 0 obj\r<< \r/D [ 66 0 R /XYZ 127 481 null ] \r>> \rendobj\r1798 0 obj\r<< \r/D [ 66 0 R /XYZ 127 481 null ] \r>> \rendobj\r1799 0 obj\r<< \r/D [ 66 0 R /XYZ 56 774 null ] \r>> \rendobj\r1800 0 obj\r<< \r/D [ 66 0 R /XYZ 56 753 null ] \r>> \rendobj\r1801 0 obj\r<< \r/D [ 66 0 R /XYZ 56 735 null ] \r>> \rendobj\r1802 0 obj\r<< \r/D [ 66 0 R /XYZ 56 691 null ] \r>> \rendobj\r1803 0 obj\r<< \r/D [ 66 0 R /XYZ 56 660 null ] \r>> \rendobj\r1804 0 obj\r<< \r/D [ 66 0 R /XYZ 56 642 null ] \r>> \rendobj\r1805 0 obj\r<< \r/D [ 66 0 R /XYZ 56 611 null ] \r>> \rendobj\r1806 0 obj\r<< \r/D [ 66 0 R /XYZ 56 580 null ] \r>> \rendobj\r1807 0 obj\r<< \r/D [ 66 0 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236 null ] \r>> \rendobj\r2075 0 obj\r<< \r/D [ 83 0 R /XYZ null null null ] \r>> \rendobj\r2076 0 obj\r<< \r/D [ 83 0 R /XYZ 56 735 null ] \r>> \rendobj\r2077 0 obj\r<< \r/D [ 83 0 R /XYZ 56 714 null ] \r>> \rendobj\r2078 0 obj\r<< \r/D [ 83 0 R /XYZ 56 605 null ] \r>> \rendobj\r2079 0 obj\r<< \r/D [ 83 0 R /XYZ 56 561 null ] \r>> \rendobj\r2080 0 obj\r<< \r/D [ 83 0 R /XYZ 56 504 null ] \r>> \rendobj\r2081 0 obj\r<< \r/D [ 83 0 R /XYZ 56 478 null ] \r>> \rendobj\r2082 0 obj\r<< \r/D [ 83 0 R /XYZ 56 450 null ] \r>> \rendobj\r2083 0 obj\r<< \r/D [ 83 0 R /XYZ 56 429 null ] \r>> \rendobj\r2084 0 obj\r<< \r/D [ 83 0 R /XYZ 56 320 null ] \r>> \rendobj\r2085 0 obj\r<< \r/D [ 83 0 R /XYZ 56 198 null ] \r>> \rendobj\r2086 0 obj\r<< \r/D [ 86 0 R /XYZ null null null ] \r>> \rendobj\r2087 0 obj\r<< \r/D [ 86 0 R /XYZ 283 443 null ] \r>> \rendobj\r2088 0 obj\r<< \r/D [ 86 0 R /XYZ 283 443 null ] \r>> \rendobj\r2089 0 obj\r<< \r/D [ 86 0 R /XYZ 56 774 null ] \r>> \rendobj\r2090 0 obj\r<< \r/D [ 86 0 R /XYZ 56 753 null ] \r>> \rendobj\r2091 0 obj\r<< \r/D [ 86 0 R /XYZ 56 584 null ] \r>> \rendobj\r2092 0 obj\r<< \r/D [ 86 0 R /XYZ 56 565 null ] \r>> \rendobj\r2093 0 obj\r<< \r/D [ 86 0 R /XYZ 56 553 null ] \r>> \rendobj\r2094 0 obj\r<< \r/D [ 86 0 R /XYZ 56 541 null ] \r>> \rendobj\r2095 0 obj\r<< \r/D [ 86 0 R /XYZ 56 529 null ] \r>> \rendobj\r2096 0 obj\r<< \r/D [ 86 0 R /XYZ 56 486 null ] \r>> \rendobj\r2097 0 obj\r<< \r/D [ 86 0 R /XYZ 56 468 null ] \r>> \rendobj\r2098 0 obj\r<< \r/D [ 86 0 R /XYZ 56 415 null ] \r>> \rendobj\r2099 0 obj\r<< \r/D [ 86 0 R /XYZ 56 388 null ] \r>> \rendobj\r2100 0 obj\r<< \r/D [ 86 0 R /XYZ 56 367 null ] \r>> \rendobj\r2101 0 obj\r<< \r/D [ 86 0 R /XYZ 56 224 null ] \r>> \rendobj\r2102 0 obj\r<< \r/D [ 86 0 R /XYZ 56 203 null ] \r>> \rendobj\r2103 0 obj\r<< \r/D [ 86 0 R /XYZ 56 133 null ] \r>> \rendobj\r2104 0 obj\r<< \r/D [ 86 0 R /XYZ 216 614 null ] \r>> \rendobj\r2105 0 obj\r<< \r/D [ 90 0 R /XYZ null null null ] \r>> \rendobj\r2106 0 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449 null ] \r>> \rendobj\r2138 0 obj\r<< \r/D [ 99 0 R /XYZ 279 449 null ] \r>> \rendobj\r2139 0 obj\r<< \r/D [ 99 0 R /XYZ 56 657 null ] \r>> \rendobj\r2140 0 obj\r<< \r/D [ 99 0 R /XYZ 56 645 null ] \r>> \rendobj\r2141 0 obj\r<< \r/D [ 99 0 R /XYZ 56 633 null ] \r>> \rendobj\r2142 0 obj\r<< \r/D [ 99 0 R /XYZ 56 621 null ] \r>> \rendobj\r2143 0 obj\r<< \r/D [ 99 0 R /XYZ 56 609 null ] \r>> \rendobj\r2144 0 obj\r<< \r/D [ 99 0 R /XYZ 56 597 null ] \r>> \rendobj\r2145 0 obj\r<< \r/D [ 99 0 R /XYZ 56 574 null ] \r>> \rendobj\r2146 0 obj\r<< \r/D [ 99 0 R /XYZ 56 551 null ] \r>> \rendobj\r2147 0 obj\r<< \r/D [ 99 0 R /XYZ 56 528 null ] \r>> \rendobj\r2148 0 obj\r<< \r/D [ 99 0 R /XYZ 56 505 null ] \r>> \rendobj\r2149 0 obj\r<< \r/D [ 99 0 R /XYZ 56 483 null ] \r>> \rendobj\r2150 0 obj\r<< \r/D [ 99 0 R /XYZ 56 465 null ] \r>> \rendobj\r2151 0 obj\r<< \r/D [ 99 0 R /XYZ 56 361 null ] \r>> \rendobj\r2152 0 obj\r<< \r/D [ 99 0 R /XYZ 56 340 null ] \r>> \rendobj\r2153 0 obj\r<< \r/D [ 99 0 R /XYZ 56 309 null ] \r>> \rendobj\r2154 0 obj\r<< \r/D [ 99 0 R /XYZ 56 213 null ] \r>> \rendobj\r2155 0 obj\r<< \r/D [ 99 0 R /XYZ 56 201 null ] \r>> \rendobj\r2156 0 obj\r<< \r/D [ 99 0 R /XYZ 56 178 null ] \r>> \rendobj\r2157 0 obj\r<< \r/D [ 99 0 R /XYZ 56 166 null ] \r>> \rendobj\r2158 0 obj\r<< \r/D [ 99 0 R /XYZ 56 143 null ] \r>> \rendobj\r2159 0 obj\r<< \r/D [ 99 0 R /XYZ 56 131 null ] \r>> \rendobj\r2160 0 obj\r<< \r/D [ 99 0 R /XYZ 56 119 null ] \r>> \rendobj\r2161 0 obj\r<< \r/D [ 99 0 R /XYZ 56 107 null ] \r>> \rendobj\r2162 0 obj\r<< \r/D [ 99 0 R /XYZ 56 84 null ] \r>> \rendobj\r2163 0 obj\r<< \r/D [ 99 0 R /XYZ 203 696 null ] \r>> \rendobj\r2164 0 obj\r<< \r/D [ 99 0 R /XYZ 202 244 null ] \r>> \rendobj\r2165 0 obj\r<< \r/D [ 102 0 R /XYZ null null null ] \r>> \rendobj\r2166 0 obj\r<< \r/D [ 102 0 R /XYZ 56 774 null ] \r>> \rendobj\r2167 0 obj\r<< \r/D [ 102 0 R /XYZ 56 763 null ] \r>> \rendobj\r2168 0 obj\r<< \r/D [ 102 0 R /XYZ 56 745 null ] \r>> \rendobj\r2169 0 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] \r>> \rendobj\r2185 0 obj\r<< \r/D [ 102 0 R /XYZ 282 668 null ] \r>> \rendobj\r2186 0 obj\r<< \r/D [ 102 0 R /XYZ 91 653 null ] \r>> \rendobj\r2187 0 obj\r<< \r/D [ 102 0 R /XYZ 282 653 null ] \r>> \rendobj\r2188 0 obj\r<< \r/D [ 102 0 R /XYZ 91 638 null ] \r>> \rendobj\r2189 0 obj\r<< \r/D [ 102 0 R /XYZ 282 638 null ] \r>> \rendobj\r2190 0 obj\r<< \r/D [ 102 0 R /XYZ 91 623 null ] \r>> \rendobj\r2191 0 obj\r<< \r/D [ 102 0 R /XYZ 282 623 null ] \r>> \rendobj\r2192 0 obj\r<< \r/D [ 102 0 R /XYZ 56 372 null ] \r>> \rendobj\r2193 0 obj\r<< \r/D [ 102 0 R /XYZ 91 347 null ] \r>> \rendobj\r2194 0 obj\r<< \r/D [ 102 0 R /XYZ 254 347 null ] \r>> \rendobj\r2195 0 obj\r<< \r/D [ 102 0 R /XYZ 91 332 null ] \r>> \rendobj\r2196 0 obj\r<< \r/D [ 102 0 R /XYZ 254 332 null ] \r>> \rendobj\r2197 0 obj\r<< \r/D [ 102 0 R /XYZ 91 317 null ] \r>> \rendobj\r2198 0 obj\r<< \r/D [ 102 0 R /XYZ 254 317 null ] \r>> \rendobj\r2199 0 obj\r<< \r/D [ 102 0 R /XYZ 91 302 null ] \r>> \rendobj\r2200 0 obj\r<< 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] \r>> \rendobj\r2216 0 obj\r<< \r/D [ 105 0 R /XYZ 56 564 null ] \r>> \rendobj\r2217 0 obj\r<< \r/D [ 105 0 R /XYZ 56 499 null ] \r>> \rendobj\r2218 0 obj\r<< \r/D [ 105 0 R /XYZ 56 476 null ] \r>> \rendobj\r2219 0 obj\r<< \r/D [ 105 0 R /XYZ 56 398 null ] \r>> \rendobj\r2220 0 obj\r<< \r/D [ 105 0 R /XYZ 56 377 null ] \r>> \rendobj\r2221 0 obj\r<< \r/D [ 105 0 R /XYZ 56 281 null ] \r>> \rendobj\r2222 0 obj\r<< \r/D [ 105 0 R /XYZ 56 729 null ] \r>> \rendobj\r2223 0 obj\r<< \r/D [ 105 0 R /XYZ 91 704 null ] \r>> \rendobj\r2224 0 obj\r<< \r/D [ 105 0 R /XYZ 282 704 null ] \r>> \rendobj\r2225 0 obj\r<< \r/D [ 105 0 R /XYZ 91 689 null ] \r>> \rendobj\r2226 0 obj\r<< \r/D [ 105 0 R /XYZ 282 689 null ] \r>> \rendobj\r2227 0 obj\r<< \r/D [ 105 0 R /XYZ 91 674 null ] \r>> \rendobj\r2228 0 obj\r<< \r/D [ 105 0 R /XYZ 282 674 null ] \r>> \rendobj\r2229 0 obj\r<< \r/D [ 105 0 R /XYZ 91 659 null ] \r>> \rendobj\r2230 0 obj\r<< \r/D [ 105 0 R /XYZ 282 659 null ] \r>> \rendobj\r2231 0 obj\r<< \r/D [ 105 0 R /XYZ 91 644 null ] \r>> \rendobj\r2232 0 obj\r<< \r/D [ 105 0 R /XYZ 282 644 null ] \r>> \rendobj\r2233 0 obj\r<< \r/D [ 105 0 R /XYZ 91 629 null ] \r>> \rendobj\r2234 0 obj\r<< \r/D [ 105 0 R /XYZ 282 629 null ] \r>> \rendobj\r2235 0 obj\r<< \r/D [ 105 0 R /XYZ 56 218 null ] \r>> \rendobj\r2236 0 obj\r<< \r/D [ 105 0 R /XYZ 91 193 null ] \r>> \rendobj\r2237 0 obj\r<< \r/D [ 105 0 R /XYZ 424 193 null ] \r>> \rendobj\r2238 0 obj\r<< \r/D [ 105 0 R /XYZ 481 193 null ] \r>> \rendobj\r2239 0 obj\r<< \r/D [ 105 0 R /XYZ 91 178 null ] \r>> \rendobj\r2240 0 obj\r<< \r/D [ 105 0 R /XYZ 424 178 null ] \r>> \rendobj\r2241 0 obj\r<< \r/D [ 105 0 R /XYZ 424 163 null ] \r>> \rendobj\r2242 0 obj\r<< \r/D [ 105 0 R /XYZ 481 178 null ] \r>> \rendobj\r2243 0 obj\r<< \r/D [ 105 0 R /XYZ 481 163 null ] \r>> \rendobj\r2244 0 obj\r<< \r/D [ 105 0 R /XYZ 91 148 null ] \r>> \rendobj\r2245 0 obj\r<< \r/D [ 105 0 R /XYZ 424 148 null ] \r>> \rendobj\r2246 0 obj\r<< \r/D [ 105 0 R /XYZ 481 148 null ] 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null ] \r>> \rendobj\r2309 0 obj\r<< \r/D [ 111 0 R /XYZ 409 632 null ] \r>> \rendobj\r2310 0 obj\r<< \r/D [ 111 0 R /XYZ 473 632 null ] \r>> \rendobj\r2311 0 obj\r<< \r/D [ 111 0 R /XYZ 91 617 null ] \r>> \rendobj\r2312 0 obj\r<< \r/D [ 111 0 R /XYZ 254 617 null ] \r>> \rendobj\r2313 0 obj\r<< \r/D [ 111 0 R /XYZ 306 617 null ] \r>> \rendobj\r2314 0 obj\r<< \r/D [ 111 0 R /XYZ 357 617 null ] \r>> \rendobj\r2315 0 obj\r<< \r/D [ 111 0 R /XYZ 409 617 null ] \r>> \rendobj\r2316 0 obj\r<< \r/D [ 111 0 R /XYZ 473 617 null ] \r>> \rendobj\r2317 0 obj\r<< \r/D [ 111 0 R /XYZ 91 602 null ] \r>> \rendobj\r2318 0 obj\r<< \r/D [ 111 0 R /XYZ 254 602 null ] \r>> \rendobj\r2319 0 obj\r<< \r/D [ 111 0 R /XYZ 306 602 null ] \r>> \rendobj\r2320 0 obj\r<< \r/D [ 111 0 R /XYZ 357 602 null ] \r>> \rendobj\r2321 0 obj\r<< \r/D [ 111 0 R /XYZ 409 602 null ] \r>> \rendobj\r2322 0 obj\r<< \r/D [ 111 0 R /XYZ 473 602 null ] \r>> \rendobj\r2323 0 obj\r<< \r/D [ 111 0 R /XYZ 56 479 null ] \r>> \rendobj\r2324 0 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453 409 null ] \r>> \rendobj\r2340 0 obj\r<< \r/D [ 111 0 R /XYZ 91 394 null ] \r>> \rendobj\r2341 0 obj\r<< \r/D [ 111 0 R /XYZ 169 394 null ] \r>> \rendobj\r2342 0 obj\r<< \r/D [ 111 0 R /XYZ 353 394 null ] \r>> \rendobj\r2343 0 obj\r<< \r/D [ 111 0 R /XYZ 453 394 null ] \r>> \rendobj\r2344 0 obj\r<< \r/D [ 114 0 R /XYZ null null null ] \r>> \rendobj\r2345 0 obj\r<< \r/D [ 114 0 R /XYZ 91 779 null ] \r>> \rendobj\r2346 0 obj\r<< \r/D [ 114 0 R /XYZ 91 779 null ] \r>> \rendobj\r2347 0 obj\r<< \r/D [ 114 0 R /XYZ 127 733 null ] \r>> \rendobj\r2348 0 obj\r<< \r/D [ 114 0 R /XYZ 127 733 null ] \r>> \rendobj\r2349 0 obj\r<< \r/D [ 114 0 R /XYZ 56 775 null ] \r>> \rendobj\r2350 0 obj\r<< \r/D [ 114 0 R /XYZ 56 752 null ] \r>> \rendobj\r2351 0 obj\r<< \r/D [ 114 0 R /XYZ 56 728 null ] \r>> \rendobj\r2352 0 obj\r<< \r/D [ 114 0 R /XYZ 91 703 null ] \r>> \rendobj\r2353 0 obj\r<< \r/D [ 114 0 R /XYZ 169 703 null ] \r>> \rendobj\r2354 0 obj\r<< \r/D [ 114 0 R /XYZ 410 703 null ] \r>> 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91 693 null ] \r>> \rendobj\r2417 0 obj\r<< \r/D [ 118 0 R /XYZ 169 693 null ] \r>> \rendobj\r2418 0 obj\r<< \r/D [ 118 0 R /XYZ 410 693 null ] \r>> \rendobj\r2419 0 obj\r<< \r/D [ 118 0 R /XYZ 481 693 null ] \r>> \rendobj\r2420 0 obj\r<< \r/D [ 118 0 R /XYZ 91 678 null ] \r>> \rendobj\r2421 0 obj\r<< \r/D [ 118 0 R /XYZ 169 678 null ] \r>> \rendobj\r2422 0 obj\r<< \r/D [ 118 0 R /XYZ 410 678 null ] \r>> \rendobj\r2423 0 obj\r<< \r/D [ 118 0 R /XYZ 481 678 null ] \r>> \rendobj\r2424 0 obj\r<< \r/D [ 118 0 R /XYZ 91 663 null ] \r>> \rendobj\r2425 0 obj\r<< \r/D [ 118 0 R /XYZ 169 663 null ] \r>> \rendobj\r2426 0 obj\r<< \r/D [ 118 0 R /XYZ 410 663 null ] \r>> \rendobj\r2427 0 obj\r<< \r/D [ 118 0 R /XYZ 481 663 null ] \r>> \rendobj\r2428 0 obj\r<< \r/D [ 118 0 R /XYZ 91 648 null ] \r>> \rendobj\r2429 0 obj\r<< \r/D [ 118 0 R /XYZ 169 648 null ] \r>> \rendobj\r2430 0 obj\r<< \r/D [ 118 0 R /XYZ 410 648 null ] \r>> \rendobj\r2431 0 obj\r<< \r/D [ 118 0 R /XYZ 481 648 null ] \r>> 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268 486 null ] \r>> \rendobj\r2772 0 obj\r<< \r/D [ 136 0 R /XYZ 297 486 null ] \r>> \rendobj\r2773 0 obj\r<< \r/D [ 136 0 R /XYZ 339 486 null ] \r>> \rendobj\r2774 0 obj\r<< \r/D [ 136 0 R /XYZ 396 486 null ] \r>> \rendobj\r2775 0 obj\r<< \r/D [ 136 0 R /XYZ 91 456 null ] \r>> \rendobj\r2776 0 obj\r<< \r/D [ 136 0 R /XYZ 169 456 null ] \r>> \rendobj\r2777 0 obj\r<< \r/D [ 136 0 R /XYZ 169 441 null ] \r>> \rendobj\r2778 0 obj\r<< \r/D [ 136 0 R /XYZ 240 456 null ] \r>> \rendobj\r2779 0 obj\r<< \r/D [ 136 0 R /XYZ 268 456 null ] \r>> \rendobj\r2780 0 obj\r<< \r/D [ 136 0 R /XYZ 297 456 null ] \r>> \rendobj\r2781 0 obj\r<< \r/D [ 136 0 R /XYZ 339 456 null ] \r>> \rendobj\r2782 0 obj\r<< \r/D [ 136 0 R /XYZ 396 456 null ] \r>> \rendobj\r2783 0 obj\r<< \r/D [ 136 0 R /XYZ 91 419 null ] \r>> \rendobj\r2784 0 obj\r<< \r/D [ 136 0 R /XYZ 169 419 null ] \r>> \rendobj\r2785 0 obj\r<< \r/D [ 136 0 R /XYZ 169 404 null ] \r>> \rendobj\r2786 0 obj\r<< \r/D [ 136 0 R /XYZ 240 419 null ] \r>> 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null ] \r>> \rendobj\r2818 0 obj\r<< \r/D [ 136 0 R /XYZ 169 248 null ] \r>> \rendobj\r2819 0 obj\r<< \r/D [ 136 0 R /XYZ 240 248 null ] \r>> \rendobj\r2820 0 obj\r<< \r/D [ 136 0 R /XYZ 268 248 null ] \r>> \rendobj\r2821 0 obj\r<< \r/D [ 136 0 R /XYZ 297 248 null ] \r>> \rendobj\r2822 0 obj\r<< \r/D [ 136 0 R /XYZ 339 248 null ] \r>> \rendobj\r2823 0 obj\r<< \r/D [ 136 0 R /XYZ 396 248 null ] \r>> \rendobj\r2824 0 obj\r<< \r/D [ 136 0 R /XYZ 91 233 null ] \r>> \rendobj\r2825 0 obj\r<< \r/D [ 136 0 R /XYZ 169 233 null ] \r>> \rendobj\r2826 0 obj\r<< \r/D [ 136 0 R /XYZ 240 233 null ] \r>> \rendobj\r2827 0 obj\r<< \r/D [ 136 0 R /XYZ 268 233 null ] \r>> \rendobj\r2828 0 obj\r<< \r/D [ 136 0 R /XYZ 297 233 null ] \r>> \rendobj\r2829 0 obj\r<< \r/D [ 136 0 R /XYZ 339 233 null ] \r>> \rendobj\r2830 0 obj\r<< \r/D [ 136 0 R /XYZ 396 233 null ] \r>> \rendobj\r2831 0 obj\r<< \r/D [ 136 0 R /XYZ 91 218 null ] \r>> \rendobj\r2832 0 obj\r<< \r/D [ 136 0 R /XYZ 169 218 null ] \r>> \rendobj\r2833 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203 0 R /XYZ 56 354 null ] \r>> \rendobj\r3499 0 obj\r<< \r/D [ 203 0 R /XYZ 56 333 null ] \r>> \rendobj\r3500 0 obj\r<< \r/D [ 203 0 R /XYZ 188 476 null ] \r>> \rendobj\r3501 0 obj\r<< \r/D [ 206 0 R /XYZ null null null ] \r>> \rendobj\r3502 0 obj\r<< \r/D [ 206 0 R /XYZ 304 416 null ] \r>> \rendobj\r3503 0 obj\r<< \r/D [ 206 0 R /XYZ 304 416 null ] \r>> \rendobj\r3504 0 obj\r<< \r/D [ 206 0 R /XYZ 56 775 null ] \r>> \rendobj\r3505 0 obj\r<< \r/D [ 206 0 R /XYZ 56 752 null ] \r>> \rendobj\r3506 0 obj\r<< \r/D [ 206 0 R /XYZ 56 507 null ] \r>> \rendobj\r3507 0 obj\r<< \r/D [ 206 0 R /XYZ 56 481 null ] \r>> \rendobj\r3508 0 obj\r<< \r/D [ 206 0 R /XYZ 56 379 null ] \r>> \rendobj\r3509 0 obj\r<< \r/D [ 206 0 R /XYZ 56 367 null ] \r>> \rendobj\r3510 0 obj\r<< \r/D [ 206 0 R /XYZ 56 355 null ] \r>> \rendobj\r3511 0 obj\r<< \r/D [ 206 0 R /XYZ 56 343 null ] \r>> \rendobj\r3512 0 obj\r<< \r/D [ 206 0 R /XYZ 56 319 null ] \r>> \rendobj\r3513 0 obj\r<< \r/D [ 206 0 R /XYZ 56 213 null ] \r>> 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206 0 R /XYZ 91 600 null ] \r>> \rendobj\r3530 0 obj\r<< \r/D [ 206 0 R /XYZ 282 600 null ] \r>> \rendobj\r3531 0 obj\r<< \r/D [ 206 0 R /XYZ 91 585 null ] \r>> \rendobj\r3532 0 obj\r<< \r/D [ 206 0 R /XYZ 282 585 null ] \r>> \rendobj\r3533 0 obj\r<< \r/D [ 206 0 R /XYZ 91 570 null ] \r>> \rendobj\r3534 0 obj\r<< \r/D [ 206 0 R /XYZ 282 570 null ] \r>> \rendobj\r3535 0 obj\r<< \r/D [ 206 0 R /XYZ 91 555 null ] \r>> \rendobj\r3536 0 obj\r<< \r/D [ 206 0 R /XYZ 282 555 null ] \r>> \rendobj\r3537 0 obj\r<< \r/D [ 206 0 R /XYZ 91 540 null ] \r>> \rendobj\r3538 0 obj\r<< \r/D [ 206 0 R /XYZ 282 540 null ] \r>> \rendobj\r3539 0 obj\r<< \r/D [ 206 0 R /XYZ 91 525 null ] \r>> \rendobj\r3540 0 obj\r<< \r/D [ 206 0 R /XYZ 282 525 null ] \r>> \rendobj\r3541 0 obj\r<< \r/D [ 206 0 R /XYZ 186 410 null ] \r>> \rendobj\r3542 0 obj\r<< \r/D [ 206 0 R /XYZ 186 248 null ] \r>> \rendobj\r3543 0 obj\r<< \r/D [ 209 0 R /XYZ null null null ] \r>> \rendobj\r3544 0 obj\r<< \r/D [ 209 0 R /XYZ 304 555 null ] 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209 0 R /XYZ 56 185 null ] \r>> \rendobj\r3561 0 obj\r<< \r/D [ 209 0 R /XYZ 56 173 null ] \r>> \rendobj\r3562 0 obj\r<< \r/D [ 209 0 R /XYZ 186 703 null ] \r>> \rendobj\r3563 0 obj\r<< \r/D [ 209 0 R /XYZ 186 550 null ] \r>> \rendobj\r3564 0 obj\r<< \r/D [ 209 0 R /XYZ 186 396 null ] \r>> \rendobj\r3565 0 obj\r<< \r/D [ 209 0 R /XYZ 186 232 null ] \r>> \rendobj\r3566 0 obj\r<< \r/D [ 212 0 R /XYZ null null null ] \r>> \rendobj\r3567 0 obj\r<< \r/D [ 212 0 R /XYZ 127 348 null ] \r>> \rendobj\r3568 0 obj\r<< \r/D [ 212 0 R /XYZ 127 348 null ] \r>> \rendobj\r3569 0 obj\r<< \r/D [ 212 0 R /XYZ 127 517 null ] \r>> \rendobj\r3570 0 obj\r<< \r/D [ 212 0 R /XYZ 127 517 null ] \r>> \rendobj\r3571 0 obj\r<< \r/D [ 212 0 R /XYZ 91 625 null ] \r>> \rendobj\r3572 0 obj\r<< \r/D [ 212 0 R /XYZ 56 774 null ] \r>> \rendobj\r3573 0 obj\r<< \r/D [ 212 0 R /XYZ 56 668 null ] \r>> \rendobj\r3574 0 obj\r<< \r/D [ 212 0 R /XYZ 56 656 null ] \r>> \rendobj\r3575 0 obj\r<< \r/D [ 212 0 R /XYZ 56 644 null ] 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91 212 null ] \r>> \rendobj\r3638 0 obj\r<< \r/D [ 212 0 R /XYZ 169 212 null ] \r>> \rendobj\r3639 0 obj\r<< \r/D [ 212 0 R /XYZ 254 212 null ] \r>> \rendobj\r3640 0 obj\r<< \r/D [ 212 0 R /XYZ 297 212 null ] \r>> \rendobj\r3641 0 obj\r<< \r/D [ 212 0 R /XYZ 481 212 null ] \r>> \rendobj\r3642 0 obj\r<< \r/D [ 212 0 R /XYZ 169 197 null ] \r>> \rendobj\r3643 0 obj\r<< \r/D [ 212 0 R /XYZ 297 197 null ] \r>> \rendobj\r3644 0 obj\r<< \r/D [ 212 0 R /XYZ 481 197 null ] \r>> \rendobj\r3645 0 obj\r<< \r/D [ 212 0 R /XYZ 169 182 null ] \r>> \rendobj\r3646 0 obj\r<< \r/D [ 212 0 R /XYZ 297 182 null ] \r>> \rendobj\r3647 0 obj\r<< \r/D [ 212 0 R /XYZ 481 182 null ] \r>> \rendobj\r3648 0 obj\r<< \r/D [ 212 0 R /XYZ 91 167 null ] \r>> \rendobj\r3649 0 obj\r<< \r/D [ 212 0 R /XYZ 186 703 null ] \r>> \rendobj\r3650 0 obj\r<< \r/D [ 217 0 R /XYZ null null null ] \r>> \rendobj\r3651 0 obj\r<< \r/D [ 217 0 R /XYZ null null null ] \r>> \rendobj\r3652 0 obj\r<< \r/D [ 217 0 R /XYZ 127 733 null ] \r>> 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null ] \r>> \rendobj\r7872 0 obj\r<< \r/D [ 494 0 R /XYZ 460 619 null ] \r>> \rendobj\r7873 0 obj\r<< \r/D [ 494 0 R /XYZ 91 604 null ] \r>> \rendobj\r7874 0 obj\r<< \r/D [ 494 0 R /XYZ 112 604 null ] \r>> \rendobj\r7875 0 obj\r<< \r/D [ 494 0 R /XYZ 240 604 null ] \r>> \rendobj\r7876 0 obj\r<< \r/D [ 494 0 R /XYZ 368 604 null ] \r>> \rendobj\r7877 0 obj\r<< \r/D [ 494 0 R /XYZ 460 604 null ] \r>> \rendobj\r7878 0 obj\r<< \r/D [ 494 0 R /XYZ 91 589 null ] \r>> \rendobj\r7879 0 obj\r<< \r/D [ 494 0 R /XYZ 112 589 null ] \r>> \rendobj\r7880 0 obj\r<< \r/D [ 494 0 R /XYZ 240 589 null ] \r>> \rendobj\r7881 0 obj\r<< \r/D [ 494 0 R /XYZ 368 589 null ] \r>> \rendobj\r7882 0 obj\r<< \r/D [ 494 0 R /XYZ 460 589 null ] \r>> \rendobj\r7883 0 obj\r<< \r/D [ 494 0 R /XYZ 91 574 null ] \r>> \rendobj\r7884 0 obj\r<< \r/D [ 494 0 R /XYZ 112 574 null ] \r>> \rendobj\r7885 0 obj\r<< \r/D [ 494 0 R /XYZ 240 574 null ] \r>> \rendobj\r7886 0 obj\r<< \r/D [ 494 0 R /XYZ 368 574 null ] \r>> \rendobj\r7887 0 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460 529 null ] \r>> \rendobj\r7903 0 obj\r<< \r/D [ 494 0 R /XYZ 91 514 null ] \r>> \rendobj\r7904 0 obj\r<< \r/D [ 494 0 R /XYZ 112 514 null ] \r>> \rendobj\r7905 0 obj\r<< \r/D [ 494 0 R /XYZ 240 514 null ] \r>> \rendobj\r7906 0 obj\r<< \r/D [ 494 0 R /XYZ 368 514 null ] \r>> \rendobj\r7907 0 obj\r<< \r/D [ 494 0 R /XYZ 460 514 null ] \r>> \rendobj\r7908 0 obj\r<< \r/D [ 494 0 R /XYZ 91 499 null ] \r>> \rendobj\r7909 0 obj\r<< \r/D [ 494 0 R /XYZ 112 499 null ] \r>> \rendobj\r7910 0 obj\r<< \r/D [ 494 0 R /XYZ 240 499 null ] \r>> \rendobj\r7911 0 obj\r<< \r/D [ 494 0 R /XYZ 368 499 null ] \r>> \rendobj\r7912 0 obj\r<< \r/D [ 494 0 R /XYZ 460 499 null ] \r>> \rendobj\r7913 0 obj\r<< \r/D [ 494 0 R /XYZ 91 484 null ] \r>> \rendobj\r7914 0 obj\r<< \r/D [ 494 0 R /XYZ 112 484 null ] \r>> \rendobj\r7915 0 obj\r<< \r/D [ 494 0 R /XYZ 240 484 null ] \r>> \rendobj\r7916 0 obj\r<< \r/D [ 494 0 R /XYZ 368 484 null ] \r>> \rendobj\r7917 0 obj\r<< \r/D [ 494 0 R /XYZ 460 484 null ] \r>> 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(G10.1055686)4945 0 R \r(G10.1055718)4959 0 R (G10.1055719)4946 0 R (G10.1055720)4947 0 R \r(G10.1055721)4948 0 R (G10.1055722)4949 0 R (G10.1055723)4950 0 R \r(G10.1055724)4951 0 R (G10.1055725)4952 0 R (G10.1055726)4953 0 R \r(G10.1055727)4954 0 R (G10.1055728)4955 0 R (G10.1055729)4956 0 R \r(G10.1055730)4966 0 R (G10.1055737)4971 0 R (G10.1055745)4972 0 R \r(G10.1055747)4973 0 R ] \r>> \rendobj\r9664 0 obj\r<< \r/Limits [ (G10.1055749)(G10.1055885)] \r/Names [ (G10.1055749)4974 0 R (G10.1055751)4975 0 R (G10.1055753)4976 0 R \r(G10.1055755)4977 0 R (G10.1055757)4978 0 R (G10.1055759)4979 0 R \r(G10.1055761)4980 0 R (G10.1055763)4981 0 R (G10.1055765)4982 0 R \r(G10.1055767)4983 0 R (G10.1055769)4984 0 R (G10.1055771)4985 0 R \r(G10.1055773)4986 0 R (G10.1055775)4987 0 R (G10.1055777)4988 0 R \r(G10.1055779)4989 0 R (G10.1055781)4990 0 R (G10.1055783)4991 0 R \r(G10.1055785)4992 0 R (G10.1055787)4993 0 R (G10.1055789)4994 0 R \r(G10.1055791)4995 0 R (G10.1055793)4996 0 R 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(G10.1055887)(G10.1056204)] \r/Names [ (G10.1055887)5036 0 R (G10.1055889)5037 0 R (G10.1055891)5038 0 R \r(G10.1055893)5039 0 R (G10.1055895)5040 0 R (G10.1055897)5041 0 R \r(G10.1055899)5042 0 R (G10.1055901)5043 0 R (G10.1055905)5044 0 R \r(G10.1055907)5045 0 R (G10.1055909)5046 0 R (G10.1055911)5047 0 R \r(G10.1055913)5048 0 R (G10.1055915)5049 0 R (G10.1055917)5050 0 R \r(G10.1055919)5051 0 R (G10.1055921)5052 0 R (G10.1055925)5053 0 R \r(G10.1055927)5054 0 R (G10.1055929)5055 0 R (G10.1055931)5056 0 R \r(G10.1055935)5057 0 R (G10.1055937)5058 0 R (G10.1055939)5059 0 R \r(G10.1055941)5060 0 R (G10.1055943)5061 0 R (G10.1055952)4969 0 R \r(G10.1056144)5066 0 R (G10.1056151)5112 0 R (G10.1056159)5113 0 R \r(G10.1056161)5114 0 R (G10.1056163)5115 0 R (G10.1056165)5116 0 R \r(G10.1056167)5117 0 R (G10.1056169)5118 0 R (G10.1056171)5119 0 R \r(G10.1056173)5120 0 R (G10.1056175)5121 0 R (G10.1056177)5122 0 R \r(G10.1056179)5123 0 R (G10.1056181)5124 0 R (G10.1056182)5067 0 R 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(G11.1040563)5157 0 R \r(G11.1040577)5262 0 R ] \r>> \rendobj\r9667 0 obj\r<< \r/Limits [ (G11.1040578)(G11.1040723)] \r/Names [ (G11.1040578)5184 0 R (G11.1040579)5185 0 R (G11.1040580)5186 0 R \r(G11.1040581)5187 0 R (G11.1040588)5192 0 R (G11.1040596)5193 0 R \r(G11.1040598)5194 0 R (G11.1040600)5195 0 R (G11.1040602)5196 0 R \r(G11.1040604)5197 0 R (G11.1040606)5198 0 R (G11.1040608)5199 0 R \r(G11.1040610)5200 0 R (G11.1040612)5201 0 R (G11.1040614)5202 0 R \r(G11.1040616)5203 0 R (G11.1040618)5204 0 R (G11.1040620)5205 0 R \r(G11.1040622)5206 0 R (G11.1040624)5207 0 R (G11.1040626)5208 0 R \r(G11.1040628)5209 0 R (G11.1040630)5210 0 R (G11.1040632)5211 0 R \r(G11.1040634)5212 0 R (G11.1040636)5213 0 R (G11.1040638)5214 0 R \r(G11.1040640)5215 0 R (G11.1040642)5216 0 R (G11.1040644)5217 0 R \r(G11.1040646)5218 0 R (G11.1040648)5219 0 R (G11.1040650)5220 0 R \r(G11.1040651)5188 0 R (G11.1040652)5189 0 R (G11.1040659)5221 0 R \r(G11.1040669)5222 0 R (G11.1040671)5223 0 R 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(G12.1079592)5494 0 R (G12.1079596)5495 0 R \r(G12.1079598)5496 0 R (G12.1079600)5497 0 R (G12.1079602)5498 0 R \r(G12.1079606)5499 0 R (G12.1079608)5500 0 R (G12.1079610)5501 0 R \r(G12.1079612)5502 0 R (G12.1079616)5503 0 R (G12.1079618)5504 0 R \r(G12.1079620)5505 0 R (G12.1079622)5506 0 R (G12.1079624)5507 0 R \r(G12.1079633)5413 0 R (G12.1079641)5508 0 R (G12.1079649)5509 0 R \r(G12.1079651)5510 0 R (G12.1079653)5511 0 R (G12.1079655)5512 0 R \r(G12.1079657)5513 0 R (G12.1079659)5514 0 R (G12.1079661)5515 0 R \r(G12.1079663)5516 0 R (G12.1079665)5517 0 R (G12.1079667)5518 0 R \r(G12.1079669)5519 0 R (G12.1079671)5520 0 R (G12.1079672)5415 0 R \r(G12.1079675)5419 0 R (G12.1079676)5420 0 R (G12.1079677)5421 0 R \r(G12.1079678)5422 0 R (G12.1079679)5423 0 R (G12.1079680)5522 0 R \r(G12.1079681)5523 0 R (G12.1079682)5524 0 R (G12.1079683)5525 0 R \r(G12.1079684)5526 0 R (G12.1079685)5527 0 R (G12.1079686)5528 0 R \r(G12.1079687)5529 0 R (G12.1079688)5530 0 R (G12.1079689)5531 0 R \r(G12.1079690)5532 0 R (G12.1079691)5533 0 R (G12.1079692)5534 0 R \r(G12.1079693)5535 0 R (G12.1079694)5536 0 R (G12.1079695)5537 0 R \r(G12.1079696)5538 0 R (G12.1079697)5539 0 R (G12.1079698)5540 0 R \r(G12.1079699)5541 0 R ] \r>> \rendobj\r9671 0 obj\r<< \r/Limits [ (G12.1079700)(G12.1081198)] \r/Names [ (G12.1079700)5542 0 R (G12.1079701)5543 0 R (G12.1079702)5544 0 R \r(G12.1079703)5545 0 R (G12.1079704)5546 0 R (G12.1079709)5547 0 R \r(G12.1079763)5362 0 R (G12.1079765)5391 0 R (G12.1079974)5416 0 R \r(G12.1079978)5352 0 R (G12.1079989)5366 0 R (G12.1080557)5381 0 R \r(G12.1080572)5414 0 R (G12.1080697)5364 0 R (G12.1081114)5574 0 R \r(G12.1081136)5575 0 R (G12.1081138)5576 0 R (G12.1081140)5577 0 R \r(G12.1081142)5578 0 R (G12.1081144)5579 0 R (G12.1081146)5580 0 R \r(G12.1081148)5581 0 R (G12.1081150)5582 0 R (G12.1081152)5583 0 R \r(G12.1081154)5584 0 R (G12.1081156)5585 0 R (G12.1081158)5586 0 R \r(G12.1081160)5587 0 R (G12.1081162)5588 0 R (G12.1081164)5589 0 R \r(G12.1081165)5590 0 R (G12.1081166)5591 0 R (G12.1081167)5592 0 R \r(G12.1081168)5593 0 R (G12.1081169)5594 0 R (G12.1081170)5595 0 R \r(G12.1081171)5596 0 R (G12.1081172)5597 0 R (G12.1081173)5598 0 R \r(G12.1081174)5599 0 R (G12.1081175)5600 0 R (G12.1081176)5601 0 R \r(G12.1081177)5602 0 R (G12.1081178)5603 0 R (G12.1081179)5604 0 R \r(G12.1081180)5605 0 R (G12.1081181)5606 0 R (G12.1081182)5607 0 R \r(G12.1081183)5608 0 R (G12.1081184)5609 0 R (G12.1081185)5610 0 R \r(G12.1081186)5611 0 R (G12.1081187)5612 0 R (G12.1081188)5613 0 R \r(G12.1081189)5614 0 R (G12.1081190)5615 0 R (G12.1081191)5616 0 R \r(G12.1081192)5617 0 R (G12.1081193)5618 0 R (G12.1081194)5619 0 R \r(G12.1081195)5620 0 R (G12.1081196)5621 0 R (G12.1081197)5622 0 R \r(G12.1081198)5623 0 R ] \r>> \rendobj\r9672 0 obj\r<< \r/Limits [ (G12.1081200)(G12.1081303)] \r/Names [ (G12.1081200)5624 0 R (G12.1081202)5625 0 R (G12.1081204)5626 0 R \r(G12.1081206)5627 0 R (G12.1081207)5628 0 R (G12.1081208)5629 0 R \r(G12.1081209)5630 0 R (G12.1081210)5631 0 R (G12.1081211)5632 0 R \r(G12.1081212)5633 0 R (G12.1081213)5634 0 R (G12.1081214)5635 0 R \r(G12.1081215)5636 0 R (G12.1081216)5637 0 R (G12.1081217)5638 0 R \r(G12.1081218)5639 0 R (G12.1081219)5640 0 R (G12.1081220)5641 0 R \r(G12.1081221)5642 0 R (G12.1081222)5643 0 R (G12.1081223)5644 0 R \r(G12.1081224)5645 0 R (G12.1081225)5646 0 R (G12.1081226)5647 0 R \r(G12.1081227)5648 0 R (G12.1081228)5649 0 R (G12.1081229)5650 0 R \r(G12.1081230)5651 0 R (G12.1081231)5652 0 R (G12.1081232)5653 0 R \r(G12.1081233)5654 0 R (G12.1081234)5655 0 R (G12.1081235)5656 0 R \r(G12.1081236)5657 0 R (G12.1081237)5658 0 R (G12.1081238)5659 0 R \r(G12.1081239)5660 0 R (G12.1081241)5661 0 R (G12.1081243)5662 0 R \r(G12.1081245)5663 0 R (G12.1081247)5664 0 R (G12.1081249)5665 0 R \r(G12.1081251)5666 0 R (G12.1081255)5667 0 R (G12.1081257)5668 0 R \r(G12.1081259)5669 0 R (G12.1081263)5670 0 R (G12.1081265)5671 0 R \r(G12.1081267)5672 0 R (G12.1081269)5673 0 R (G12.1081271)5674 0 R \r(G12.1081273)5675 0 R (G12.1081277)5676 0 R (G12.1081279)5677 0 R \r(G12.1081281)5678 0 R (G12.1081285)5679 0 R (G12.1081287)5680 0 R \r(G12.1081289)5681 0 R (G12.1081291)5682 0 R (G12.1081293)5683 0 R \r(G12.1081295)5684 0 R (G12.1081299)5685 0 R (G12.1081301)5686 0 R \r(G12.1081303)5687 0 R ] \r>> \rendobj\r9673 0 obj\r<< \r/Limits [ (G12.1081307)(G12.1081461)] \r/Names [ (G12.1081307)5688 0 R (G12.1081309)5689 0 R (G12.1081311)5690 0 R \r(G12.1081313)5691 0 R (G12.1081315)5692 0 R (G12.1081317)5693 0 R \r(G12.1081321)5694 0 R (G12.1081323)5695 0 R (G12.1081325)5696 0 R \r(G12.1081329)5697 0 R (G12.1081331)5698 0 R (G12.1081333)5699 0 R \r(G12.1081335)5700 0 R (G12.1081337)5701 0 R (G12.1081339)5702 0 R \r(G12.1081343)5703 0 R (G12.1081345)5704 0 R (G12.1081347)5705 0 R \r(G12.1081351)5706 0 R (G12.1081353)5707 0 R (G12.1081355)5708 0 R \r(G12.1081357)5709 0 R (G12.1081359)5710 0 R (G12.1081361)5711 0 R \r(G12.1081365)5712 0 R (G12.1081367)5713 0 R (G12.1081369)5714 0 R \r(G12.1081373)5715 0 R (G12.1081375)5716 0 R (G12.1081377)5717 0 R \r(G12.1081379)5718 0 R (G12.1081381)5719 0 R (G12.1081383)5720 0 R \r(G12.1081387)5721 0 R (G12.1081389)5722 0 R (G12.1081391)5723 0 R \r(G12.1081395)5724 0 R (G12.1081397)5725 0 R (G12.1081399)5726 0 R \r(G12.1081401)5727 0 R (G12.1081403)5728 0 R (G12.1081405)5729 0 R \r(G12.1081409)5730 0 R (G12.1081411)5731 0 R (G12.1081413)5732 0 R \r(G12.1081417)5733 0 R (G12.1081419)5734 0 R (G12.1081421)5735 0 R \r(G12.1081423)5736 0 R (G12.1081425)5737 0 R (G12.1081427)5738 0 R \r(G12.1081431)5739 0 R (G12.1081433)5740 0 R (G12.1081435)5741 0 R \r(G12.1081439)5742 0 R (G12.1081441)5743 0 R (G12.1081443)5744 0 R \r(G12.1081445)5745 0 R (G12.1081447)5746 0 R (G12.1081449)5747 0 R \r(G12.1081453)5748 0 R (G12.1081455)5749 0 R (G12.1081457)5750 0 R \r(G12.1081461)5751 0 R ] \r>> \rendobj\r9674 0 obj\r<< \r/Limits [ (G12.1081463)(G12.1081617)] \r/Names [ (G12.1081463)5752 0 R (G12.1081465)5753 0 R (G12.1081467)5754 0 R \r(G12.1081469)5755 0 R (G12.1081471)5756 0 R (G12.1081475)5757 0 R \r(G12.1081477)5758 0 R (G12.1081479)5759 0 R (G12.1081483)5760 0 R \r(G12.1081485)5761 0 R (G12.1081487)5762 0 R (G12.1081489)5763 0 R \r(G12.1081491)5764 0 R (G12.1081493)5765 0 R (G12.1081497)5766 0 R \r(G12.1081499)5767 0 R (G12.1081501)5768 0 R (G12.1081505)5769 0 R \r(G12.1081507)5770 0 R (G12.1081509)5771 0 R (G12.1081511)5772 0 R \r(G12.1081513)5773 0 R (G12.1081515)5774 0 R (G12.1081519)5775 0 R \r(G12.1081521)5776 0 R (G12.1081523)5777 0 R (G12.1081527)5778 0 R \r(G12.1081529)5779 0 R (G12.1081531)5780 0 R (G12.1081533)5781 0 R \r(G12.1081535)5782 0 R (G12.1081537)5783 0 R (G12.1081541)5784 0 R \r(G12.1081543)5785 0 R (G12.1081545)5786 0 R (G12.1081549)5787 0 R \r(G12.1081551)5788 0 R (G12.1081553)5789 0 R (G12.1081555)5790 0 R \r(G12.1081557)5791 0 R (G12.1081559)5792 0 R (G12.1081563)5793 0 R \r(G12.1081565)5794 0 R (G12.1081567)5795 0 R (G12.1081571)5796 0 R \r(G12.1081573)5797 0 R (G12.1081575)5798 0 R (G12.1081577)5799 0 R \r(G12.1081579)5800 0 R (G12.1081581)5801 0 R (G12.1081585)5802 0 R \r(G12.1081587)5803 0 R (G12.1081589)5804 0 R (G12.1081593)5805 0 R \r(G12.1081595)5806 0 R (G12.1081597)5807 0 R (G12.1081599)5808 0 R \r(G12.1081601)5809 0 R (G12.1081603)5810 0 R (G12.1081607)5811 0 R \r(G12.1081609)5812 0 R (G12.1081611)5813 0 R (G12.1081615)5814 0 R \r(G12.1081617)5815 0 R ] \r>> \rendobj\r9675 0 obj\r<< \r/Limits [ (G12.1081619)(G12.1081773)] \r/Names [ (G12.1081619)5816 0 R (G12.1081621)5817 0 R (G12.1081623)5818 0 R \r(G12.1081625)5819 0 R (G12.1081629)5820 0 R (G12.1081631)5821 0 R \r(G12.1081633)5822 0 R (G12.1081637)5823 0 R (G12.1081639)5824 0 R \r(G12.1081641)5825 0 R (G12.1081643)5826 0 R (G12.1081645)5827 0 R \r(G12.1081647)5828 0 R (G12.1081651)5829 0 R (G12.1081653)5830 0 R \r(G12.1081655)5831 0 R (G12.1081659)5832 0 R (G12.1081661)5833 0 R \r(G12.1081663)5834 0 R (G12.1081665)5835 0 R (G12.1081667)5836 0 R \r(G12.1081669)5837 0 R (G12.1081673)5838 0 R (G12.1081675)5839 0 R \r(G12.1081677)5840 0 R (G12.1081681)5841 0 R (G12.1081683)5842 0 R \r(G12.1081685)5843 0 R (G12.1081687)5844 0 R (G12.1081689)5845 0 R \r(G12.1081691)5846 0 R (G12.1081695)5847 0 R (G12.1081697)5848 0 R \r(G12.1081699)5849 0 R (G12.1081703)5850 0 R (G12.1081705)5851 0 R \r(G12.1081707)5852 0 R (G12.1081709)5853 0 R (G12.1081711)5854 0 R \r(G12.1081713)5855 0 R (G12.1081717)5856 0 R (G12.1081719)5857 0 R \r(G12.1081721)5858 0 R (G12.1081725)5859 0 R (G12.1081727)5860 0 R \r(G12.1081729)5861 0 R (G12.1081731)5862 0 R (G12.1081733)5863 0 R \r(G12.1081735)5864 0 R (G12.1081739)5865 0 R (G12.1081741)5866 0 R \r(G12.1081743)5867 0 R (G12.1081747)5868 0 R (G12.1081749)5869 0 R \r(G12.1081751)5870 0 R (G12.1081753)5871 0 R (G12.1081755)5872 0 R \r(G12.1081757)5873 0 R (G12.1081761)5874 0 R (G12.1081763)5875 0 R \r(G12.1081765)5876 0 R (G12.1081769)5877 0 R (G12.1081771)5878 0 R \r(G12.1081773)5879 0 R ] \r>> \rendobj\r9676 0 obj\r<< \r/Limits [ (G12.1081775)(G12.1081929)] \r/Names [ (G12.1081775)5880 0 R (G12.1081777)5881 0 R (G12.1081779)5882 0 R \r(G12.1081783)5883 0 R (G12.1081785)5884 0 R (G12.1081787)5885 0 R \r(G12.1081791)5886 0 R (G12.1081793)5887 0 R (G12.1081795)5888 0 R \r(G12.1081797)5889 0 R (G12.1081799)5890 0 R (G12.1081801)5891 0 R \r(G12.1081805)5892 0 R (G12.1081807)5893 0 R (G12.1081809)5894 0 R \r(G12.1081813)5895 0 R (G12.1081815)5896 0 R (G12.1081817)5897 0 R \r(G12.1081819)5898 0 R (G12.1081821)5899 0 R (G12.1081823)5900 0 R \r(G12.1081827)5901 0 R (G12.1081829)5902 0 R (G12.1081831)5903 0 R \r(G12.1081835)5904 0 R (G12.1081837)5905 0 R (G12.1081839)5906 0 R \r(G12.1081841)5907 0 R (G12.1081843)5908 0 R (G12.1081845)5909 0 R \r(G12.1081849)5910 0 R (G12.1081851)5911 0 R (G12.1081853)5912 0 R \r(G12.1081857)5913 0 R (G12.1081859)5914 0 R (G12.1081861)5915 0 R \r(G12.1081863)5916 0 R (G12.1081865)5917 0 R (G12.1081867)5918 0 R \r(G12.1081871)5919 0 R (G12.1081873)5920 0 R (G12.1081875)5921 0 R \r(G12.1081879)5922 0 R (G12.1081881)5923 0 R (G12.1081883)5924 0 R \r(G12.1081885)5925 0 R (G12.1081887)5926 0 R (G12.1081889)5927 0 R \r(G12.1081893)5928 0 R (G12.1081895)5929 0 R (G12.1081897)5930 0 R \r(G12.1081901)5931 0 R (G12.1081903)5932 0 R (G12.1081905)5933 0 R \r(G12.1081907)5934 0 R (G12.1081909)5935 0 R (G12.1081911)5936 0 R \r(G12.1081915)5937 0 R (G12.1081917)5938 0 R (G12.1081919)5939 0 R \r(G12.1081923)5940 0 R (G12.1081925)5941 0 R (G12.1081927)5942 0 R \r(G12.1081929)5943 0 R ] \r>> \rendobj\r9677 0 obj\r<< \r/Limits [ (G12.1081931)(G12.1082071)] \r/Names [ (G12.1081931)5944 0 R (G12.1081933)5945 0 R (G12.1081937)5946 0 R \r(G12.1081939)5947 0 R (G12.1081941)5948 0 R (G12.1081945)5949 0 R \r(G12.1081947)5950 0 R (G12.1081949)5951 0 R (G12.1081951)5952 0 R \r(G12.1081953)5953 0 R (G12.1081955)5954 0 R (G12.1081959)5955 0 R \r(G12.1081961)5956 0 R (G12.1081963)5957 0 R (G12.1081967)5958 0 R \r(G12.1081969)5959 0 R (G12.1081971)5960 0 R (G12.1081973)5961 0 R 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(G12.1082069)6007 0 R \r(G12.1082071)6008 0 R ] \r>> \rendobj\r9678 0 obj\r<< \r/Limits [ (G12.1082073)(G12.1082208)] \r/Names [ (G12.1082073)6009 0 R (G12.1082075)6010 0 R (G12.1082077)6011 0 R \r(G12.1082079)6012 0 R (G12.1082081)6013 0 R (G12.1082083)6014 0 R \r(G12.1082085)6015 0 R (G12.1082087)6016 0 R (G12.1082089)6017 0 R \r(G12.1082091)6018 0 R (G12.1082093)6019 0 R (G12.1082095)6020 0 R \r(G12.1082097)6021 0 R (G12.1082099)6022 0 R (G12.1082101)6023 0 R \r(G12.1082103)6024 0 R (G12.1082105)6025 0 R (G12.1082107)6026 0 R \r(G12.1082109)6027 0 R (G12.1082111)6028 0 R (G12.1082113)6029 0 R \r(G12.1082115)6030 0 R (G12.1082117)6031 0 R (G12.1082118)5972 0 R \r(G12.1082121)6032 0 R (G12.1082127)6033 0 R (G12.1082129)6034 0 R \r(G12.1082131)6035 0 R (G12.1082133)6036 0 R (G12.1082135)6037 0 R \r(G12.1082137)6038 0 R (G12.1082139)6039 0 R (G12.1082141)6040 0 R \r(G12.1082143)6041 0 R (G12.1082145)6042 0 R (G12.1082147)6043 0 R \r(G12.1082149)6044 0 R (G12.1082150)5973 0 R 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(G12.1082448)6179 0 R (G12.1082450)6180 0 R \r(G12.1082452)6181 0 R (G12.1082454)6182 0 R (G12.1082458)6183 0 R \r(G12.1082460)6184 0 R (G12.1082464)6185 0 R (G12.1082466)6186 0 R \r(G12.1082470)6187 0 R (G12.1082472)6188 0 R (G12.1082474)6189 0 R \r(G12.1082476)6190 0 R (G12.1082480)6191 0 R (G12.1082482)6192 0 R \r(G12.1082486)6193 0 R (G12.1082488)6194 0 R (G12.1082492)6195 0 R \r(G12.1082494)6196 0 R (G12.1082496)6197 0 R (G12.1082498)6198 0 R \r(G12.1082502)6199 0 R (G12.1082504)6200 0 R (G12.1082508)6201 0 R \r(G12.1082510)6202 0 R (G12.1082514)6203 0 R (G12.1082516)6204 0 R \r(G12.1082518)6205 0 R (G12.1082520)6206 0 R (G12.1082524)6207 0 R \r(G12.1082526)6208 0 R ] \r>> \rendobj\r9681 0 obj\r<< \r/Limits [ (G12.1082530)(G12.1084757)] \r/Names [ (G12.1082530)6209 0 R (G12.1082532)6210 0 R (G12.1082536)6211 0 R \r(G12.1082538)6212 0 R (G12.1082539)6111 0 R (G12.1082542)6213 0 R \r(G12.1082546)6214 0 R (G12.1082548)6215 0 R (G12.1082550)6216 0 R \r(G12.1082552)6217 0 R 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(G14.1063440)6446 0 R (G14.1063441)6434 0 R \r(G14.1063442)6455 0 R (G14.1063443)6456 0 R (G14.1063444)6457 0 R \r(G14.1063451)6468 0 R (G14.1063459)6469 0 R (G14.1063461)6470 0 R \r(G14.1063463)6471 0 R (G14.1063465)6472 0 R (G14.1063467)6473 0 R \r(G14.1063469)6474 0 R (G14.1063471)6475 0 R (G14.1063473)6476 0 R \r(G14.1063475)6477 0 R (G14.1063477)6478 0 R (G14.1063479)6479 0 R \r(G14.1063481)6480 0 R ] \r>> \rendobj\r9686 0 obj\r<< \r/Limits [ (G14.1063483)(G14.1063626)] \r/Names [ (G14.1063483)6481 0 R (G14.1063485)6482 0 R (G14.1063487)6483 0 R \r(G14.1063489)6484 0 R (G14.1063491)6485 0 R (G14.1063493)6486 0 R \r(G14.1063495)6487 0 R (G14.1063497)6488 0 R (G14.1063498)6458 0 R \r(G14.1063499)6459 0 R (G14.1063506)6489 0 R (G14.1063516)6490 0 R \r(G14.1063518)6491 0 R (G14.1063520)6492 0 R (G14.1063522)6493 0 R \r(G14.1063524)6494 0 R (G14.1063526)6495 0 R (G14.1063528)6496 0 R \r(G14.1063530)6497 0 R (G14.1063532)6498 0 R (G14.1063534)6499 0 R \r(G14.1063536)6500 0 R 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(G14.1063628)(G14.1063731)] \r/Names [ (G14.1063628)6543 0 R (G14.1063630)6544 0 R (G14.1063632)6545 0 R \r(G14.1063634)6546 0 R (G14.1063636)6547 0 R (G14.1063645)6460 0 R \r(G14.1063650)6461 0 R (G14.1063657)6548 0 R (G14.1063665)6549 0 R \r(G14.1063667)6550 0 R (G14.1063669)6551 0 R (G14.1063671)6552 0 R \r(G14.1063673)6553 0 R (G14.1063675)6554 0 R (G14.1063677)6555 0 R \r(G14.1063679)6556 0 R (G14.1063681)6557 0 R (G14.1063683)6558 0 R \r(G14.1063685)6559 0 R (G14.1063687)6560 0 R (G14.1063688)6462 0 R \r(G14.1063689)6463 0 R (G14.1063690)6464 0 R (G14.1063691)6465 0 R \r(G14.1063692)6466 0 R (G14.1063693)6467 0 R (G14.1063694)6563 0 R \r(G14.1063695)6564 0 R (G14.1063696)6565 0 R (G14.1063697)6566 0 R \r(G14.1063698)6567 0 R (G14.1063699)6568 0 R (G14.1063700)6569 0 R \r(G14.1063701)6570 0 R (G14.1063702)6571 0 R (G14.1063703)6572 0 R \r(G14.1063704)6573 0 R (G14.1063705)6574 0 R (G14.1063706)6575 0 R \r(G14.1063707)6576 0 R (G14.1063708)6577 0 R (G14.1063709)6578 0 R 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(G15.1055716)6784 0 R \r(G15.1055717)6743 0 R ] \r>> \rendobj\r9689 0 obj\r<< \r/Limits [ (G15.1056351)(G15.1057071)] \r/Names [ (G15.1056351)6793 0 R (G15.1056358)6900 0 R (G15.1056366)6901 0 R \r(G15.1056368)6902 0 R (G15.1056370)6903 0 R (G15.1056372)6904 0 R \r(G15.1056374)6905 0 R (G15.1056376)6906 0 R (G15.1056378)6907 0 R \r(G15.1056380)6908 0 R (G15.1056382)6909 0 R (G15.1056384)6910 0 R \r(G15.1056386)6911 0 R (G15.1056388)6912 0 R (G15.1056389)6794 0 R \r(G15.1056390)6795 0 R (G15.1056391)6796 0 R (G15.1056392)6797 0 R \r(G15.1056393)6798 0 R (G15.1056394)6799 0 R (G15.1056395)6800 0 R \r(G15.1056396)6801 0 R (G15.1056397)6802 0 R (G15.1056398)6803 0 R \r(G15.1056399)6804 0 R (G15.1056400)6805 0 R (G15.1056401)6915 0 R \r(G15.1056402)6916 0 R (G15.1056403)6917 0 R (G15.1056404)6918 0 R \r(G15.1056405)6919 0 R (G15.1056406)6920 0 R (G15.1056407)6921 0 R \r(G15.1056408)6922 0 R (G15.1056409)6923 0 R (G15.1056410)6924 0 R \r(G15.1056411)6925 0 R (G15.1056412)6926 0 R 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(G17.1141160)7635 0 R \r(G17.1141161)7636 0 R (G17.1141162)7694 0 R (G17.1141165)7707 0 R \r(G17.1141171)7708 0 R (G17.1141173)7709 0 R (G17.1141175)7710 0 R \r(G17.1141177)7711 0 R (G17.1141179)7712 0 R (G17.1141181)7713 0 R \r(G17.1141183)7714 0 R (G17.1141185)7715 0 R (G17.1141187)7716 0 R \r(G17.1141189)7717 0 R (G17.1141191)7718 0 R (G17.1141193)7719 0 R \r(G17.1141195)7720 0 R (G17.1141197)7721 0 R (G17.1141199)7722 0 R \r(G17.1141201)7723 0 R (G17.1141203)7724 0 R (G17.1141205)7725 0 R \r(G17.1141207)7726 0 R (G17.1141209)7727 0 R (G17.1141211)7728 0 R \r(G17.1141213)7729 0 R (G17.1141215)7730 0 R (G17.1141217)7731 0 R \r(G17.1141219)7732 0 R (G17.1141221)7733 0 R (G17.1141223)7734 0 R \r(G17.1141224)7695 0 R (G17.1141225)7696 0 R (G17.1141226)7697 0 R \r(G17.1141227)7698 0 R (G17.1141228)7699 0 R (G17.1141229)7700 0 R \r(G17.1141230)7701 0 R (G17.1141231)7702 0 R (G17.1141234)7735 0 R \r(G17.1141240)7736 0 R (G17.1141242)7737 0 R (G17.1141244)7738 0 R \r(G17.1141246)7739 0 R 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(G17.1141340)7784 0 R (G17.1141342)7785 0 R \r(G17.1141344)7786 0 R (G17.1141346)7787 0 R (G17.1141348)7788 0 R \r(G17.1141350)7789 0 R (G17.1141352)7790 0 R (G17.1141354)7791 0 R \r(G17.1141356)7792 0 R (G17.1141358)7793 0 R (G17.1141360)7794 0 R \r(G17.1141362)7795 0 R (G17.1141364)7796 0 R (G17.1141366)7797 0 R \r(G17.1141368)7798 0 R (G17.1141370)7799 0 R (G17.1141372)7800 0 R \r(G17.1141374)7801 0 R (G17.1141376)7802 0 R (G17.1141378)7803 0 R \r(G17.1141380)7804 0 R (G17.1141382)7805 0 R (G17.1141384)7806 0 R \r(G17.1141386)7807 0 R (G17.1141388)7808 0 R (G17.1141390)7809 0 R \r(G17.1141392)7810 0 R (G17.1141394)7811 0 R (G17.1141396)7812 0 R \r(G17.1141398)7813 0 R ] \r>> \rendobj\r9703 0 obj\r<< \r/Limits [ (G17.1141400)(G17.1141671)] \r/Names [ (G17.1141400)7814 0 R (G17.1141402)7815 0 R (G17.1141404)7816 0 R \r(G17.1141406)7817 0 R (G17.1141422)7818 0 R (G17.1141424)7819 0 R \r(G17.1141426)7820 0 R (G17.1141442)7821 0 R (G17.1141444)7822 0 R \r(G17.1141446)7823 0 R (G17.1141462)7824 0 R (G17.1141464)7825 0 R \r(G17.1141466)7826 0 R (G17.1141482)7827 0 R (G17.1141484)7828 0 R \r(G17.1141486)7829 0 R (G17.1141502)7830 0 R (G17.1141504)7831 0 R \r(G17.1141506)7832 0 R (G17.1141522)7833 0 R (G17.1141524)7834 0 R \r(G17.1141526)7835 0 R (G17.1141542)7836 0 R (G17.1141544)7837 0 R \r(G17.1141546)7838 0 R (G17.1141561)7767 0 R (G17.1141562)7768 0 R \r(G17.1141563)7769 0 R (G17.1141564)7770 0 R (G17.1141565)7771 0 R \r(G17.1141566)7772 0 R (G17.1141567)7773 0 R (G17.1141568)7840 0 R \r(G17.1141571)7844 0 R (G17.1141585)7845 0 R (G17.1141587)7846 0 R \r(G17.1141595)7847 0 R (G17.1141597)7848 0 R (G17.1141601)7849 0 R \r(G17.1141605)7850 0 R (G17.1141609)7851 0 R (G17.1141611)7852 0 R \r(G17.1141613)7853 0 R (G17.1141615)7854 0 R (G17.1141619)7855 0 R \r(G17.1141623)7856 0 R (G17.1141625)7857 0 R (G17.1141627)7858 0 R \r(G17.1141629)7859 0 R (G17.1141633)7860 0 R (G17.1141637)7861 0 R \r(G17.1141639)7862 0 R (G17.1141641)7863 0 R (G17.1141643)7864 0 R \r(G17.1141647)7865 0 R (G17.1141651)7866 0 R (G17.1141653)7867 0 R \r(G17.1141655)7868 0 R (G17.1141657)7869 0 R (G17.1141661)7870 0 R \r(G17.1141665)7871 0 R (G17.1141667)7872 0 R (G17.1141669)7873 0 R \r(G17.1141671)7874 0 R ] \r>> \rendobj\r9704 0 obj\r<< \r/Limits [ (G17.1141675)(G17.1141847)] \r/Names [ (G17.1141675)7875 0 R (G17.1141679)7876 0 R (G17.1141681)7877 0 R \r(G17.1141683)7878 0 R (G17.1141685)7879 0 R (G17.1141689)7880 0 R \r(G17.1141693)7881 0 R (G17.1141695)7882 0 R (G17.1141697)7883 0 R \r(G17.1141699)7884 0 R (G17.1141703)7885 0 R (G17.1141707)7886 0 R \r(G17.1141709)7887 0 R (G17.1141711)7888 0 R (G17.1141713)7889 0 R \r(G17.1141717)7890 0 R (G17.1141721)7891 0 R (G17.1141723)7892 0 R \r(G17.1141725)7893 0 R (G17.1141727)7894 0 R (G17.1141731)7895 0 R \r(G17.1141735)7896 0 R (G17.1141737)7897 0 R (G17.1141739)7898 0 R \r(G17.1141741)7899 0 R (G17.1141745)7900 0 R (G17.1141749)7901 0 R \r(G17.1141751)7902 0 R (G17.1141753)7903 0 R (G17.1141755)7904 0 R \r(G17.1141759)7905 0 R (G17.1141763)7906 0 R (G17.1141765)7907 0 R \r(G17.1141767)7908 0 R (G17.1141769)7909 0 R (G17.1141773)7910 0 R \r(G17.1141777)7911 0 R (G17.1141779)7912 0 R (G17.1141781)7913 0 R \r(G17.1141783)7914 0 R (G17.1141787)7915 0 R (G17.1141791)7916 0 R \r(G17.1141793)7917 0 R (G17.1141795)7918 0 R (G17.1141797)7919 0 R \r(G17.1141801)7920 0 R (G17.1141805)7921 0 R (G17.1141807)7922 0 R \r(G17.1141809)7923 0 R (G17.1141811)7924 0 R (G17.1141815)7925 0 R \r(G17.1141819)7926 0 R (G17.1141821)7927 0 R (G17.1141823)7928 0 R \r(G17.1141825)7929 0 R (G17.1141829)7930 0 R (G17.1141833)7931 0 R \r(G17.1141835)7932 0 R (G17.1141837)7933 0 R (G17.1141839)7934 0 R \r(G17.1141841)7935 0 R (G17.1141843)7936 0 R (G17.1141845)7937 0 R \r(G17.1141847)7938 0 R ] \r>> \rendobj\r9705 0 obj\r<< \r/Limits [ (G17.1141849)(G17.1141975)] \r/Names [ (G17.1141849)7939 0 R (G17.1141851)7940 0 R (G17.1141853)7941 0 R \r(G17.1141855)7942 0 R (G17.1141857)7943 0 R (G17.1141859)7944 0 R \r(G17.1141861)7945 0 R (G17.1141863)7946 0 R (G17.1141865)7947 0 R \r(G17.1141867)7948 0 R (G17.1141869)7949 0 R (G17.1141871)7950 0 R \r(G17.1141873)7951 0 R (G17.1141875)7952 0 R (G17.1141877)7953 0 R \r(G17.1141879)7954 0 R (G17.1141881)7955 0 R (G17.1141883)7956 0 R \r(G17.1141885)7957 0 R (G17.1141887)7958 0 R (G17.1141889)7959 0 R \r(G17.1141891)7960 0 R (G17.1141893)7961 0 R (G17.1141895)7962 0 R \r(G17.1141897)7963 0 R (G17.1141899)7964 0 R (G17.1141901)7965 0 R \r(G17.1141903)7966 0 R (G17.1141905)7967 0 R (G17.1141907)7968 0 R \r(G17.1141909)7969 0 R (G17.1141911)7970 0 R (G17.1141913)7971 0 R \r(G17.1141915)7972 0 R (G17.1141917)7973 0 R (G17.1141919)7974 0 R \r(G17.1141921)7975 0 R (G17.1141923)7976 0 R (G17.1141925)7977 0 R \r(G17.1141927)7978 0 R (G17.1141929)7979 0 R (G17.1141931)7980 0 R \r(G17.1141933)7981 0 R (G17.1141935)7982 0 R (G17.1141937)7983 0 R \r(G17.1141939)7984 0 R (G17.1141941)7985 0 R (G17.1141943)7986 0 R \r(G17.1141945)7987 0 R (G17.1141947)7988 0 R (G17.1141949)7989 0 R \r(G17.1141951)7990 0 R (G17.1141953)7991 0 R (G17.1141955)7992 0 R \r(G17.1141957)7993 0 R (G17.1141959)7994 0 R (G17.1141961)7995 0 R \r(G17.1141963)7996 0 R (G17.1141965)7997 0 R (G17.1141967)7998 0 R \r(G17.1141969)7999 0 R (G17.1141971)8000 0 R (G17.1141973)8001 0 R \r(G17.1141975)8002 0 R ] \r>> \rendobj\r9706 0 obj\r<< \r/Limits [ (G17.1141977)(G17.1142117)] \r/Names [ (G17.1141977)8003 0 R (G17.1141979)8004 0 R (G17.1141981)8005 0 R \r(G17.1141983)8006 0 R (G17.1141985)8007 0 R (G17.1141987)8008 0 R \r(G17.1141989)8009 0 R (G17.1141991)8010 0 R (G17.1141993)8011 0 R \r(G17.1141995)8012 0 R (G17.1141997)8013 0 R (G17.1141999)8014 0 R \r(G17.1142001)8015 0 R (G17.1142003)8016 0 R (G17.1142005)8017 0 R \r(G17.1142007)8018 0 R (G17.1142009)8019 0 R (G17.1142011)8020 0 R \r(G17.1142013)8021 0 R (G17.1142015)8022 0 R (G17.1142017)8023 0 R \r(G17.1142019)8024 0 R (G17.1142021)8025 0 R (G17.1142025)8026 0 R \r(G17.1142029)8027 0 R (G17.1142031)8028 0 R (G17.1142033)8029 0 R \r(G17.1142035)8030 0 R (G17.1142039)8031 0 R (G17.1142043)8032 0 R \r(G17.1142045)8033 0 R (G17.1142047)8034 0 R (G17.1142049)8035 0 R \r(G17.1142053)8036 0 R (G17.1142057)8037 0 R (G17.1142059)8038 0 R \r(G17.1142060)7841 0 R (G17.1142061)7842 0 R (G17.1142062)7843 0 R \r(G17.1142065)8052 0 R (G17.1142071)8053 0 R (G17.1142073)8054 0 R \r(G17.1142075)8055 0 R (G17.1142077)8056 0 R (G17.1142079)8057 0 R \r(G17.1142081)8058 0 R (G17.1142083)8059 0 R (G17.1142085)8060 0 R \r(G17.1142087)8061 0 R (G17.1142089)8062 0 R (G17.1142091)8063 0 R \r(G17.1142093)8064 0 R (G17.1142095)8065 0 R (G17.1142097)8066 0 R \r(G17.1142099)8067 0 R (G17.1142101)8068 0 R (G17.1142103)8069 0 R \r(G17.1142105)8070 0 R (G17.1142107)8071 0 R (G17.1142109)8072 0 R \r(G17.1142111)8073 0 R (G17.1142113)8074 0 R (G17.1142115)8075 0 R \r(G17.1142117)8076 0 R ] \r>> \rendobj\r9707 0 obj\r<< \r/Limits [ (G17.1142119)(G17.1142242)] \r/Names [ (G17.1142119)8077 0 R (G17.1142121)8078 0 R (G17.1142123)8079 0 R \r(G17.1142124)8040 0 R (G17.1142125)8041 0 R (G17.1142126)8042 0 R \r(G17.1142127)8043 0 R (G17.1142128)8044 0 R (G17.1142131)8080 0 R \r(G17.1142137)8081 0 R (G17.1142139)8082 0 R (G17.1142141)8083 0 R \r(G17.1142143)8084 0 R (G17.1142145)8085 0 R (G17.1142147)8086 0 R \r(G17.1142149)8087 0 R (G17.1142151)8088 0 R (G17.1142153)8089 0 R \r(G17.1142155)8090 0 R (G17.1142157)8091 0 R (G17.1142159)8092 0 R \r(G17.1142161)8093 0 R (G17.1142163)8094 0 R (G17.1142165)8095 0 R \r(G17.1142167)8096 0 R (G17.1142169)8097 0 R (G17.1142171)8098 0 R \r(G17.1142173)8099 0 R (G17.1142175)8100 0 R (G17.1142177)8101 0 R \r(G17.1142179)8102 0 R (G17.1142181)8103 0 R (G17.1142183)8104 0 R \r(G17.1142185)8105 0 R (G17.1142187)8106 0 R (G17.1142189)8107 0 R \r(G17.1142190)8045 0 R (G17.1142191)8046 0 R (G17.1142192)8047 0 R \r(G17.1142193)8048 0 R (G17.1142194)8049 0 R (G17.1142195)8050 0 R \r(G17.1142196)8051 0 R (G17.1142197)8109 0 R (G17.1142200)8119 0 R \r(G17.1142206)8120 0 R (G17.1142208)8121 0 R (G17.1142210)8122 0 R \r(G17.1142212)8123 0 R (G17.1142214)8124 0 R (G17.1142216)8125 0 R \r(G17.1142218)8126 0 R (G17.1142220)8127 0 R (G17.1142222)8128 0 R \r(G17.1142224)8129 0 R (G17.1142226)8130 0 R (G17.1142228)8131 0 R \r(G17.1142230)8132 0 R (G17.1142232)8133 0 R (G17.1142234)8134 0 R \r(G17.1142236)8135 0 R (G17.1142238)8136 0 R (G17.1142240)8137 0 R \r(G17.1142242)8138 0 R ] \r>> \rendobj\r9708 0 obj\r<< \r/Limits [ (G17.1142244)(G17.1142369)] \r/Names [ (G17.1142244)8139 0 R (G17.1142246)8140 0 R (G17.1142248)8141 0 R \r(G17.1142250)8142 0 R (G17.1142252)8143 0 R (G17.1142254)8144 0 R \r(G17.1142256)8145 0 R (G17.1142258)8146 0 R (G17.1142259)8110 0 R \r(G17.1142260)8111 0 R (G17.1142261)8112 0 R (G17.1142262)8113 0 R \r(G17.1142263)8114 0 R (G17.1142264)8115 0 R (G17.1142265)8116 0 R \r(G17.1142268)8147 0 R (G17.1142274)8148 0 R (G17.1142276)8149 0 R \r(G17.1142278)8150 0 R (G17.1142280)8151 0 R (G17.1142282)8152 0 R \r(G17.1142284)8153 0 R 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(G17.1142371)(G17.1142508)] \r/Names [ (G17.1142371)8200 0 R (G17.1142373)8201 0 R (G17.1142375)8202 0 R \r(G17.1142377)8203 0 R (G17.1142379)8204 0 R (G17.1142381)8205 0 R \r(G17.1142383)8206 0 R (G17.1142385)8207 0 R (G17.1142387)8208 0 R \r(G17.1142389)8209 0 R (G17.1142391)8210 0 R (G17.1142392)8178 0 R \r(G17.1142395)8211 0 R (G17.1142401)8212 0 R (G17.1142403)8213 0 R \r(G17.1142405)8214 0 R (G17.1142407)8215 0 R (G17.1142409)8216 0 R \r(G17.1142411)8217 0 R (G17.1142413)8218 0 R (G17.1142415)8219 0 R \r(G17.1142417)8220 0 R (G17.1142418)8179 0 R (G17.1142419)8180 0 R \r(G17.1142422)8221 0 R (G17.1142428)8222 0 R (G17.1142430)8223 0 R \r(G17.1142432)8224 0 R (G17.1142434)8225 0 R (G17.1142436)8226 0 R \r(G17.1142438)8227 0 R (G17.1142440)8228 0 R (G17.1142442)8229 0 R \r(G17.1142444)8230 0 R (G17.1142446)8231 0 R (G17.1142448)8232 0 R \r(G17.1142450)8233 0 R (G17.1142451)8181 0 R (G17.1142452)8182 0 R \r(G17.1142455)8234 0 R (G17.1142459)8235 0 R (G17.1142461)8236 0 R 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(G17.1142626)8336 0 R \r(G17.1142628)8337 0 R ] \r>> \rendobj\r9711 0 obj\r<< \r/Limits [ (G17.1142630)(G17.1142777)] \r/Names [ (G17.1142630)8338 0 R (G17.1142632)8339 0 R (G17.1142634)8340 0 R \r(G17.1142636)8341 0 R (G17.1142638)8342 0 R (G17.1142640)8343 0 R \r(G17.1142642)8344 0 R (G17.1142644)8345 0 R (G17.1142646)8346 0 R \r(G17.1142648)8347 0 R (G17.1142650)8348 0 R (G17.1142652)8349 0 R \r(G17.1142654)8350 0 R (G17.1142656)8351 0 R (G17.1142658)8352 0 R \r(G17.1142660)8353 0 R (G17.1142662)8354 0 R (G17.1142664)8355 0 R \r(G17.1142666)8356 0 R (G17.1142668)8357 0 R (G17.1142670)8358 0 R \r(G17.1142672)8359 0 R (G17.1142674)8360 0 R (G17.1142676)8361 0 R \r(G17.1142677)8307 0 R (G17.1142678)8308 0 R (G17.1142681)8362 0 R \r(G17.1142697)8363 0 R (G17.1142699)8364 0 R (G17.1142701)8365 0 R \r(G17.1142703)8366 0 R (G17.1142705)8367 0 R (G17.1142707)8368 0 R \r(G17.1142709)8369 0 R (G17.1142711)8370 0 R (G17.1142713)8371 0 R \r(G17.1142715)8372 0 R (G17.1142717)8373 0 R (G17.1142719)8374 0 R \r(G17.1142721)8375 0 R (G17.1142723)8376 0 R (G17.1142725)8377 0 R \r(G17.1142727)8378 0 R (G17.1142728)8309 0 R (G17.1142729)8310 0 R \r(G17.1142730)8311 0 R (G17.1142731)8312 0 R (G17.1142732)8313 0 R \r(G17.1142733)8314 0 R (G17.1142734)8315 0 R (G17.1142737)8379 0 R \r(G17.1142753)8380 0 R (G17.1142755)8381 0 R (G17.1142757)8382 0 R \r(G17.1142759)8383 0 R (G17.1142761)8384 0 R (G17.1142763)8385 0 R \r(G17.1142765)8386 0 R (G17.1142767)8387 0 R (G17.1142769)8388 0 R \r(G17.1142771)8389 0 R (G17.1142773)8390 0 R (G17.1142775)8391 0 R \r(G17.1142777)8392 0 R ] \r>> \rendobj\r9712 0 obj\r<< \r/Limits [ (G17.1142779)(G17.1142940)] \r/Names [ (G17.1142779)8393 0 R (G17.1142781)8394 0 R (G17.1142783)8395 0 R \r(G17.1142784)8316 0 R (G17.1142785)8317 0 R (G17.1142786)8318 0 R \r(G17.1142789)8413 0 R (G17.1142805)8414 0 R (G17.1142807)8415 0 R \r(G17.1142809)8416 0 R (G17.1142811)8417 0 R (G17.1142813)8418 0 R \r(G17.1142815)8419 0 R (G17.1142817)8420 0 R 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(G17.1142930)8458 0 R (G17.1142932)8459 0 R \r(G17.1142934)8460 0 R (G17.1142936)8461 0 R (G17.1142938)8462 0 R \r(G17.1142940)8463 0 R ] \r>> \rendobj\r9713 0 obj\r<< \r/Limits [ (G17.1142941)(G17.1143075)] \r/Names [ (G17.1142941)8404 0 R (G17.1142942)8405 0 R (G17.1142943)8406 0 R \r(G17.1142946)8464 0 R (G17.1142962)8465 0 R (G17.1142964)8466 0 R \r(G17.1142966)8467 0 R (G17.1142968)8468 0 R (G17.1142970)8469 0 R \r(G17.1142972)8470 0 R (G17.1142974)8471 0 R (G17.1142976)8472 0 R \r(G17.1142978)8473 0 R (G17.1142980)8474 0 R (G17.1142982)8475 0 R \r(G17.1142984)8476 0 R (G17.1142986)8477 0 R (G17.1142988)8478 0 R \r(G17.1142990)8479 0 R (G17.1142992)8480 0 R (G17.1142993)8407 0 R \r(G17.1142994)8408 0 R (G17.1142995)8409 0 R (G17.1142996)8410 0 R \r(G17.1142997)8411 0 R (G17.1142998)8412 0 R (G17.1143001)8498 0 R \r(G17.1143003)8499 0 R (G17.1143005)8500 0 R (G17.1143007)8501 0 R \r(G17.1143009)8502 0 R (G17.1143011)8503 0 R (G17.1143013)8504 0 R \r(G17.1143015)8505 0 R (G17.1143017)8506 0 R (G17.1143019)8507 0 R \r(G17.1143021)8508 0 R (G17.1143023)8509 0 R (G17.1143025)8510 0 R \r(G17.1143027)8511 0 R (G17.1143029)8512 0 R (G17.1143031)8513 0 R \r(G17.1143033)8514 0 R (G17.1143035)8515 0 R (G17.1143037)8516 0 R \r(G17.1143039)8517 0 R (G17.1143041)8518 0 R (G17.1143043)8519 0 R \r(G17.1143045)8520 0 R (G17.1143047)8521 0 R (G17.1143049)8522 0 R \r(G17.1143051)8523 0 R (G17.1143053)8524 0 R (G17.1143055)8525 0 R \r(G17.1143057)8526 0 R (G17.1143059)8527 0 R (G17.1143061)8528 0 R \r(G17.1143063)8529 0 R (G17.1143065)8530 0 R (G17.1143067)8531 0 R \r(G17.1143069)8532 0 R (G17.1143071)8533 0 R (G17.1143073)8534 0 R \r(G17.1143075)8535 0 R ] \r>> \rendobj\r9714 0 obj\r<< \r/Limits [ (G17.1143077)(G17.1143236)] \r/Names [ (G17.1143077)8536 0 R (G17.1143079)8537 0 R (G17.1143081)8538 0 R \r(G17.1143083)8539 0 R (G17.1143084)8482 0 R (G17.1143085)8483 0 R \r(G17.1143088)8540 0 R (G17.1143104)8541 0 R (G17.1143106)8542 0 R \r(G17.1143108)8543 0 R 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(G17.1143472)8682 0 R \r(G17.1143473)8683 0 R (G17.1143474)8684 0 R (G17.1143475)8685 0 R \r(G17.1143476)8686 0 R (G17.1143477)8707 0 R (G17.1143478)8708 0 R \r(G17.1143479)8709 0 R (G17.1143480)8710 0 R (G17.1143481)8711 0 R \r(G17.1143482)8712 0 R (G17.1143483)8713 0 R (G17.1143484)8714 0 R \r(G17.1143485)8715 0 R ] \r>> \rendobj\r9717 0 obj\r<< \r/Limits [ (G17.1143486)(G17.1143603)] \r/Names [ (G17.1143486)8716 0 R (G17.1143487)8717 0 R (G17.1143488)8718 0 R \r(G17.1143489)8719 0 R (G17.1143490)8720 0 R (G17.1143491)8721 0 R \r(G17.1143492)8722 0 R (G17.1143493)8723 0 R (G17.1143494)8724 0 R \r(G17.1143495)8725 0 R (G17.1143496)8726 0 R (G17.1143497)8727 0 R \r(G17.1143498)8728 0 R (G17.1143499)8729 0 R (G17.1143500)8730 0 R \r(G17.1143501)8732 0 R (G17.1143502)8733 0 R (G17.1143505)8750 0 R \r(G17.1143511)8751 0 R (G17.1143513)8752 0 R (G17.1143515)8753 0 R \r(G17.1143517)8754 0 R (G17.1143519)8755 0 R (G17.1143521)8756 0 R \r(G17.1143523)8757 0 R (G17.1143525)8758 0 R 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(G17.1143609)8791 0 R \r(G17.1143611)8792 0 R (G17.1143613)8793 0 R (G17.1143615)8794 0 R \r(G17.1143616)8742 0 R (G17.1143617)8743 0 R (G17.1143618)8744 0 R \r(G17.1143619)8745 0 R (G17.1143620)8746 0 R (G17.1143621)8747 0 R \r(G17.1143622)8748 0 R (G17.1143623)8749 0 R (G17.1143624)8798 0 R \r(G17.1143625)8799 0 R (G17.1143626)8800 0 R (G17.1143627)8801 0 R \r(G17.1143628)8802 0 R (G17.1143629)8803 0 R (G17.1143630)8804 0 R \r(G17.1143631)8805 0 R (G17.1143632)8806 0 R (G17.1143633)8807 0 R \r(G17.1143634)8808 0 R (G17.1143635)8809 0 R (G17.1143636)8810 0 R \r(G17.1143637)8811 0 R (G17.1143638)8812 0 R (G17.1143639)8813 0 R \r(G17.1143640)8814 0 R (G17.1143641)8815 0 R (G17.1143642)8816 0 R \r(G17.1143643)8817 0 R (G17.1143644)8818 0 R (G17.1143645)8819 0 R \r(G17.1143648)8821 0 R (G17.1143656)8822 0 R (G17.1143658)8823 0 R \r(G17.1143660)8824 0 R (G17.1143662)8825 0 R (G17.1143664)8826 0 R \r(G17.1143666)8827 0 R (G17.1143668)8828 0 R (G17.1143670)8829 0 R \r(G17.1143672)8830 0 R (G17.1143674)8831 0 R (G17.1143676)8832 0 R \r(G17.1143678)8833 0 R (G17.1143680)8834 0 R (G17.1143682)8835 0 R \r(G17.1143684)8836 0 R (G17.1143686)8837 0 R (G17.1143688)8838 0 R \r(G17.1143690)8839 0 R (G17.1143692)8840 0 R (G17.1143694)8841 0 R \r(G17.1143696)8842 0 R (G17.1143698)8843 0 R (G17.1143700)8844 0 R \r(G17.1143702)8845 0 R (G17.1143703)8820 0 R (G17.1143704)8853 0 R \r(G17.1143711)8879 0 R ] \r>> \rendobj\r9719 0 obj\r<< \r/Limits [ (G17.1143721)(G17.1144212)] \r/Names [ (G17.1143721)8880 0 R (G17.1143723)8881 0 R (G17.1143725)8882 0 R \r(G17.1143727)8883 0 R (G17.1143729)8884 0 R (G17.1143731)8885 0 R \r(G17.1143733)8886 0 R (G17.1143735)8887 0 R (G17.1143737)8888 0 R \r(G17.1143739)8889 0 R (G17.1143741)8890 0 R (G17.1143743)8891 0 R \r(G17.1143745)8892 0 R (G17.1143747)8893 0 R (G17.1143749)8894 0 R \r(G17.1143751)8895 0 R (G17.1143753)8896 0 R (G17.1143755)8897 0 R \r(G17.1143757)8898 0 R (G17.1143759)8899 0 R (G17.1143761)8900 0 R \r(G17.1143763)8901 0 R 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(G17.1144213)(G17.1145366)] \r/Names [ (G17.1144213)8870 0 R (G17.1144214)8871 0 R (G17.1144215)8872 0 R \r(G17.1144216)8873 0 R (G17.1144217)8874 0 R (G17.1144218)8875 0 R \r(G17.1144219)8876 0 R (G17.1144220)8877 0 R (G17.1144375)8319 0 R \r(G17.1144381)8497 0 R (G17.1145252)7457 0 R (G17.1145262)7458 0 R \r(G17.1145264)7459 0 R (G17.1145266)7460 0 R (G17.1145268)7461 0 R \r(G17.1145270)7462 0 R (G17.1145272)7463 0 R (G17.1145274)7464 0 R \r(G17.1145276)7465 0 R (G17.1145278)7466 0 R (G17.1145280)7467 0 R \r(G17.1145282)7468 0 R (G17.1145284)7469 0 R (G17.1145286)7470 0 R \r(G17.1145288)7471 0 R (G17.1145290)7472 0 R (G17.1145292)7473 0 R \r(G17.1145294)7474 0 R (G17.1145296)7475 0 R (G17.1145298)7476 0 R \r(G17.1145300)7477 0 R (G17.1145302)7478 0 R (G17.1145304)7479 0 R \r(G17.1145306)7480 0 R (G17.1145308)7481 0 R (G17.1145310)7482 0 R \r(G17.1145312)7483 0 R (G17.1145314)7484 0 R (G17.1145316)7485 0 R \r(G17.1145318)7486 0 R (G17.1145320)7487 0 R (G17.1145322)7488 0 R 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(G18.630805)9196 0 R (G18.630807)9197 0 R (G18.630809)9198 0 R \r(G18.630811)9199 0 R (G18.630813)9200 0 R (G18.630815)9201 0 R (G18.630817)\r9202 0 R (G18.630819)9203 0 R (G18.630821)9204 0 R (G18.630823)9205 0 R \r(G18.630825)9206 0 R (G18.630827)9207 0 R (G18.630829)9208 0 R (G18.630831)\r9209 0 R (G18.630833)9210 0 R (G18.630835)9211 0 R (G18.630837)9212 0 R \r(G18.630839)9213 0 R (G18.630841)9214 0 R (G18.630843)9215 0 R (G18.630845)\r9216 0 R (G18.630847)9217 0 R (G18.630849)9218 0 R (G18.630851)9219 0 R \r(G18.630853)9220 0 R ] \r>> \rendobj\r9725 0 obj\r<< \r/Limits [ (G18.630855)(G18.630981)] \r/Names [ (G18.630855)9221 0 R (G18.630857)9222 0 R (G18.630859)9223 0 R (G18.630861)\r9224 0 R (G18.630863)9225 0 R (G18.630865)9226 0 R (G18.630867)9227 0 R \r(G18.630869)9228 0 R (G18.630871)9229 0 R (G18.630873)9230 0 R (G18.630875)\r9231 0 R (G18.630877)9232 0 R (G18.630879)9233 0 R (G18.630881)9234 0 R \r(G18.630883)9235 0 R (G18.630885)9236 0 R (G18.630887)9237 0 R (G18.630889)\r9238 0 R (G18.630891)9239 0 R (G18.630893)9240 0 R (G18.630895)9241 0 R \r(G18.630897)9242 0 R (G18.630899)9243 0 R (G18.630901)9244 0 R (G18.630903)\r9245 0 R (G18.630905)9246 0 R (G18.630907)9247 0 R (G18.630909)9301 0 R \r(G18.630911)9302 0 R (G18.630913)9303 0 R (G18.630915)9304 0 R (G18.630917)\r9305 0 R (G18.630919)9306 0 R (G18.630921)9307 0 R (G18.630923)9308 0 R \r(G18.630925)9309 0 R (G18.630927)9310 0 R (G18.630929)9311 0 R (G18.630931)\r9312 0 R (G18.630933)9313 0 R (G18.630935)9314 0 R (G18.630937)9315 0 R \r(G18.630939)9316 0 R (G18.630941)9317 0 R (G18.630943)9318 0 R (G18.630945)\r9319 0 R (G18.630947)9320 0 R (G18.630949)9321 0 R (G18.630951)9322 0 R \r(G18.630953)9323 0 R (G18.630955)9324 0 R (G18.630957)9325 0 R (G18.630959)\r9326 0 R (G18.630961)9327 0 R (G18.630963)9328 0 R (G18.630965)9329 0 R \r(G18.630967)9330 0 R (G18.630969)9331 0 R (G18.630971)9332 0 R (G18.630973)\r9333 0 R (G18.630975)9334 0 R (G18.630977)9335 0 R (G18.630979)9336 0 R \r(G18.630981)9337 0 R ] \r>> \rendobj\r9726 0 obj\r<< \r/Limits [ (F1)(G18.630981)] \r/Kids [ 9662 0 R 9663 0 R 9664 0 R 9665 0 R 9666 0 R 9667 0 R 9668 0 R 9669 0 R \r9670 0 R 9671 0 R 9672 0 R 9673 0 R 9674 0 R 9675 0 R 9676 0 R 9677 0 R \r9678 0 R 9679 0 R 9680 0 R 9681 0 R 9682 0 R 9683 0 R 9684 0 R 9685 0 R \r9686 0 R 9687 0 R 9688 0 R 9689 0 R 9690 0 R 9691 0 R 9692 0 R 9693 0 R \r9694 0 R 9695 0 R 9696 0 R 9697 0 R 9698 0 R 9699 0 R 9700 0 R 9701 0 R \r9702 0 R 9703 0 R 9704 0 R 9705 0 R 9706 0 R 9707 0 R 9708 0 R 9709 0 R \r9710 0 R 9711 0 R 9712 0 R 9713 0 R 9714 0 R 9715 0 R 9716 0 R 9717 0 R \r9718 0 R 9719 0 R 9720 0 R 9721 0 R 9722 0 R 9723 0 R 9724 0 R 9725 0 R \r] \r>> \rendobj\r9727 0 obj\r<< \r/Limits [ (G18.630983)(G18.631109)] \r/Names [ (G18.630983)9338 0 R (G18.630985)9339 0 R (G18.630987)9340 0 R (G18.630989)\r9341 0 R (G18.630991)9342 0 R (G18.630993)9343 0 R (G18.630995)9344 0 R \r(G18.630997)9345 0 R (G18.630999)9346 0 R (G18.631001)9347 0 R (G18.631003)\r9348 0 R (G18.631005)9349 0 R (G18.631007)9350 0 R (G18.631009)9351 0 R \r(G18.631011)9352 0 R (G18.631013)9404 0 R (G18.631015)9405 0 R (G18.631017)\r9406 0 R (G18.631019)9407 0 R (G18.631021)9408 0 R (G18.631023)9409 0 R \r(G18.631025)9410 0 R (G18.631027)9411 0 R (G18.631029)9412 0 R (G18.631031)\r9413 0 R (G18.631033)9414 0 R (G18.631035)9415 0 R (G18.631037)9416 0 R \r(G18.631039)9417 0 R (G18.631041)9418 0 R (G18.631043)9419 0 R (G18.631045)\r9420 0 R (G18.631047)9421 0 R (G18.631049)9422 0 R (G18.631051)9423 0 R \r(G18.631053)9424 0 R (G18.631055)9425 0 R (G18.631057)9426 0 R (G18.631059)\r9427 0 R (G18.631061)9428 0 R (G18.631063)9429 0 R (G18.631065)9430 0 R \r(G18.631067)9431 0 R (G18.631069)9432 0 R (G18.631071)9433 0 R (G18.631073)\r9434 0 R (G18.631075)9435 0 R (G18.631077)9436 0 R (G18.631079)9437 0 R \r(G18.631081)9438 0 R (G18.631083)9439 0 R (G18.631085)9440 0 R (G18.631087)\r9441 0 R (G18.631089)9442 0 R (G18.631091)9443 0 R (G18.631093)9444 0 R \r(G18.631095)9445 0 R (G18.631097)9446 0 R (G18.631099)9447 0 R (G18.631101)\r9448 0 R (G18.631103)9449 0 R (G18.631105)9450 0 R (G18.631107)9451 0 R \r(G18.631109)9452 0 R ] \r>> \rendobj\r9728 0 obj\r<< \r/Limits [ (G18.631111)(G18.631237)] \r/Names [ (G18.631111)9453 0 R (G18.631113)9507 0 R (G18.631115)9508 0 R (G18.631117)\r9509 0 R (G18.631119)9510 0 R (G18.631121)9511 0 R (G18.631123)9512 0 R \r(G18.631125)9513 0 R (G18.631127)9514 0 R (G18.631129)9515 0 R (G18.631131)\r9516 0 R (G18.631133)9517 0 R (G18.631135)9518 0 R (G18.631137)9519 0 R \r(G18.631139)9520 0 R (G18.631141)9521 0 R (G18.631143)9522 0 R (G18.631145)\r9523 0 R (G18.631147)9524 0 R (G18.631149)9525 0 R (G18.631151)9526 0 R \r(G18.631153)9527 0 R (G18.631155)9528 0 R (G18.631157)9529 0 R (G18.631159)\r9530 0 R (G18.631161)9531 0 R (G18.631163)9532 0 R (G18.631165)9533 0 R \r(G18.631167)9534 0 R (G18.631169)9535 0 R (G18.631171)9536 0 R (G18.631173)\r9537 0 R (G18.631175)9538 0 R (G18.631177)9539 0 R (G18.631179)9540 0 R \r(G18.631181)9541 0 R (G18.631183)9542 0 R (G18.631185)9543 0 R (G18.631187)\r9544 0 R (G18.631189)9545 0 R (G18.631191)9546 0 R (G18.631193)9547 0 R \r(G18.631195)9548 0 R (G18.631197)9549 0 R (G18.631199)9550 0 R (G18.631201)\r9551 0 R (G18.631203)9552 0 R (G18.631205)9553 0 R (G18.631207)9554 0 R \r(G18.631209)9555 0 R (G18.631211)9556 0 R (G18.631213)9557 0 R (G18.631215)\r9558 0 R (G18.631217)9605 0 R (G18.631219)9606 0 R (G18.631221)9607 0 R \r(G18.631223)9608 0 R (G18.631225)9609 0 R (G18.631227)9610 0 R (G18.631229)\r9611 0 R (G18.631231)9612 0 R (G18.631233)9613 0 R (G18.631235)9614 0 R \r(G18.631237)9615 0 R ] \r>> \rendobj\r9729 0 obj\r<< \r/Limits [ (G18.631239)(G2.1022151)] \r/Names [ (G18.631239)9616 0 R (G18.631241)9617 0 R (G18.631243)9618 0 R (G18.631245)\r9619 0 R (G18.631247)9620 0 R (G18.631249)9621 0 R (G18.631251)9622 0 R \r(G18.631253)9623 0 R (G18.631255)9624 0 R (G18.631257)9625 0 R (G18.631259)\r9626 0 R (G18.631261)9627 0 R (G18.631263)9628 0 R (G18.631265)9629 0 R \r(G18.631267)9630 0 R (G18.631269)9631 0 R (G18.631271)9632 0 R (G18.631273)\r9633 0 R (G18.631275)9634 0 R (G18.631277)9635 0 R (G18.631279)9636 0 R \r(G18.631281)9637 0 R (G18.631283)9638 0 R (G18.631285)9639 0 R (G18.631287)\r9640 0 R (G18.631289)9641 0 R (G18.631291)9642 0 R (G18.631293)9643 0 R \r(G18.631295)9644 0 R (G18.631297)9645 0 R (G18.631299)9646 0 R (G18.631301)\r9647 0 R (G18.631303)9648 0 R (G19.1041534)9653 0 R (G19.1041535)\r9654 0 R (G19.1041536)9655 0 R (G19.1041538)9656 0 R (G19.1041539)\r9657 0 R (G19.1041540)9658 0 R (G19.1041541)9659 0 R (G19.1041542)\r9660 0 R (G19.1041543)9661 0 R (G2.1020755)1124 0 R (G2.1020764)\r1151 0 R (G2.1021754)1125 0 R (G2.1021755)1126 0 R (G2.1021756)1127 0 R \r(G2.1021757)1128 0 R (G2.1021811)1149 0 R (G2.1021822)1153 0 R (G2.1021835)\r1161 0 R (G2.1021837)1157 0 R (G2.1021838)1160 0 R (G2.1021848)1163 0 R \r(G2.1021985)1172 0 R (G2.1021987)1166 0 R (G2.1021994)1173 0 R (G2.1022045)\r1179 0 R (G2.1022060)1201 0 R (G2.1022063)1174 0 R (G2.1022064)1175 0 R \r(G2.1022141)1216 0 R (G2.1022149)1217 0 R (G2.1022151)1218 0 R ] \r>> \rendobj\r9730 0 obj\r<< \r/Limits [ (G2.1022153)(G2.1023515)] \r/Names [ (G2.1022153)1219 0 R (G2.1022155)1220 0 R (G2.1022299)1212 0 R (G2.1022304)\r1213 0 R (G2.1022307)1285 0 R (G2.1022311)1286 0 R (G2.1022313)1287 0 R \r(G2.1022334)1214 0 R (G2.1022335)1215 0 R (G2.1022336)1305 0 R (G2.1022339)\r1314 0 R (G2.1022345)1315 0 R (G2.1022347)1316 0 R (G2.1022349)1317 0 R \r(G2.1022394)1306 0 R (G2.1022395)1307 0 R (G2.1022396)1308 0 R (G2.1022405)\r1338 0 R (G2.1022411)1339 0 R (G2.1022413)1340 0 R (G2.1022415)1341 0 R \r(G2.1022464)1309 0 R (G2.1022465)1310 0 R (G2.1022466)1311 0 R (G2.1022467)\r1544 0 R (G2.1022536)1744 0 R (G2.1022538)1594 0 R (G2.1023118)1129 0 R \r(G2.1023119)1130 0 R (G2.1023120)1131 0 R (G2.1023121)1132 0 R (G2.1023122)\r1133 0 R (G2.1023123)1134 0 R (G2.1023124)1135 0 R (G2.1023125)1136 0 R \r(G2.1023126)1137 0 R (G2.1023127)1138 0 R (G2.1023143)1139 0 R (G2.1023144)\r1140 0 R (G2.1023145)1141 0 R (G2.1023146)1142 0 R (G2.1023147)1143 0 R \r(G2.1023148)1144 0 R (G2.1023149)1145 0 R (G2.1023150)1146 0 R (G2.1023151)\r1147 0 R (G2.1023152)1148 0 R (G2.1023162)1152 0 R (G2.1023178)1154 0 R \r(G2.1023179)1155 0 R (G2.1023180)1156 0 R (G2.1023205)1159 0 R (G2.1023223)\r1164 0 R (G2.1023224)1165 0 R (G2.1023228)1171 0 R (G2.1023242)1162 0 R \r(G2.1023368)1167 0 R (G2.1023387)1176 0 R (G2.1023503)1180 0 R (G2.1023511)\r1177 0 R (G2.1023512)1178 0 R (G2.1023513)1182 0 R (G2.1023514)1183 0 R \r(G2.1023515)1184 0 R ] \r>> \rendobj\r9731 0 obj\r<< \r/Limits [ (G2.1023516)(G2.1023675)] \r/Names [ (G2.1023516)1185 0 R (G2.1023517)1186 0 R (G2.1023518)1187 0 R (G2.1023519)\r1188 0 R (G2.1023520)1189 0 R (G2.1023521)1190 0 R (G2.1023522)1191 0 R \r(G2.1023523)1192 0 R (G2.1023524)1193 0 R (G2.1023525)1194 0 R (G2.1023526)\r1195 0 R (G2.1023527)1196 0 R (G2.1023528)1197 0 R (G2.1023529)1198 0 R \r(G2.1023530)1199 0 R (G2.1023531)1200 0 R (G2.1023535)1211 0 R (G2.1023577)\r1221 0 R (G2.1023580)1222 0 R (G2.1023582)1223 0 R (G2.1023584)1224 0 R \r(G2.1023586)1225 0 R (G2.1023588)1226 0 R (G2.1023590)1227 0 R (G2.1023592)\r1228 0 R (G2.1023594)1229 0 R (G2.1023596)1230 0 R (G2.1023598)1231 0 R \r(G2.1023600)1232 0 R (G2.1023602)1233 0 R (G2.1023604)1234 0 R (G2.1023606)\r1235 0 R (G2.1023608)1236 0 R (G2.1023610)1237 0 R (G2.1023613)1238 0 R \r(G2.1023615)1239 0 R (G2.1023617)1240 0 R (G2.1023619)1241 0 R (G2.1023622)\r1242 0 R (G2.1023624)1243 0 R (G2.1023626)1244 0 R (G2.1023628)1245 0 R \r(G2.1023631)1246 0 R (G2.1023633)1247 0 R (G2.1023635)1248 0 R (G2.1023637)\r1249 0 R (G2.1023639)1250 0 R (G2.1023641)1251 0 R (G2.1023643)1252 0 R \r(G2.1023645)1253 0 R (G2.1023647)1254 0 R (G2.1023649)1255 0 R (G2.1023651)\r1256 0 R (G2.1023653)1257 0 R (G2.1023656)1258 0 R (G2.1023658)1259 0 R \r(G2.1023660)1260 0 R (G2.1023662)1261 0 R (G2.1023665)1262 0 R (G2.1023667)\r1263 0 R (G2.1023669)1264 0 R (G2.1023671)1265 0 R (G2.1023673)1266 0 R \r(G2.1023675)1267 0 R ] \r>> \rendobj\r9732 0 obj\r<< \r/Limits [ (G2.1023677)(G2.1023803)] \r/Names [ (G2.1023677)1268 0 R (G2.1023679)1269 0 R (G2.1023681)1270 0 R (G2.1023683)\r1271 0 R (G2.1023685)1272 0 R (G2.1023687)1273 0 R (G2.1023689)1274 0 R \r(G2.1023691)1275 0 R (G2.1023693)1276 0 R (G2.1023695)1277 0 R (G2.1023697)\r1278 0 R (G2.1023699)1279 0 R (G2.1023701)1280 0 R (G2.1023703)1281 0 R \r(G2.1023705)1282 0 R (G2.1023707)1283 0 R (G2.1023709)1284 0 R (G2.1023713)\r1288 0 R (G2.1023715)1289 0 R (G2.1023717)1290 0 R (G2.1023719)1291 0 R \r(G2.1023721)1292 0 R (G2.1023723)1293 0 R (G2.1023725)1294 0 R (G2.1023727)\r1295 0 R (G2.1023729)1296 0 R (G2.1023731)1297 0 R (G2.1023733)1298 0 R \r(G2.1023735)1299 0 R (G2.1023737)1300 0 R (G2.1023739)1301 0 R (G2.1023741)\r1302 0 R (G2.1023743)1303 0 R (G2.1023745)1318 0 R (G2.1023747)1319 0 R \r(G2.1023748)1320 0 R (G2.1023749)1321 0 R (G2.1023751)1322 0 R (G2.1023753)\r1323 0 R (G2.1023755)1324 0 R (G2.1023757)1325 0 R (G2.1023759)1326 0 R \r(G2.1023761)1327 0 R (G2.1023763)1328 0 R (G2.1023765)1329 0 R (G2.1023767)\r1330 0 R (G2.1023769)1331 0 R (G2.1023771)1332 0 R (G2.1023773)1333 0 R \r(G2.1023775)1334 0 R (G2.1023777)1335 0 R (G2.1023779)1336 0 R (G2.1023781)\r1337 0 R (G2.1023783)1342 0 R (G2.1023785)1343 0 R (G2.1023787)1344 0 R \r(G2.1023789)1345 0 R (G2.1023791)1346 0 R (G2.1023793)1347 0 R (G2.1023795)\r1348 0 R (G2.1023797)1349 0 R (G2.1023799)1350 0 R (G2.1023801)1351 0 R \r(G2.1023803)1352 0 R ] \r>> \rendobj\r9733 0 obj\r<< \r/Limits [ (G2.1023805)(G2.1023941)] \r/Names [ (G2.1023805)1353 0 R (G2.1023807)1354 0 R (G2.1023809)1355 0 R (G2.1023811)\r1356 0 R (G2.1023813)1357 0 R (G2.1023815)1358 0 R (G2.1023817)1359 0 R \r(G2.1023819)1360 0 R (G2.1023821)1361 0 R (G2.1023823)1362 0 R (G2.1023825)\r1363 0 R (G2.1023827)1364 0 R (G2.1023829)1365 0 R (G2.1023831)1366 0 R \r(G2.1023833)1367 0 R (G2.1023835)1368 0 R (G2.1023837)1369 0 R (G2.1023839)\r1370 0 R (G2.1023841)1371 0 R (G2.1023843)1372 0 R (G2.1023845)1373 0 R \r(G2.1023847)1374 0 R (G2.1023849)1375 0 R (G2.1023851)1376 0 R (G2.1023853)\r1377 0 R (G2.1023855)1378 0 R (G2.1023857)1379 0 R (G2.1023859)1380 0 R \r(G2.1023860)1312 0 R (G2.1023865)1313 0 R (G2.1023869)1381 0 R (G2.1023877)\r1382 0 R (G2.1023879)1383 0 R (G2.1023881)1384 0 R (G2.1023883)1385 0 R \r(G2.1023885)1386 0 R (G2.1023887)1387 0 R (G2.1023889)1388 0 R (G2.1023891)\r1389 0 R (G2.1023893)1390 0 R (G2.1023895)1391 0 R (G2.1023897)1392 0 R \r(G2.1023899)1393 0 R (G2.1023901)1397 0 R (G2.1023903)1398 0 R (G2.1023905)\r1399 0 R (G2.1023907)1400 0 R (G2.1023909)1401 0 R (G2.1023911)1402 0 R \r(G2.1023913)1403 0 R (G2.1023915)1404 0 R (G2.1023917)1405 0 R (G2.1023919)\r1406 0 R (G2.1023921)1407 0 R (G2.1023923)1408 0 R (G2.1023925)1409 0 R \r(G2.1023927)1410 0 R (G2.1023929)1411 0 R (G2.1023931)1412 0 R (G2.1023933)\r1413 0 R (G2.1023935)1414 0 R (G2.1023937)1415 0 R (G2.1023939)1416 0 R \r(G2.1023941)1417 0 R ] \r>> \rendobj\r9734 0 obj\r<< \r/Limits [ (G2.1023943)(G2.1024069)] \r/Names [ (G2.1023943)1418 0 R (G2.1023945)1419 0 R (G2.1023947)1420 0 R (G2.1023949)\r1421 0 R (G2.1023951)1422 0 R (G2.1023953)1423 0 R (G2.1023955)1424 0 R \r(G2.1023957)1425 0 R (G2.1023959)1426 0 R (G2.1023961)1427 0 R (G2.1023963)\r1428 0 R (G2.1023965)1429 0 R (G2.1023967)1430 0 R (G2.1023969)1431 0 R \r(G2.1023971)1432 0 R (G2.1023973)1433 0 R (G2.1023975)1434 0 R (G2.1023977)\r1435 0 R (G2.1023979)1436 0 R (G2.1023981)1437 0 R (G2.1023983)1438 0 R \r(G2.1023985)1439 0 R (G2.1023987)1440 0 R (G2.1023989)1441 0 R (G2.1023991)\r1442 0 R (G2.1023993)1443 0 R (G2.1023995)1444 0 R (G2.1023997)1445 0 R \r(G2.1023999)1446 0 R (G2.1024001)1447 0 R (G2.1024003)1448 0 R (G2.1024005)\r1449 0 R (G2.1024007)1450 0 R (G2.1024009)1451 0 R (G2.1024011)1452 0 R \r(G2.1024013)1453 0 R (G2.1024015)1454 0 R (G2.1024017)1455 0 R (G2.1024019)\r1456 0 R (G2.1024021)1457 0 R (G2.1024023)1458 0 R (G2.1024025)1459 0 R \r(G2.1024027)1460 0 R (G2.1024029)1461 0 R (G2.1024031)1462 0 R (G2.1024033)\r1463 0 R (G2.1024035)1464 0 R (G2.1024037)1465 0 R (G2.1024039)1466 0 R \r(G2.1024041)1467 0 R (G2.1024043)1468 0 R (G2.1024045)1469 0 R (G2.1024047)\r1470 0 R (G2.1024049)1471 0 R (G2.1024051)1472 0 R (G2.1024053)1473 0 R \r(G2.1024055)1474 0 R (G2.1024057)1475 0 R (G2.1024059)1476 0 R (G2.1024061)\r1477 0 R (G2.1024063)1478 0 R (G2.1024065)1479 0 R (G2.1024067)1480 0 R \r(G2.1024069)1481 0 R ] \r>> \rendobj\r9735 0 obj\r<< \r/Limits [ (G2.1024071)(G2.1024207)] \r/Names [ (G2.1024071)1482 0 R (G2.1024073)1483 0 R (G2.1024075)1484 0 R (G2.1024077)\r1485 0 R (G2.1024079)1486 0 R (G2.1024081)1487 0 R (G2.1024083)1488 0 R \r(G2.1024085)1489 0 R (G2.1024087)1490 0 R (G2.1024089)1491 0 R (G2.1024091)\r1492 0 R (G2.1024093)1493 0 R (G2.1024095)1494 0 R (G2.1024097)1495 0 R \r(G2.1024099)1496 0 R (G2.1024101)1497 0 R (G2.1024103)1498 0 R (G2.1024105)\r1499 0 R (G2.1024107)1500 0 R (G2.1024109)1501 0 R (G2.1024111)1502 0 R \r(G2.1024113)1503 0 R (G2.1024115)1504 0 R (G2.1024117)1505 0 R (G2.1024119)\r1506 0 R (G2.1024121)1507 0 R (G2.1024123)1508 0 R (G2.1024125)1509 0 R \r(G2.1024127)1510 0 R (G2.1024129)1511 0 R (G2.1024131)1512 0 R (G2.1024133)\r1513 0 R (G2.1024135)1514 0 R (G2.1024137)1515 0 R (G2.1024139)1516 0 R \r(G2.1024141)1517 0 R (G2.1024143)1518 0 R (G2.1024145)1519 0 R (G2.1024147)\r1520 0 R (G2.1024149)1521 0 R (G2.1024151)1522 0 R (G2.1024153)1523 0 R \r(G2.1024155)1524 0 R (G2.1024157)1525 0 R (G2.1024159)1526 0 R (G2.1024161)\r1527 0 R (G2.1024163)1528 0 R (G2.1024165)1529 0 R (G2.1024167)1530 0 R \r(G2.1024169)1531 0 R (G2.1024171)1532 0 R (G2.1024173)1533 0 R (G2.1024175)\r1534 0 R (G2.1024177)1535 0 R (G2.1024179)1536 0 R (G2.1024181)1537 0 R \r(G2.1024183)1538 0 R (G2.1024185)1539 0 R (G2.1024187)1540 0 R (G2.1024193)\r1395 0 R (G2.1024194)1396 0 R (G2.1024197)1547 0 R (G2.1024205)1548 0 R \r(G2.1024207)1549 0 R ] \r>> \rendobj\r9736 0 obj\r<< \r/Limits [ (G18.630983)(G2.1024207)] \r/Kids [ 9727 0 R 9728 0 R 9729 0 R 9730 0 R 9731 0 R 9732 0 R 9733 0 R 9734 0 R \r9735 0 R ] \r>> \rendobj\r9737 0 obj\r<< \r/Limits [ (G2.1024209)(G2.1024371)] \r/Names [ (G2.1024209)1550 0 R (G2.1024211)1551 0 R (G2.1024213)1552 0 R (G2.1024214)\r1553 0 R (G2.1024216)1554 0 R (G2.1024218)1555 0 R (G2.1024220)1556 0 R \r(G2.1024222)1557 0 R (G2.1024223)1558 0 R (G2.1024225)1559 0 R (G2.1024227)\r1560 0 R (G2.1024229)1561 0 R (G2.1024231)1562 0 R (G2.1024232)1563 0 R \r(G2.1024234)1564 0 R (G2.1024236)1565 0 R (G2.1024238)1566 0 R (G2.1024240)\r1567 0 R (G2.1024241)1568 0 R (G2.1024243)1569 0 R (G2.1024245)1570 0 R \r(G2.1024247)1571 0 R (G2.1024248)1542 0 R (G2.1024249)1543 0 R (G2.1024258)\r1546 0 R (G2.1024260)1545 0 R (G2.1024270)1572 0 R (G2.1024278)1573 0 R \r(G2.1024280)1574 0 R (G2.1024282)1575 0 R (G2.1024284)1576 0 R (G2.1024286)\r1577 0 R (G2.1024288)1578 0 R (G2.1024290)1579 0 R (G2.1024292)1580 0 R \r(G2.1024294)1581 0 R (G2.1024296)1582 0 R (G2.1024298)1583 0 R (G2.1024300)\r1584 0 R (G2.1024302)1585 0 R (G2.1024304)1586 0 R (G2.1024306)1587 0 R \r(G2.1024308)1588 0 R (G2.1024310)1589 0 R (G2.1024312)1590 0 R (G2.1024314)\r1591 0 R (G2.1024316)1592 0 R (G2.1024350)1595 0 R (G2.1024351)1596 0 R \r(G2.1024352)1597 0 R (G2.1024353)1598 0 R (G2.1024354)1599 0 R (G2.1024356)\r1600 0 R (G2.1024357)1601 0 R (G2.1024358)1602 0 R (G2.1024362)1606 0 R \r(G2.1024363)1607 0 R (G2.1024364)1608 0 R (G2.1024365)1609 0 R (G2.1024366)\r1610 0 R (G2.1024368)1611 0 R (G2.1024369)1612 0 R (G2.1024370)1613 0 R \r(G2.1024371)1614 0 R ] \r>> \rendobj\r9738 0 obj\r<< \r/Limits [ (G2.1024372)(G2.1024435)] \r/Names [ (G2.1024372)1617 0 R (G2.1024373)1618 0 R (G2.1024374)1619 0 R (G2.1024375)\r1620 0 R (G2.1024376)1621 0 R (G2.1024377)1622 0 R (G2.1024378)1623 0 R \r(G2.1024379)1624 0 R (G2.1024380)1625 0 R (G2.1024381)1626 0 R (G2.1024382)\r1627 0 R (G2.1024383)1628 0 R (G2.1024384)1629 0 R (G2.1024385)1630 0 R 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(G2.1024432)1677 0 R (G2.1024433)1678 0 R (G2.1024434)1680 0 R \r(G2.1024435)1681 0 R ] \r>> \rendobj\r9739 0 obj\r<< \r/Limits [ (G2.1024436)(G2.1024647)] \r/Names [ (G2.1024436)1682 0 R (G2.1024437)1683 0 R (G2.1024438)1684 0 R (G2.1024439)\r1685 0 R (G2.1024440)1686 0 R (G2.1024441)1687 0 R (G2.1024442)1688 0 R \r(G2.1024443)1689 0 R (G2.1024444)1690 0 R (G2.1024445)1691 0 R (G2.1024446)\r1692 0 R (G2.1024447)1693 0 R (G2.1024448)1694 0 R (G2.1024449)1695 0 R \r(G2.1024450)1696 0 R (G2.1024451)1697 0 R (G2.1024452)1698 0 R (G2.1024453)\r1699 0 R (G2.1024454)1700 0 R (G2.1024456)1701 0 R (G2.1024457)1702 0 R \r(G2.1024458)1703 0 R (G2.1024460)1705 0 R (G2.1024461)1706 0 R (G2.1024463)\r1708 0 R (G2.1024464)1709 0 R (G2.1024465)1710 0 R (G2.1024466)1711 0 R \r(G2.1024467)1712 0 R (G2.1024468)1713 0 R (G2.1024469)1714 0 R (G2.1024470)\r1715 0 R (G2.1024471)1716 0 R (G2.1024472)1717 0 R (G2.1024473)1718 0 R \r(G2.1024474)1721 0 R (G2.1024475)1722 0 R (G2.1024476)1723 0 R (G2.1024477)\r1724 0 R (G2.1024478)1725 0 R (G2.1024479)1726 0 R (G2.1024480)1727 0 R \r(G2.1024481)1728 0 R (G2.1024482)1729 0 R (G2.1024483)1730 0 R (G2.1024484)\r1731 0 R (G2.1024485)1732 0 R (G2.1024486)1733 0 R (G2.1024487)1734 0 R \r(G2.1024488)1735 0 R (G2.1024489)1737 0 R (G2.1024490)1738 0 R (G2.1024492)\r1739 0 R (G2.1024493)1740 0 R (G2.1024495)1741 0 R (G2.1024496)1742 0 R \r(G2.1024497)1743 0 R (G2.1024547)1615 0 R (G2.1024616)1736 0 R (G2.1024619)\r1704 0 R (G2.1024625)1707 0 R (G2.1024645)1603 0 R (G2.1024646)1604 0 R \r(G2.1024647)1605 0 R ] \r>> \rendobj\r9740 0 obj\r<< \r/Limits [ (G3.1012533)(G3.1059316)] \r/Names [ (G3.1012533)1755 0 R (G3.1015710)1752 0 R (G3.1059005)1762 0 R (G3.1059006)\r1756 0 R (G3.1059007)1757 0 R (G3.1059008)1758 0 R (G3.1059009)1759 0 R \r(G3.1059010)1760 0 R (G3.1059011)1761 0 R (G3.1059012)1765 0 R (G3.1059013)\r1766 0 R (G3.1059014)1767 0 R (G3.1059015)1768 0 R (G3.1059016)1769 0 R \r(G3.1059017)1770 0 R (G3.1059018)1771 0 R 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(G3.1059314)1832 0 R \r(G3.1059316)1833 0 R ] \r>> \rendobj\r9741 0 obj\r<< \r/Limits [ (G3.1059318)(G3.1059467)] \r/Names [ (G3.1059318)1834 0 R (G3.1059320)1835 0 R (G3.1059322)1836 0 R (G3.1059323)\r1808 0 R (G3.1059324)1810 0 R (G3.1059325)1812 0 R (G3.1059326)1813 0 R \r(G3.1059327)1814 0 R (G3.1059328)1815 0 R (G3.1059329)1838 0 R (G3.1059330)\r1839 0 R (G3.1059331)1840 0 R (G3.1059332)1841 0 R (G3.1059333)1842 0 R \r(G3.1059334)1843 0 R (G3.1059335)1844 0 R (G3.1059336)1845 0 R (G3.1059337)\r1846 0 R (G3.1059338)1847 0 R (G3.1059339)1848 0 R (G3.1059340)1849 0 R \r(G3.1059341)1850 0 R (G3.1059342)1851 0 R (G3.1059343)1852 0 R (G3.1059344)\r1853 0 R (G3.1059345)1854 0 R (G3.1059346)1855 0 R (G3.1059374)1857 0 R \r(G3.1059375)1856 0 R (G3.1059378)1859 0 R (G3.1059379)1860 0 R (G3.1059380)\r1861 0 R (G3.1059381)1862 0 R (G3.1059382)1863 0 R (G3.1059383)1864 0 R \r(G3.1059384)1865 0 R (G3.1059385)1866 0 R (G3.1059388)1867 0 R (G3.1059390)\r1868 0 R (G3.1059391)1869 0 R (G3.1059429)1883 0 R (G3.1059430)1870 0 R \r(G3.1059431)1871 0 R (G3.1059432)1872 0 R (G3.1059433)1873 0 R (G3.1059434)\r1874 0 R (G3.1059435)1875 0 R (G3.1059436)1876 0 R (G3.1059437)1877 0 R \r(G3.1059438)1878 0 R (G3.1059439)1879 0 R (G3.1059440)1880 0 R (G3.1059441)\r1881 0 R (G3.1059442)1882 0 R (G3.1059443)1885 0 R (G3.1059444)1886 0 R \r(G3.1059447)1890 0 R (G3.1059455)1891 0 R (G3.1059457)1892 0 R (G3.1059459)\r1893 0 R (G3.1059461)1894 0 R (G3.1059463)1895 0 R (G3.1059465)1896 0 R \r(G3.1059467)1897 0 R ] \r>> \rendobj\r9742 0 obj\r<< \r/Limits [ (G3.1059469)(G3.1059595)] \r/Names [ (G3.1059469)1898 0 R (G3.1059471)1899 0 R (G3.1059473)1900 0 R (G3.1059475)\r1901 0 R (G3.1059477)1902 0 R (G3.1059479)1903 0 R (G3.1059481)1904 0 R \r(G3.1059483)1905 0 R (G3.1059485)1906 0 R (G3.1059487)1907 0 R (G3.1059489)\r1908 0 R (G3.1059491)1909 0 R (G3.1059493)1910 0 R (G3.1059495)1911 0 R \r(G3.1059497)1912 0 R (G3.1059499)1913 0 R (G3.1059501)1914 0 R (G3.1059503)\r1915 0 R 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(G3.1059683)2005 0 R (G3.1059685)2006 0 R (G3.1059687)\r2007 0 R (G3.1059689)2008 0 R (G3.1059691)2009 0 R (G3.1059693)2010 0 R \r(G3.1059695)2011 0 R (G3.1059697)2012 0 R (G3.1059699)2013 0 R (G3.1059701)\r2014 0 R (G3.1059703)2015 0 R (G3.1059705)2016 0 R (G3.1059707)2017 0 R \r(G3.1059709)2018 0 R (G3.1059711)2019 0 R (G3.1059713)2020 0 R (G3.1059715)\r2021 0 R (G3.1059717)2022 0 R (G3.1059719)2023 0 R (G3.1059721)2024 0 R \r(G3.1059723)2025 0 R ] \r>> \rendobj\r9744 0 obj\r<< \r/Limits [ (G3.1059725)(G3.1059880)] \r/Names [ (G3.1059725)2026 0 R (G3.1059727)2027 0 R (G3.1059729)2028 0 R (G3.1059731)\r2029 0 R (G3.1059733)2030 0 R (G3.1059734)1887 0 R (G3.1059735)1888 0 R \r(G3.1059736)1889 0 R (G3.1059737)2034 0 R (G3.1059738)2035 0 R (G3.1059742)\r2045 0 R (G3.1059746)2046 0 R (G3.1059748)2047 0 R (G3.1059750)2048 0 R \r(G3.1059752)2049 0 R (G3.1059754)2050 0 R (G3.1059756)2051 0 R (G3.1059758)\r2052 0 R (G3.1059760)2053 0 R (G3.1059762)2054 0 R (G3.1059764)2055 0 R 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(G3.1061395)\r1809 0 R (G3.1061804)2150 0 R (G3.1061834)2685 0 R (G3.1061836)2542 0 R \r(G3.1061839)2635 0 R (G3.1061847)2636 0 R (G3.1061849)2637 0 R (G3.1061851)\r2638 0 R (G3.1061853)2639 0 R (G3.1061855)2640 0 R (G3.1061857)2641 0 R \r(G3.1061859)2642 0 R ] \r>> \rendobj\r9752 0 obj\r<< \r/Limits [ (G3.1061861)(G3.1061928)] \r/Names [ (G3.1061861)2643 0 R (G3.1061863)2644 0 R (G3.1061865)2645 0 R (G3.1061867)\r2646 0 R (G3.1061869)2647 0 R (G3.1061870)2543 0 R (G3.1061871)2544 0 R \r(G3.1061872)2545 0 R (G3.1061873)2547 0 R (G3.1061874)2548 0 R (G3.1061875)\r2549 0 R (G3.1061876)2550 0 R (G3.1061877)2551 0 R (G3.1061878)2552 0 R \r(G3.1061879)2553 0 R (G3.1061880)2554 0 R (G3.1061881)2555 0 R (G3.1061882)\r2556 0 R (G3.1061883)2557 0 R (G3.1061884)2558 0 R (G3.1061885)2559 0 R \r(G3.1061886)2560 0 R (G3.1061887)2561 0 R (G3.1061888)2562 0 R (G3.1061889)\r2563 0 R (G3.1061890)2564 0 R (G3.1061891)2565 0 R (G3.1061892)2566 0 R \r(G3.1061893)2567 0 R (G3.1061894)2568 0 R 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0 R (G4.999328)2892 0 R (G4.999330)\r2893 0 R (G5.1014921)3022 0 R (G5.1015655)3478 0 R (G5.1015708)3023 0 R \r(G5.1015807)3024 0 R (G5.1062952)3297 0 R (G5.1063755)3421 0 R (G5.1063781)\r3045 0 R (G5.1065422)3025 0 R (G5.1065498)3036 0 R (G5.1065499)3026 0 R \r(G5.1065500)3027 0 R (G5.1065501)3028 0 R (G5.1065502)3029 0 R (G5.1065503)\r3030 0 R (G5.1065504)3031 0 R (G5.1065505)3032 0 R (G5.1065506)3033 0 R \r(G5.1065507)3034 0 R (G5.1065508)3035 0 R (G5.1065509)3043 0 R (G5.1065510)\r3044 0 R (G5.1065515)3046 0 R (G5.1065516)3047 0 R (G5.1065517)3048 0 R \r(G5.1065518)3049 0 R ] \r>> \rendobj\r9759 0 obj\r<< \r/Limits [ (G5.1065519)(G5.1065651)] \r/Names [ (G5.1065519)3050 0 R (G5.1065520)3051 0 R (G5.1065522)3052 0 R (G5.1065523)\r3053 0 R (G5.1065527)3057 0 R (G5.1065533)3058 0 R (G5.1065535)3059 0 R \r(G5.1065537)3060 0 R (G5.1065539)3061 0 R (G5.1065541)3062 0 R (G5.1065543)\r3063 0 R (G5.1065545)3064 0 R (G5.1065547)3065 0 R (G5.1065549)3066 0 R \r(G5.1065551)3067 0 R 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(G5.1065647)3119 0 R (G5.1065649)3120 0 R \r(G5.1065651)3121 0 R ] \r>> \rendobj\r9760 0 obj\r<< \r/Limits [ (G5.1065653)(G5.1065779)] \r/Names [ (G5.1065653)3122 0 R (G5.1065655)3123 0 R (G5.1065657)3124 0 R (G5.1065659)\r3125 0 R (G5.1065661)3126 0 R (G5.1065663)3127 0 R (G5.1065665)3128 0 R \r(G5.1065667)3129 0 R (G5.1065669)3130 0 R (G5.1065671)3131 0 R (G5.1065673)\r3132 0 R (G5.1065675)3133 0 R (G5.1065677)3134 0 R (G5.1065679)3135 0 R \r(G5.1065681)3136 0 R (G5.1065683)3137 0 R (G5.1065685)3138 0 R (G5.1065687)\r3139 0 R (G5.1065689)3140 0 R (G5.1065690)3110 0 R (G5.1065691)3111 0 R \r(G5.1065692)3112 0 R (G5.1065693)3144 0 R (G5.1065697)3145 0 R (G5.1065701)\r3150 0 R (G5.1065705)3151 0 R (G5.1065707)3152 0 R (G5.1065709)3153 0 R \r(G5.1065711)3154 0 R (G5.1065713)3155 0 R (G5.1065715)3156 0 R (G5.1065717)\r3157 0 R (G5.1065719)3158 0 R (G5.1065721)3159 0 R (G5.1065723)3160 0 R \r(G5.1065725)3161 0 R (G5.1065727)3162 0 R (G5.1065729)3163 0 R (G5.1065731)\r3164 0 R (G5.1065733)3165 0 R (G5.1065735)3166 0 R (G5.1065737)3167 0 R \r(G5.1065739)3168 0 R (G5.1065741)3169 0 R (G5.1065743)3170 0 R (G5.1065745)\r3171 0 R (G5.1065747)3172 0 R (G5.1065749)3173 0 R (G5.1065751)3174 0 R \r(G5.1065752)3175 0 R (G5.1065754)3176 0 R (G5.1065756)3177 0 R (G5.1065758)\r3178 0 R (G5.1065760)3179 0 R (G5.1065761)3180 0 R (G5.1065763)3181 0 R \r(G5.1065765)3182 0 R (G5.1065767)3183 0 R (G5.1065769)3184 0 R (G5.1065771)\r3185 0 R (G5.1065773)3186 0 R (G5.1065775)3187 0 R (G5.1065777)3188 0 R \r(G5.1065779)3189 0 R ] \r>> \rendobj\r9761 0 obj\r<< \r/Limits [ (G5.1065781)(G5.1065979)] \r/Names [ (G5.1065781)3190 0 R (G5.1065783)3191 0 R (G5.1065785)3192 0 R (G5.1065787)\r3193 0 R (G5.1065789)3194 0 R (G5.1065791)3195 0 R (G5.1065793)3196 0 R \r(G5.1065795)3197 0 R (G5.1065797)3198 0 R (G5.1065799)3199 0 R (G5.1065801)\r3200 0 R (G5.1065803)3201 0 R (G5.1065805)3202 0 R (G5.1065807)3203 0 R \r(G5.1065809)3204 0 R (G5.1065811)3205 0 R (G5.1065813)3206 0 R (G5.1065815)\r3207 0 R (G5.1065817)3208 0 R (G5.1065819)3209 0 R (G5.1065821)3210 0 R \r(G5.1065822)3211 0 R (G5.1065823)3212 0 R (G5.1065824)3213 0 R (G5.1065825)\r3214 0 R (G5.1065826)3215 0 R (G5.1065827)3216 0 R (G5.1065828)3146 0 R \r(G5.1065829)3147 0 R (G5.1065830)3148 0 R (G5.1065831)3149 0 R (G5.1065832)\r3218 0 R (G5.1065833)3219 0 R (G5.1065834)3220 0 R (G5.1065835)3221 0 R \r(G5.1065836)3222 0 R (G5.1065884)3243 0 R (G5.1065885)3223 0 R (G5.1065886)\r3224 0 R (G5.1065887)3225 0 R (G5.1065888)3226 0 R (G5.1065889)3227 0 R \r(G5.1065890)3228 0 R (G5.1065891)3229 0 R (G5.1065892)3230 0 R (G5.1065893)\r3231 0 R (G5.1065894)3232 0 R (G5.1065895)3233 0 R (G5.1065896)3234 0 R \r(G5.1065897)3235 0 R (G5.1065898)3236 0 R (G5.1065899)3237 0 R (G5.1065934)\r3244 0 R (G5.1065935)3238 0 R (G5.1065936)3239 0 R (G5.1065937)3240 0 R \r(G5.1065938)3241 0 R (G5.1065939)3242 0 R (G5.1065974)3259 0 R (G5.1065975)\r3246 0 R (G5.1065976)3247 0 R (G5.1065977)3248 0 R (G5.1065978)3249 0 R \r(G5.1065979)3250 0 R ] \r>> \rendobj\r9762 0 obj\r<< \r/Limits [ (G5.1066000)(G5.1066195)] \r/Names [ (G5.1066000)3260 0 R (G5.1066001)3251 0 R (G5.1066002)3252 0 R (G5.1066003)\r3253 0 R (G5.1066004)3254 0 R (G5.1066017)3261 0 R (G5.1066018)3255 0 R \r(G5.1066019)3256 0 R (G5.1066020)3257 0 R (G5.1066033)3262 0 R (G5.1066034)\r3258 0 R (G5.1066035)3264 0 R (G5.1066053)3279 0 R (G5.1066054)3265 0 R \r(G5.1066055)3266 0 R (G5.1066056)3267 0 R (G5.1066057)3268 0 R (G5.1066058)\r3269 0 R (G5.1066059)3270 0 R (G5.1066073)3280 0 R (G5.1066074)3271 0 R \r(G5.1066075)3272 0 R (G5.1066076)3273 0 R (G5.1066104)3281 0 R (G5.1066105)\r3274 0 R (G5.1066106)3275 0 R (G5.1066107)3276 0 R (G5.1066108)3277 0 R \r(G5.1066109)3278 0 R (G5.1066110)3288 0 R (G5.1066111)3289 0 R (G5.1066124)\r3387 0 R (G5.1066125)3290 0 R (G5.1066126)3291 0 R (G5.1066127)3292 0 R \r(G5.1066128)3293 0 R (G5.1066135)3298 0 R (G5.1066143)3299 0 R (G5.1066145)\r3300 0 R (G5.1066147)3301 0 R (G5.1066149)3302 0 R (G5.1066151)3303 0 R \r(G5.1066153)3304 0 R (G5.1066155)3305 0 R (G5.1066157)3306 0 R (G5.1066159)\r3307 0 R (G5.1066161)3308 0 R (G5.1066163)3309 0 R (G5.1066165)3310 0 R \r(G5.1066167)3311 0 R (G5.1066169)3312 0 R (G5.1066171)3313 0 R (G5.1066173)\r3314 0 R (G5.1066175)3315 0 R (G5.1066177)3316 0 R (G5.1066179)3317 0 R \r(G5.1066181)3318 0 R (G5.1066183)3319 0 R (G5.1066185)3320 0 R (G5.1066187)\r3321 0 R (G5.1066189)3322 0 R (G5.1066191)3323 0 R (G5.1066193)3324 0 R \r(G5.1066195)3325 0 R ] \r>> \rendobj\r9763 0 obj\r<< \r/Limits [ (G5.1066197)(G5.1066343)] \r/Names [ (G5.1066197)3326 0 R (G5.1066199)3327 0 R (G5.1066201)3328 0 R (G5.1066203)\r3329 0 R (G5.1066205)3330 0 R (G5.1066206)3294 0 R (G5.1066207)3295 0 R \r(G5.1066214)3331 0 R (G5.1066224)3332 0 R (G5.1066226)3333 0 R (G5.1066228)\r3334 0 R (G5.1066230)3335 0 R (G5.1066232)3336 0 R (G5.1066234)3337 0 R \r(G5.1066236)3338 0 R (G5.1066238)3339 0 R (G5.1066240)3340 0 R (G5.1066242)\r3341 0 R (G5.1066244)3342 0 R (G5.1066246)3343 0 R (G5.1066248)3344 0 R \r(G5.1066250)3345 0 R (G5.1066252)3346 0 R (G5.1066254)3347 0 R (G5.1066256)\r3348 0 R (G5.1066258)3349 0 R (G5.1066260)3350 0 R (G5.1066262)3351 0 R \r(G5.1066264)3352 0 R (G5.1066266)3353 0 R (G5.1066268)3354 0 R (G5.1066270)\r3355 0 R (G5.1066272)3356 0 R (G5.1066274)3357 0 R (G5.1066276)3358 0 R \r(G5.1066278)3359 0 R (G5.1066280)3360 0 R (G5.1066282)3361 0 R (G5.1066284)\r3362 0 R (G5.1066286)3363 0 R (G5.1066288)3364 0 R (G5.1066290)3365 0 R \r(G5.1066292)3366 0 R (G5.1066294)3367 0 R (G5.1066296)3368 0 R (G5.1066298)\r3369 0 R (G5.1066300)3370 0 R (G5.1066302)3371 0 R (G5.1066304)3372 0 R \r(G5.1066306)3373 0 R (G5.1066308)3374 0 R (G5.1066310)3375 0 R (G5.1066312)\r3376 0 R (G5.1066316)3377 0 R (G5.1066318)3378 0 R (G5.1066320)3379 0 R \r(G5.1066322)3380 0 R (G5.1066324)3381 0 R (G5.1066326)3382 0 R (G5.1066328)\r3383 0 R (G5.1066330)3384 0 R (G5.1066332)3385 0 R (G5.1066334)3386 0 R \r(G5.1066343)3296 0 R ] \r>> \rendobj\r9764 0 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0 R (G5.1066656)3423 0 R (G5.1066657)\r3424 0 R (G5.1066658)3425 0 R (G5.1066659)3426 0 R (G5.1066660)3427 0 R \r(G5.1066661)3428 0 R (G5.1066662)3429 0 R (G5.1066663)3430 0 R (G5.1066664)\r3431 0 R (G5.1066665)3432 0 R (G5.1066666)3433 0 R (G5.1066667)3434 0 R \r(G5.1066668)3435 0 R (G5.1066669)3436 0 R (G5.1066670)3437 0 R (G5.1066671)\r3438 0 R (G5.1066672)3439 0 R (G5.1066673)3440 0 R (G5.1066674)3441 0 R \r(G5.1066675)3457 0 R ] \r>> \rendobj\r9765 0 obj\r<< \r/Limits [ (G5.1066676)(G6.1134720)] \r/Names [ (G5.1066676)3458 0 R (G5.1066677)3459 0 R (G5.1066678)3460 0 R (G5.1066679)\r3461 0 R (G5.1066680)3462 0 R (G5.1066681)3463 0 R (G5.1066682)3464 0 R \r(G5.1066683)3465 0 R (G5.1066684)3466 0 R (G5.1066685)3467 0 R (G5.1066686)\r3468 0 R (G5.1066687)3469 0 R (G5.1066688)3470 0 R (G5.1066689)3471 0 R \r(G5.1066690)3472 0 R (G5.1066691)3473 0 R (G5.1066692)3474 0 R (G5.1066693)\r3475 0 R (G5.1066694)3476 0 R (G5.1066695)3477 0 R (G5.1066765)3021 0 R \r(G5.1066774)3042 0 R (G6.1011047)3485 0 R (G6.1052164)3707 0 R (G6.1118359)\r3487 0 R (G6.1134406)3486 0 R (G6.1134463)3493 0 R (G6.1134464)3488 0 R \r(G6.1134465)3489 0 R (G6.1134466)3490 0 R (G6.1134467)3491 0 R (G6.1134468)\r3492 0 R (G6.1134554)3500 0 R (G6.1134555)3496 0 R (G6.1134556)3497 0 R \r(G6.1134557)3498 0 R (G6.1134558)3499 0 R (G6.1134559)3504 0 R (G6.1134560)\r3505 0 R (G6.1134614)3506 0 R (G6.1134632)3541 0 R (G6.1134633)3507 0 R \r(G6.1134634)3508 0 R (G6.1134635)3509 0 R (G6.1134636)3510 0 R (G6.1134637)\r3511 0 R (G6.1134654)3542 0 R (G6.1134655)3512 0 R (G6.1134656)3513 0 R \r(G6.1134657)3514 0 R (G6.1134658)3515 0 R (G6.1134675)3562 0 R (G6.1134676)\r3546 0 R (G6.1134677)3547 0 R (G6.1134678)3548 0 R (G6.1134679)3549 0 R \r(G6.1134697)3563 0 R (G6.1134698)3550 0 R (G6.1134699)3551 0 R (G6.1134700)\r3552 0 R (G6.1134701)3553 0 R (G6.1134718)3564 0 R (G6.1134719)3554 0 R \r(G6.1134720)3555 0 R ] \r>> \rendobj\r9766 0 obj\r<< \r/Limits [ (G6.1134721)(G6.1134952)] \r/Names [ (G6.1134721)3556 0 R (G6.1134722)3557 0 R (G6.1134739)3565 0 R (G6.1134740)\r3558 0 R (G6.1134741)3559 0 R (G6.1134742)3560 0 R (G6.1134743)3561 0 R \r(G6.1134763)3649 0 R (G6.1134764)3572 0 R (G6.1134765)3573 0 R (G6.1134766)\r3574 0 R (G6.1134767)3575 0 R (G6.1134837)3576 0 R (G6.1134838)3577 0 R \r(G6.1134839)3578 0 R (G6.1134842)3582 0 R (G6.1134850)3583 0 R (G6.1134852)\r3584 0 R (G6.1134854)3585 0 R (G6.1134856)3586 0 R (G6.1134858)3587 0 R \r(G6.1134860)3588 0 R (G6.1134862)3589 0 R (G6.1134864)3590 0 R (G6.1134866)\r3591 0 R (G6.1134868)3592 0 R (G6.1134870)3593 0 R (G6.1134872)3594 0 R \r(G6.1134874)3595 0 R (G6.1134876)3596 0 R (G6.1134878)3597 0 R (G6.1134880)\r3598 0 R (G6.1134882)3599 0 R (G6.1134884)3600 0 R (G6.1134886)3601 0 R \r(G6.1134888)3602 0 R (G6.1134889)3579 0 R (G6.1134890)3580 0 R (G6.1134894)\r3603 0 R (G6.1134904)3604 0 R (G6.1134906)3605 0 R (G6.1134908)3606 0 R \r(G6.1134910)3607 0 R (G6.1134912)3608 0 R (G6.1134914)3609 0 R (G6.1134916)\r3610 0 R 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(G7.1019513)\r3989 0 R (G7.1019515)3990 0 R (G7.1019517)3991 0 R (G7.1019519)3992 0 R \r(G7.1019521)3993 0 R (G7.1019523)3994 0 R (G7.1019525)3995 0 R (G7.1019527)\r3996 0 R (G7.1019529)3997 0 R (G7.1019531)3998 0 R (G7.1019533)3999 0 R \r(G7.1019535)4000 0 R (G7.1019537)4001 0 R (G7.1019539)4002 0 R (G7.1019541)\r4003 0 R (G7.1019543)4004 0 R (G7.1019545)4005 0 R (G7.1019547)4006 0 R \r(G7.1019549)4007 0 R (G7.1019551)4008 0 R (G7.1019552)3919 0 R (G7.1019559)\r4018 0 R (G7.1019560)4019 0 R (G7.1019562)4241 0 R (G7.1019563)4239 0 R \r(G7.1019597)4102 0 R (G7.1019599)4103 0 R (G7.1019601)4104 0 R (G7.1019603)\r4105 0 R (G7.1019614)4009 0 R (G7.1019616)4010 0 R (G7.1019618)4011 0 R \r(G7.1019620)4012 0 R (G7.1019624)4110 0 R (G7.1019626)4111 0 R (G7.1019628)\r4112 0 R (G7.1019630)4113 0 R (G7.1019640)4115 0 R (G7.1019642)4116 0 R \r(G7.1019644)4117 0 R (G7.1019646)4114 0 R (G7.1019664)4070 0 R (G7.1019666)\r4071 0 R (G7.1019668)4072 0 R (G7.1019670)4073 0 R (G7.1019692)3758 0 R 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(G8.1030417)4334 0 R \r(G8.1030419)4335 0 R (G8.1030421)4336 0 R (G8.1030424)4329 0 R (G8.1030496)\r4470 0 R (G8.1030504)4471 0 R (G8.1030506)4472 0 R (G8.1030508)4473 0 R \r(G8.1030510)4474 0 R (G8.1030512)4475 0 R (G8.1030514)4476 0 R (G8.1030516)\r4477 0 R (G8.1030518)4478 0 R (G8.1030520)4479 0 R (G8.1030522)4480 0 R \r(G8.1030524)4481 0 R (G8.1030526)4482 0 R (G8.1030528)4483 0 R (G8.1030530)\r4484 0 R (G8.1030532)4485 0 R (G8.1030534)4486 0 R (G8.1030536)4487 0 R \r(G8.1030538)4488 0 R (G8.1030540)4489 0 R (G8.1030542)4490 0 R (G8.1030544)\r4491 0 R (G8.1030546)4492 0 R (G8.1030548)4493 0 R (G8.1030550)4494 0 R \r(G8.1030551)4408 0 R ] \r>> \rendobj\r9778 0 obj\r<< \r/Limits [ (G8.1030672)(G8.1030753)] \r/Names [ (G8.1030672)4537 0 R (G8.1030680)4538 0 R (G8.1030682)4539 0 R (G8.1030684)\r4540 0 R (G8.1030686)4541 0 R (G8.1030688)4542 0 R (G8.1030690)4543 0 R \r(G8.1030692)4544 0 R (G8.1030694)4545 0 R (G8.1030696)4546 0 R (G8.1030698)\r4547 0 R (G8.1030700)4548 0 R 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(G9.1089892)4696 0 R \r(G9.1089893)4697 0 R ] \r>> \rendobj\r9783 0 obj\r<< \r/Limits [ (G9.1089894)(G9.1090046)] \r/Names [ (G9.1089894)4698 0 R (G9.1089895)4699 0 R (G9.1089896)4700 0 R (G9.1089897)\r4701 0 R (G9.1089898)4702 0 R (G9.1089912)4708 0 R (G9.1089913)4703 0 R \r(G9.1089914)4704 0 R (G9.1089915)4705 0 R (G9.1089916)4717 0 R (G9.1089923)\r4729 0 R (G9.1089931)4730 0 R (G9.1089933)4731 0 R (G9.1089935)4732 0 R \r(G9.1089937)4733 0 R (G9.1089939)4734 0 R (G9.1089941)4735 0 R (G9.1089943)\r4736 0 R (G9.1089945)4737 0 R (G9.1089947)4738 0 R (G9.1089949)4739 0 R \r(G9.1089951)4740 0 R (G9.1089953)4741 0 R (G9.1089955)4742 0 R (G9.1089957)\r4743 0 R (G9.1089959)4744 0 R (G9.1089961)4745 0 R (G9.1089963)4746 0 R \r(G9.1089965)4747 0 R (G9.1089967)4748 0 R (G9.1089969)4749 0 R (G9.1089971)\r4750 0 R (G9.1089973)4751 0 R (G9.1089975)4752 0 R (G9.1089977)4753 0 R \r(G9.1089979)4754 0 R (G9.1089981)4755 0 R (G9.1089983)4756 0 R (G9.1089985)\r4757 0 R (G9.1089987)4758 0 R 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\rendobj\r9785 0 obj\r<< \r/Limits [ (G9.1090187)(I12.1.1082889)] \r/Names [ (G9.1090187)4838 0 R (G9.1090188)4839 0 R (G9.1090189)4840 0 R (G9.1090190)\r4841 0 R (G9.1090191)4842 0 R (G9.1090192)4843 0 R (G9.1090193)4844 0 R \r(G9.1090194)4845 0 R (G9.1090195)4846 0 R (G9.1090196)4847 0 R (G9.1090197)\r4848 0 R (G9.1090198)4849 0 R (G9.1090199)4850 0 R (G9.1090200)4851 0 R \r(G9.1090201)4852 0 R (G9.1090202)4853 0 R (G9.1090203)4854 0 R (G9.1090204)\r4855 0 R (G9.1090205)4856 0 R (G9.1090206)4857 0 R (G9.1090207)4858 0 R \r(G9.1090208)4859 0 R (G9.1090209)4860 0 R (G9.1090210)4861 0 R (G9.1090211)\r4862 0 R (G9.1090212)4863 0 R (G9.1090213)4864 0 R (G9.1090214)4865 0 R \r(G9.1090215)4866 0 R (G9.1090216)4867 0 R (G9.1090217)4868 0 R (G9.1090218)\r4869 0 R (G9.1090219)4870 0 R (G9.1090220)4871 0 R (G9.1090221)4872 0 R \r(G9.1090222)4873 0 R (G9.1090223)4874 0 R (G9.1090224)4875 0 R (G9.1090529)\r4642 0 R (G9.1090538)4630 0 R (G9.966345)4631 0 R (I10.1.1016815)\r4880 0 R (I10.1.1055534)4895 0 R (I10.1.1055605)4897 0 R (I10.1.1055717)\r4939 0 R (I10.1.1055736)4963 0 R (I10.1.1055832)4965 0 R (I10.1.1055958)\r4961 0 R (I10.1.1056150)5065 0 R (I11.1.1017081)5130 0 R (I11.1.1040437)\r5128 0 R (I11.1.1040446)5143 0 R (I11.1.1040500)5145 0 R (I11.1.1040561)\r5147 0 R (I11.1.1040587)5181 0 R (I11.1.1040658)5183 0 R (I11.1.1040764)\r5179 0 R (I11.1.1041030)5266 0 R (I12.1.1079066)5349 0 R (I12.1.1079640)\r5409 0 R (I12.1.1080704)5334 0 R (I12.1.1081111)5571 0 R (I12.1.1082151)\r6049 0 R (I12.1.1082889)5330 0 R ] \r>> \rendobj\r9786 0 obj\r<< \r/Limits [ (I12.1.1082939)(I18.1.630636)] \r/Names [ (I12.1.1082939)5332 0 R (I12.1.1083441)5569 0 R (I12.1.1083831)5360 0 R \r(I12.1.1083857)6047 0 R (I12.1.1085011)5405 0 R (I12.1.1085013)5407 0 R \r(I13.1.1074775)6227 0 R (I13.1.1080457)6277 0 R (I13.1.1080745)6229 0 R \r(I13.1.1083134)6273 0 R (I13.1.1083161)6275 0 R (I14.1.1063345)6408 0 R \r(I14.1.1063450)6451 0 R (I14.1.1063505)6453 0 R (I14.1.1063656)6449 0 R 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(I18.1.630622)8944 0 R \r(I18.1.630624)8945 0 R (I18.1.630626)8946 0 R (I18.1.630628)8947 0 R \r(I18.1.630630)8948 0 R (I18.1.630632)8949 0 R (I18.1.630634)8950 0 R \r(I18.1.630636)8951 0 R ] \r>> \rendobj\r9787 0 obj\r<< \r/Limits [ (I18.1.630638)(I18.1.630764)] \r/Names [ (I18.1.630638)8952 0 R (I18.1.630640)8953 0 R (I18.1.630642)8954 0 R \r(I18.1.630644)8955 0 R (I18.1.630646)8956 0 R (I18.1.630648)8957 0 R \r(I18.1.630650)8958 0 R (I18.1.630652)8959 0 R (I18.1.630654)8960 0 R \r(I18.1.630656)8961 0 R (I18.1.630658)8962 0 R (I18.1.630660)8963 0 R \r(I18.1.630662)8964 0 R (I18.1.630664)8965 0 R (I18.1.630666)8966 0 R \r(I18.1.630668)8967 0 R (I18.1.630670)8968 0 R (I18.1.630672)8969 0 R \r(I18.1.630674)8970 0 R (I18.1.630676)8971 0 R (I18.1.630678)8972 0 R \r(I18.1.630680)8973 0 R (I18.1.630682)8974 0 R (I18.1.630684)8975 0 R \r(I18.1.630686)8976 0 R (I18.1.630688)8977 0 R (I18.1.630690)9028 0 R \r(I18.1.630692)9029 0 R (I18.1.630694)9030 0 R (I18.1.630696)9031 0 R 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(I18.1.630774)9070 0 R (I18.1.630776)9071 0 R \r(I18.1.630778)9072 0 R (I18.1.630780)9073 0 R (I18.1.630782)9074 0 R \r(I18.1.630784)9075 0 R (I18.1.630786)9076 0 R (I18.1.630788)9077 0 R \r(I18.1.630790)9078 0 R (I18.1.630792)9079 0 R (I18.1.630794)9080 0 R \r(I18.1.630796)9081 0 R (I18.1.630798)9082 0 R (I18.1.630800)9083 0 R \r(I18.1.630802)9142 0 R (I18.1.630804)9143 0 R (I18.1.630806)9144 0 R \r(I18.1.630808)9145 0 R (I18.1.630810)9146 0 R (I18.1.630812)9147 0 R \r(I18.1.630814)9148 0 R (I18.1.630816)9149 0 R (I18.1.630818)9150 0 R \r(I18.1.630820)9151 0 R (I18.1.630822)9152 0 R (I18.1.630824)9153 0 R \r(I18.1.630826)9154 0 R (I18.1.630828)9155 0 R (I18.1.630830)9156 0 R \r(I18.1.630832)9157 0 R (I18.1.630834)9158 0 R (I18.1.630836)9159 0 R \r(I18.1.630838)9160 0 R (I18.1.630840)9161 0 R (I18.1.630842)9162 0 R \r(I18.1.630844)9163 0 R (I18.1.630846)9164 0 R (I18.1.630848)9165 0 R \r(I18.1.630850)9166 0 R (I18.1.630852)9167 0 R (I18.1.630854)9168 0 R \r(I18.1.630856)9169 0 R (I18.1.630858)9170 0 R (I18.1.630860)9171 0 R \r(I18.1.630862)9172 0 R (I18.1.630864)9173 0 R (I18.1.630866)9174 0 R \r(I18.1.630868)9175 0 R (I18.1.630870)9176 0 R (I18.1.630872)9177 0 R \r(I18.1.630874)9178 0 R (I18.1.630876)9179 0 R (I18.1.630878)9180 0 R \r(I18.1.630880)9181 0 R (I18.1.630882)9182 0 R (I18.1.630884)9183 0 R \r(I18.1.630886)9184 0 R (I18.1.630888)9185 0 R (I18.1.630890)9186 0 R \r(I18.1.630892)9187 0 R ] \r>> \rendobj\r9789 0 obj\r<< \r/Limits [ (I18.1.630894)(I18.1.631020)] \r/Names [ (I18.1.630894)9188 0 R (I18.1.630896)9189 0 R (I18.1.630898)9190 0 R \r(I18.1.630900)9191 0 R (I18.1.630902)9192 0 R (I18.1.630904)9193 0 R \r(I18.1.630906)9194 0 R (I18.1.630908)9249 0 R (I18.1.630910)9250 0 R \r(I18.1.630912)9251 0 R (I18.1.630914)9252 0 R (I18.1.630916)9253 0 R \r(I18.1.630918)9254 0 R (I18.1.630920)9255 0 R (I18.1.630922)9256 0 R \r(I18.1.630924)9257 0 R (I18.1.630926)9258 0 R (I18.1.630928)9259 0 R \r(I18.1.630930)9260 0 R (I18.1.630932)9261 0 R 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(I18.1.631018)9357 0 R \r(I18.1.631020)9358 0 R ] \r>> \rendobj\r9790 0 obj\r<< \r/Limits [ (I18.1.631022)(I18.1.631148)] \r/Names [ (I18.1.631022)9359 0 R (I18.1.631024)9360 0 R (I18.1.631026)9361 0 R \r(I18.1.631028)9362 0 R (I18.1.631030)9363 0 R (I18.1.631032)9364 0 R \r(I18.1.631034)9365 0 R (I18.1.631036)9366 0 R (I18.1.631038)9367 0 R \r(I18.1.631040)9368 0 R (I18.1.631042)9369 0 R (I18.1.631044)9370 0 R \r(I18.1.631046)9371 0 R (I18.1.631048)9372 0 R (I18.1.631050)9373 0 R \r(I18.1.631052)9374 0 R (I18.1.631054)9375 0 R (I18.1.631056)9376 0 R \r(I18.1.631058)9377 0 R (I18.1.631060)9378 0 R (I18.1.631062)9379 0 R \r(I18.1.631064)9380 0 R (I18.1.631066)9381 0 R (I18.1.631068)9382 0 R \r(I18.1.631070)9383 0 R (I18.1.631072)9384 0 R (I18.1.631074)9385 0 R \r(I18.1.631076)9386 0 R (I18.1.631078)9387 0 R (I18.1.631080)9388 0 R \r(I18.1.631082)9389 0 R (I18.1.631084)9390 0 R (I18.1.631086)9391 0 R \r(I18.1.631088)9392 0 R (I18.1.631090)9393 0 R (I18.1.631092)9394 0 R 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(I18.1.631254)9580 0 R (I18.1.631256)9581 0 R \r(I18.1.631258)9582 0 R (I18.1.631260)9583 0 R (I18.1.631262)9584 0 R \r(I18.1.631264)9585 0 R (I18.1.631266)9586 0 R (I18.1.631268)9587 0 R \r(I18.1.631270)9588 0 R (I18.1.631272)9589 0 R (I18.1.631274)9590 0 R \r(I18.1.631276)9591 0 R ] \r>> \rendobj\r9792 0 obj\r<< \r/Limits [ (I18.1.631278)(I6.1.1135913)] \r/Names [ (I18.1.631278)9592 0 R (I18.1.631280)9593 0 R (I18.1.631282)9594 0 R \r(I18.1.631284)9595 0 R (I18.1.631286)9596 0 R (I18.1.631288)9597 0 R \r(I18.1.631290)9598 0 R (I18.1.631292)9599 0 R (I18.1.631294)9600 0 R \r(I18.1.631296)9601 0 R (I18.1.631298)9602 0 R (I18.1.631300)9603 0 R \r(I18.1.631302)9604 0 R (I19.1.1041537)9652 0 R (I2.1.1022284)1204 0 R \r(I2.1.1023502)1170 0 R (I2.1.1023579)1205 0 R (I2.1.1023612)1206 0 R \r(I2.1.1023621)1207 0 R (I2.1.1023630)1208 0 R (I2.1.1023655)1209 0 R \r(I2.1.1023664)1210 0 R (I3.1.1024359)1748 0 R (I3.1.1025048)1750 0 R \r(I3.1.1059262)1783 0 R (I3.1.1059279)1798 0 R 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--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
+<html><head>
+ <meta http-equiv="CONTENT-TYPE" content="text/html; charset=iso-8859-1"><title>LEON3MP Reference Design</title>
+
+ <meta name="GENERATOR" content="OpenOffice.org 1.1.0 (Linux)">
+ <meta name="CREATED" content="20040423;18351200">
+ <meta name="CHANGED" content="20040426;16351800"></head>
+<body dir="ltr" lang="en-US">
+<table border="0" cellpadding="2" cellspacing="2" width="750">
+ <tbody>
+ <tr>
+ <td valign="top">
+ <h3><span style="font-family: helvetica,arial,sans-serif;">LEON3MP
+reference design for the GR-XS3C-1500 board<br>
+</span></h3>
+
+
+ <h4 style="font-family: helvetica,arial,sans-serif;">Introduction</h4>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">The
+LEON3MP is a generic reference
+design for LEON3-based systems. This version is specially adapted for
+the <a href="http://www.pender.ch/">GR-XC3S-1500 Spartan3 development board</a>, and contains the following
+functionality:<br>
+<br>
+</span></small>
+ <table border="0" cellpadding="2" cellspacing="2" width="700">
+
+ <tbody>
+ <tr>
+ <td valign="top">
+ <ul><li><small><span style="font-family: helvetica,arial,sans-serif;">1 -
+4 LEON3 processor
+cores with MP support</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Multi-processor
+debug support unit (DSU)<br>
+ </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">8-bit
+PROM controller</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit SDRAM controller<br>
+ </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Round-robin
+AHB arbiter/controller</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">AHB/APB bridge with
+plug&play support<br>
+ </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Multi-processor
+interrupt controller</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit modular timer
+unit</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">1 -
+2 UARTs with FIFO<br>
+ </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">10/100 ethernet MAC</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">PS2 mouse/keyboard interface</span></small></li>
+ <li><small><span style="font-family: helvetica,arial,sans-serif;">24-bit Video DAC interface<br>
+ </span></small></li>
+<li><small><span style="font-family: helvetica,arial,sans-serif;">Serial debug
+communication link</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Etherner debug
+communication link</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">JTAG debug communication link</span></small></li></ul>
+ </td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"><img alt="" src="../../boards/gr-xc3s-1500/gr-xc3s_top_small.jpg" align="right" height="212" width="320"></span></small></td>
+ </tr>
+ </tbody>
+ </table>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
+<br>
+The LEON3MP-GR-XS3C-1500 design is provided together with GRLIB, and is
+located in grlib/designs/leon3-gr-xc3s-1500 .<br>
+</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
+</span></small>
+ <h4><span style="font-family: helvetica,arial,sans-serif;">Reference
+architecture</span></h4>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">The
+LEON3MP is made up by cores from the GRLIB IP library, which are
+connected together via the AMBA AHB and APB buses. The plug&play
+configuration method of GRLIB makes it possible to assign any
+combination of addresses and interrupts to the cores. However, to be
+software compatible with simple operating systems such as the LEON
+Bare-C cross-compiler, some of the vital cores must be assigned to
+predefined addresses and interrupts. The table below shows the
+reference assigment in the LEON3MP design:<br>
+<br>
+</span></small>
+ <table style="width: 100%; text-align: left;" border="1" cellpadding="2" cellspacing="2">
+
+ <tbody>
+ <tr>
+ <th style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Core</span></small></th>
+ <th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory area<br>
+ </span></small></th>
+ <th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt</span></small></th>
+ </tr>
+ <tr>
+ <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">PROM/SDRAM controller<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x00000000 -
+0x20000000 : 8 Mbyte 8-bit flash PROM<br>
+0x40000000 - 0x80000000 : 64 Mbyte 32-bit SDRAM<br>
+0x80000000 - 0x80000100 : Configuration registers (APB)<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
+ </tr>
+
+
+<tr>
+ <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">APB bridge<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000000 -
+0x80100000 : APB bus<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
+ </tr>
+ <tr>
+ <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">UART</span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000100 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000200 : UART1
+registers</span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">2</span></small><br>
+ </td>
+ </tr>
+ <tr>
+ <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt controller</span></small><br>
+ </td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000200 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000300 : IRQ
+registers<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
+ </tr>
+ <tr>
+ <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Timer unit<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000300</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0x80000400 : timer
+registers<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">8, 9<br>
+ </span></small></td>
+ </tr>
+ <tr>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">LEON3 debug support
+unit (DSU)<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x90000000 -
+0xA0000000 : DSU registers<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
+ </tr>
+ </tbody>
+ </table>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;"><br>
+Additional (optional) IP cores are assigned addresses and interrupts as
+desribed in the table below. These assignments are LEON3MP specific and
+can be changed without impact on software compatibility.<br>
+<br>
+</span></small>
+ <table style="width: 100%; text-align: left;" border="1" cellpadding="2" cellspacing="2">
+
+ <tbody>
+ <tr>
+ <th style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Core</span></small></th>
+ <th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory area<br>
+ </span></small></th>
+ <th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt</span></small></th>
+ </tr>
+
+
+
+ <tr>
+ <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Serial debug
+communication link<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000700 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000800 : AHB UART
+registers</span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small> </td>
+ </tr>
+ <tr>
+ <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Ethernet debug
+communication link</span></small><br>
+ </td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small> </td>
+ </tr>
+ <tr>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">JTAG debug
+communication link</span></small></td>
+ <td valign="top">-<br>
+ </td>
+ <td valign="top">-<br>
+ </td>
+ </tr>
+<tr>
+ <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">10/100 Mbit ethernet MAC<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xFFFB0000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xFFFB1000 :
+ethernet
+control registers<br>
+ </span></small></td>
+ <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">12</span></small></td>
+ </tr>
+
+ <tr>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">On-chip RAM<br>
+
+ </span></small></td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xA0000000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xA0100000 : On-chip
+RAM<br>
+ </span></small></td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
+ </tr>
+ <tr>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">UART</span></small></td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000900 -
+0x80000A00 : Secondary UART<br>
+ </span></small></td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">3</span></small></td>
+ </tr><tr>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">PS/2 Keyboard interface</span></small><br>
+ </td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000500 -
+0x80000600 : PS/2 registers<br>
+</span></small></td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">4</span></small><br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">VGA controller<br>
+</span></small></td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000600 -
+0x80000700 : VGA registers</span></small></td>
+ <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
+ </tr>
+
+ </tbody>
+ </table>
+
+ <br>
+
+ <h4><small><span style="font-family: helvetica,arial,sans-serif;">
+</span></small></h4>
+
+ <h4><span style="font-family: helvetica,arial,sans-serif;">Configuration</span></h4>
+
+ <div style="text-align: left;"><small><span style="font-family: helvetica,arial,sans-serif;">The configuartion of
+the LEON3MP design is defined through the config package located <a href="config.vhd">config.vhd</a>.
+This file can be automatically generated using a GUI based on tkconfig.
+To launch the GUI, do 'make xconfig'. After the configuration is
+completed, save and
+exit the tool and config.vhd will be created automatically.<br>
+<br>
+<img alt="" src="../share/gui.gif" height="148" width="561"><br>
+<br>
+<i>Figure 1. LEON3MP configuration GUI</i></span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><br style="font-family: helvetica,arial,sans-serif;">
+<small>
+</small></div>
+
+ <h4><span style="font-family: helvetica,arial,sans-serif;">Simulation</span></h4>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">To
+simulate the testbench, first compile the model for simulation. This
+can be done automatically for three different simulators. Execute one
+of the following commands:</span><br style="font-family: helvetica,arial,sans-serif;">
+ </small>
+ <ul style="font-family: helvetica,arial,sans-serif;">
+<li><small>make vsim</small></li><li><small>make ncsim</small></li><li><small>make ghdl</small></li>
+ </ul>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">For vsim,
+start the simulation with 'vsim testbench' and do 'run 100'. This
+should print the current LEON3MP configuration:</span><br style="font-family: helvetica,arial,sans-serif;">
+ </small><br>
+
+ <small><span style="font-family: courier new,courier,monospace;">$ vsim
+-c -quiet testbench</span><br style="font-family: courier new,courier,monospace;">
+<span style="font-family: courier new,courier,monospace;">Reading
+/usr/local/model58/tcl/vsim/pref.tcl</span><br style="font-family: courier new,courier,monospace;">
+<span style="font-family: courier new,courier,monospace;">Reading
+/home/jiri/modelsim.tcl</span><br style="font-family: courier new,courier,monospace;">
+ </small><small><span style="font-family: courier new,courier,monospace;"></span></small><br style="font-family: courier new,courier,monospace;">
+
+ <small><span style="font-family: courier new,courier,monospace;"># 5.8</span><br style="font-family: courier new,courier,monospace;">
+ </small><small><span style="font-family: courier new,courier,monospace;"></span><big><tt>#
+VSIM 1> run<br>
+# LEON3 Demonstration design<br>
+# GRLIB Version 0.13<br>
+# Target technology: virtex2 , memory library: virtex2<br>
+# ahbctrl: mst0: Gaisler
+Research Leon3 SPARC V8
+Processor<br>
+# ahbctrl: mst1: Gaisler
+Research AHB Debug UART<br>
+# ahbctrl: mst2: Gaisler
+Research Fast 32-bit PCI
+Bridge<br>
+# ahbctrl: mst3: Gaisler
+Research AMBA DMA controller<br>
+# ahbctrl: mst5: Gaisler
+Research OC ethernet AHB
+interface<br>
+# ahbctrl: slv0: Gaisler
+Research Simple SRAM
+Controller<br>
+# ahbctrl: memory at 0x00000000,
+size 16 Mbyte, cacheable, prefetch<br>
+# ahbctrl: memory at 0x40000000,
+size 16 Mbyte, cacheable, prefetch<br>
+# ahbctrl: slv1: Gaisler
+Research AHB/APB Bridge<br>
+# ahbctrl: memory at 0x80000000,
+size 1 Mbyte<br>
+# ahbctrl: slv2: Gaisler
+Research Leon3 Debug Support
+Unit<br>
+# ahbctrl: memory at 0x90000000,
+size 256 Mbyte<br>
+# ahbctrl: slv4: Gaisler
+Research Fast 32-bit PCI
+Bridge<br>
+# ahbctrl: memory at 0xe0000000,
+size 256 Mbyte<br>
+# ahbctrl: I/O port at 0xfff80000,
+size 128kbyte<br>
+# ahbctrl: slv5: Gaisler
+Research OC ethernet AHB
+interface<br>
+# ahbctrl: I/O port at 0xfffb0000,
+size 4kbyte<br>
+# ahbctrl: slv6: Gaisler
+Research OC CAN AHB interface<br>
+# ahbctrl: I/O port at 0xfffc0000,
+size 4kbyte<br>
+# ahbctrl: slv7: Gaisler
+Research Generic AHB SRAM
+module<br>
+# ahbctrl: memory at 0xa0000000,
+size 1 Mbyte, cacheable, prefetch<br>
+# ahbctrl: AHB arbiter/multiplexer rev 1<br>
+# ahbctrl: Common I/O area at 0xfff00000, 1 Mbyte<br>
+# ahbctrl: Configuration area at 0xfffff000, 4 kbyte<br>
+# apbctrl: APB Bridge at 0x80000000 rev 1<br>
+# apbctrl: slv1: Gaisler
+Research Generic UART<br>
+# apbctrl: I/O ports at 0x80000100,
+size 256 byte<br>
+# apbctrl: slv2: Gaisler
+Research Multi-processor
+Interrupt Ctrl.<br>
+# apbctrl: I/O ports at 0x80000200,
+size 256 byte<br>
+# apbctrl: slv3: Gaisler
+Research Modular Timer Unit<br>
+# apbctrl: I/O ports at 0x80000300,
+size 256 byte<br>
+# apbctrl: slv4: Gaisler
+Research Fast 32-bit PCI
+Bridge<br>
+# apbctrl: I/O ports at 0x80000400,
+size 256 byte<br>
+# apbctrl: slv5: Gaisler
+Research AMBA DMA controller<br>
+# apbctrl: I/O ports at 0x80000500,
+size 256 byte<br>
+# apbctrl: slv7: Gaisler
+Research AHB Debug UART<br>
+# apbctrl: I/O ports at 0x80000700,
+size 256 byte<br>
+# ahbram7: AHB SRAM Module rev 1, 2 kbytes<br>
+# can_oc6: Opencores CAN MAC, rev 0, irq 13<br>
+# eth_oc5: Wishbone/AHB interface for OC ethernet MAC, irq 12<br>
+# eth_oc5: Opencores 10/100 Mbit ethernet MAC, rev 0<br>
+# pci_mtf4: 32-bit PCI/AHB bridge rev 0, 2 Mbyte PCI memory BAR,
+8-word FIFOs<br>
+# dmactrl5: 32-bit DMA controller & AHB/AHB bridge rev 0<br>
+# gptimer3: GR Timer Unit rev 0, 16-bit scaler, 1 32-bit timers, irq 8<br>
+# irqmp: Multi-processor Interrupt Controller rev 1, #cpu 1<br>
+# apbuart1: Generic UART rev 1, irq 2<br>
+# srctrl0: 32-bit PROM/SRAM controller rev 0<br>
+# ahbuart7: AHB Debug UART rev 0<br>
+# dsu3_2: LEON3 Debug support unit<br>
+# leon3_0: LEON3 SPARC V8 processor rev 0<br>
+# leon3_0: icache 1*4 kbyte, dcache 1*4 kbyte</tt></big><br style="font-family: courier new,courier,monospace;">
+<span style="font-family: courier new,courier,monospace;"></span><span style="font-family: courier new,courier,monospace;"></span><br style="font-family: courier new,courier,monospace;">
+<span style="font-family: courier new,courier,monospace;">VSIM 2>
+run -all<br># **** GRLIB system test starting ****<br>
+# Leon3 SPARC V8 Processor<br>
+# register file<br>
+# multiplier<br>
+# radix-2 divider<br>
+# cache system<br>
+# Multi-processor Interrupt Ctrl.<br>
+# Generic UART<br>
+# Modular Timer Unit<br>
+# Test passed, halting with IU error mode<br>
+#<br>
+# ** Failure: *** IU in error mode, simulation halted ***<br>
+# Time: 669213500 ps Iteration: 1 Process: /testbench/iuerr File: testbench.vhd<br>
+# Break at testbench.vhd line 263<br>
+# Stopped at testbench.vhd line 263<br>
+ <br>
+</span></small><h4><small><span style="font-family: helvetica,arial,sans-serif;">Synthesis<br>
+</span></small></h4>
+
+ <h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">To
+synthesize and place&route, use the make utility and issue either 'make ise' or 'make ise-synp' to<br>
+use the XST or Synplify tools respectively.<br>
+<br>
+</span></small><small><span style="font-family: helvetica,arial,sans-serif;">Alternatively, the design can be implemented using
+the graphical XGrlib tool, which is started with 'make xgrlib'.<br>
+<br>
+<br>
+<img alt="" src="../../doc/grlib/xgrlib.gif" height="537" width="619"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> </span></small><br>
+
+ <div style="text-align: justify;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></div>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">
+<br>
+</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><i>Figure 2. XGrlib
+implementation tool</i></span></small><br>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;"><br>
+To program the fpga, issue 'make ise-prog-fpga'. To re-program the configuration proms, do 'make ise-prog-prom'.<br>
+After programming the proms, power-cycle the board to re-load the fpga.<br>
+<br>
+</span></small><small><span style="font-family: helvetica,arial,sans-serif;">To get
+started quicker, suitable leon3mp.bit and leon3mp.msk files are provided in the <i>bitfiles</i>
+directory. The fpga or
+configuration proms can be programmed directly with this configuration,
+using the following commands: 'make ise-prog-fpga-ref' or 'make
+ise-prog-prom-ref '.</span></small><br>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">
+</span></small>
+ <h4><small><span style="font-family: helvetica,arial,sans-serif;">Software
+development</span></small></h4>
+
+ <h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">To
+develop RTEMS applications, download and install the <a href="http://www.gaisler.se/bin/linux/rcc-1.0.0.pdf">LEON3 RTEMS
+Cross-compiler</a> from gaisler.com. The LEON3 bsp automatically
+detects
+the location of UARTs, timers, interrupt controller and ethernet core
+using the plug&play information. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">
+A <a href="http://www.gaisler.com/doc/bcc.html">LEON3 bare-C compiler</a>
+is also available for download from gaisler.com. Both the RTEMS
+and the bare-C compilers now come with full source code for both the
+low-level I/O routines as well as the mkprom prom builder. This should
+allow users to adapt the run-time to their own needs. All sources are
+provided under GNU GPL, contact <a href="mailto:sales@gaisler.com">Gaisler
+Research</a> for commercial licenses of this software.<br>
+<br>
+A Leon3 port of uClinux and linux-2.6.11 is available in the <a href="http://www.gaisler.com/products/linux.html">snapgear
+linux distribution</a>.<br>
+</span></small>
+ <h4><small><span style="font-family: helvetica,arial,sans-serif;">Debugging<br>
+</span></small></h4>
+
+ <small><span style="font-family: helvetica,arial,sans-serif;">The
+on-chip debug support unit (DSU) makes debugging of target hardware
+relatively easy. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">The
+design support both serial, ethernet and JTAG debug interface, and the </span></small><small><span style="font-family: helvetica,arial,sans-serif;"> <a href="http://www.gaisler.com/products/grmon/grmon.html">GRMON debug
+monitor</a></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> can be attached with a serial cable, over a LAN, or using the Xilinx JTAG programming cable. </span></small><small><span style="font-family: helvetica,arial,sans-serif;"> Note that when you use the ethernet or the JTAG
+interface, you need specify the frequency of the AHB clock since it is
+not auto-detected. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">Below
+is a log from a debug session.<br>
+<br>
+</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">
+<br style="font-family: courier new,courier,monospace;">
+<span style="font-family: courier new,courier,monospace;">$jiri@home:~$ grmon -u -grlib -jtag -freq 40<br>
+<br>
+ GRMON - The LEON multi purpose monitor v1.0.9<br>
+<br>
+ Copyright (C) 2004, Gaisler Research - all rights reserved.<br>
+ For latest updates, go to http://www.gaisler.com/<br>
+ Comments or bug-reports to grmon@gaisler.com<br>
+<br>
+<br>
+ GRLIB DSU Monitor backend 1.0.2 (professional version)<br>
+<br>
+using JTAG cable on parallel port<br>
+<br>
+ initialising .............<br>
+<br> Component
+Vendor<br>
+ Leon3 SPARC V8 Processor Gaisler Research<br>
+ AHB Debug
+UART
+Gaisler Research<br>
+ AHB Debug JTAG
+TAP
+Gaisler Research<br>
+ AHB interface for 10/100 Mbit MA Gaisler Research<br>
+ Nuhorizons Spartan3 I/O interfac Gaisler Research<br>
+ AHB/APB
+Bridge
+Gaisler Research<br>
+ Leon3 Debug Support Unit Gaisler Research<br>
+ 32-bit PC133 SDRAM Controller Gaisler Research<br>
+ AHB interface for 10/100 Mbit MA Gaisler Research<br>
+ CAN
+controller
+Gaisler Research<br>
+ Generic APB
+UART
+Gaisler Research<br>
+ Multi-processor Interrupt Ctrl Gaisler Research<br>
+ Modular Timer
+Unit
+Gaisler Research<br>
+<br>
+ Use command 'info sys' to print a detailed report of attached cores<br>
+<br>
+grmon[grlib]> inf sys<br>
+00.01:003 Gaisler Research Leon3 SPARC V8 Processor (ver 0)<br>
+ ahb master 0<br>
+01.01:007 Gaisler Research AHB Debug UART (ver 0)<br>
+ ahb master 1<br>
+ apb: 80000700 - 80000800<br>
+ baud rate 115200, ahb frequency 40.00<br>
+02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0)<br>
+ ahb master 2<br>
+03.01:005 Gaisler Research AHB interface for 10/100 Mbit MA (ver 0)<br>
+ ahb master 3<br>
+00.01:02b Gaisler Research Nuhorizons Spartan3 I/O interfac (ver 0)<br>
+ ahb: 00000000 - 00400000<br>
+ 16-bit prom @ 0x00000000<br>
+01.01:006 Gaisler Research AHB/APB Bridge (ver 0)<br>
+ ahb: 80000000 - 80100000<br>
+02.01:004 Gaisler Research Leon3 Debug Support Unit (ver 0)<br>
+ ahb: 90000000 - a0000000<br>
+ AHB trace 64 lines, stack pointer 0x00000000<br>
+ CPU#0 win 8, hwbp 4, itrace 64, V8 mul/div, lddel 1<br>
+
+icache 2 * 4 kbyte, 32 byte/line lru<br>
+
+dcache 2 * 4 kbyte, 32 byte/line lru<br>
+03.01:009 Gaisler Research 32-bit PC133 SDRAM Controller (ver 0)<br>
+ ahb: 40000000 - 48000000<br>
+ ahb: fff00100 - fff00200<br>
+
+32-bit sdram: 1 * 16 Mbyte @ 0x40000000, col 8, cas 2, ref 15.6 us<br>
+05.01:005 Gaisler Research AHB interface for 10/100 Mbit MA (ver 0)<br>
+ irq 12<br>
+ ahb: fffb0000 - fffb1000<br>
+06.01:019 Gaisler Research CAN controller (ver 0)<br>
+ irq 13<br>
+ ahb: fffc0000 - fffc1000<br>
+01.01:00c Gaisler Research Generic APB UART (ver 1)<br>
+ irq 2<br>
+ apb: 80000100 - 80000200<br>
+ baud rate 38400, DSU mode<br>
+02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 2)<br>
+ apb: 80000200 - 80000300<br>
+03.01:011 Gaisler Research Modular Timer Unit (ver 0)<br>
+ irq 8<br>
+ apb: 80000300 - 80000400<br>
+ 8-bit scaler, 2 * 32-bit timers, divisor 40<br>
+grmon[grlib]> lo /opt/sparc-elf/src/examples/stanford<br>
+section: .text at 0x40000000, size 61200 bytes<br>
+section: .data at 0x4000ef10, size 2080 bytes<br>
+total size: 63280 bytes (222.1 kbit/s)<br>
+read 197 symbols<br>
+entry point: 0x40000000<br>
+grmon[grlib]> run<br>
+Starting<br>
+ Perm Towers Queens
+Intmm Mm Puzzle
+Quick Bubble Tree FFT<br>
+ 34
+50 34
+34 900
+316 34
+50 217 1083<br>
+<br>
+Nonfloating point composite is 114<br>
+<br>
+Floating point composite is 857<br>
+<br>
+Program exited normally.<br>
+grmon[grlib]></span><span style="font-family: courier new,courier,monospace;"></span><br>
+<br>
+<br>
+The LEON3MP test bench includes memory models of both boot-prom, sram
+and sdram. To build memory images for these models, do 'make soft' .
+Note: this will require that the bare-C compiler for LEON3 is
+installed,
+and /opt/sparc-elf/bin is added to the PATH.<br>
+<br>
+<br>
+</span></small></td>
+ </tr>
+ <tr>
+ <td valign="top"><br>
+ </td>
+ </tr>
+ </tbody>
+</table>
+<h3><br>
+<span style="font-family: helvetica,arial,sans-serif;"></span></h3>
+<small><span style="font-family: helvetica,arial,sans-serif;">
+</span></small>
+</body></html>
\ No newline at end of file
--- /dev/null
+# FILE: header.tk
+# This file is boilerplate TCL/TK function definitions for 'make xconfig'.
+#
+# CHANGES
+# =======
+#
+# 8 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
+# - Remove unused do_cmd function (part of the 2.0 sound support).
+# - Arrange buttons in three columns for better screen fitting.
+# - Add CONSTANT_Y, CONSTANT_M, CONSTANT_N for commands like:
+# dep_tristate 'foo' CONFIG_FOO m
+#
+# 23 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
+# - Shut vfix the hell up.
+#
+# 24 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
+# - Improve the exit message (Jeff Ronne).
+
+#
+# This is a handy replacement for ".widget cget" that requires neither tk4
+# nor additional source code uglification.
+#
+proc cget { w option } {
+ return "[lindex [$w configure $option] 4]"
+}
+
+#
+# Function to compensate for broken config.in scripts like the sound driver,
+# which make dependencies on variables that are never even conditionally
+# defined.
+#
+proc vfix { var } {
+ global $var
+ if [ catch {eval concat $$var} ] {
+ set $var 4
+ }
+}
+
+#
+# Constant values used by certain dep_tristate commands.
+#
+set CONSTANT_Y 1
+set CONSTANT_M 2
+set CONSTANT_N 0
+set CONSTANT_E 4
+
+#
+# Create a "reference" object to steal colors from.
+#
+button .ref
+
+#
+# On monochrome displays, -disabledforeground is blank by default; that's
+# bad. Fill it with -foreground instead.
+#
+if { [cget .ref -disabledforeground] == "" } {
+ .ref configure -disabledforeground [cget .ref -foreground]
+}
+
+
+#
+# Define some macros we will need to parse the config.in file.
+#
+
+proc mainmenu_name { text } {
+ wm title . "$text"
+}
+
+proc menu_option { w menu_num text } {
+ global menus_per_column
+ global processed_top_level
+ set processed_top_level [expr $processed_top_level + 1]
+ if { $processed_top_level <= $menus_per_column } then {
+ set myframe left
+ } elseif { $processed_top_level <= [expr 2 * $menus_per_column] } then {
+ set myframe middle
+ } else {
+ set myframe right
+ }
+ button .f0.x$menu_num -anchor w -text "$text" \
+ -command "$w .$w \"$text\""
+ pack .f0.x$menu_num -pady 0 -side top -fill x -in .f0.$myframe
+}
+
+proc load_configfile { w title func } {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+ global loadfile
+ frame $w.x
+ label $w.bm -bitmap questhead
+ pack $w.bm -pady 10 -side top -padx 10
+ label $w.x.l -text "Enter filename:" -relief raised
+ entry $w.x.x -width 35 -relief sunken -borderwidth 2 \
+ -textvariable loadfile
+ pack $w.x.l $w.x.x -anchor w -side left
+ pack $w.x -side top -pady 10
+ wm title $w "$title"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "OK" -width 20 \
+ -command "destroy $w; focus $oldFocus;$func .fileio"
+ button $w.f.canc -text "Cancel" \
+ -width 20 -command "destroy $w; focus $oldFocus"
+ pack $w.f.back $w.f.canc -side left -pady 10 -padx 45
+ pack $w.f -pady 10 -side bottom -padx 10 -anchor w
+ focus $w
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+}
+
+bind all <Alt-q> {maybe_exit .maybe}
+
+proc maybe_exit { w } {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+ label $w.bm -bitmap questhead
+ pack $w.bm -pady 10 -side top -padx 10
+ message $w.m -width 400 -aspect 300 \
+ -text "Changes will be lost. Are you sure?" -relief flat
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Are you sure?"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "OK" -width 20 \
+ -command "exit 1"
+ button $w.f.canc -text "Cancel" \
+ -width 20 -command "destroy $w; focus $oldFocus"
+ pack $w.f.back $w.f.canc -side left -pady 10 -padx 45
+ pack $w.f -pady 10 -side bottom -padx 10 -anchor w
+ bind $w <Return> "exit 1"
+ bind $w <Escape> "destroy $w; focus $oldFocus"
+ focus $w
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+}
+
+proc read_config_file { w } {
+ global loadfile
+ if { [string length $loadfile] != 0 && [file readable $loadfile] == 1 } then {
+ read_config $loadfile
+ } else {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+ message $w.m -width 400 -aspect 300 -text \
+ "Unable to read file $loadfile" \
+ -relief raised
+ label $w.bm -bitmap error
+ pack $w.bm $w.m -pady 10 -side top -padx 10
+ wm title $w "Xconfig Internal Error"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "Bummer" \
+ -width 10 -command "destroy $w; focus $oldFocus"
+ pack $w.f.back -side bottom -pady 10 -anchor s
+ pack $w.f -pady 10 -side top -padx 10 -anchor s
+ focus $w
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+ }
+}
+
+proc write_config_file { w } {
+ global loadfile
+ if { [string length $loadfile] != 0
+ && ([file writable $loadfile] == 1 || ([file exists $loadfile] == 0 && [file writable [file dirname $loadfile]] == 1)) } then {
+ writeconfig $loadfile .null
+ } else {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+ message $w.m -width 400 -aspect 300 -text \
+ "Unable to write file $loadfile" \
+ -relief raised
+ label $w.bm -bitmap error
+ pack $w.bm $w.m -pady 10 -side top -padx 10
+ wm title $w "Xconfig Internal Error"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 10 -command "destroy $w; focus $oldFocus"
+ pack $w.f.back -side bottom -pady 10 -anchor s
+ pack $w.f -pady 10 -side top -padx 10 -anchor s
+ focus $w
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+ }
+}
+
+proc read_config { filename } {
+ set file1 [open $filename r]
+ clear_choices
+ while { [gets $file1 line] >= 0} {
+ if [regexp {([0-9A-Za-z_]+)=([ynm])} $line foo var value] {
+ if { $value == "y" } then { set cmd "global $var; set $var 1" }
+ if { $value == "n" } then { set cmd "global $var; set $var 0" }
+ if { $value == "m" } then { set cmd "global $var; set $var 2" }
+ eval $cmd
+ }
+ if [regexp {# ([0-9A-Za-z_]+) is not set} $line foo var] {
+ set cmd "global $var; set $var 0"
+ eval $cmd
+ }
+ if [regexp {([0-9A-Za-z_]+)=([0-9A-Fa-f]+)} $line foo var value] {
+ set cmd "global $var; set $var $value"
+ eval $cmd
+ }
+ if [regexp {([0-9A-Za-z_]+)="([^"]*)"} $line foo var value] {
+ set cmd "global $var; set $var \"$value\""
+ eval $cmd
+ }
+ }
+ close $file1
+ update_choices
+ update_mainmenu
+}
+proc write_comment { file1 file2 text } {
+ puts $file1 ""
+ puts $file1 "#"
+ puts $file1 "# $text"
+ puts $file1 "#"
+ puts $file2 "/*"
+ puts $file2 " * $text"
+ puts $file2 " */"
+}
+
+proc effective_dep { deplist } {
+ global CONFIG_MODULES
+ set depend 1
+ foreach i $deplist {
+ if {$i == 0} then {set depend 0}
+ if {$i == 2 && $depend == 1} then {set depend 2}
+ }
+ if {$depend == 2 && $CONFIG_MODULES == 0} then {set depend 0}
+ return $depend
+}
+
+proc sync_tristate { var dep } {
+ global CONFIG_MODULES
+ if {$dep == 0 && ($var == 1 || $var == 2)} then {
+ set var 0
+ } elseif {$dep == 2 && $var == 1} then {
+ set var 2
+ } elseif {$var == 2 && $CONFIG_MODULES == 0} then {
+ if {$dep == 1} then {set var 1} else {set var 0}
+ }
+ return $var
+}
+
+proc sync_bool { var dep modset } {
+ set var [sync_tristate $var $dep]
+ if {$dep == 2 && $var == 2} then {
+ set var $modset
+ }
+ return $var
+}
+
+proc write_tristate { file1 file2 varname variable deplist modset } {
+ set variable [sync_tristate $variable [effective_dep $deplist]]
+ if { $variable == 2 } \
+ then { set variable $modset }
+ if { $variable == 1 } \
+ then { puts $file1 "$varname=y"; \
+ puts $file2 "#define $varname 1" } \
+ elseif { $variable == 2 } \
+ then { puts $file1 "$varname=m"; \
+ puts $file2 "#undef $varname"; \
+ puts $file2 "#define ${varname}_MODULE 1" } \
+ elseif { $variable == 0 } \
+ then { puts $file1 "# $varname is not set"; \
+ puts $file2 "#undef $varname"} \
+ else { \
+ puts stdout "ERROR - Attempting to write value for unconfigured variable ($varname)." \
+ }
+}
+
+proc write_int { file1 file2 varname variable dep } {
+ if { $dep == 0 } \
+ then { puts $file1 "# $varname is not set"; \
+ puts $file2 "#undef $varname"} \
+ else {
+ puts $file1 "$varname=$variable"; \
+ puts $file2 "#define $varname ($variable)"; \
+ }
+}
+
+proc write_hex { file1 file2 varname variable dep } {
+ if { $dep == 0 } \
+ then { puts $file1 "# $varname is not set"; \
+ puts $file2 "#undef $varname"} \
+ else {
+ puts $file1 "$varname=$variable"; \
+ puts -nonewline $file2 "#define $varname "; \
+ puts $file2 [exec echo $variable | sed s/^0\[xX\]//]; \
+ }
+}
+
+proc write_string { file1 file2 varname variable dep } {
+ if { $dep == 0 } \
+ then { puts $file1 "# $varname is not set"; \
+ puts $file2 "#undef $varname"} \
+ else {
+ puts $file1 "$varname=\"$variable\""; \
+ puts $file2 "#define $varname \"$variable\""; \
+ }
+}
+
+proc option_name {w mnum line text helpidx} {
+ button $w.x$line.l -text "$text" -relief groove -anchor w
+ $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
+ -activeback [cget $w.x$line.l -bg]
+ button $w.x$line.help -text "Help" -relief raised \
+ -command "dohelp .dohelp $helpidx .menu$mnum"
+ pack $w.x$line.help -side right -fill y
+ pack $w.x$line.l -side right -fill both -expand on
+}
+
+proc toggle_switch2 {w mnum line text variable} {
+ frame $w.x$line -relief sunken
+ radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \
+ -relief groove -width 2 -command "update_active"
+# radiobutton $w.x$line.m -text "-" -variable $variable -value 2 \
+# -relief groove -width 2 -command "update_active"
+ radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \
+ -relief groove -width 2 -command "update_active"
+
+ option_name $w $mnum $line $text $variable
+
+ pack $w.x$line.n $w.x$line.y -side right -fill y
+}
+
+proc toggle_switch3 {w mnum line text variable} {
+ frame $w.x$line -relief sunken
+ radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \
+ -relief groove -width 2 -command "update_active"
+ radiobutton $w.x$line.m -text "m" -variable $variable -value 2 \
+ -relief groove -width 2 -command "update_active"
+ radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \
+ -relief groove -width 2 -command "update_active"
+
+ option_name $w $mnum $line $text $variable
+
+ global CONFIG_MODULES
+ if {($CONFIG_MODULES == 0)} then {
+ $w.x$line.m configure -state disabled
+ }
+ pack $w.x$line.n $w.x$line.m $w.x$line.y -side right -fill y
+}
+
+proc bool {w mnum line text variable} {
+ toggle_switch2 $w $mnum $line $text $variable
+# $w.x$line.m configure -state disabled
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc tristate {w mnum line text variable } {
+ toggle_switch3 $w $mnum $line $text $variable
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc dep_tristate {w mnum line text variable } {
+ tristate $w $mnum $line $text $variable
+}
+
+proc dep_bool {w mnum line text variable } {
+ bool $w $mnum $line $text $variable
+}
+
+proc int { w mnum line text variable } {
+ frame $w.x$line
+ entry $w.x$line.x -width 11 -relief sunken -borderwidth 2 \
+ -textvariable $variable
+ option_name $w $mnum $line $text $variable
+ pack $w.x$line.x -anchor w -side right -fill y
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc hex { w mnum line text variable } {
+ int $w $mnum $line $text $variable
+}
+
+proc istring { w mnum line text variable } {
+ frame $w.x$line
+ entry $w.x$line.x -width 18 -relief sunken -borderwidth 2 \
+ -textvariable $variable
+ option_name $w $mnum $line $text $variable
+ pack $w.x$line.x -anchor w -side right -fill y
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc minimenu { w mnum line text variable helpidx } {
+ frame $w.x$line
+ menubutton $w.x$line.x -textvariable $variable -menu \
+ $w.x$line.x.menu -relief raised \
+ -anchor w
+ option_name $w $mnum $line $text $helpidx
+ pack $w.x$line.x -anchor w -side right -fill y
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc menusplit {w m n} {
+ if { $n > 2 } then {
+ update idletasks
+ set menuoptsize [expr [$m yposition 2] - [$m yposition 1]]
+ set maxsize [winfo screenheight $w]
+ set splitpoint [expr $maxsize * 4 / 5 / $menuoptsize - 1]
+ for {set i [expr $splitpoint + 1]} {$i <= $n} {incr i $splitpoint} {
+ $m entryconfigure $i -columnbreak 1
+ }
+ }
+}
+
+proc menutitle {text menu w} {
+ wm title $w "$text"
+}
+
+proc submenu { w mnum line text subnum } {
+ frame $w.x$line
+ button $w.x$line.l -text "" -width 9 -relief groove
+ $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
+ -activeback [cget $w.x$line.l -bg] -state disabled
+ button $w.x$line.m -text "$text" -relief raised -anchor w \
+ -command "catch {destroy .menu$subnum}; menu$subnum .menu$subnum \"$text\""
+ pack $w.x$line.l -side left -fill both
+ pack $w.x$line.m -anchor w -side right -fill both -expand on
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc comment {w mnum line text } {
+ frame $w.x$line
+ button $w.x$line.l -text "" -width 15 -relief groove
+ $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
+ -activeback [cget $w.x$line.l -bg] -state disabled
+ button $w.x$line.m -text "$text" -relief groove -anchor w
+ $w.x$line.m configure -activefore [cget $w.x$line.m -fg] \
+ -activeback [cget $w.x$line.m -bg]
+ pack $w.x$line.l -side left -fill both
+ pack $w.x$line.m -anchor w -side right -fill both -expand on
+ pack $w.x$line -anchor w -fill both -expand on
+}
+
+proc readhelp {tag fn} {
+ set message ""
+ set b 0
+ if { [file readable $fn] == 1} then {
+ set fhandle [open $fn r]
+ while {[gets $fhandle inline] >= 0} {
+ if { $b == 0 } {
+ if { [regexp $tag $inline ] } {
+ set b 1
+ set message "$inline:\n"
+ }
+ } else {
+ if { [regexp {^[^ \t]} $inline]} {
+ break
+ }
+ set message "$message\n$inline"
+ }
+ }
+ close $fhandle
+ }
+ return $message
+}
+
+proc dohelp {w var parent} {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+
+ set filefound 0
+ set found 0
+ set lineno 0
+
+ if { [file readable config.help] == 1} then {
+ set filefound 1
+ # First escape sed regexp special characters in var:
+ set var [exec echo "$var" | sed s/\[\]\[\/.^$*\]/\\\\&/g]
+ # Now pick out right help text:
+ set message [readhelp $var config.help]
+ set found [expr [string length "$message"] > 0]
+ }
+
+ frame $w.f1
+ pack $w.f1 -fill both -expand on
+
+ # Do the OK button
+ #
+ set oldFocus [focus]
+ frame $w.f2
+ button $w.f2.ok -text "OK" \
+ -width 10 -command "destroy $w; catch {focus $oldFocus}"
+ pack $w.f2.ok -side bottom -pady 6 -anchor n
+ pack $w.f2 -side bottom -padx 10 -anchor s
+
+ scrollbar $w.f1.vscroll -command "$w.f1.canvas yview"
+ pack $w.f1.vscroll -side right -fill y
+
+ canvas $w.f1.canvas -relief flat -borderwidth 0 \
+ -yscrollcommand "$w.f1.vscroll set"
+ frame $w.f1.f
+ pack $w.f1.canvas -side right -fill y -expand on
+
+ if { $found == 0 } then {
+ if { $filefound == 0 } then {
+ message $w.f1.f.m -width 750 -aspect 300 -relief flat -text \
+ "No help available - unable to open file config.help."
+ } else {
+ message $w.f1.f.m -width 400 -aspect 300 -relief flat -text \
+ "No help available for $var"
+ }
+ label $w.f1.bm -bitmap error
+ wm title $w "RTFM"
+ } else {
+ text $w.f1.f.m -width 73 -relief flat -wrap word
+ $w.f1.f.m insert 0.0 $message
+ $w.f1.f.m conf -state disabled -height [$w.f1.f.m index end]
+
+ label $w.f1.bm -bitmap info
+ wm title $w "Configuration help"
+ }
+ pack $w.f1.f.m -side left
+ pack $w.f1.bm $w.f1.f -side left -padx 10
+
+ focus $w
+ set winx [expr [winfo x $parent]+20]
+ set winy [expr [winfo y $parent]+20]
+ wm geometry $w +$winx+$winy
+ set sizok [expr [winfo reqheight $w.f2.ok] + 12]
+ set maxy [expr [winfo screenheight .] * 3 / 4]
+ set canvtotal [winfo reqheight $w.f1.f.m]
+ if [expr $sizok + $canvtotal < $maxy] {
+ set sizy $canvtotal
+ } else {
+ set sizy [expr $maxy - $sizok]
+ }
+ $w.f1.canvas configure -height $sizy -width [winfo reqwidth $w.f1.f.m] \
+ -scrollregion "0 0 [winfo reqwidth $w.f1.f.m] \
+ [winfo reqheight $w.f1.f.m]"
+ $w.f1.canvas create window 0 0 -anchor nw -window $w.f1.f
+ update idletasks
+
+ set maxy [winfo screenheight .]
+ if [expr $sizok + $canvtotal < $maxy] {
+ set sizy [expr $sizok + $canvtotal]
+ } else {
+ set sizy $maxy
+ }
+ wm maxsize $w [winfo width $w] $sizy
+}
+
+bind all <Alt-s> { catch {exec cp -f .config .config.old}; \
+ writeconfig .config config.h; wrapup .wrap }
+
+proc wrapup {w } {
+ catch {destroy $w}
+ toplevel $w -class Dialog
+
+ global CONFIG_MODVERSIONS; vfix CONFIG_MODVERSIONS
+ message $w.m -width 460 -aspect 300 -relief raised -text \
+ "End of design configuration. "
+ label $w.bm -bitmap info
+ pack $w.bm $w.m -pady 10 -side top -padx 10
+ wm title $w "LEON build instructions"
+
+ set oldFocus [focus]
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 10 -command "exit 2"
+ pack $w.f.back -side bottom -pady 10 -anchor s
+ pack $w.f -pady 10 -side top -padx 10 -anchor s
+ focus $w
+ bind $w <Return> "exit 2"
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ wm geometry $w +$winx+$winy
+
+}
+
+proc unregister_active {num} {
+ global active_menus
+ set index [lsearch -exact $active_menus $num]
+ if {$index != -1} then {set active_menus [lreplace $active_menus $index $index]}
+}
+
+proc update_active {} {
+ global active_menus total_menus
+ set max 0
+ if {[llength $active_menus] > 0} then {
+ set max [lindex $active_menus end]
+ update_define [toplevel_menu [lindex $active_menus 0]] $max 0
+ }
+ foreach i $active_menus {
+ if {[winfo exists .menu$i] == 0} then {
+ unregister_active $i
+ } else {
+ update_menu$i
+ }
+ }
+ update_define [expr $max + 1] $total_menus 1
+ update_mainmenu
+}
+
+proc configure_entry {w option items} {
+ foreach i $items {
+ $w.$i configure -state $option
+ }
+}
+
+proc validate_int {name val default} {
+ if {([exec echo $val | sed s/^-//g | tr -d \[:digit:\] ] != "")} then {
+ global $name; set $name $default
+ }
+}
+
+proc validate_hex {name val default} {
+ if {([exec echo $val | tr -d \[:xdigit:\] ] != "")} then {
+ global $name; set $name $default
+ }
+}
+
+proc update_define {first last allow_update} {
+ for {set i $first} {$i <= $last} {incr i} {
+ update_define_menu$i
+ if {$allow_update == 1} then update
+ }
+}
+
+#
+# Next set up the particulars for the top level menu, and define a few
+# buttons which we will stick down at the bottom.
+#
+
+frame .f0
+frame .f0.left
+frame .f0.middle
+frame .f0.right
+
+set active_menus [list]
+set processed_top_level 0
+set ARCH sparc
+set menus_per_column 4
+set total_menus 24
+
+proc toplevel_menu {num} {
+ if {$num == 4} then {return 3}
+ if {$num == 5} then {return 3}
+ if {$num == 6} then {return 3}
+ if {$num == 7} then {return 3}
+ if {$num == 8} then {return 3}
+ if {$num == 9} then {return 3}
+ if {$num == 10} then {return 3}
+ if {$num == 14} then {return 13}
+ if {$num == 15} then {return 14}
+ if {$num == 16} then {return 13}
+ if {$num == 17} then {return 13}
+ if {$num == 18} then {return 13}
+ if {$num == 19} then {return 13}
+ if {$num == 20} then {return 13}
+ if {$num == 21} then {return 13}
+ if {$num == 22} then {return 13}
+ if {$num == 23} then {return 13}
+ return $num
+}
+
+mainmenu_name "LEON3MP Design Configuration"
+menu_option menu1 1 "Synthesis "
+proc menu1 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 1}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 1]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Synthesis " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Synthesis "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 1; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu2 .menu2 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu0 .menu0 \"$title\""
+ $w.f.prev configure -state disabled
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ global tmpvar_0
+ minimenu $w.config.f 1 0 "Target technology " tmpvar_0 CONFIG_SYN_INFERRED
+ menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Target technology \""
+ $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_0 -value "Inferred" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-Stratix" -variable tmpvar_0 -value "Altera-Stratix" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixII" -variable tmpvar_0 -value "Altera-StratixII" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixIII" -variable tmpvar_0 -value "Altera-StratixIII" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-CycloneIII" -variable tmpvar_0 -value "Altera-CycloneIII" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-Others" -variable tmpvar_0 -value "Altera-Others" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator" -variable tmpvar_0 -value "Actel-Axcelerator" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator-DSP" -variable tmpvar_0 -value "Actel-Axcelerator-DSP" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic" -variable tmpvar_0 -value "Actel-Proasic" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-ProasicPlus" -variable tmpvar_0 -value "Actel-ProasicPlus" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic3/E/L" -variable tmpvar_0 -value "Actel-Proasic3/E/L" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-IGLOO/p/L" -variable tmpvar_0 -value "Actel-IGLOO/p/L" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT025CRH" -variable tmpvar_0 -value "Aeroflex-UT025CRH" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18" -variable tmpvar_0 -value "Atmel-ATC18" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18RHA" -variable tmpvar_0 -value "Atmel-ATC18RHA" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Custom1" -variable tmpvar_0 -value "Custom1" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "eASIC90" -variable tmpvar_0 -value "eASIC90" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "IHP25" -variable tmpvar_0 -value "IHP25" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "IHP25RH" -variable tmpvar_0 -value "IHP25RH" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Lattice-EC/ECP/XP" -variable tmpvar_0 -value "Lattice-EC/ECP/XP" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Quicklogic-Eclipse" -variable tmpvar_0 -value "Quicklogic-Eclipse" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Peregrine" -variable tmpvar_0 -value "Peregrine" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T" -variable tmpvar_0 -value "RH-LIB18T" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_0 -value "RH-UMC" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "SMIC130" -variable tmpvar_0 -value "SMIC130" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan2" -variable tmpvar_0 -value "Xilinx-Spartan2" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3" -variable tmpvar_0 -value "Xilinx-Spartan3" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3E" -variable tmpvar_0 -value "Xilinx-Spartan3E" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan6" -variable tmpvar_0 -value "Xilinx-Spartan6" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex" -variable tmpvar_0 -value "Xilinx-Virtex" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-VirtexE" -variable tmpvar_0 -value "Xilinx-VirtexE" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex2" -variable tmpvar_0 -value "Xilinx-Virtex2" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex4" -variable tmpvar_0 -value "Xilinx-Virtex4" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex5" -variable tmpvar_0 -value "Xilinx-Virtex5" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex6" -variable tmpvar_0 -value "Xilinx-Virtex6" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "UMC180" -variable tmpvar_0 -value "UMC180" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "TSMC90" -variable tmpvar_0 -value "TSMC90" -command "update_active"
+ menusplit $w $w.config.f.x0.x.menu 37
+ global tmpvar_1
+ minimenu $w.config.f 1 1 "Memory Library " tmpvar_1 CONFIG_MEM_INFERRED
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Memory Library \""
+ $w.config.f.x1.x.menu add radiobutton -label "Inferred" -variable tmpvar_1 -value "Inferred" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "UMC18" -variable tmpvar_1 -value "UMC18" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_1 -value "RH-UMC" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Artisan" -variable tmpvar_1 -value "Artisan" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Custom1" -variable tmpvar_1 -value "Custom1" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Virage" -variable tmpvar_1 -value "Virage" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Virage-TSMC90" -variable tmpvar_1 -value "Virage-TSMC90" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 7
+ bool $w.config.f 1 2 "Infer RAM" CONFIG_SYN_INFER_RAM
+ bool $w.config.f 1 3 "Infer pads" CONFIG_SYN_INFER_PADS
+ bool $w.config.f 1 4 "Disable asynchronous reset" CONFIG_SYN_NO_ASYNC
+ bool $w.config.f 1 5 "Enable scan support " CONFIG_SYN_SCAN
+ global tmpvar_2
+ minimenu $w.config.f 1 6 "FPGA type " tmpvar_2 CONFIG_FPGA_1500
+ menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"FPGA type \""
+ $w.config.f.x6.x.menu add radiobutton -label "XC3S-1500" -variable tmpvar_2 -value "XC3S-1500" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "XC3S-2000" -variable tmpvar_2 -value "XC3S-2000" -command "update_active"
+ menusplit $w $w.config.f.x6.x.menu 2
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu1 {} {
+ global CONFIG_SYN_INFERRED
+ global CONFIG_SYN_CUSTOM1
+ global CONFIG_SYN_ATC18
+ global CONFIG_SYN_TSMC90
+ global CONFIG_SYN_UMC
+ global CONFIG_SYN_RHUMC
+ global CONFIG_SYN_ARTISAN
+ if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then {configure_entry .menu1.config.f.x1 normal {x l}} else {configure_entry .menu1.config.f.x1 disabled {x l}}
+ global CONFIG_SYN_INFER_RAM
+ if {($CONFIG_SYN_INFERRED != 1)} then {
+ configure_entry .menu1.config.f.x2 normal {n l y}} else {configure_entry .menu1.config.f.x2 disabled {y n l}}
+ global CONFIG_SYN_INFER_PADS
+ if {($CONFIG_SYN_INFERRED != 1)} then {
+ configure_entry .menu1.config.f.x3 normal {n l y}} else {configure_entry .menu1.config.f.x3 disabled {y n l}}
+}
+
+
+proc update_define_menu1 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global tmpvar_0
+ global CONFIG_SYN_INFERRED
+ if {$tmpvar_0 == "Inferred"} then {set CONFIG_SYN_INFERRED 1} else {set CONFIG_SYN_INFERRED 0}
+ global CONFIG_SYN_STRATIX
+ if {$tmpvar_0 == "Altera-Stratix"} then {set CONFIG_SYN_STRATIX 1} else {set CONFIG_SYN_STRATIX 0}
+ global CONFIG_SYN_STRATIXII
+ if {$tmpvar_0 == "Altera-StratixII"} then {set CONFIG_SYN_STRATIXII 1} else {set CONFIG_SYN_STRATIXII 0}
+ global CONFIG_SYN_STRATIXIII
+ if {$tmpvar_0 == "Altera-StratixIII"} then {set CONFIG_SYN_STRATIXIII 1} else {set CONFIG_SYN_STRATIXIII 0}
+ global CONFIG_SYN_CYCLONEIII
+ if {$tmpvar_0 == "Altera-CycloneIII"} then {set CONFIG_SYN_CYCLONEIII 1} else {set CONFIG_SYN_CYCLONEIII 0}
+ global CONFIG_SYN_ALTERA
+ if {$tmpvar_0 == "Altera-Others"} then {set CONFIG_SYN_ALTERA 1} else {set CONFIG_SYN_ALTERA 0}
+ global CONFIG_SYN_AXCEL
+ if {$tmpvar_0 == "Actel-Axcelerator"} then {set CONFIG_SYN_AXCEL 1} else {set CONFIG_SYN_AXCEL 0}
+ global CONFIG_SYN_AXDSP
+ if {$tmpvar_0 == "Actel-Axcelerator-DSP"} then {set CONFIG_SYN_AXDSP 1} else {set CONFIG_SYN_AXDSP 0}
+ global CONFIG_SYN_PROASIC
+ if {$tmpvar_0 == "Actel-Proasic"} then {set CONFIG_SYN_PROASIC 1} else {set CONFIG_SYN_PROASIC 0}
+ global CONFIG_SYN_PROASICPLUS
+ if {$tmpvar_0 == "Actel-ProasicPlus"} then {set CONFIG_SYN_PROASICPLUS 1} else {set CONFIG_SYN_PROASICPLUS 0}
+ global CONFIG_SYN_PROASIC3
+ if {$tmpvar_0 == "Actel-Proasic3/E/L"} then {set CONFIG_SYN_PROASIC3 1} else {set CONFIG_SYN_PROASIC3 0}
+ global CONFIG_SYN_IGLOO
+ if {$tmpvar_0 == "Actel-IGLOO/p/L"} then {set CONFIG_SYN_IGLOO 1} else {set CONFIG_SYN_IGLOO 0}
+ global CONFIG_SYN_UT025CRH
+ if {$tmpvar_0 == "Aeroflex-UT025CRH"} then {set CONFIG_SYN_UT025CRH 1} else {set CONFIG_SYN_UT025CRH 0}
+ global CONFIG_SYN_ATC18
+ if {$tmpvar_0 == "Atmel-ATC18"} then {set CONFIG_SYN_ATC18 1} else {set CONFIG_SYN_ATC18 0}
+ global CONFIG_SYN_ATC18RHA
+ if {$tmpvar_0 == "Atmel-ATC18RHA"} then {set CONFIG_SYN_ATC18RHA 1} else {set CONFIG_SYN_ATC18RHA 0}
+ global CONFIG_SYN_CUSTOM1
+ if {$tmpvar_0 == "Custom1"} then {set CONFIG_SYN_CUSTOM1 1} else {set CONFIG_SYN_CUSTOM1 0}
+ global CONFIG_SYN_EASIC90
+ if {$tmpvar_0 == "eASIC90"} then {set CONFIG_SYN_EASIC90 1} else {set CONFIG_SYN_EASIC90 0}
+ global CONFIG_SYN_IHP25
+ if {$tmpvar_0 == "IHP25"} then {set CONFIG_SYN_IHP25 1} else {set CONFIG_SYN_IHP25 0}
+ global CONFIG_SYN_IHP25RH
+ if {$tmpvar_0 == "IHP25RH"} then {set CONFIG_SYN_IHP25RH 1} else {set CONFIG_SYN_IHP25RH 0}
+ global CONFIG_SYN_LATTICE
+ if {$tmpvar_0 == "Lattice-EC/ECP/XP"} then {set CONFIG_SYN_LATTICE 1} else {set CONFIG_SYN_LATTICE 0}
+ global CONFIG_SYN_ECLIPSE
+ if {$tmpvar_0 == "Quicklogic-Eclipse"} then {set CONFIG_SYN_ECLIPSE 1} else {set CONFIG_SYN_ECLIPSE 0}
+ global CONFIG_SYN_PEREGRINE
+ if {$tmpvar_0 == "Peregrine"} then {set CONFIG_SYN_PEREGRINE 1} else {set CONFIG_SYN_PEREGRINE 0}
+ global CONFIG_SYN_RH_LIB18T
+ if {$tmpvar_0 == "RH-LIB18T"} then {set CONFIG_SYN_RH_LIB18T 1} else {set CONFIG_SYN_RH_LIB18T 0}
+ global CONFIG_SYN_RHUMC
+ if {$tmpvar_0 == "RH-UMC"} then {set CONFIG_SYN_RHUMC 1} else {set CONFIG_SYN_RHUMC 0}
+ global CONFIG_SYN_SMIC13
+ if {$tmpvar_0 == "SMIC130"} then {set CONFIG_SYN_SMIC13 1} else {set CONFIG_SYN_SMIC13 0}
+ global CONFIG_SYN_SPARTAN2
+ if {$tmpvar_0 == "Xilinx-Spartan2"} then {set CONFIG_SYN_SPARTAN2 1} else {set CONFIG_SYN_SPARTAN2 0}
+ global CONFIG_SYN_SPARTAN3
+ if {$tmpvar_0 == "Xilinx-Spartan3"} then {set CONFIG_SYN_SPARTAN3 1} else {set CONFIG_SYN_SPARTAN3 0}
+ global CONFIG_SYN_SPARTAN3E
+ if {$tmpvar_0 == "Xilinx-Spartan3E"} then {set CONFIG_SYN_SPARTAN3E 1} else {set CONFIG_SYN_SPARTAN3E 0}
+ global CONFIG_SYN_SPARTAN6
+ if {$tmpvar_0 == "Xilinx-Spartan6"} then {set CONFIG_SYN_SPARTAN6 1} else {set CONFIG_SYN_SPARTAN6 0}
+ global CONFIG_SYN_VIRTEX
+ if {$tmpvar_0 == "Xilinx-Virtex"} then {set CONFIG_SYN_VIRTEX 1} else {set CONFIG_SYN_VIRTEX 0}
+ global CONFIG_SYN_VIRTEXE
+ if {$tmpvar_0 == "Xilinx-VirtexE"} then {set CONFIG_SYN_VIRTEXE 1} else {set CONFIG_SYN_VIRTEXE 0}
+ global CONFIG_SYN_VIRTEX2
+ if {$tmpvar_0 == "Xilinx-Virtex2"} then {set CONFIG_SYN_VIRTEX2 1} else {set CONFIG_SYN_VIRTEX2 0}
+ global CONFIG_SYN_VIRTEX4
+ if {$tmpvar_0 == "Xilinx-Virtex4"} then {set CONFIG_SYN_VIRTEX4 1} else {set CONFIG_SYN_VIRTEX4 0}
+ global CONFIG_SYN_VIRTEX5
+ if {$tmpvar_0 == "Xilinx-Virtex5"} then {set CONFIG_SYN_VIRTEX5 1} else {set CONFIG_SYN_VIRTEX5 0}
+ global CONFIG_SYN_VIRTEX6
+ if {$tmpvar_0 == "Xilinx-Virtex6"} then {set CONFIG_SYN_VIRTEX6 1} else {set CONFIG_SYN_VIRTEX6 0}
+ global CONFIG_SYN_UMC
+ if {$tmpvar_0 == "UMC180"} then {set CONFIG_SYN_UMC 1} else {set CONFIG_SYN_UMC 0}
+ global CONFIG_SYN_TSMC90
+ if {$tmpvar_0 == "TSMC90"} then {set CONFIG_SYN_TSMC90 1} else {set CONFIG_SYN_TSMC90 0}
+ global tmpvar_1
+ global CONFIG_MEM_INFERRED
+ if {$tmpvar_1 == "Inferred"} then {set CONFIG_MEM_INFERRED 1} else {set CONFIG_MEM_INFERRED 0}
+ global CONFIG_MEM_UMC
+ if {$tmpvar_1 == "UMC18"} then {set CONFIG_MEM_UMC 1} else {set CONFIG_MEM_UMC 0}
+ global CONFIG_MEM_RHUMC
+ if {$tmpvar_1 == "RH-UMC"} then {set CONFIG_MEM_RHUMC 1} else {set CONFIG_MEM_RHUMC 0}
+ global CONFIG_MEM_ARTISAN
+ if {$tmpvar_1 == "Artisan"} then {set CONFIG_MEM_ARTISAN 1} else {set CONFIG_MEM_ARTISAN 0}
+ global CONFIG_MEM_CUSTOM1
+ if {$tmpvar_1 == "Custom1"} then {set CONFIG_MEM_CUSTOM1 1} else {set CONFIG_MEM_CUSTOM1 0}
+ global CONFIG_MEM_VIRAGE
+ if {$tmpvar_1 == "Virage"} then {set CONFIG_MEM_VIRAGE 1} else {set CONFIG_MEM_VIRAGE 0}
+ global CONFIG_MEM_VIRAGE90
+ if {$tmpvar_1 == "Virage-TSMC90"} then {set CONFIG_MEM_VIRAGE90 1} else {set CONFIG_MEM_VIRAGE90 0}
+ global CONFIG_SYN_INFER_RAM
+ if {($CONFIG_SYN_INFERRED != 1)} then {
+ set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM&15]} else {set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM|16]}
+ global CONFIG_SYN_INFER_PADS
+ if {($CONFIG_SYN_INFERRED != 1)} then {
+ set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS&15]} else {set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS|16]}
+ global tmpvar_2
+ global CONFIG_FPGA_1500
+ if {$tmpvar_2 == "XC3S-1500"} then {set CONFIG_FPGA_1500 1} else {set CONFIG_FPGA_1500 0}
+ global CONFIG_FPGA_2000
+ if {$tmpvar_2 == "XC3S-2000"} then {set CONFIG_FPGA_2000 1} else {set CONFIG_FPGA_2000 0}
+}
+
+
+menu_option menu2 2 "Clock generation"
+proc menu2 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 2}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 2]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Clock generation" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Clock generation"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 2; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu3 .menu3 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ global tmpvar_3
+ minimenu $w.config.f 2 0 "Clock generator " tmpvar_3 CONFIG_CLK_INFERRED
+ menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Clock generator \""
+ $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_3 -value "Inferred" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Actel-HCLKBUF" -variable tmpvar_3 -value "Actel-HCLKBUF" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Altera-ALTPLL" -variable tmpvar_3 -value "Altera-ALTPLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Lattice-EXPLL" -variable tmpvar_3 -value "Lattice-EXPLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Proasic3-PLLL" -variable tmpvar_3 -value "Proasic3-PLLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T-PLL" -variable tmpvar_3 -value "RH-LIB18T-PLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "DARE-PLL" -variable tmpvar_3 -value "DARE-PLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-CLKDLL" -variable tmpvar_3 -value "Xilinx-CLKDLL" -command "update_active"
+ $w.config.f.x0.x.menu add radiobutton -label "Xilinx-DCM" -variable tmpvar_3 -value "Xilinx-DCM" -command "update_active"
+ menusplit $w $w.config.f.x0.x.menu 9
+ int $w.config.f 2 1 "Clock multiplication factor (2 - 32)" CONFIG_CLK_MUL
+ int $w.config.f 2 2 "Clock division factor (2 - 32)" CONFIG_CLK_DIV
+ int $w.config.f 2 3 "Outout division factor (2 - 32)" CONFIG_OCLK_DIV
+ bool $w.config.f 2 4 "Enable Xilinx CLKDLL for PCI clock" CONFIG_PCI_CLKDLL
+ bool $w.config.f 2 5 "Disable external feedback for SDRAM clock" CONFIG_CLK_NOFB
+ bool $w.config.f 2 6 "Use PCI clock as system clock" CONFIG_PCI_SYSCLK
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu2 {} {
+ global CONFIG_CLK_DCM
+ global CONFIG_CLK_ALTDLL
+ global CONFIG_CLK_LATDLL
+ global CONFIG_CLK_PRO3PLL
+ global CONFIG_CLK_CLKDLL
+ global CONFIG_CLK_LIB18T
+ global CONFIG_CLK_MUL
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x1.l configure -state normal; } else {.menu2.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x1.l configure -state disabled}
+ global CONFIG_CLK_DIV
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x2.l configure -state normal; } else {.menu2.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x2.l configure -state disabled}
+ global CONFIG_OCLK_DIV
+ if {($CONFIG_CLK_PRO3PLL == 1)} then {.menu2.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x3.l configure -state normal; } else {.menu2.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x3.l configure -state disabled}
+ global CONFIG_PCI_CLKDLL
+ if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {
+ configure_entry .menu2.config.f.x4 normal {n l y}} else {configure_entry .menu2.config.f.x4 disabled {y n l}}
+ global CONFIG_CLK_NOFB
+ if {($CONFIG_CLK_DCM == 1)} then {
+ configure_entry .menu2.config.f.x5 normal {n l y}} else {configure_entry .menu2.config.f.x5 disabled {y n l}}
+ global CONFIG_PCI_ENABLE
+ global CONFIG_PCI_SYSCLK
+ if {($CONFIG_PCI_ENABLE != 1)} then {
+ configure_entry .menu2.config.f.x6 normal {n l y}} else {configure_entry .menu2.config.f.x6 disabled {y n l}}
+}
+
+
+proc update_define_menu2 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global tmpvar_3
+ global CONFIG_CLK_INFERRED
+ if {$tmpvar_3 == "Inferred"} then {set CONFIG_CLK_INFERRED 1} else {set CONFIG_CLK_INFERRED 0}
+ global CONFIG_CLK_HCLKBUF
+ if {$tmpvar_3 == "Actel-HCLKBUF"} then {set CONFIG_CLK_HCLKBUF 1} else {set CONFIG_CLK_HCLKBUF 0}
+ global CONFIG_CLK_ALTDLL
+ if {$tmpvar_3 == "Altera-ALTPLL"} then {set CONFIG_CLK_ALTDLL 1} else {set CONFIG_CLK_ALTDLL 0}
+ global CONFIG_CLK_LATDLL
+ if {$tmpvar_3 == "Lattice-EXPLL"} then {set CONFIG_CLK_LATDLL 1} else {set CONFIG_CLK_LATDLL 0}
+ global CONFIG_CLK_PRO3PLL
+ if {$tmpvar_3 == "Proasic3-PLLL"} then {set CONFIG_CLK_PRO3PLL 1} else {set CONFIG_CLK_PRO3PLL 0}
+ global CONFIG_CLK_LIB18T
+ if {$tmpvar_3 == "RH-LIB18T-PLL"} then {set CONFIG_CLK_LIB18T 1} else {set CONFIG_CLK_LIB18T 0}
+ global CONFIG_CLK_RHUMC
+ if {$tmpvar_3 == "DARE-PLL"} then {set CONFIG_CLK_RHUMC 1} else {set CONFIG_CLK_RHUMC 0}
+ global CONFIG_CLK_CLKDLL
+ if {$tmpvar_3 == "Xilinx-CLKDLL"} then {set CONFIG_CLK_CLKDLL 1} else {set CONFIG_CLK_CLKDLL 0}
+ global CONFIG_CLK_DCM
+ if {$tmpvar_3 == "Xilinx-DCM"} then {set CONFIG_CLK_DCM 1} else {set CONFIG_CLK_DCM 0}
+ global CONFIG_CLK_MUL
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_MUL "$CONFIG_CLK_MUL" 2}
+ global CONFIG_CLK_DIV
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_DIV "$CONFIG_CLK_DIV" 2}
+ global CONFIG_OCLK_DIV
+ if {($CONFIG_CLK_PRO3PLL == 1)} then {validate_int CONFIG_OCLK_DIV "$CONFIG_OCLK_DIV" 2}
+ global CONFIG_PCI_CLKDLL
+ if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {
+ set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL&15]} else {set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL|16]}
+ global CONFIG_CLK_NOFB
+ if {($CONFIG_CLK_DCM == 1)} then {
+ set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB&15]} else {set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB|16]}
+ global CONFIG_PCI_ENABLE
+ global CONFIG_PCI_SYSCLK
+ if {($CONFIG_PCI_ENABLE != 1)} then {
+ set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK&15]} else {set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK|16]}
+}
+
+
+menu_option menu3 3 "Processor "
+proc menu3 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 3}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 3]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Processor " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Processor "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 3; break"
+ set nextscript "catch {focus $oldFocus}; menu4 .menu4 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 3 0 "Enable LEON3 SPARC V8 Processor" CONFIG_LEON3
+ int $w.config.f 3 1 "Number of processors" CONFIG_PROC_NUM
+ submenu $w.config.f 3 2 "Integer unit " 4
+ submenu $w.config.f 3 3 "Floating-point unit" 5
+ submenu $w.config.f 3 4 "Cache system" 6
+ submenu $w.config.f 3 5 "MMU" 7
+ submenu $w.config.f 3 6 "Debug Support Unit " 8
+ submenu $w.config.f 3 7 "Fault-tolerance " 9
+ submenu $w.config.f 3 8 "VHDL debug settings " 10
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu3 {} {
+ global CONFIG_LEON3
+ global CONFIG_PROC_NUM
+ if {($CONFIG_LEON3 == 1)} then {.menu3.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu3.config.f.x1.l configure -state normal; } else {.menu3.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu3.config.f.x1.l configure -state disabled}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x2 normal {m}} else {configure_entry .menu3.config.f.x2 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x3 normal {m}} else {configure_entry .menu3.config.f.x3 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x4 normal {m}} else {configure_entry .menu3.config.f.x4 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x5 normal {m}} else {configure_entry .menu3.config.f.x5 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x6 normal {m}} else {configure_entry .menu3.config.f.x6 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x7 normal {m}} else {configure_entry .menu3.config.f.x7 disabled {m}}
+ if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x8 normal {m}} else {configure_entry .menu3.config.f.x8 disabled {m}}
+}
+
+
+proc update_define_menu3 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_PROC_NUM
+ if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_PROC_NUM "$CONFIG_PROC_NUM" 1}
+}
+
+
+proc menu4 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 4}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 4]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Integer unit " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Integer unit "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 4; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu5 .menu5 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ int $w.config.f 4 0 "SPARC register windows" CONFIG_IU_NWINDOWS
+ bool $w.config.f 4 1 "SPARC V8 MUL/DIV instructions" CONFIG_IU_V8MULDIV
+ global tmpvar_4
+ minimenu $w.config.f 4 2 "Hardware multiplier latency" tmpvar_4 CONFIG_IU_MUL_LATENCY_2
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Hardware multiplier latency\""
+ $w.config.f.x2.x.menu add radiobutton -label "2-cycles" -variable tmpvar_4 -value "2-cycles" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "4-cycles" -variable tmpvar_4 -value "4-cycles" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "5-cycles" -variable tmpvar_4 -value "5-cycles" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 3
+ bool $w.config.f 4 3 "SPARC V8e SMAC/UMAC instructions " CONFIG_IU_MUL_MAC
+ bool $w.config.f 4 4 "Branch prediction " CONFIG_IU_BP
+ bool $w.config.f 4 5 "Single-vector trapping" CONFIG_IU_SVT
+ int $w.config.f 4 6 "Load delay" CONFIG_IU_LDELAY
+ int $w.config.f 4 7 "Hardware watchpoints" CONFIG_IU_WATCHPOINTS
+ bool $w.config.f 4 8 "Enable power-down mode " CONFIG_PWD
+ hex $w.config.f 4 9 " Reset start address (addr\[31:12\]) " CONFIG_IU_RSTADDR
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu4 {} {
+ global CONFIG_LEON3
+ global CONFIG_IU_NWINDOWS
+ if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x0.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x0.l configure -state normal; } else {.menu4.config.f.x0.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x0.l configure -state disabled}
+ global CONFIG_IU_V8MULDIV
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu4.config.f.x1 normal {n l y}} else {configure_entry .menu4.config.f.x1 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {configure_entry .menu4.config.f.x2 normal {x l}} else {configure_entry .menu4.config.f.x2 disabled {x l}}
+ global CONFIG_IU_MUL_LATENCY_4
+ global CONFIG_IU_MUL_LATENCY_5
+ global CONFIG_IU_MUL_MAC
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {
+ configure_entry .menu4.config.f.x3 normal {n l y}} else {configure_entry .menu4.config.f.x3 disabled {y n l}}
+ global CONFIG_IU_BP
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu4.config.f.x4 normal {n l y}} else {configure_entry .menu4.config.f.x4 disabled {y n l}}
+ global CONFIG_IU_SVT
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu4.config.f.x5 normal {n l y}} else {configure_entry .menu4.config.f.x5 disabled {y n l}}
+ global CONFIG_IU_LDELAY
+ if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x6.l configure -state normal; } else {.menu4.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x6.l configure -state disabled}
+ global CONFIG_IU_WATCHPOINTS
+ if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x7.l configure -state normal; } else {.menu4.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x7.l configure -state disabled}
+ global CONFIG_PWD
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu4.config.f.x8 normal {n l y}} else {configure_entry .menu4.config.f.x8 disabled {y n l}}
+ global CONFIG_IU_RSTADDR
+ if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x9.l configure -state normal; } else {.menu4.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x9.l configure -state disabled}
+}
+
+
+proc update_define_menu4 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_IU_NWINDOWS
+ if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_NWINDOWS "$CONFIG_IU_NWINDOWS" 8}
+ global CONFIG_IU_V8MULDIV
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV&15]} else {set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV|16]}
+ global tmpvar_4
+ global CONFIG_IU_MUL_LATENCY_2
+ if {$tmpvar_4 == "2-cycles"} then {set CONFIG_IU_MUL_LATENCY_2 1} else {set CONFIG_IU_MUL_LATENCY_2 0}
+ global CONFIG_IU_MUL_LATENCY_4
+ if {$tmpvar_4 == "4-cycles"} then {set CONFIG_IU_MUL_LATENCY_4 1} else {set CONFIG_IU_MUL_LATENCY_4 0}
+ global CONFIG_IU_MUL_LATENCY_5
+ if {$tmpvar_4 == "5-cycles"} then {set CONFIG_IU_MUL_LATENCY_5 1} else {set CONFIG_IU_MUL_LATENCY_5 0}
+ global CONFIG_IU_MUL_MAC
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {
+ set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC&15]} else {set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC|16]}
+ global CONFIG_IU_BP
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_IU_BP [expr $CONFIG_IU_BP&15]} else {set CONFIG_IU_BP [expr $CONFIG_IU_BP|16]}
+ global CONFIG_IU_SVT
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_IU_SVT [expr $CONFIG_IU_SVT&15]} else {set CONFIG_IU_SVT [expr $CONFIG_IU_SVT|16]}
+ global CONFIG_IU_LDELAY
+ if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_LDELAY "$CONFIG_IU_LDELAY" 1}
+ global CONFIG_IU_WATCHPOINTS
+ if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_WATCHPOINTS "$CONFIG_IU_WATCHPOINTS" 0}
+ global CONFIG_PWD
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_PWD [expr $CONFIG_PWD&15]} else {set CONFIG_PWD [expr $CONFIG_PWD|16]}
+ global CONFIG_IU_RSTADDR
+ if {($CONFIG_LEON3 == 1)} then {validate_hex CONFIG_IU_RSTADDR "$CONFIG_IU_RSTADDR" 00000}
+}
+
+
+proc menu5 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 5}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 5]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Floating-point unit" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Floating-point unit"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 5; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu6 .menu6 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 5 0 "Enable FPU " CONFIG_FPU_ENABLE
+ global tmpvar_5
+ minimenu $w.config.f 5 1 "FPU core" tmpvar_5 CONFIG_FPU_GRFPU
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"FPU core\""
+ $w.config.f.x1.x.menu add radiobutton -label "GRFPU" -variable tmpvar_5 -value "GRFPU" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "GRFPU-LITE" -variable tmpvar_5 -value "GRFPU-LITE" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "Meiko" -variable tmpvar_5 -value "Meiko" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 3
+ global tmpvar_6
+ minimenu $w.config.f 5 2 "GRFPU multiplier" tmpvar_6 CONFIG_FPU_GRFPU_INFMUL
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"GRFPU multiplier\""
+ $w.config.f.x2.x.menu add radiobutton -label "Inferred" -variable tmpvar_6 -value "Inferred" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "DW" -variable tmpvar_6 -value "DW" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "ModGen" -variable tmpvar_6 -value "ModGen" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "TechSpec" -variable tmpvar_6 -value "TechSpec" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 4
+ global tmpvar_7
+ minimenu $w.config.f 5 3 "GRFPU-LITE controller" tmpvar_7 CONFIG_FPU_GRFPC0
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"GRFPU-LITE controller\""
+ $w.config.f.x3.x.menu add radiobutton -label "Simple" -variable tmpvar_7 -value "Simple" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "Data-forwarding" -variable tmpvar_7 -value "Data-forwarding" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "Non-blocking" -variable tmpvar_7 -value "Non-blocking" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 3
+ bool $w.config.f 5 4 "Use VHDL netlist " CONFIG_FPU_NETLIST
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu5 {} {
+ global CONFIG_LEON3
+ global CONFIG_FPU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu5.config.f.x0 normal {n l y}} else {configure_entry .menu5.config.f.x0 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {configure_entry .menu5.config.f.x1 normal {x l}} else {configure_entry .menu5.config.f.x1 disabled {x l}}
+ global CONFIG_FPU_GRFPU
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then {configure_entry .menu5.config.f.x2 normal {x l}} else {configure_entry .menu5.config.f.x2 disabled {x l}}
+ global CONFIG_FPU_GRFPULITE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then {configure_entry .menu5.config.f.x3 normal {x l}} else {configure_entry .menu5.config.f.x3 disabled {x l}}
+ global CONFIG_FPU_NETLIST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {
+ configure_entry .menu5.config.f.x4 normal {n l y}} else {configure_entry .menu5.config.f.x4 disabled {y n l}}
+}
+
+
+proc update_define_menu5 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_FPU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE&15]} else {set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE|16]}
+ global tmpvar_5
+ global CONFIG_FPU_GRFPU
+ if {$tmpvar_5 == "GRFPU"} then {set CONFIG_FPU_GRFPU 1} else {set CONFIG_FPU_GRFPU 0}
+ global CONFIG_FPU_GRFPULITE
+ if {$tmpvar_5 == "GRFPU-LITE"} then {set CONFIG_FPU_GRFPULITE 1} else {set CONFIG_FPU_GRFPULITE 0}
+ global CONFIG_FPU_MEIKO
+ if {$tmpvar_5 == "Meiko"} then {set CONFIG_FPU_MEIKO 1} else {set CONFIG_FPU_MEIKO 0}
+ global tmpvar_6
+ global CONFIG_FPU_GRFPU_INFMUL
+ if {$tmpvar_6 == "Inferred"} then {set CONFIG_FPU_GRFPU_INFMUL 1} else {set CONFIG_FPU_GRFPU_INFMUL 0}
+ global CONFIG_FPU_GRFPU_DWMUL
+ if {$tmpvar_6 == "DW"} then {set CONFIG_FPU_GRFPU_DWMUL 1} else {set CONFIG_FPU_GRFPU_DWMUL 0}
+ global CONFIG_FPU_GRFPU_MODGEN
+ if {$tmpvar_6 == "ModGen"} then {set CONFIG_FPU_GRFPU_MODGEN 1} else {set CONFIG_FPU_GRFPU_MODGEN 0}
+ global CONFIG_FPU_GRFPU_TECHSPEC
+ if {$tmpvar_6 == "TechSpec"} then {set CONFIG_FPU_GRFPU_TECHSPEC 1} else {set CONFIG_FPU_GRFPU_TECHSPEC 0}
+ global tmpvar_7
+ global CONFIG_FPU_GRFPC0
+ if {$tmpvar_7 == "Simple"} then {set CONFIG_FPU_GRFPC0 1} else {set CONFIG_FPU_GRFPC0 0}
+ global CONFIG_FPU_GRFPC1
+ if {$tmpvar_7 == "Data-forwarding"} then {set CONFIG_FPU_GRFPC1 1} else {set CONFIG_FPU_GRFPC1 0}
+ global CONFIG_FPU_GRFPC2
+ if {$tmpvar_7 == "Non-blocking"} then {set CONFIG_FPU_GRFPC2 1} else {set CONFIG_FPU_GRFPC2 0}
+ global CONFIG_FPU_NETLIST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {
+ set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST&15]} else {set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST|16]}
+}
+
+
+proc menu6 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 6}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 6]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Cache system" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Cache system"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 6; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu7 .menu7 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 6 0 "Enable instruction cache " CONFIG_ICACHE_ENABLE
+ global tmpvar_8
+ minimenu $w.config.f 6 1 "Associativity (sets) " tmpvar_8 CONFIG_ICACHE_ASSO1
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Associativity (sets) \""
+ $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_8 -value "1" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_8 -value "2" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "3" -variable tmpvar_8 -value "3" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_8 -value "4" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 4
+ global tmpvar_9
+ minimenu $w.config.f 6 2 "Set size (kbytes/set)" tmpvar_9 CONFIG_ICACHE_SZ1
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\""
+ $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_9 -value "1" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_9 -value "2" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_9 -value "4" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_9 -value "8" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_9 -value "16" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_9 -value "32" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_9 -value "64" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "128" -variable tmpvar_9 -value "128" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "256" -variable tmpvar_9 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 9
+ global tmpvar_10
+ minimenu $w.config.f 6 3 "Line size (bytes/line)" tmpvar_10 CONFIG_ICACHE_LZ16
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\""
+ $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_10 -value "16" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_10 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 2
+ global tmpvar_11
+ minimenu $w.config.f 6 4 "Replacement alorithm" tmpvar_11 CONFIG_ICACHE_ALGORND
+ menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Replacement alorithm\""
+ $w.config.f.x4.x.menu add radiobutton -label "Random" -variable tmpvar_11 -value "Random" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "LRR" -variable tmpvar_11 -value "LRR" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "LRU" -variable tmpvar_11 -value "LRU" -command "update_active"
+ menusplit $w $w.config.f.x4.x.menu 3
+ bool $w.config.f 6 5 "Cache locking " CONFIG_ICACHE_LOCK
+ bool $w.config.f 6 6 "Enable local instruction RAM " CONFIG_ICACHE_LRAM
+ global tmpvar_12
+ minimenu $w.config.f 6 7 "Local data RAM size (kbytes)" tmpvar_12 CONFIG_ICACHE_LRAM_SZ1
+ menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\""
+ $w.config.f.x7.x.menu add radiobutton -label "1" -variable tmpvar_12 -value "1" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "2" -variable tmpvar_12 -value "2" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "4" -variable tmpvar_12 -value "4" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_12 -value "8" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_12 -value "16" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_12 -value "32" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_12 -value "64" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_12 -value "128" -command "update_active"
+ $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_12 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x7.x.menu 9
+ hex $w.config.f 6 8 " Local instruction RAM start address (8 MSB) " CONFIG_ICACHE_LRSTART
+ bool $w.config.f 6 9 "Enable data cache " CONFIG_DCACHE_ENABLE
+ global tmpvar_13
+ minimenu $w.config.f 6 10 "Associativity (sets)" tmpvar_13 CONFIG_DCACHE_ASSO1
+ menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Associativity (sets)\""
+ $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_13 -value "1" -command "update_active"
+ $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_13 -value "2" -command "update_active"
+ $w.config.f.x10.x.menu add radiobutton -label "3" -variable tmpvar_13 -value "3" -command "update_active"
+ $w.config.f.x10.x.menu add radiobutton -label "4" -variable tmpvar_13 -value "4" -command "update_active"
+ menusplit $w $w.config.f.x10.x.menu 4
+ global tmpvar_14
+ minimenu $w.config.f 6 11 "Set size (kbytes/set)" tmpvar_14 CONFIG_DCACHE_SZ1
+ menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\""
+ $w.config.f.x11.x.menu add radiobutton -label "1" -variable tmpvar_14 -value "1" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "2" -variable tmpvar_14 -value "2" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "4" -variable tmpvar_14 -value "4" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "8" -variable tmpvar_14 -value "8" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "16" -variable tmpvar_14 -value "16" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "32" -variable tmpvar_14 -value "32" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "64" -variable tmpvar_14 -value "64" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "128" -variable tmpvar_14 -value "128" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_14 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x11.x.menu 9
+ global tmpvar_15
+ minimenu $w.config.f 6 12 "Line size (bytes/line)" tmpvar_15 CONFIG_DCACHE_LZ16
+ menu $w.config.f.x12.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\""
+ $w.config.f.x12.x.menu add radiobutton -label "16" -variable tmpvar_15 -value "16" -command "update_active"
+ $w.config.f.x12.x.menu add radiobutton -label "32" -variable tmpvar_15 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x12.x.menu 2
+ global tmpvar_16
+ minimenu $w.config.f 6 13 "Replacement alorithm" tmpvar_16 CONFIG_DCACHE_ALGORND
+ menu $w.config.f.x13.x.menu -tearoffcommand "menutitle \"Replacement alorithm\""
+ $w.config.f.x13.x.menu add radiobutton -label "Random" -variable tmpvar_16 -value "Random" -command "update_active"
+ $w.config.f.x13.x.menu add radiobutton -label "LRR" -variable tmpvar_16 -value "LRR" -command "update_active"
+ $w.config.f.x13.x.menu add radiobutton -label "LRU" -variable tmpvar_16 -value "LRU" -command "update_active"
+ menusplit $w $w.config.f.x13.x.menu 3
+ bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK
+ bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP
+ bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST
+ bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG
+ hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED
+ bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM
+ global tmpvar_17
+ minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_17 CONFIG_DCACHE_LRAM_SZ1
+ menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\""
+ $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_17 -value "1" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_17 -value "2" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_17 -value "4" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_17 -value "8" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_17 -value "16" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_17 -value "32" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_17 -value "64" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_17 -value "128" -command "update_active"
+ $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_17 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x20.x.menu 9
+ hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu6 {} {
+ global CONFIG_LEON3
+ global CONFIG_ICACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu6.config.f.x0 normal {n l y}} else {configure_entry .menu6.config.f.x0 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x1 normal {x l}} else {configure_entry .menu6.config.f.x1 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x2 normal {x l}} else {configure_entry .menu6.config.f.x2 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x3 normal {x l}} else {configure_entry .menu6.config.f.x3 disabled {x l}}
+ global CONFIG_ICACHE_ASSO1
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x4 normal {x l}} else {configure_entry .menu6.config.f.x4 disabled {x l}}
+ global CONFIG_ICACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {
+ configure_entry .menu6.config.f.x5 normal {n l y}} else {configure_entry .menu6.config.f.x5 disabled {y n l}}
+ global CONFIG_MMU_ENABLE
+ global CONFIG_ICACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {
+ configure_entry .menu6.config.f.x6 normal {n l y}} else {configure_entry .menu6.config.f.x6 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x7 normal {x l}} else {configure_entry .menu6.config.f.x7 disabled {x l}}
+ global CONFIG_ICACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {.menu6.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x8.l configure -state normal; } else {.menu6.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x8.l configure -state disabled}
+ global CONFIG_DCACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu6.config.f.x9 normal {n l y}} else {configure_entry .menu6.config.f.x9 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x10 normal {x l}} else {configure_entry .menu6.config.f.x10 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x11 normal {x l}} else {configure_entry .menu6.config.f.x11 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x12 normal {x l}} else {configure_entry .menu6.config.f.x12 disabled {x l}}
+ global CONFIG_DCACHE_ASSO1
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x13 normal {x l}} else {configure_entry .menu6.config.f.x13 disabled {x l}}
+ global CONFIG_DCACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {
+ configure_entry .menu6.config.f.x14 normal {n l y}} else {configure_entry .menu6.config.f.x14 disabled {y n l}}
+ global CONFIG_DCACHE_SNOOP
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}}
+ global CONFIG_DCACHE_SNOOP_FAST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {
+ configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}}
+ global CONFIG_DCACHE_SNOOP_SEPTAG
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {
+ configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}}
+ global CONFIG_CACHE_FIXED
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled}
+ global CONFIG_DCACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {
+ configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}}
+ global CONFIG_DCACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled}
+}
+
+
+proc update_define_menu6 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_ICACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE&15]} else {set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE|16]}
+ global tmpvar_8
+ global CONFIG_ICACHE_ASSO1
+ if {$tmpvar_8 == "1"} then {set CONFIG_ICACHE_ASSO1 1} else {set CONFIG_ICACHE_ASSO1 0}
+ global CONFIG_ICACHE_ASSO2
+ if {$tmpvar_8 == "2"} then {set CONFIG_ICACHE_ASSO2 1} else {set CONFIG_ICACHE_ASSO2 0}
+ global CONFIG_ICACHE_ASSO3
+ if {$tmpvar_8 == "3"} then {set CONFIG_ICACHE_ASSO3 1} else {set CONFIG_ICACHE_ASSO3 0}
+ global CONFIG_ICACHE_ASSO4
+ if {$tmpvar_8 == "4"} then {set CONFIG_ICACHE_ASSO4 1} else {set CONFIG_ICACHE_ASSO4 0}
+ global tmpvar_9
+ global CONFIG_ICACHE_SZ1
+ if {$tmpvar_9 == "1"} then {set CONFIG_ICACHE_SZ1 1} else {set CONFIG_ICACHE_SZ1 0}
+ global CONFIG_ICACHE_SZ2
+ if {$tmpvar_9 == "2"} then {set CONFIG_ICACHE_SZ2 1} else {set CONFIG_ICACHE_SZ2 0}
+ global CONFIG_ICACHE_SZ4
+ if {$tmpvar_9 == "4"} then {set CONFIG_ICACHE_SZ4 1} else {set CONFIG_ICACHE_SZ4 0}
+ global CONFIG_ICACHE_SZ8
+ if {$tmpvar_9 == "8"} then {set CONFIG_ICACHE_SZ8 1} else {set CONFIG_ICACHE_SZ8 0}
+ global CONFIG_ICACHE_SZ16
+ if {$tmpvar_9 == "16"} then {set CONFIG_ICACHE_SZ16 1} else {set CONFIG_ICACHE_SZ16 0}
+ global CONFIG_ICACHE_SZ32
+ if {$tmpvar_9 == "32"} then {set CONFIG_ICACHE_SZ32 1} else {set CONFIG_ICACHE_SZ32 0}
+ global CONFIG_ICACHE_SZ64
+ if {$tmpvar_9 == "64"} then {set CONFIG_ICACHE_SZ64 1} else {set CONFIG_ICACHE_SZ64 0}
+ global CONFIG_ICACHE_SZ128
+ if {$tmpvar_9 == "128"} then {set CONFIG_ICACHE_SZ128 1} else {set CONFIG_ICACHE_SZ128 0}
+ global CONFIG_ICACHE_SZ256
+ if {$tmpvar_9 == "256"} then {set CONFIG_ICACHE_SZ256 1} else {set CONFIG_ICACHE_SZ256 0}
+ global tmpvar_10
+ global CONFIG_ICACHE_LZ16
+ if {$tmpvar_10 == "16"} then {set CONFIG_ICACHE_LZ16 1} else {set CONFIG_ICACHE_LZ16 0}
+ global CONFIG_ICACHE_LZ32
+ if {$tmpvar_10 == "32"} then {set CONFIG_ICACHE_LZ32 1} else {set CONFIG_ICACHE_LZ32 0}
+ global tmpvar_11
+ global CONFIG_ICACHE_ALGORND
+ if {$tmpvar_11 == "Random"} then {set CONFIG_ICACHE_ALGORND 1} else {set CONFIG_ICACHE_ALGORND 0}
+ global CONFIG_ICACHE_ALGOLRR
+ if {$tmpvar_11 == "LRR"} then {set CONFIG_ICACHE_ALGOLRR 1} else {set CONFIG_ICACHE_ALGOLRR 0}
+ global CONFIG_ICACHE_ALGOLRU
+ if {$tmpvar_11 == "LRU"} then {set CONFIG_ICACHE_ALGOLRU 1} else {set CONFIG_ICACHE_ALGOLRU 0}
+ global CONFIG_ICACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {
+ set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK&15]} else {set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK|16]}
+ global CONFIG_MMU_ENABLE
+ global CONFIG_ICACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {
+ set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM&15]} else {set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM|16]}
+ global tmpvar_12
+ global CONFIG_ICACHE_LRAM_SZ1
+ if {$tmpvar_12 == "1"} then {set CONFIG_ICACHE_LRAM_SZ1 1} else {set CONFIG_ICACHE_LRAM_SZ1 0}
+ global CONFIG_ICACHE_LRAM_SZ2
+ if {$tmpvar_12 == "2"} then {set CONFIG_ICACHE_LRAM_SZ2 1} else {set CONFIG_ICACHE_LRAM_SZ2 0}
+ global CONFIG_ICACHE_LRAM_SZ4
+ if {$tmpvar_12 == "4"} then {set CONFIG_ICACHE_LRAM_SZ4 1} else {set CONFIG_ICACHE_LRAM_SZ4 0}
+ global CONFIG_ICACHE_LRAM_SZ8
+ if {$tmpvar_12 == "8"} then {set CONFIG_ICACHE_LRAM_SZ8 1} else {set CONFIG_ICACHE_LRAM_SZ8 0}
+ global CONFIG_ICACHE_LRAM_SZ16
+ if {$tmpvar_12 == "16"} then {set CONFIG_ICACHE_LRAM_SZ16 1} else {set CONFIG_ICACHE_LRAM_SZ16 0}
+ global CONFIG_ICACHE_LRAM_SZ32
+ if {$tmpvar_12 == "32"} then {set CONFIG_ICACHE_LRAM_SZ32 1} else {set CONFIG_ICACHE_LRAM_SZ32 0}
+ global CONFIG_ICACHE_LRAM_SZ64
+ if {$tmpvar_12 == "64"} then {set CONFIG_ICACHE_LRAM_SZ64 1} else {set CONFIG_ICACHE_LRAM_SZ64 0}
+ global CONFIG_ICACHE_LRAM_SZ128
+ if {$tmpvar_12 == "128"} then {set CONFIG_ICACHE_LRAM_SZ128 1} else {set CONFIG_ICACHE_LRAM_SZ128 0}
+ global CONFIG_ICACHE_LRAM_SZ256
+ if {$tmpvar_12 == "256"} then {set CONFIG_ICACHE_LRAM_SZ256 1} else {set CONFIG_ICACHE_LRAM_SZ256 0}
+ global CONFIG_ICACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {validate_hex CONFIG_ICACHE_LRSTART "$CONFIG_ICACHE_LRSTART" 8e}
+ global CONFIG_DCACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE&15]} else {set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE|16]}
+ global tmpvar_13
+ global CONFIG_DCACHE_ASSO1
+ if {$tmpvar_13 == "1"} then {set CONFIG_DCACHE_ASSO1 1} else {set CONFIG_DCACHE_ASSO1 0}
+ global CONFIG_DCACHE_ASSO2
+ if {$tmpvar_13 == "2"} then {set CONFIG_DCACHE_ASSO2 1} else {set CONFIG_DCACHE_ASSO2 0}
+ global CONFIG_DCACHE_ASSO3
+ if {$tmpvar_13 == "3"} then {set CONFIG_DCACHE_ASSO3 1} else {set CONFIG_DCACHE_ASSO3 0}
+ global CONFIG_DCACHE_ASSO4
+ if {$tmpvar_13 == "4"} then {set CONFIG_DCACHE_ASSO4 1} else {set CONFIG_DCACHE_ASSO4 0}
+ global tmpvar_14
+ global CONFIG_DCACHE_SZ1
+ if {$tmpvar_14 == "1"} then {set CONFIG_DCACHE_SZ1 1} else {set CONFIG_DCACHE_SZ1 0}
+ global CONFIG_DCACHE_SZ2
+ if {$tmpvar_14 == "2"} then {set CONFIG_DCACHE_SZ2 1} else {set CONFIG_DCACHE_SZ2 0}
+ global CONFIG_DCACHE_SZ4
+ if {$tmpvar_14 == "4"} then {set CONFIG_DCACHE_SZ4 1} else {set CONFIG_DCACHE_SZ4 0}
+ global CONFIG_DCACHE_SZ8
+ if {$tmpvar_14 == "8"} then {set CONFIG_DCACHE_SZ8 1} else {set CONFIG_DCACHE_SZ8 0}
+ global CONFIG_DCACHE_SZ16
+ if {$tmpvar_14 == "16"} then {set CONFIG_DCACHE_SZ16 1} else {set CONFIG_DCACHE_SZ16 0}
+ global CONFIG_DCACHE_SZ32
+ if {$tmpvar_14 == "32"} then {set CONFIG_DCACHE_SZ32 1} else {set CONFIG_DCACHE_SZ32 0}
+ global CONFIG_DCACHE_SZ64
+ if {$tmpvar_14 == "64"} then {set CONFIG_DCACHE_SZ64 1} else {set CONFIG_DCACHE_SZ64 0}
+ global CONFIG_DCACHE_SZ128
+ if {$tmpvar_14 == "128"} then {set CONFIG_DCACHE_SZ128 1} else {set CONFIG_DCACHE_SZ128 0}
+ global CONFIG_DCACHE_SZ256
+ if {$tmpvar_14 == "256"} then {set CONFIG_DCACHE_SZ256 1} else {set CONFIG_DCACHE_SZ256 0}
+ global tmpvar_15
+ global CONFIG_DCACHE_LZ16
+ if {$tmpvar_15 == "16"} then {set CONFIG_DCACHE_LZ16 1} else {set CONFIG_DCACHE_LZ16 0}
+ global CONFIG_DCACHE_LZ32
+ if {$tmpvar_15 == "32"} then {set CONFIG_DCACHE_LZ32 1} else {set CONFIG_DCACHE_LZ32 0}
+ global tmpvar_16
+ global CONFIG_DCACHE_ALGORND
+ if {$tmpvar_16 == "Random"} then {set CONFIG_DCACHE_ALGORND 1} else {set CONFIG_DCACHE_ALGORND 0}
+ global CONFIG_DCACHE_ALGOLRR
+ if {$tmpvar_16 == "LRR"} then {set CONFIG_DCACHE_ALGOLRR 1} else {set CONFIG_DCACHE_ALGOLRR 0}
+ global CONFIG_DCACHE_ALGOLRU
+ if {$tmpvar_16 == "LRU"} then {set CONFIG_DCACHE_ALGOLRU 1} else {set CONFIG_DCACHE_ALGOLRU 0}
+ global CONFIG_DCACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {
+ set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK&15]} else {set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK|16]}
+ global CONFIG_DCACHE_SNOOP
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]}
+ global CONFIG_DCACHE_SNOOP_FAST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {
+ set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]}
+ global CONFIG_DCACHE_SNOOP_SEPTAG
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {
+ set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]}
+ global CONFIG_CACHE_FIXED
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {validate_hex CONFIG_CACHE_FIXED "$CONFIG_CACHE_FIXED" 0}
+ global CONFIG_DCACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {
+ set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM&15]} else {set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM|16]}
+ global tmpvar_17
+ global CONFIG_DCACHE_LRAM_SZ1
+ if {$tmpvar_17 == "1"} then {set CONFIG_DCACHE_LRAM_SZ1 1} else {set CONFIG_DCACHE_LRAM_SZ1 0}
+ global CONFIG_DCACHE_LRAM_SZ2
+ if {$tmpvar_17 == "2"} then {set CONFIG_DCACHE_LRAM_SZ2 1} else {set CONFIG_DCACHE_LRAM_SZ2 0}
+ global CONFIG_DCACHE_LRAM_SZ4
+ if {$tmpvar_17 == "4"} then {set CONFIG_DCACHE_LRAM_SZ4 1} else {set CONFIG_DCACHE_LRAM_SZ4 0}
+ global CONFIG_DCACHE_LRAM_SZ8
+ if {$tmpvar_17 == "8"} then {set CONFIG_DCACHE_LRAM_SZ8 1} else {set CONFIG_DCACHE_LRAM_SZ8 0}
+ global CONFIG_DCACHE_LRAM_SZ16
+ if {$tmpvar_17 == "16"} then {set CONFIG_DCACHE_LRAM_SZ16 1} else {set CONFIG_DCACHE_LRAM_SZ16 0}
+ global CONFIG_DCACHE_LRAM_SZ32
+ if {$tmpvar_17 == "32"} then {set CONFIG_DCACHE_LRAM_SZ32 1} else {set CONFIG_DCACHE_LRAM_SZ32 0}
+ global CONFIG_DCACHE_LRAM_SZ64
+ if {$tmpvar_17 == "64"} then {set CONFIG_DCACHE_LRAM_SZ64 1} else {set CONFIG_DCACHE_LRAM_SZ64 0}
+ global CONFIG_DCACHE_LRAM_SZ128
+ if {$tmpvar_17 == "128"} then {set CONFIG_DCACHE_LRAM_SZ128 1} else {set CONFIG_DCACHE_LRAM_SZ128 0}
+ global CONFIG_DCACHE_LRAM_SZ256
+ if {$tmpvar_17 == "256"} then {set CONFIG_DCACHE_LRAM_SZ256 1} else {set CONFIG_DCACHE_LRAM_SZ256 0}
+ global CONFIG_DCACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {validate_hex CONFIG_DCACHE_LRSTART "$CONFIG_DCACHE_LRSTART" 8f}
+}
+
+
+proc menu7 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 7}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 7]]
+ message $w.m -width 400 -aspect 300 -text \
+ "MMU" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "MMU"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 7; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu8 .menu8 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 7 0 "Enable MMU " CONFIG_MMU_ENABLE
+ global tmpvar_18
+ minimenu $w.config.f 7 1 "MMU type " tmpvar_18 CONFIG_MMU_COMBINED
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"MMU type \""
+ $w.config.f.x1.x.menu add radiobutton -label "combined" -variable tmpvar_18 -value "combined" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "split" -variable tmpvar_18 -value "split" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 2
+ global tmpvar_19
+ minimenu $w.config.f 7 2 "TLB replacement sheme " tmpvar_19 CONFIG_MMU_REPARRAY
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"TLB replacement sheme \""
+ $w.config.f.x2.x.menu add radiobutton -label "LRU" -variable tmpvar_19 -value "LRU" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "Increment" -variable tmpvar_19 -value "Increment" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 2
+ global tmpvar_20
+ minimenu $w.config.f 7 3 "Instruction (or combined) TLB entries" tmpvar_20 CONFIG_MMU_I2
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Instruction (or combined) TLB entries\""
+ $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_20 -value "2" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_20 -value "4" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_20 -value "8" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_20 -value "16" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_20 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 5
+ global tmpvar_21
+ minimenu $w.config.f 7 4 "Data TLB entries" tmpvar_21 CONFIG_MMU_D2
+ menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Data TLB entries\""
+ $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_21 -value "2" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_21 -value "4" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_21 -value "8" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_21 -value "16" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_21 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x4.x.menu 5
+ bool $w.config.f 7 5 "Fast writebuffer " CONFIG_MMU_FASTWB
+ global tmpvar_22
+ minimenu $w.config.f 7 6 "MMU page size" tmpvar_22 CONFIG_MMU_PAGE_4K
+ menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"MMU page size\""
+ $w.config.f.x6.x.menu add radiobutton -label "4K" -variable tmpvar_22 -value "4K" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "8K" -variable tmpvar_22 -value "8K" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "16K" -variable tmpvar_22 -value "16K" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "32K" -variable tmpvar_22 -value "32K" -command "update_active"
+ $w.config.f.x6.x.menu add radiobutton -label "Programmable" -variable tmpvar_22 -value "Programmable" -command "update_active"
+ menusplit $w $w.config.f.x6.x.menu 5
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu7 {} {
+ global CONFIG_LEON3
+ global CONFIG_MMU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu7.config.f.x0 normal {n l y}} else {configure_entry .menu7.config.f.x0 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x1 normal {x l}} else {configure_entry .menu7.config.f.x1 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x2 normal {x l}} else {configure_entry .menu7.config.f.x2 disabled {x l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x3 normal {x l}} else {configure_entry .menu7.config.f.x3 disabled {x l}}
+ global CONFIG_MMU_SPLIT
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {configure_entry .menu7.config.f.x4 normal {x l}} else {configure_entry .menu7.config.f.x4 disabled {x l}}
+ global CONFIG_MMU_FASTWB
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {
+ configure_entry .menu7.config.f.x5 normal {n l y}} else {configure_entry .menu7.config.f.x5 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x6 normal {x l}} else {configure_entry .menu7.config.f.x6 disabled {x l}}
+}
+
+
+proc update_define_menu7 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_MMU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE&15]} else {set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE|16]}
+ global tmpvar_18
+ global CONFIG_MMU_COMBINED
+ if {$tmpvar_18 == "combined"} then {set CONFIG_MMU_COMBINED 1} else {set CONFIG_MMU_COMBINED 0}
+ global CONFIG_MMU_SPLIT
+ if {$tmpvar_18 == "split"} then {set CONFIG_MMU_SPLIT 1} else {set CONFIG_MMU_SPLIT 0}
+ global tmpvar_19
+ global CONFIG_MMU_REPARRAY
+ if {$tmpvar_19 == "LRU"} then {set CONFIG_MMU_REPARRAY 1} else {set CONFIG_MMU_REPARRAY 0}
+ global CONFIG_MMU_REPINCREMENT
+ if {$tmpvar_19 == "Increment"} then {set CONFIG_MMU_REPINCREMENT 1} else {set CONFIG_MMU_REPINCREMENT 0}
+ global tmpvar_20
+ global CONFIG_MMU_I2
+ if {$tmpvar_20 == "2"} then {set CONFIG_MMU_I2 1} else {set CONFIG_MMU_I2 0}
+ global CONFIG_MMU_I4
+ if {$tmpvar_20 == "4"} then {set CONFIG_MMU_I4 1} else {set CONFIG_MMU_I4 0}
+ global CONFIG_MMU_I8
+ if {$tmpvar_20 == "8"} then {set CONFIG_MMU_I8 1} else {set CONFIG_MMU_I8 0}
+ global CONFIG_MMU_I16
+ if {$tmpvar_20 == "16"} then {set CONFIG_MMU_I16 1} else {set CONFIG_MMU_I16 0}
+ global CONFIG_MMU_I32
+ if {$tmpvar_20 == "32"} then {set CONFIG_MMU_I32 1} else {set CONFIG_MMU_I32 0}
+ global tmpvar_21
+ global CONFIG_MMU_D2
+ if {$tmpvar_21 == "2"} then {set CONFIG_MMU_D2 1} else {set CONFIG_MMU_D2 0}
+ global CONFIG_MMU_D4
+ if {$tmpvar_21 == "4"} then {set CONFIG_MMU_D4 1} else {set CONFIG_MMU_D4 0}
+ global CONFIG_MMU_D8
+ if {$tmpvar_21 == "8"} then {set CONFIG_MMU_D8 1} else {set CONFIG_MMU_D8 0}
+ global CONFIG_MMU_D16
+ if {$tmpvar_21 == "16"} then {set CONFIG_MMU_D16 1} else {set CONFIG_MMU_D16 0}
+ global CONFIG_MMU_D32
+ if {$tmpvar_21 == "32"} then {set CONFIG_MMU_D32 1} else {set CONFIG_MMU_D32 0}
+ global CONFIG_MMU_FASTWB
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {
+ set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB&15]} else {set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB|16]}
+ global tmpvar_22
+ global CONFIG_MMU_PAGE_4K
+ if {$tmpvar_22 == "4K"} then {set CONFIG_MMU_PAGE_4K 1} else {set CONFIG_MMU_PAGE_4K 0}
+ global CONFIG_MMU_PAGE_8K
+ if {$tmpvar_22 == "8K"} then {set CONFIG_MMU_PAGE_8K 1} else {set CONFIG_MMU_PAGE_8K 0}
+ global CONFIG_MMU_PAGE_16K
+ if {$tmpvar_22 == "16K"} then {set CONFIG_MMU_PAGE_16K 1} else {set CONFIG_MMU_PAGE_16K 0}
+ global CONFIG_MMU_PAGE_32K
+ if {$tmpvar_22 == "32K"} then {set CONFIG_MMU_PAGE_32K 1} else {set CONFIG_MMU_PAGE_32K 0}
+ global CONFIG_MMU_PAGE_PROG
+ if {$tmpvar_22 == "Programmable"} then {set CONFIG_MMU_PAGE_PROG 1} else {set CONFIG_MMU_PAGE_PROG 0}
+}
+
+
+proc menu8 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 8}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 8]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Debug Support Unit " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Debug Support Unit "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 8; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu9 .menu9 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 8 0 "Enable LEON3 Debug support unit " CONFIG_DSU_ENABLE
+ bool $w.config.f 8 1 "Instruction trace buffer" CONFIG_DSU_ITRACE
+ global tmpvar_23
+ minimenu $w.config.f 8 2 "Instruction trace buffer size (kbytes)" tmpvar_23 CONFIG_DSU_ITRACESZ1
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Instruction trace buffer size (kbytes)\""
+ $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_23 -value "1" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_23 -value "2" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_23 -value "4" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_23 -value "8" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_23 -value "16" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 5
+ bool $w.config.f 8 3 "AHB trace buffer" CONFIG_DSU_ATRACE
+ global tmpvar_24
+ minimenu $w.config.f 8 4 "AHB trace buffer size (kbytes)" tmpvar_24 CONFIG_DSU_ATRACESZ1
+ menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB trace buffer size (kbytes)\""
+ $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_24 -value "1" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_24 -value "2" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_24 -value "4" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_24 -value "8" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_24 -value "16" -command "update_active"
+ menusplit $w $w.config.f.x4.x.menu 5
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu8 {} {
+ global CONFIG_LEON3
+ global CONFIG_DSU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu8.config.f.x0 normal {n l y}} else {configure_entry .menu8.config.f.x0 disabled {y n l}}
+ global CONFIG_DSU_ITRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {
+ configure_entry .menu8.config.f.x1 normal {n l y}} else {configure_entry .menu8.config.f.x1 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then {configure_entry .menu8.config.f.x2 normal {x l}} else {configure_entry .menu8.config.f.x2 disabled {x l}}
+ global CONFIG_DSU_ATRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {
+ configure_entry .menu8.config.f.x3 normal {n l y}} else {configure_entry .menu8.config.f.x3 disabled {y n l}}
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then {configure_entry .menu8.config.f.x4 normal {x l}} else {configure_entry .menu8.config.f.x4 disabled {x l}}
+}
+
+
+proc update_define_menu8 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_DSU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE&15]} else {set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE|16]}
+ global CONFIG_DSU_ITRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {
+ set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE&15]} else {set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE|16]}
+ global tmpvar_23
+ global CONFIG_DSU_ITRACESZ1
+ if {$tmpvar_23 == "1"} then {set CONFIG_DSU_ITRACESZ1 1} else {set CONFIG_DSU_ITRACESZ1 0}
+ global CONFIG_DSU_ITRACESZ2
+ if {$tmpvar_23 == "2"} then {set CONFIG_DSU_ITRACESZ2 1} else {set CONFIG_DSU_ITRACESZ2 0}
+ global CONFIG_DSU_ITRACESZ4
+ if {$tmpvar_23 == "4"} then {set CONFIG_DSU_ITRACESZ4 1} else {set CONFIG_DSU_ITRACESZ4 0}
+ global CONFIG_DSU_ITRACESZ8
+ if {$tmpvar_23 == "8"} then {set CONFIG_DSU_ITRACESZ8 1} else {set CONFIG_DSU_ITRACESZ8 0}
+ global CONFIG_DSU_ITRACESZ16
+ if {$tmpvar_23 == "16"} then {set CONFIG_DSU_ITRACESZ16 1} else {set CONFIG_DSU_ITRACESZ16 0}
+ global CONFIG_DSU_ATRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {
+ set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE&15]} else {set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE|16]}
+ global tmpvar_24
+ global CONFIG_DSU_ATRACESZ1
+ if {$tmpvar_24 == "1"} then {set CONFIG_DSU_ATRACESZ1 1} else {set CONFIG_DSU_ATRACESZ1 0}
+ global CONFIG_DSU_ATRACESZ2
+ if {$tmpvar_24 == "2"} then {set CONFIG_DSU_ATRACESZ2 1} else {set CONFIG_DSU_ATRACESZ2 0}
+ global CONFIG_DSU_ATRACESZ4
+ if {$tmpvar_24 == "4"} then {set CONFIG_DSU_ATRACESZ4 1} else {set CONFIG_DSU_ATRACESZ4 0}
+ global CONFIG_DSU_ATRACESZ8
+ if {$tmpvar_24 == "8"} then {set CONFIG_DSU_ATRACESZ8 1} else {set CONFIG_DSU_ATRACESZ8 0}
+ global CONFIG_DSU_ATRACESZ16
+ if {$tmpvar_24 == "16"} then {set CONFIG_DSU_ATRACESZ16 1} else {set CONFIG_DSU_ATRACESZ16 0}
+}
+
+
+proc menu9 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 9}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 9]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Fault-tolerance " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Fault-tolerance "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 9; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu10 .menu10 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu9 {} {
+}
+
+
+proc update_define_menu9 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+proc menu10 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu3}
+ catch {destroy $w; unregister_active 10}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 10]]
+ message $w.m -width 400 -aspect 300 -text \
+ "VHDL debug settings " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "VHDL debug settings "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 10; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 10; catch {destroy .menu3}; unregister_active 3; menu11 .menu11 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 10 0 "Processor disassembly to console " CONFIG_IU_DISAS
+ bool $w.config.f 10 1 "Processor disassembly in netlist " CONFIG_IU_DISAS_NET
+ bool $w.config.f 10 2 "32-bit program counters " CONFIG_DEBUG_PC32
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "}
+ set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu10 {} {
+ global CONFIG_LEON3
+ global CONFIG_IU_DISAS
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu10.config.f.x0 normal {n l y}} else {configure_entry .menu10.config.f.x0 disabled {y n l}}
+ global CONFIG_IU_DISAS_NET
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {
+ configure_entry .menu10.config.f.x1 normal {n l y}} else {configure_entry .menu10.config.f.x1 disabled {y n l}}
+ global CONFIG_DEBUG_PC32
+ if {($CONFIG_LEON3 == 1)} then {
+ configure_entry .menu10.config.f.x2 normal {n l y}} else {configure_entry .menu10.config.f.x2 disabled {y n l}}
+}
+
+
+proc update_define_menu10 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_LEON3
+ global CONFIG_IU_DISAS
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS&15]} else {set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS|16]}
+ global CONFIG_IU_DISAS_NET
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {
+ set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET&15]} else {set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET|16]}
+ global CONFIG_DEBUG_PC32
+ if {($CONFIG_LEON3 == 1)} then {
+ set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32&15]} else {set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32|16]}
+}
+
+
+menu_option menu11 11 "AMBA configuration"
+proc menu11 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 11}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 11]]
+ message $w.m -width 400 -aspect 300 -text \
+ "AMBA configuration" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "AMBA configuration"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 11; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu12 .menu12 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ int $w.config.f 11 0 "Default AHB master" CONFIG_AHB_DEFMST
+ bool $w.config.f 11 1 "Round-robin arbiter " CONFIG_AHB_RROBIN
+ bool $w.config.f 11 2 "AHB split-transaction support " CONFIG_AHB_SPLIT
+ hex $w.config.f 11 3 "I/O area start address (haddr\[31:20\]) " CONFIG_AHB_IOADDR
+ hex $w.config.f 11 4 "AHB/APB bridge address (haddr\[31:20\]) " CONFIG_APB_HADDR
+ bool $w.config.f 11 5 "Enable AMBA AHB monitor " CONFIG_AHB_MON
+ bool $w.config.f 11 6 "Report AHB errors " CONFIG_AHB_MONERR
+ bool $w.config.f 11 7 "Report AHB warings " CONFIG_AHB_MONWAR
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu11 {} {
+ global CONFIG_AHB_MON
+ global CONFIG_AHB_MONERR
+ if {($CONFIG_AHB_MON == 1)} then {
+ configure_entry .menu11.config.f.x6 normal {n l y}} else {configure_entry .menu11.config.f.x6 disabled {y n l}}
+ global CONFIG_AHB_MONWAR
+ if {($CONFIG_AHB_MON == 1)} then {
+ configure_entry .menu11.config.f.x7 normal {n l y}} else {configure_entry .menu11.config.f.x7 disabled {y n l}}
+}
+
+
+proc update_define_menu11 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_AHB_MON
+ global CONFIG_AHB_MONERR
+ if {($CONFIG_AHB_MON == 1)} then {
+ set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR&15]} else {set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR|16]}
+ global CONFIG_AHB_MONWAR
+ if {($CONFIG_AHB_MON == 1)} then {
+ set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR&15]} else {set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR|16]}
+}
+
+
+menu_option menu12 12 "Debug Link "
+proc menu12 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 12}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 12]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Debug Link " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Debug Link "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 12; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu13 .menu13 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 12 0 "Serial Debug Link (RS232) " CONFIG_DSU_UART
+ bool $w.config.f 12 1 "JTAG Debug Link" CONFIG_DSU_JTAG
+ bool $w.config.f 12 2 "USB Debug Communication Link" CONFIG_GRUSB_DCL
+ global tmpvar_26
+ minimenu $w.config.f 12 3 "USB Transceiver Interface" tmpvar_26 CONFIG_GRUSB_DCL_ULPI
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"USB Transceiver Interface\""
+ $w.config.f.x3.x.menu add radiobutton -label "ULPI" -variable tmpvar_26 -value "ULPI" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "UTMI/UTMI+8-bit" -variable tmpvar_26 -value "UTMI/UTMI+8-bit" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "UTMI/UTMI+16-bit" -variable tmpvar_26 -value "UTMI/UTMI+16-bit" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 3
+ bool $w.config.f 12 4 "Ethernet Debug Communication Link (EDCL)" CONFIG_DSU_ETH
+ global tmpvar_27
+ minimenu $w.config.f 12 5 "Ethernet/AHB bridge buffer size (kbytes)" tmpvar_27 CONFIG_DSU_ETHSZ1
+ menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"Ethernet/AHB bridge buffer size (kbytes)\""
+ $w.config.f.x5.x.menu add radiobutton -label "1" -variable tmpvar_27 -value "1" -command "update_active"
+ $w.config.f.x5.x.menu add radiobutton -label "2" -variable tmpvar_27 -value "2" -command "update_active"
+ $w.config.f.x5.x.menu add radiobutton -label "4" -variable tmpvar_27 -value "4" -command "update_active"
+ $w.config.f.x5.x.menu add radiobutton -label "8" -variable tmpvar_27 -value "8" -command "update_active"
+ $w.config.f.x5.x.menu add radiobutton -label "16" -variable tmpvar_27 -value "16" -command "update_active"
+ menusplit $w $w.config.f.x5.x.menu 5
+ hex $w.config.f 12 6 "MSB 16 bits of IP address (hex) " CONFIG_DSU_IPMSB
+ hex $w.config.f 12 7 "LSB 16 bits of IP address (hex) " CONFIG_DSU_IPLSB
+ hex $w.config.f 12 8 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB
+ hex $w.config.f 12 9 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB
+ bool $w.config.f 12 10 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu12 {} {
+ global CONFIG_GRUSB_DCL
+ if {($CONFIG_GRUSB_DCL == 1)} then {configure_entry .menu12.config.f.x3 normal {x l}} else {configure_entry .menu12.config.f.x3 disabled {x l}}
+ global CONFIG_GRETH_ENABLE
+ global CONFIG_DSU_ETH
+ if {($CONFIG_GRETH_ENABLE == 1)} then {
+ configure_entry .menu12.config.f.x4 normal {n l y}} else {configure_entry .menu12.config.f.x4 disabled {y n l}}
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {configure_entry .menu12.config.f.x5 normal {x l}} else {configure_entry .menu12.config.f.x5 disabled {x l}}
+ global CONFIG_DSU_IPMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled}
+ global CONFIG_DSU_IPLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled}
+ global CONFIG_DSU_ETHMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x8.l configure -state normal; } else {.menu12.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x8.l configure -state disabled}
+ global CONFIG_DSU_ETHLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x9.l configure -state normal; } else {.menu12.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x9.l configure -state disabled}
+ global CONFIG_GRETH_GIGA
+ global CONFIG_DSU_ETH_PROG
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {
+ configure_entry .menu12.config.f.x10 normal {n l y}} else {configure_entry .menu12.config.f.x10 disabled {y n l}}
+}
+
+
+proc update_define_menu12 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global tmpvar_26
+ global CONFIG_GRUSB_DCL_ULPI
+ if {$tmpvar_26 == "ULPI"} then {set CONFIG_GRUSB_DCL_ULPI 1} else {set CONFIG_GRUSB_DCL_ULPI 0}
+ global CONFIG_GRUSB_DCL_UTMI8
+ if {$tmpvar_26 == "UTMI/UTMI+8-bit"} then {set CONFIG_GRUSB_DCL_UTMI8 1} else {set CONFIG_GRUSB_DCL_UTMI8 0}
+ global CONFIG_GRUSB_DCL_UTMI16
+ if {$tmpvar_26 == "UTMI/UTMI+16-bit"} then {set CONFIG_GRUSB_DCL_UTMI16 1} else {set CONFIG_GRUSB_DCL_UTMI16 0}
+ global CONFIG_GRETH_ENABLE
+ global CONFIG_DSU_ETH
+ if {($CONFIG_GRETH_ENABLE == 1)} then {
+ set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH&15]} else {set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH|16]}
+ global tmpvar_27
+ global CONFIG_DSU_ETHSZ1
+ if {$tmpvar_27 == "1"} then {set CONFIG_DSU_ETHSZ1 1} else {set CONFIG_DSU_ETHSZ1 0}
+ global CONFIG_DSU_ETHSZ2
+ if {$tmpvar_27 == "2"} then {set CONFIG_DSU_ETHSZ2 1} else {set CONFIG_DSU_ETHSZ2 0}
+ global CONFIG_DSU_ETHSZ4
+ if {$tmpvar_27 == "4"} then {set CONFIG_DSU_ETHSZ4 1} else {set CONFIG_DSU_ETHSZ4 0}
+ global CONFIG_DSU_ETHSZ8
+ if {$tmpvar_27 == "8"} then {set CONFIG_DSU_ETHSZ8 1} else {set CONFIG_DSU_ETHSZ8 0}
+ global CONFIG_DSU_ETHSZ16
+ if {$tmpvar_27 == "16"} then {set CONFIG_DSU_ETHSZ16 1} else {set CONFIG_DSU_ETHSZ16 0}
+ global CONFIG_DSU_IPMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPMSB "$CONFIG_DSU_IPMSB" C0A8}
+ global CONFIG_DSU_IPLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPLSB "$CONFIG_DSU_IPLSB" 0033}
+ global CONFIG_DSU_ETHMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000}
+ global CONFIG_DSU_ETHLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000}
+ global CONFIG_GRETH_GIGA
+ global CONFIG_DSU_ETH_PROG
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {
+ set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]}
+}
+
+
+menu_option menu13 13 "Peripherals "
+proc menu13 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 13}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 13]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Peripherals " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Peripherals "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 13; break"
+ set nextscript "catch {focus $oldFocus}; menu14 .menu14 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ submenu $w.config.f 13 0 "Memory controller " 14
+ submenu $w.config.f 13 1 "On-chip RAM/ROM " 16
+ submenu $w.config.f 13 2 "Ethernet " 17
+ submenu $w.config.f 13 3 "IDE Disk controller " 18
+ submenu $w.config.f 13 4 "CAN " 19
+ submenu $w.config.f 13 5 "USB 2.0 Device Controller " 20
+ submenu $w.config.f 13 6 "UART, timer, I/O port and interrupt controller" 21
+ submenu $w.config.f 13 7 "Spacewire " 22
+ submenu $w.config.f 13 8 "Keybord and VGA interface" 23
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu13 {} {
+}
+
+
+proc update_define_menu13 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+proc menu14 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 14}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 14]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Memory controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Memory controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 14; break"
+ set nextscript "catch {focus $oldFocus}; menu15 .menu15 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ submenu $w.config.f 14 0 "Leon2 memory controller " 15
+ bool $w.config.f 14 1 "Enable AHB Status Register " CONFIG_AHBSTAT_ENABLE
+ int $w.config.f 14 2 "Number of correctable-error slaves " CONFIG_AHBSTAT_NFTSLV
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu14 {} {
+ global CONFIG_AHBSTAT_ENABLE
+ global CONFIG_AHBSTAT_NFTSLV
+ if {($CONFIG_AHBSTAT_ENABLE == 1)} then {.menu14.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu14.config.f.x2.l configure -state normal; } else {.menu14.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu14.config.f.x2.l configure -state disabled}
+}
+
+
+proc update_define_menu14 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_AHBSTAT_ENABLE
+ global CONFIG_AHBSTAT_NFTSLV
+ if {($CONFIG_AHBSTAT_ENABLE == 1)} then {validate_int CONFIG_AHBSTAT_NFTSLV "$CONFIG_AHBSTAT_NFTSLV" 1}
+}
+
+
+proc menu15 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu14}
+ catch {destroy $w; unregister_active 15}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 15]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Leon2 memory controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Leon2 memory controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 15; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 15; catch {destroy .menu14}; unregister_active 14; menu16 .menu16 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 15 0 "Enable Leon2 memory controller " CONFIG_MCTRL_LEON2
+ bool $w.config.f 15 1 "8-bit PROM/SRAM bus support " CONFIG_MCTRL_8BIT
+ bool $w.config.f 15 2 "16-bit PROM/SRAM bus support " CONFIG_MCTRL_16BIT
+ bool $w.config.f 15 3 "5th SRAM chip-select " CONFIG_MCTRL_5CS
+ bool $w.config.f 15 4 "SDRAM controller " CONFIG_MCTRL_SDRAM
+ bool $w.config.f 15 5 "Separate address and data buses" CONFIG_MCTRL_SDRAM_SEPBUS
+ bool $w.config.f 15 6 "64-bit SDRAM data bus" CONFIG_MCTRL_SDRAM_BUS64
+ bool $w.config.f 15 7 "Unsynchronized sdclock" CONFIG_MCTRL_SDRAM_INVCLK
+ bool $w.config.f 15 8 "Enable page burst operation " CONFIG_MCTRL_PAGE
+ bool $w.config.f 15 9 "Enable programmable page burst " CONFIG_MCTRL_PROGPAGE
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controller "}
+ set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu15 {} {
+ global CONFIG_MCTRL_LEON2
+ global CONFIG_MCTRL_8BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ configure_entry .menu15.config.f.x1 normal {n l y}} else {configure_entry .menu15.config.f.x1 disabled {y n l}}
+ global CONFIG_MCTRL_16BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ configure_entry .menu15.config.f.x2 normal {n l y}} else {configure_entry .menu15.config.f.x2 disabled {y n l}}
+ global CONFIG_MCTRL_5CS
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ configure_entry .menu15.config.f.x3 normal {n l y}} else {configure_entry .menu15.config.f.x3 disabled {y n l}}
+ global CONFIG_MCTRL_SDRAM
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ configure_entry .menu15.config.f.x4 normal {n l y}} else {configure_entry .menu15.config.f.x4 disabled {y n l}}
+ global CONFIG_MCTRL_SDRAM_SEPBUS
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {
+ configure_entry .menu15.config.f.x5 normal {n l y}} else {configure_entry .menu15.config.f.x5 disabled {y n l}}
+ global CONFIG_MCTRL_SDRAM_BUS64
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {
+ configure_entry .menu15.config.f.x6 normal {n l y}} else {configure_entry .menu15.config.f.x6 disabled {y n l}}
+ global CONFIG_MCTRL_SDRAM_INVCLK
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {
+ configure_entry .menu15.config.f.x7 normal {n l y}} else {configure_entry .menu15.config.f.x7 disabled {y n l}}
+ global CONFIG_MCTRL_PAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {
+ configure_entry .menu15.config.f.x8 normal {n l y}} else {configure_entry .menu15.config.f.x8 disabled {y n l}}
+ global CONFIG_MCTRL_PROGPAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {
+ configure_entry .menu15.config.f.x9 normal {n l y}} else {configure_entry .menu15.config.f.x9 disabled {y n l}}
+}
+
+
+proc update_define_menu15 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_MCTRL_LEON2
+ global CONFIG_MCTRL_8BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT&15]} else {set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT|16]}
+ global CONFIG_MCTRL_16BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT&15]} else {set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT|16]}
+ global CONFIG_MCTRL_5CS
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS&15]} else {set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS|16]}
+ global CONFIG_MCTRL_SDRAM
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {
+ set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM&15]} else {set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM|16]}
+ global CONFIG_MCTRL_SDRAM_SEPBUS
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {
+ set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS&15]} else {set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS|16]}
+ global CONFIG_MCTRL_SDRAM_BUS64
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {
+ set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64&15]} else {set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64|16]}
+ global CONFIG_MCTRL_SDRAM_INVCLK
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {
+ set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK&15]} else {set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK|16]}
+ global CONFIG_MCTRL_PAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {
+ set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE&15]} else {set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE|16]}
+ global CONFIG_MCTRL_PROGPAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {
+ set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE&15]} else {set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE|16]}
+}
+
+
+proc menu16 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 16}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 16]]
+ message $w.m -width 400 -aspect 300 -text \
+ "On-chip RAM/ROM " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "On-chip RAM/ROM "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 16; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu17 .menu17 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 16 0 "On-chip AHB ROM " CONFIG_AHBROM_ENABLE
+ hex $w.config.f 16 1 "ROM start address (haddr\[31:20\]) " CONFIG_AHBROM_START
+ bool $w.config.f 16 2 "Pipelined ROM access " CONFIG_AHBROM_PIPE
+ bool $w.config.f 16 3 "On-chip AHB RAM " CONFIG_AHBRAM_ENABLE
+ global tmpvar_28
+ minimenu $w.config.f 16 4 "AHB RAM size (Kbyte)" tmpvar_28 CONFIG_AHBRAM_SZ1
+ menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB RAM size (Kbyte)\""
+ $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_28 -value "1" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_28 -value "2" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_28 -value "4" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_28 -value "8" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_28 -value "16" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_28 -value "32" -command "update_active"
+ $w.config.f.x4.x.menu add radiobutton -label "64" -variable tmpvar_28 -value "64" -command "update_active"
+ menusplit $w $w.config.f.x4.x.menu 7
+ hex $w.config.f 16 5 "RAM start address (haddr\[31:20\]) " CONFIG_AHBRAM_START
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu16 {} {
+ global CONFIG_AHBROM_ENABLE
+ global CONFIG_AHBROM_START
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {.menu16.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu16.config.f.x1.l configure -state normal; } else {.menu16.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu16.config.f.x1.l configure -state disabled}
+ global CONFIG_AHBROM_PIPE
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {
+ configure_entry .menu16.config.f.x2 normal {n l y}} else {configure_entry .menu16.config.f.x2 disabled {y n l}}
+ global CONFIG_AHBRAM_ENABLE
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {configure_entry .menu16.config.f.x4 normal {x l}} else {configure_entry .menu16.config.f.x4 disabled {x l}}
+ global CONFIG_AHBRAM_START
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {.menu16.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu16.config.f.x5.l configure -state normal; } else {.menu16.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu16.config.f.x5.l configure -state disabled}
+}
+
+
+proc update_define_menu16 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_AHBROM_ENABLE
+ global CONFIG_AHBROM_START
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {validate_hex CONFIG_AHBROM_START "$CONFIG_AHBROM_START" 000}
+ global CONFIG_AHBROM_PIPE
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {
+ set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE&15]} else {set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE|16]}
+ global tmpvar_28
+ global CONFIG_AHBRAM_SZ1
+ if {$tmpvar_28 == "1"} then {set CONFIG_AHBRAM_SZ1 1} else {set CONFIG_AHBRAM_SZ1 0}
+ global CONFIG_AHBRAM_SZ2
+ if {$tmpvar_28 == "2"} then {set CONFIG_AHBRAM_SZ2 1} else {set CONFIG_AHBRAM_SZ2 0}
+ global CONFIG_AHBRAM_SZ4
+ if {$tmpvar_28 == "4"} then {set CONFIG_AHBRAM_SZ4 1} else {set CONFIG_AHBRAM_SZ4 0}
+ global CONFIG_AHBRAM_SZ8
+ if {$tmpvar_28 == "8"} then {set CONFIG_AHBRAM_SZ8 1} else {set CONFIG_AHBRAM_SZ8 0}
+ global CONFIG_AHBRAM_SZ16
+ if {$tmpvar_28 == "16"} then {set CONFIG_AHBRAM_SZ16 1} else {set CONFIG_AHBRAM_SZ16 0}
+ global CONFIG_AHBRAM_SZ32
+ if {$tmpvar_28 == "32"} then {set CONFIG_AHBRAM_SZ32 1} else {set CONFIG_AHBRAM_SZ32 0}
+ global CONFIG_AHBRAM_SZ64
+ if {$tmpvar_28 == "64"} then {set CONFIG_AHBRAM_SZ64 1} else {set CONFIG_AHBRAM_SZ64 0}
+ global CONFIG_AHBRAM_ENABLE
+ global CONFIG_AHBRAM_START
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {validate_hex CONFIG_AHBRAM_START "$CONFIG_AHBRAM_START" A00}
+}
+
+
+proc menu17 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 17}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 17]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Ethernet " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Ethernet "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 17; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu18 .menu18 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 17 0 "Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH_ENABLE
+ bool $w.config.f 17 1 "Enable 1000 Mbit support " CONFIG_GRETH_GIGA
+ global tmpvar_29
+ minimenu $w.config.f 17 2 "AHB FIFO size (words) " tmpvar_29 CONFIG_GRETH_FIFO4
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB FIFO size (words) \""
+ $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_29 -value "4" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_29 -value "8" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_29 -value "16" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_29 -value "32" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_29 -value "64" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 5
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu17 {} {
+ global CONFIG_GRETH_ENABLE
+ global CONFIG_GRETH_GIGA
+ if {($CONFIG_GRETH_ENABLE == 1)} then {
+ configure_entry .menu17.config.f.x1 normal {n l y}} else {configure_entry .menu17.config.f.x1 disabled {y n l}}
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {configure_entry .menu17.config.f.x2 normal {x l}} else {configure_entry .menu17.config.f.x2 disabled {x l}}
+}
+
+
+proc update_define_menu17 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_GRETH_ENABLE
+ global CONFIG_GRETH_GIGA
+ if {($CONFIG_GRETH_ENABLE == 1)} then {
+ set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA&15]} else {set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA|16]}
+ global tmpvar_29
+ global CONFIG_GRETH_FIFO4
+ if {$tmpvar_29 == "4"} then {set CONFIG_GRETH_FIFO4 1} else {set CONFIG_GRETH_FIFO4 0}
+ global CONFIG_GRETH_FIFO8
+ if {$tmpvar_29 == "8"} then {set CONFIG_GRETH_FIFO8 1} else {set CONFIG_GRETH_FIFO8 0}
+ global CONFIG_GRETH_FIFO16
+ if {$tmpvar_29 == "16"} then {set CONFIG_GRETH_FIFO16 1} else {set CONFIG_GRETH_FIFO16 0}
+ global CONFIG_GRETH_FIFO32
+ if {$tmpvar_29 == "32"} then {set CONFIG_GRETH_FIFO32 1} else {set CONFIG_GRETH_FIFO32 0}
+ global CONFIG_GRETH_FIFO64
+ if {$tmpvar_29 == "64"} then {set CONFIG_GRETH_FIFO64 1} else {set CONFIG_GRETH_FIFO64 0}
+}
+
+
+proc menu18 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 18}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 18]]
+ message $w.m -width 400 -aspect 300 -text \
+ "IDE Disk controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "IDE Disk controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 18; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu19 .menu19 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 18 0 "Enable ATA interface " CONFIG_ATA_ENABLE
+ hex $w.config.f 18 1 "ATA I/O area start address (haddr\[19:8\]) " CONFIG_ATAIO
+ int $w.config.f 18 2 "Interrupt number " CONFIG_ATAIRQ
+ bool $w.config.f 18 3 "Enable MWDMA support " CONFIG_ATA_MWDMA
+ int $w.config.f 18 4 "FIFO depth " CONFIG_ATA_FIFO
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu18 {} {
+ global CONFIG_ATA_ENABLE
+ global CONFIG_ATAIO
+ if {($CONFIG_ATA_ENABLE == 1)} then {.menu18.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x1.l configure -state normal; } else {.menu18.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x1.l configure -state disabled}
+ global CONFIG_ATAIRQ
+ if {($CONFIG_ATA_ENABLE == 1)} then {.menu18.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x2.l configure -state normal; } else {.menu18.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x2.l configure -state disabled}
+ global CONFIG_ATA_MWDMA
+ if {($CONFIG_ATA_ENABLE == 1)} then {
+ configure_entry .menu18.config.f.x3 normal {n l y}} else {configure_entry .menu18.config.f.x3 disabled {y n l}}
+ global CONFIG_ATA_FIFO
+ if {($CONFIG_ATA_ENABLE == 1) && ($CONFIG_ATA_MWDMA == 1)} then {.menu18.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x4.l configure -state normal; } else {.menu18.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x4.l configure -state disabled}
+}
+
+
+proc update_define_menu18 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_ATA_ENABLE
+ global CONFIG_ATAIO
+ if {($CONFIG_ATA_ENABLE == 1)} then {validate_hex CONFIG_ATAIO "$CONFIG_ATAIO" A00}
+ global CONFIG_ATAIRQ
+ if {($CONFIG_ATA_ENABLE == 1)} then {validate_int CONFIG_ATAIRQ "$CONFIG_ATAIRQ" 10}
+ global CONFIG_ATA_MWDMA
+ if {($CONFIG_ATA_ENABLE == 1)} then {
+ set CONFIG_ATA_MWDMA [expr $CONFIG_ATA_MWDMA&15]} else {set CONFIG_ATA_MWDMA [expr $CONFIG_ATA_MWDMA|16]}
+ global CONFIG_ATA_FIFO
+ if {($CONFIG_ATA_ENABLE == 1) && ($CONFIG_ATA_MWDMA == 1)} then {validate_int CONFIG_ATA_FIFO "$CONFIG_ATA_FIFO" 8}
+}
+
+
+proc menu19 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 19}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 19]]
+ message $w.m -width 400 -aspect 300 -text \
+ "CAN " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "CAN "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 19; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu20 .menu20 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 19 0 "Enable multi-core CAN interface " CONFIG_CAN_ENABLE
+ int $w.config.f 19 1 "Number of CAN cores " CONFIG_CAN_NUM
+ hex $w.config.f 19 2 "CAN I/O area start address (haddr\[19:8\]) " CONFIG_CANIO
+ int $w.config.f 19 3 "Interrupt number " CONFIG_CANIRQ
+ bool $w.config.f 19 4 "Enable separate interrupts " CONFIG_CANSEPIRQ
+ bool $w.config.f 19 5 "Enable synchronous reset " CONFIG_CAN_SYNCRST
+ bool $w.config.f 19 6 "Enable FT FIFO memory " CONFIG_CAN_FT
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu19 {} {
+ global CONFIG_CAN_ENABLE
+ global CONFIG_CAN_NUM
+ if {($CONFIG_CAN_ENABLE == 1)} then {.menu19.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x1.l configure -state normal; } else {.menu19.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x1.l configure -state disabled}
+ global CONFIG_CANIO
+ if {($CONFIG_CAN_ENABLE == 1)} then {.menu19.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x2.l configure -state normal; } else {.menu19.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x2.l configure -state disabled}
+ global CONFIG_CANIRQ
+ if {($CONFIG_CAN_ENABLE == 1)} then {.menu19.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x3.l configure -state normal; } else {.menu19.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x3.l configure -state disabled}
+ global CONFIG_CANSEPIRQ
+ if {($CONFIG_CAN_ENABLE == 1)} then {
+ configure_entry .menu19.config.f.x4 normal {n l y}} else {configure_entry .menu19.config.f.x4 disabled {y n l}}
+ global CONFIG_CAN_SYNCRST
+ if {($CONFIG_CAN_ENABLE == 1)} then {
+ configure_entry .menu19.config.f.x5 normal {n l y}} else {configure_entry .menu19.config.f.x5 disabled {y n l}}
+ global CONFIG_CAN_FT
+ if {($CONFIG_CAN_ENABLE == 1)} then {
+ configure_entry .menu19.config.f.x6 normal {n l y}} else {configure_entry .menu19.config.f.x6 disabled {y n l}}
+}
+
+
+proc update_define_menu19 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_CAN_ENABLE
+ global CONFIG_CAN_NUM
+ if {($CONFIG_CAN_ENABLE == 1)} then {validate_int CONFIG_CAN_NUM "$CONFIG_CAN_NUM" 1}
+ global CONFIG_CANIO
+ if {($CONFIG_CAN_ENABLE == 1)} then {validate_hex CONFIG_CANIO "$CONFIG_CANIO" C00}
+ global CONFIG_CANIRQ
+ if {($CONFIG_CAN_ENABLE == 1)} then {validate_int CONFIG_CANIRQ "$CONFIG_CANIRQ" 13}
+ global CONFIG_CANSEPIRQ
+ if {($CONFIG_CAN_ENABLE == 1)} then {
+ set CONFIG_CANSEPIRQ [expr $CONFIG_CANSEPIRQ&15]} else {set CONFIG_CANSEPIRQ [expr $CONFIG_CANSEPIRQ|16]}
+ global CONFIG_CAN_SYNCRST
+ if {($CONFIG_CAN_ENABLE == 1)} then {
+ set CONFIG_CAN_SYNCRST [expr $CONFIG_CAN_SYNCRST&15]} else {set CONFIG_CAN_SYNCRST [expr $CONFIG_CAN_SYNCRST|16]}
+ global CONFIG_CAN_FT
+ if {($CONFIG_CAN_ENABLE == 1)} then {
+ set CONFIG_CAN_FT [expr $CONFIG_CAN_FT&15]} else {set CONFIG_CAN_FT [expr $CONFIG_CAN_FT|16]}
+}
+
+
+proc menu20 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 20}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 20]]
+ message $w.m -width 400 -aspect 300 -text \
+ "USB 2.0 Device Controller " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "USB 2.0 Device Controller "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 20; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu21 .menu21 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 20 0 "Gaisler Research USB 2.0 Device Controller " CONFIG_GRUSBDC_ENABLE
+ bool $w.config.f 20 1 "AHB Master Interface" CONFIG_GRUSBDC_AIFACE
+ global tmpvar_30
+ minimenu $w.config.f 20 2 "USB Transceiver Interface" tmpvar_30 CONFIG_GRUSBDC_ULPI
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"USB Transceiver Interface\""
+ $w.config.f.x2.x.menu add radiobutton -label "ULPI" -variable tmpvar_30 -value "ULPI" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "UTMI/UTMI+8-bit" -variable tmpvar_30 -value "UTMI/UTMI+8-bit" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "UTMI/UTMI+16-bit" -variable tmpvar_30 -value "UTMI/UTMI+16-bit" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 3
+ int $w.config.f 20 3 "Number of IN endpoints " CONFIG_GRUSBDC_NEPI
+ int $w.config.f 20 4 "Number of OUT endpoints" CONFIG_GRUSBDC_NEPO
+ int $w.config.f 20 5 "Buffer size for IN endpoint 0 " CONFIG_GRUSBDC_I0
+ int $w.config.f 20 6 "Buffer size for IN endpoint 1 " CONFIG_GRUSBDC_I1
+ int $w.config.f 20 7 "Buffer size for IN endpoint 2 " CONFIG_GRUSBDC_I2
+ int $w.config.f 20 8 "Buffer size for IN endpoint 3 " CONFIG_GRUSBDC_I3
+ int $w.config.f 20 9 "Buffer size for IN endpoint 4 " CONFIG_GRUSBDC_I4
+ int $w.config.f 20 10 "Buffer size for IN endpoint 5 " CONFIG_GRUSBDC_I5
+ int $w.config.f 20 11 "Buffer size for IN endpoint 6 " CONFIG_GRUSBDC_I6
+ int $w.config.f 20 12 "Buffer size for IN endpoint 7 " CONFIG_GRUSBDC_I7
+ int $w.config.f 20 13 "Buffer size for IN endpoint 8 " CONFIG_GRUSBDC_I8
+ int $w.config.f 20 14 "Buffer size for IN endpoint 9 " CONFIG_GRUSBDC_I9
+ int $w.config.f 20 15 "Buffer size for IN endpoint 10 " CONFIG_GRUSBDC_I10
+ int $w.config.f 20 16 "Buffer size for IN endpoint 11 " CONFIG_GRUSBDC_I11
+ int $w.config.f 20 17 "Buffer size for IN endpoint 12 " CONFIG_GRUSBDC_I12
+ int $w.config.f 20 18 "Buffer size for IN endpoint 13 " CONFIG_GRUSBDC_I13
+ int $w.config.f 20 19 "Buffer size for IN endpoint 14 " CONFIG_GRUSBDC_I14
+ int $w.config.f 20 20 "Buffer size for IN endpoint 15 " CONFIG_GRUSBDC_I15
+ int $w.config.f 20 21 "Buffer size for OUT endpoint 0" CONFIG_GRUSBDC_O0
+ int $w.config.f 20 22 "Buffer size for OUT endpoint 1" CONFIG_GRUSBDC_O1
+ int $w.config.f 20 23 "Buffer size for OUT endpoint 2" CONFIG_GRUSBDC_O2
+ int $w.config.f 20 24 "Buffer size for OUT endpoint 3" CONFIG_GRUSBDC_O3
+ int $w.config.f 20 25 "Buffer size for OUT endpoint 4" CONFIG_GRUSBDC_O4
+ int $w.config.f 20 26 "Buffer size for OUT endpoint 5" CONFIG_GRUSBDC_O5
+ int $w.config.f 20 27 "Buffer size for OUT endpoint 6" CONFIG_GRUSBDC_O6
+ int $w.config.f 20 28 "Buffer size for OUT endpoint 7" CONFIG_GRUSBDC_O7
+ int $w.config.f 20 29 "Buffer size for OUT endpoint 8" CONFIG_GRUSBDC_O8
+ int $w.config.f 20 30 "Buffer size for OUT endpoint 9" CONFIG_GRUSBDC_O9
+ int $w.config.f 20 31 "Buffer size for OUT endpoint 10" CONFIG_GRUSBDC_O10
+ int $w.config.f 20 32 "Buffer size for OUT endpoint 11" CONFIG_GRUSBDC_O11
+ int $w.config.f 20 33 "Buffer size for OUT endpoint 12" CONFIG_GRUSBDC_O12
+ int $w.config.f 20 34 "Buffer size for OUT endpoint 13" CONFIG_GRUSBDC_O13
+ int $w.config.f 20 35 "Buffer size for OUT endpoint 14" CONFIG_GRUSBDC_O14
+ int $w.config.f 20 36 "Buffer size for OUT endpoint 15" CONFIG_GRUSBDC_O15
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu20 {} {
+ global CONFIG_GRUSBDC_ENABLE
+ global CONFIG_GRUSBDC_AIFACE
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {
+ configure_entry .menu20.config.f.x1 normal {n l y}} else {configure_entry .menu20.config.f.x1 disabled {y n l}}
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {configure_entry .menu20.config.f.x2 normal {x l}} else {configure_entry .menu20.config.f.x2 disabled {x l}}
+ global CONFIG_GRUSBDC_NEPI
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x3.l configure -state normal; } else {.menu20.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x3.l configure -state disabled}
+ global CONFIG_GRUSBDC_NEPO
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x4.l configure -state normal; } else {.menu20.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x4.l configure -state disabled}
+ global CONFIG_GRUSBDC_I0
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x5.l configure -state normal; } else {.menu20.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x5.l configure -state disabled}
+ global CONFIG_GRUSBDC_I1
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x6.l configure -state normal; } else {.menu20.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x6.l configure -state disabled}
+ global CONFIG_GRUSBDC_I2
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x7.l configure -state normal; } else {.menu20.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x7.l configure -state disabled}
+ global CONFIG_GRUSBDC_I3
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x8.l configure -state normal; } else {.menu20.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x8.l configure -state disabled}
+ global CONFIG_GRUSBDC_I4
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x9.l configure -state normal; } else {.menu20.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x9.l configure -state disabled}
+ global CONFIG_GRUSBDC_I5
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x10.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x10.l configure -state normal; } else {.menu20.config.f.x10.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x10.l configure -state disabled}
+ global CONFIG_GRUSBDC_I6
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x11.l configure -state normal; } else {.menu20.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x11.l configure -state disabled}
+ global CONFIG_GRUSBDC_I7
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x12.l configure -state normal; } else {.menu20.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x12.l configure -state disabled}
+ global CONFIG_GRUSBDC_I8
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x13.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x13.l configure -state normal; } else {.menu20.config.f.x13.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x13.l configure -state disabled}
+ global CONFIG_GRUSBDC_I9
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x14.l configure -state normal; } else {.menu20.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x14.l configure -state disabled}
+ global CONFIG_GRUSBDC_I10
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x15.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x15.l configure -state normal; } else {.menu20.config.f.x15.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x15.l configure -state disabled}
+ global CONFIG_GRUSBDC_I11
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x16.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x16.l configure -state normal; } else {.menu20.config.f.x16.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x16.l configure -state disabled}
+ global CONFIG_GRUSBDC_I12
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x17.l configure -state normal; } else {.menu20.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x17.l configure -state disabled}
+ global CONFIG_GRUSBDC_I13
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x18.l configure -state normal; } else {.menu20.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x18.l configure -state disabled}
+ global CONFIG_GRUSBDC_I14
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x19.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x19.l configure -state normal; } else {.menu20.config.f.x19.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x19.l configure -state disabled}
+ global CONFIG_GRUSBDC_I15
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x20.l configure -state normal; } else {.menu20.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x20.l configure -state disabled}
+ global CONFIG_GRUSBDC_O0
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x21.l configure -state normal; } else {.menu20.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x21.l configure -state disabled}
+ global CONFIG_GRUSBDC_O1
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x22.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x22.l configure -state normal; } else {.menu20.config.f.x22.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x22.l configure -state disabled}
+ global CONFIG_GRUSBDC_O2
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x23.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x23.l configure -state normal; } else {.menu20.config.f.x23.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x23.l configure -state disabled}
+ global CONFIG_GRUSBDC_O3
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x24.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x24.l configure -state normal; } else {.menu20.config.f.x24.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x24.l configure -state disabled}
+ global CONFIG_GRUSBDC_O4
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x25.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x25.l configure -state normal; } else {.menu20.config.f.x25.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x25.l configure -state disabled}
+ global CONFIG_GRUSBDC_O5
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x26.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x26.l configure -state normal; } else {.menu20.config.f.x26.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x26.l configure -state disabled}
+ global CONFIG_GRUSBDC_O6
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x27.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x27.l configure -state normal; } else {.menu20.config.f.x27.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x27.l configure -state disabled}
+ global CONFIG_GRUSBDC_O7
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x28.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x28.l configure -state normal; } else {.menu20.config.f.x28.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x28.l configure -state disabled}
+ global CONFIG_GRUSBDC_O8
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x29.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x29.l configure -state normal; } else {.menu20.config.f.x29.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x29.l configure -state disabled}
+ global CONFIG_GRUSBDC_O9
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x30.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x30.l configure -state normal; } else {.menu20.config.f.x30.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x30.l configure -state disabled}
+ global CONFIG_GRUSBDC_O10
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x31.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x31.l configure -state normal; } else {.menu20.config.f.x31.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x31.l configure -state disabled}
+ global CONFIG_GRUSBDC_O11
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x32.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x32.l configure -state normal; } else {.menu20.config.f.x32.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x32.l configure -state disabled}
+ global CONFIG_GRUSBDC_O12
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x33.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x33.l configure -state normal; } else {.menu20.config.f.x33.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x33.l configure -state disabled}
+ global CONFIG_GRUSBDC_O13
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x34.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x34.l configure -state normal; } else {.menu20.config.f.x34.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x34.l configure -state disabled}
+ global CONFIG_GRUSBDC_O14
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x35.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x35.l configure -state normal; } else {.menu20.config.f.x35.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x35.l configure -state disabled}
+ global CONFIG_GRUSBDC_O15
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {.menu20.config.f.x36.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x36.l configure -state normal; } else {.menu20.config.f.x36.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x36.l configure -state disabled}
+}
+
+
+proc update_define_menu20 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_GRUSBDC_ENABLE
+ global CONFIG_GRUSBDC_AIFACE
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {
+ set CONFIG_GRUSBDC_AIFACE [expr $CONFIG_GRUSBDC_AIFACE&15]} else {set CONFIG_GRUSBDC_AIFACE [expr $CONFIG_GRUSBDC_AIFACE|16]}
+ global tmpvar_30
+ global CONFIG_GRUSBDC_ULPI
+ if {$tmpvar_30 == "ULPI"} then {set CONFIG_GRUSBDC_ULPI 1} else {set CONFIG_GRUSBDC_ULPI 0}
+ global CONFIG_GRUSBDC_UTMI8
+ if {$tmpvar_30 == "UTMI/UTMI+8-bit"} then {set CONFIG_GRUSBDC_UTMI8 1} else {set CONFIG_GRUSBDC_UTMI8 0}
+ global CONFIG_GRUSBDC_UTMI16
+ if {$tmpvar_30 == "UTMI/UTMI+16-bit"} then {set CONFIG_GRUSBDC_UTMI16 1} else {set CONFIG_GRUSBDC_UTMI16 0}
+ global CONFIG_GRUSBDC_NEPI
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_NEPI "$CONFIG_GRUSBDC_NEPI" 1}
+ global CONFIG_GRUSBDC_NEPO
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_NEPO "$CONFIG_GRUSBDC_NEPO" 1}
+ global CONFIG_GRUSBDC_I0
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I0 "$CONFIG_GRUSBDC_I0" 1024}
+ global CONFIG_GRUSBDC_I1
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I1 "$CONFIG_GRUSBDC_I1" 1024}
+ global CONFIG_GRUSBDC_I2
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I2 "$CONFIG_GRUSBDC_I2" 1024}
+ global CONFIG_GRUSBDC_I3
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I3 "$CONFIG_GRUSBDC_I3" 1024}
+ global CONFIG_GRUSBDC_I4
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I4 "$CONFIG_GRUSBDC_I4" 1024}
+ global CONFIG_GRUSBDC_I5
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I5 "$CONFIG_GRUSBDC_I5" 1024}
+ global CONFIG_GRUSBDC_I6
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I6 "$CONFIG_GRUSBDC_I6" 1024}
+ global CONFIG_GRUSBDC_I7
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I7 "$CONFIG_GRUSBDC_I7" 1024}
+ global CONFIG_GRUSBDC_I8
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I8 "$CONFIG_GRUSBDC_I8" 1024}
+ global CONFIG_GRUSBDC_I9
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I9 "$CONFIG_GRUSBDC_I9" 1024}
+ global CONFIG_GRUSBDC_I10
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I10 "$CONFIG_GRUSBDC_I10" 1024}
+ global CONFIG_GRUSBDC_I11
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I11 "$CONFIG_GRUSBDC_I11" 1024}
+ global CONFIG_GRUSBDC_I12
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I12 "$CONFIG_GRUSBDC_I12" 1024}
+ global CONFIG_GRUSBDC_I13
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I13 "$CONFIG_GRUSBDC_I13" 1024}
+ global CONFIG_GRUSBDC_I14
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I14 "$CONFIG_GRUSBDC_I14" 1024}
+ global CONFIG_GRUSBDC_I15
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_I15 "$CONFIG_GRUSBDC_I15" 1024}
+ global CONFIG_GRUSBDC_O0
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O0 "$CONFIG_GRUSBDC_O0" 1024}
+ global CONFIG_GRUSBDC_O1
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O1 "$CONFIG_GRUSBDC_O1" 1024}
+ global CONFIG_GRUSBDC_O2
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O2 "$CONFIG_GRUSBDC_O2" 1024}
+ global CONFIG_GRUSBDC_O3
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O3 "$CONFIG_GRUSBDC_O3" 1024}
+ global CONFIG_GRUSBDC_O4
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O4 "$CONFIG_GRUSBDC_O4" 1024}
+ global CONFIG_GRUSBDC_O5
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O5 "$CONFIG_GRUSBDC_O5" 1024}
+ global CONFIG_GRUSBDC_O6
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O6 "$CONFIG_GRUSBDC_O6" 1024}
+ global CONFIG_GRUSBDC_O7
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O7 "$CONFIG_GRUSBDC_O7" 1024}
+ global CONFIG_GRUSBDC_O8
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O8 "$CONFIG_GRUSBDC_O8" 1024}
+ global CONFIG_GRUSBDC_O9
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O9 "$CONFIG_GRUSBDC_O9" 1024}
+ global CONFIG_GRUSBDC_O10
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O10 "$CONFIG_GRUSBDC_O10" 1024}
+ global CONFIG_GRUSBDC_O11
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O11 "$CONFIG_GRUSBDC_O11" 1024}
+ global CONFIG_GRUSBDC_O12
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O12 "$CONFIG_GRUSBDC_O12" 1024}
+ global CONFIG_GRUSBDC_O13
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O13 "$CONFIG_GRUSBDC_O13" 1024}
+ global CONFIG_GRUSBDC_O14
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O14 "$CONFIG_GRUSBDC_O14" 1024}
+ global CONFIG_GRUSBDC_O15
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {validate_int CONFIG_GRUSBDC_O15 "$CONFIG_GRUSBDC_O15" 1024}
+}
+
+
+proc menu21 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 21}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 21]]
+ message $w.m -width 400 -aspect 300 -text \
+ "UART, timer, I/O port and interrupt controller" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "UART, timer, I/O port and interrupt controller"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 21; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu22 .menu22 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 21 0 "Enable console UART " CONFIG_UART1_ENABLE
+ global tmpvar_31
+ minimenu $w.config.f 21 1 "UART1 FIFO depth" tmpvar_31 CONFIG_UA1_FIFO1
+ menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"UART1 FIFO depth\""
+ $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_31 -value "1" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_31 -value "2" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_31 -value "4" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_31 -value "8" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_31 -value "16" -command "update_active"
+ $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_31 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x1.x.menu 6
+ bool $w.config.f 21 2 "Enable secondary UART " CONFIG_UART2_ENABLE
+ global tmpvar_32
+ minimenu $w.config.f 21 3 "UART2 FIFO depth" tmpvar_32 CONFIG_UA2_FIFO1
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"UART2 FIFO depth\""
+ $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_32 -value "1" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_32 -value "2" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_32 -value "4" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_32 -value "8" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_32 -value "16" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_32 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 6
+ bool $w.config.f 21 4 "Enable LEON3 interrupt controller " CONFIG_IRQ3_ENABLE
+ bool $w.config.f 21 5 "Enable secondary interrupts " CONFIG_IRQ3_SEC
+ int $w.config.f 21 6 "Secondary interrupt number (1 - 15) " CONFIG_IRQ3_NSEC
+ bool $w.config.f 21 7 "Enable Timer Unit " CONFIG_GPT_ENABLE
+ int $w.config.f 21 8 "Number of timers (1 - 7) " CONFIG_GPT_NTIM
+ int $w.config.f 21 9 "Scaler width (2 - 16) " CONFIG_GPT_SW
+ int $w.config.f 21 10 "Timer width (2 - 32) " CONFIG_GPT_TW
+ int $w.config.f 21 11 "Timer unit interrupt " CONFIG_GPT_IRQ
+ bool $w.config.f 21 12 "Separate interrupts " CONFIG_GPT_SEPIRQ
+ bool $w.config.f 21 13 "Watchdog enable " CONFIG_GPT_WDOGEN
+ hex $w.config.f 21 14 "Initial watchdog time-out value " CONFIG_GPT_WDOG
+ bool $w.config.f 21 15 "Enable generic GPIO port " CONFIG_GRGPIO_ENABLE
+ int $w.config.f 21 16 "GPIO width " CONFIG_GRGPIO_WIDTH
+ hex $w.config.f 21 17 "GPIO interrupt mask " CONFIG_GRGPIO_IMASK
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu21 {} {
+ global CONFIG_UART1_ENABLE
+ if {($CONFIG_UART1_ENABLE == 1)} then {configure_entry .menu21.config.f.x1 normal {x l}} else {configure_entry .menu21.config.f.x1 disabled {x l}}
+ global CONFIG_DSU_UART
+ global CONFIG_UART2_ENABLE
+ if {($CONFIG_DSU_UART != 1)} then {
+ configure_entry .menu21.config.f.x2 normal {n l y}} else {configure_entry .menu21.config.f.x2 disabled {y n l}}
+ if {($CONFIG_DSU_UART != 1) && ($CONFIG_UART2_ENABLE == 1)} then {configure_entry .menu21.config.f.x3 normal {x l}} else {configure_entry .menu21.config.f.x3 disabled {x l}}
+ global CONFIG_IRQ3_ENABLE
+ global CONFIG_IRQ3_SEC
+ if {($CONFIG_IRQ3_ENABLE == 1)} then {
+ configure_entry .menu21.config.f.x5 normal {n l y}} else {configure_entry .menu21.config.f.x5 disabled {y n l}}
+ global CONFIG_IRQ3_NSEC
+ if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {.menu21.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x6.l configure -state normal; } else {.menu21.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x6.l configure -state disabled}
+ global CONFIG_GPT_ENABLE
+ global CONFIG_GPT_NTIM
+ if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x8.l configure -state normal; } else {.menu21.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x8.l configure -state disabled}
+ global CONFIG_GPT_SW
+ if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x9.l configure -state normal; } else {.menu21.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x9.l configure -state disabled}
+ global CONFIG_GPT_TW
+ if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x10.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x10.l configure -state normal; } else {.menu21.config.f.x10.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x10.l configure -state disabled}
+ global CONFIG_GPT_IRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x11.l configure -state normal; } else {.menu21.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x11.l configure -state disabled}
+ global CONFIG_GPT_SEPIRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {
+ configure_entry .menu21.config.f.x12 normal {n l y}} else {configure_entry .menu21.config.f.x12 disabled {y n l}}
+ global CONFIG_GPT_WDOGEN
+ if {($CONFIG_GPT_ENABLE == 1)} then {
+ configure_entry .menu21.config.f.x13 normal {n l y}} else {configure_entry .menu21.config.f.x13 disabled {y n l}}
+ global CONFIG_GPT_WDOG
+ if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {.menu21.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x14.l configure -state normal; } else {.menu21.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x14.l configure -state disabled}
+ global CONFIG_GRGPIO_ENABLE
+ global CONFIG_GRGPIO_WIDTH
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu21.config.f.x16.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x16.l configure -state normal; } else {.menu21.config.f.x16.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x16.l configure -state disabled}
+ global CONFIG_GRGPIO_IMASK
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu21.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x17.l configure -state normal; } else {.menu21.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x17.l configure -state disabled}
+}
+
+
+proc update_define_menu21 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global tmpvar_31
+ global CONFIG_UA1_FIFO1
+ if {$tmpvar_31 == "1"} then {set CONFIG_UA1_FIFO1 1} else {set CONFIG_UA1_FIFO1 0}
+ global CONFIG_UA1_FIFO2
+ if {$tmpvar_31 == "2"} then {set CONFIG_UA1_FIFO2 1} else {set CONFIG_UA1_FIFO2 0}
+ global CONFIG_UA1_FIFO4
+ if {$tmpvar_31 == "4"} then {set CONFIG_UA1_FIFO4 1} else {set CONFIG_UA1_FIFO4 0}
+ global CONFIG_UA1_FIFO8
+ if {$tmpvar_31 == "8"} then {set CONFIG_UA1_FIFO8 1} else {set CONFIG_UA1_FIFO8 0}
+ global CONFIG_UA1_FIFO16
+ if {$tmpvar_31 == "16"} then {set CONFIG_UA1_FIFO16 1} else {set CONFIG_UA1_FIFO16 0}
+ global CONFIG_UA1_FIFO32
+ if {$tmpvar_31 == "32"} then {set CONFIG_UA1_FIFO32 1} else {set CONFIG_UA1_FIFO32 0}
+ global CONFIG_DSU_UART
+ global CONFIG_UART2_ENABLE
+ if {($CONFIG_DSU_UART != 1)} then {
+ set CONFIG_UART2_ENABLE [expr $CONFIG_UART2_ENABLE&15]} else {set CONFIG_UART2_ENABLE [expr $CONFIG_UART2_ENABLE|16]}
+ global tmpvar_32
+ global CONFIG_UA2_FIFO1
+ if {$tmpvar_32 == "1"} then {set CONFIG_UA2_FIFO1 1} else {set CONFIG_UA2_FIFO1 0}
+ global CONFIG_UA2_FIFO2
+ if {$tmpvar_32 == "2"} then {set CONFIG_UA2_FIFO2 1} else {set CONFIG_UA2_FIFO2 0}
+ global CONFIG_UA2_FIFO4
+ if {$tmpvar_32 == "4"} then {set CONFIG_UA2_FIFO4 1} else {set CONFIG_UA2_FIFO4 0}
+ global CONFIG_UA2_FIFO8
+ if {$tmpvar_32 == "8"} then {set CONFIG_UA2_FIFO8 1} else {set CONFIG_UA2_FIFO8 0}
+ global CONFIG_UA2_FIFO16
+ if {$tmpvar_32 == "16"} then {set CONFIG_UA2_FIFO16 1} else {set CONFIG_UA2_FIFO16 0}
+ global CONFIG_UA2_FIFO32
+ if {$tmpvar_32 == "32"} then {set CONFIG_UA2_FIFO32 1} else {set CONFIG_UA2_FIFO32 0}
+ global CONFIG_IRQ3_ENABLE
+ global CONFIG_IRQ3_SEC
+ if {($CONFIG_IRQ3_ENABLE == 1)} then {
+ set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC&15]} else {set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC|16]}
+ global CONFIG_IRQ3_NSEC
+ if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {validate_int CONFIG_IRQ3_NSEC "$CONFIG_IRQ3_NSEC" 12}
+ global CONFIG_GPT_ENABLE
+ global CONFIG_GPT_NTIM
+ if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_NTIM "$CONFIG_GPT_NTIM" 2}
+ global CONFIG_GPT_SW
+ if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_SW "$CONFIG_GPT_SW" 8}
+ global CONFIG_GPT_TW
+ if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_TW "$CONFIG_GPT_TW" 32}
+ global CONFIG_GPT_IRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_IRQ "$CONFIG_GPT_IRQ" 8}
+ global CONFIG_GPT_SEPIRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {
+ set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ&15]} else {set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ|16]}
+ global CONFIG_GPT_WDOGEN
+ if {($CONFIG_GPT_ENABLE == 1)} then {
+ set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN&15]} else {set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN|16]}
+ global CONFIG_GPT_WDOG
+ if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {validate_hex CONFIG_GPT_WDOG "$CONFIG_GPT_WDOG" FFFF}
+ global CONFIG_GRGPIO_ENABLE
+ global CONFIG_GRGPIO_WIDTH
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_int CONFIG_GRGPIO_WIDTH "$CONFIG_GRGPIO_WIDTH" 8}
+ global CONFIG_GRGPIO_IMASK
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_hex CONFIG_GRGPIO_IMASK "$CONFIG_GRGPIO_IMASK" 0000}
+}
+
+
+proc menu22 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 22}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 22]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Spacewire " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Spacewire "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 22; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu23 .menu23 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 22 0 "Enable Spacewire links " CONFIG_SPW_ENABLE
+ int $w.config.f 22 1 "Number of links (1 - 3)" CONFIG_SPW_NUM
+ global tmpvar_33
+ minimenu $w.config.f 22 2 "AHB RX/TX FIFO size (32-bit words) " tmpvar_33 CONFIG_SPW_AHBFIFO4
+ menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB RX/TX FIFO size (32-bit words) \""
+ $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_33 -value "4" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_33 -value "8" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_33 -value "16" -command "update_active"
+ $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_33 -value "32" -command "update_active"
+ menusplit $w $w.config.f.x2.x.menu 4
+ global tmpvar_34
+ minimenu $w.config.f 22 3 "Receiver FIFO size (bytes) " tmpvar_34 CONFIG_SPW_RXFIFO16
+ menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Receiver FIFO size (bytes) \""
+ $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_34 -value "16" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_34 -value "32" -command "update_active"
+ $w.config.f.x3.x.menu add radiobutton -label "64" -variable tmpvar_34 -value "64" -command "update_active"
+ menusplit $w $w.config.f.x3.x.menu 3
+ bool $w.config.f 22 4 "Enable RMAP protocol " CONFIG_SPW_RMAP
+ global tmpvar_35
+ minimenu $w.config.f 22 5 "RMAP buffer size (bytes) " tmpvar_35 CONFIG_SPW_RMAPBUF2
+ menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"RMAP buffer size (bytes) \""
+ $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_35 -value "64" -command "update_active"
+ $w.config.f.x5.x.menu add radiobutton -label "128" -variable tmpvar_35 -value "128" -command "update_active"
+ $w.config.f.x5.x.menu add radiobutton -label "192" -variable tmpvar_35 -value "192" -command "update_active"
+ $w.config.f.x5.x.menu add radiobutton -label "256" -variable tmpvar_35 -value "256" -command "update_active"
+ menusplit $w $w.config.f.x5.x.menu 4
+ bool $w.config.f 22 6 "Enable RMAP CRC check " CONFIG_SPW_RMAPCRC
+ bool $w.config.f 22 7 "Enable Rx unaligned transfers " CONFIG_SPW_RXUNAL
+ bool $w.config.f 22 8 "Spacewire FIFO protection " CONFIG_SPW_FT
+ bool $w.config.f 22 9 "Use GRSPWC netlist " CONFIG_SPW_NETLIST
+ int $w.config.f 22 10 "Number of ports (1 - 2)" CONFIG_SPW_PORTS
+ global tmpvar_36
+ minimenu $w.config.f 22 11 "Select GRSPW core (GRSPW1/GRSPW2) " tmpvar_36 CONFIG_SPW_GRSPW1
+ menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Select GRSPW core (GRSPW1/GRSPW2) \""
+ $w.config.f.x11.x.menu add radiobutton -label "1" -variable tmpvar_36 -value "1" -command "update_active"
+ $w.config.f.x11.x.menu add radiobutton -label "2" -variable tmpvar_36 -value "2" -command "update_active"
+ menusplit $w $w.config.f.x11.x.menu 2
+ int $w.config.f 22 12 "Number of DMA channels (1 - 4)" CONFIG_SPW_DMACHAN
+ bool $w.config.f 22 13 "Receiver and transmitter uses same clock " CONFIG_SPW_RTSAME
+ global tmpvar_37
+ minimenu $w.config.f 22 14 "Select receiver clock type " tmpvar_37 CONFIG_SPW_RX_SDR
+ menu $w.config.f.x14.x.menu -tearoffcommand "menutitle \"Select receiver clock type \""
+ $w.config.f.x14.x.menu add radiobutton -label "SDR" -variable tmpvar_37 -value "SDR" -command "update_active"
+ $w.config.f.x14.x.menu add radiobutton -label "DDR" -variable tmpvar_37 -value "DDR" -command "update_active"
+ $w.config.f.x14.x.menu add radiobutton -label "Xor" -variable tmpvar_37 -value "Xor" -command "update_active"
+ $w.config.f.x14.x.menu add radiobutton -label "Aeroflex" -variable tmpvar_37 -value "Aeroflex" -command "update_active"
+ menusplit $w $w.config.f.x14.x.menu 4
+ global tmpvar_38
+ minimenu $w.config.f 22 15 "Select transmitter clock type " tmpvar_38 CONFIG_SPW_TX_SDR
+ menu $w.config.f.x15.x.menu -tearoffcommand "menutitle \"Select transmitter clock type \""
+ $w.config.f.x15.x.menu add radiobutton -label "SDR" -variable tmpvar_38 -value "SDR" -command "update_active"
+ $w.config.f.x15.x.menu add radiobutton -label "DDR" -variable tmpvar_38 -value "DDR" -command "update_active"
+ $w.config.f.x15.x.menu add radiobutton -label "Aeroflex" -variable tmpvar_38 -value "Aeroflex" -command "update_active"
+ menusplit $w $w.config.f.x15.x.menu 3
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu22 {} {
+ global CONFIG_SPW_ENABLE
+ global CONFIG_SPW_NUM
+ if {($CONFIG_SPW_ENABLE == 1)} then {.menu22.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x1.l configure -state normal; } else {.menu22.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x1.l configure -state disabled}
+ if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x2 normal {x l}} else {configure_entry .menu22.config.f.x2 disabled {x l}}
+ if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x3 normal {x l}} else {configure_entry .menu22.config.f.x3 disabled {x l}}
+ global CONFIG_SPW_RMAP
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ configure_entry .menu22.config.f.x4 normal {n l y}} else {configure_entry .menu22.config.f.x4 disabled {y n l}}
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_RMAP == 1)} then {configure_entry .menu22.config.f.x5 normal {x l}} else {configure_entry .menu22.config.f.x5 disabled {x l}}
+ global CONFIG_SPW_RMAPCRC
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ configure_entry .menu22.config.f.x6 normal {n l y}} else {configure_entry .menu22.config.f.x6 disabled {y n l}}
+ global CONFIG_SPW_RXUNAL
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ configure_entry .menu22.config.f.x7 normal {n l y}} else {configure_entry .menu22.config.f.x7 disabled {y n l}}
+ global CONFIG_SPW_FT
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ configure_entry .menu22.config.f.x8 normal {n l y}} else {configure_entry .menu22.config.f.x8 disabled {y n l}}
+ global CONFIG_SPW_NETLIST
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ configure_entry .menu22.config.f.x9 normal {n l y}} else {configure_entry .menu22.config.f.x9 disabled {y n l}}
+ global CONFIG_SPW_PORTS
+ if {($CONFIG_SPW_ENABLE == 1)} then {.menu22.config.f.x10.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x10.l configure -state normal; } else {.menu22.config.f.x10.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x10.l configure -state disabled}
+ if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x11 normal {x l}} else {configure_entry .menu22.config.f.x11 disabled {x l}}
+ global CONFIG_SPW_GRSPW2
+ global CONFIG_SPW_DMACHAN
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {.menu22.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x12.l configure -state normal; } else {.menu22.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x12.l configure -state disabled}
+ global CONFIG_SPW_RTSAME
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {
+ configure_entry .menu22.config.f.x13 normal {n l y}} else {configure_entry .menu22.config.f.x13 disabled {y n l}}
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {configure_entry .menu22.config.f.x14 normal {x l}} else {configure_entry .menu22.config.f.x14 disabled {x l}}
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {configure_entry .menu22.config.f.x15 normal {x l}} else {configure_entry .menu22.config.f.x15 disabled {x l}}
+}
+
+
+proc update_define_menu22 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_SPW_ENABLE
+ global CONFIG_SPW_NUM
+ if {($CONFIG_SPW_ENABLE == 1)} then {validate_int CONFIG_SPW_NUM "$CONFIG_SPW_NUM" 1}
+ global tmpvar_33
+ global CONFIG_SPW_AHBFIFO4
+ if {$tmpvar_33 == "4"} then {set CONFIG_SPW_AHBFIFO4 1} else {set CONFIG_SPW_AHBFIFO4 0}
+ global CONFIG_SPW_AHBFIFO8
+ if {$tmpvar_33 == "8"} then {set CONFIG_SPW_AHBFIFO8 1} else {set CONFIG_SPW_AHBFIFO8 0}
+ global CONFIG_SPW_AHBFIFO16
+ if {$tmpvar_33 == "16"} then {set CONFIG_SPW_AHBFIFO16 1} else {set CONFIG_SPW_AHBFIFO16 0}
+ global CONFIG_SPW_AHBFIFO32
+ if {$tmpvar_33 == "32"} then {set CONFIG_SPW_AHBFIFO32 1} else {set CONFIG_SPW_AHBFIFO32 0}
+ global tmpvar_34
+ global CONFIG_SPW_RXFIFO16
+ if {$tmpvar_34 == "16"} then {set CONFIG_SPW_RXFIFO16 1} else {set CONFIG_SPW_RXFIFO16 0}
+ global CONFIG_SPW_RXFIFO32
+ if {$tmpvar_34 == "32"} then {set CONFIG_SPW_RXFIFO32 1} else {set CONFIG_SPW_RXFIFO32 0}
+ global CONFIG_SPW_RXFIFO64
+ if {$tmpvar_34 == "64"} then {set CONFIG_SPW_RXFIFO64 1} else {set CONFIG_SPW_RXFIFO64 0}
+ global CONFIG_SPW_RMAP
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ set CONFIG_SPW_RMAP [expr $CONFIG_SPW_RMAP&15]} else {set CONFIG_SPW_RMAP [expr $CONFIG_SPW_RMAP|16]}
+ global tmpvar_35
+ global CONFIG_SPW_RMAPBUF2
+ if {$tmpvar_35 == "64"} then {set CONFIG_SPW_RMAPBUF2 1} else {set CONFIG_SPW_RMAPBUF2 0}
+ global CONFIG_SPW_RMAPBUF4
+ if {$tmpvar_35 == "128"} then {set CONFIG_SPW_RMAPBUF4 1} else {set CONFIG_SPW_RMAPBUF4 0}
+ global CONFIG_SPW_RMAPBUF6
+ if {$tmpvar_35 == "192"} then {set CONFIG_SPW_RMAPBUF6 1} else {set CONFIG_SPW_RMAPBUF6 0}
+ global CONFIG_SPW_RMAPBUF8
+ if {$tmpvar_35 == "256"} then {set CONFIG_SPW_RMAPBUF8 1} else {set CONFIG_SPW_RMAPBUF8 0}
+ global CONFIG_SPW_RMAPCRC
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ set CONFIG_SPW_RMAPCRC [expr $CONFIG_SPW_RMAPCRC&15]} else {set CONFIG_SPW_RMAPCRC [expr $CONFIG_SPW_RMAPCRC|16]}
+ global CONFIG_SPW_RXUNAL
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ set CONFIG_SPW_RXUNAL [expr $CONFIG_SPW_RXUNAL&15]} else {set CONFIG_SPW_RXUNAL [expr $CONFIG_SPW_RXUNAL|16]}
+ global CONFIG_SPW_FT
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ set CONFIG_SPW_FT [expr $CONFIG_SPW_FT&15]} else {set CONFIG_SPW_FT [expr $CONFIG_SPW_FT|16]}
+ global CONFIG_SPW_NETLIST
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ set CONFIG_SPW_NETLIST [expr $CONFIG_SPW_NETLIST&15]} else {set CONFIG_SPW_NETLIST [expr $CONFIG_SPW_NETLIST|16]}
+ global CONFIG_SPW_PORTS
+ if {($CONFIG_SPW_ENABLE == 1)} then {validate_int CONFIG_SPW_PORTS "$CONFIG_SPW_PORTS" 1}
+ global tmpvar_36
+ global CONFIG_SPW_GRSPW1
+ if {$tmpvar_36 == "1"} then {set CONFIG_SPW_GRSPW1 1} else {set CONFIG_SPW_GRSPW1 0}
+ global CONFIG_SPW_GRSPW2
+ if {$tmpvar_36 == "2"} then {set CONFIG_SPW_GRSPW2 1} else {set CONFIG_SPW_GRSPW2 0}
+ global CONFIG_SPW_DMACHAN
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {validate_int CONFIG_SPW_DMACHAN "$CONFIG_SPW_DMACHAN" 1}
+ global CONFIG_SPW_RTSAME
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {
+ set CONFIG_SPW_RTSAME [expr $CONFIG_SPW_RTSAME&15]} else {set CONFIG_SPW_RTSAME [expr $CONFIG_SPW_RTSAME|16]}
+ global tmpvar_37
+ global CONFIG_SPW_RX_SDR
+ if {$tmpvar_37 == "SDR"} then {set CONFIG_SPW_RX_SDR 1} else {set CONFIG_SPW_RX_SDR 0}
+ global CONFIG_SPW_RX_DDR
+ if {$tmpvar_37 == "DDR"} then {set CONFIG_SPW_RX_DDR 1} else {set CONFIG_SPW_RX_DDR 0}
+ global CONFIG_SPW_RX_XOR
+ if {$tmpvar_37 == "Xor"} then {set CONFIG_SPW_RX_XOR 1} else {set CONFIG_SPW_RX_XOR 0}
+ global CONFIG_SPW_RX_AFLEX
+ if {$tmpvar_37 == "Aeroflex"} then {set CONFIG_SPW_RX_AFLEX 1} else {set CONFIG_SPW_RX_AFLEX 0}
+ global tmpvar_38
+ global CONFIG_SPW_TX_SDR
+ if {$tmpvar_38 == "SDR"} then {set CONFIG_SPW_TX_SDR 1} else {set CONFIG_SPW_TX_SDR 0}
+ global CONFIG_SPW_TX_DDR
+ if {$tmpvar_38 == "DDR"} then {set CONFIG_SPW_TX_DDR 1} else {set CONFIG_SPW_TX_DDR 0}
+ global CONFIG_SPW_TX_AFLEX
+ if {$tmpvar_38 == "Aeroflex"} then {set CONFIG_SPW_TX_AFLEX 1} else {set CONFIG_SPW_TX_AFLEX 0}
+}
+
+
+proc menu23 {w title} {
+ set oldFocus [focus]
+ catch {focus .menu13}
+ catch {destroy $w; unregister_active 23}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 23]]
+ message $w.m -width 400 -aspect 300 -text \
+ "Keybord and VGA interface" -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "Keybord and VGA interface"
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 23; break"
+ set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 23; catch {destroy .menu13}; unregister_active 13; menu24 .menu24 \"$title\""
+ frame $w.f
+ button $w.f.back -text "OK" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ bind all <Alt-n> $nextscript
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 23 0 "Keyboard/mouse (PS2) interface " CONFIG_KBD_ENABLE
+ bool $w.config.f 23 1 "Text-based VGA interface " CONFIG_VGA_ENABLE
+ bool $w.config.f 23 2 "SVGA graphical frame buffer " CONFIG_SVGA_ENABLE
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "}
+ set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu23 {} {
+ global CONFIG_VGA_ENABLE
+ global CONFIG_SVGA_ENABLE
+ if {($CONFIG_VGA_ENABLE == 0)} then {
+ configure_entry .menu23.config.f.x2 normal {n l y}} else {configure_entry .menu23.config.f.x2 disabled {y n l}}
+}
+
+
+proc update_define_menu23 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+ global CONFIG_VGA_ENABLE
+ global CONFIG_SVGA_ENABLE
+ if {($CONFIG_VGA_ENABLE == 0)} then {
+ set CONFIG_SVGA_ENABLE [expr $CONFIG_SVGA_ENABLE&15]} else {set CONFIG_SVGA_ENABLE [expr $CONFIG_SVGA_ENABLE|16]}
+}
+
+
+menu_option menu24 24 "VHDL Debugging "
+proc menu24 {w title} {
+ set oldFocus [focus]
+ catch {destroy $w; unregister_active 24}
+ toplevel $w -class Dialog
+ wm withdraw $w
+ global active_menus
+ set active_menus [lsort -integer [linsert $active_menus end 24]]
+ message $w.m -width 400 -aspect 300 -text \
+ "VHDL Debugging " -relief raised
+ pack $w.m -pady 10 -side top -padx 10
+ wm title $w "VHDL Debugging "
+
+ bind $w <Escape> "catch {focus $oldFocus}; destroy $w; unregister_active 24; break"
+ set nextscript "catch {focus $oldFocus}; menu25 .menu25 \"$title\""
+ frame $w.f
+ button $w.f.back -text "Main Menu" \
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24"
+ button $w.f.next -text "Next" -underline 0\
+ -width 15 -command $nextscript
+ $w.f.next configure -state disabled
+ bind all <Alt-n> "puts \"no more menus\" "
+ button $w.f.prev -text "Prev" -underline 0\
+ -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\""
+ bind $w <Alt-p> "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\";break"
+ pack $w.f.back $w.f.next $w.f.prev -side left -expand on
+ pack $w.f -pady 10 -side bottom -anchor w -fill x
+ frame $w.topline -relief ridge -borderwidth 2 -height 2
+ pack $w.topline -side top -fill x
+
+ frame $w.botline -relief ridge -borderwidth 2 -height 2
+ pack $w.botline -side bottom -fill x
+
+ frame $w.config
+ pack $w.config -fill y -expand on
+
+ scrollbar $w.config.vscroll -command "$w.config.canvas yview"
+ pack $w.config.vscroll -side right -fill y
+
+ canvas $w.config.canvas -height 1\
+ -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \
+ -width [expr [winfo screenwidth .] * 1 / 2]
+ frame $w.config.f
+ bind $w <Key-Down> "$w.config.canvas yview scroll 1 unit;break;"
+ bind $w <Key-Up> "$w.config.canvas yview scroll -1 unit;break;"
+ bind $w <Key-Next> "$w.config.canvas yview scroll 1 page;break;"
+ bind $w <Key-Prior> "$w.config.canvas yview scroll -1 page;break;"
+ bind $w <Key-Home> "$w.config.canvas yview moveto 0;break;"
+ bind $w <Key-End> "$w.config.canvas yview moveto 1 ;break;"
+ pack $w.config.canvas -side right -fill y
+
+
+ bool $w.config.f 24 0 "Accelerated UART tracing " CONFIG_DEBUG_UART
+
+
+
+ focus $w
+ update_active
+ global winx; global winy
+ set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
+ if {[winfo exists $w]} then {wm geometry $w +$winx+$winy}
+ update idletasks
+ if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f
+
+ $w.config.canvas configure \
+ -width [expr [winfo reqwidth $w.config.f] + 1]\
+ -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \
+ [expr [winfo reqheight $w.config.f] + 1]"
+
+ set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]]
+ set scry [expr [winfo screenh $w] / 2]
+ set maxy [expr [winfo screenh $w] * 3 / 4]
+ set canvtotal [expr [winfo reqh $w.config.f] + 2]
+ if [expr $winy + $canvtotal < $maxy] {
+ $w.config.canvas configure -height $canvtotal
+ } else {
+ $w.config.canvas configure -height [expr $scry - $winy]
+ }
+ }
+ update idletasks
+ if {[winfo exists $w]} then {
+ wm maxsize $w [winfo width $w] [winfo screenheight $w]
+ wm minsize $w [winfo width $w] 100
+
+ wm deiconify $w
+}
+}
+
+proc update_menu24 {} {
+}
+
+
+proc update_define_menu24 {} {
+ update_define_mainmenu
+ global CONFIG_MODULES
+}
+
+
+proc update_mainmenu {} {
+}
+
+
+set tmpvar_0 "(not set)"
+set CONFIG_SYN_INFERRED 0
+set CONFIG_SYN_STRATIX 0
+set CONFIG_SYN_STRATIXII 0
+set CONFIG_SYN_STRATIXIII 0
+set CONFIG_SYN_CYCLONEIII 0
+set CONFIG_SYN_ALTERA 0
+set CONFIG_SYN_AXCEL 0
+set CONFIG_SYN_AXDSP 0
+set CONFIG_SYN_PROASIC 0
+set CONFIG_SYN_PROASICPLUS 0
+set CONFIG_SYN_PROASIC3 0
+set CONFIG_SYN_IGLOO 0
+set CONFIG_SYN_UT025CRH 0
+set CONFIG_SYN_ATC18 0
+set CONFIG_SYN_ATC18RHA 0
+set CONFIG_SYN_CUSTOM1 0
+set CONFIG_SYN_EASIC90 0
+set CONFIG_SYN_IHP25 0
+set CONFIG_SYN_IHP25RH 0
+set CONFIG_SYN_LATTICE 0
+set CONFIG_SYN_ECLIPSE 0
+set CONFIG_SYN_PEREGRINE 0
+set CONFIG_SYN_RH_LIB18T 0
+set CONFIG_SYN_RHUMC 0
+set CONFIG_SYN_SMIC13 0
+set CONFIG_SYN_SPARTAN2 0
+set CONFIG_SYN_SPARTAN3 0
+set CONFIG_SYN_SPARTAN3E 0
+set CONFIG_SYN_SPARTAN6 0
+set CONFIG_SYN_VIRTEX 0
+set CONFIG_SYN_VIRTEXE 0
+set CONFIG_SYN_VIRTEX2 0
+set CONFIG_SYN_VIRTEX4 0
+set CONFIG_SYN_VIRTEX5 0
+set CONFIG_SYN_VIRTEX6 0
+set CONFIG_SYN_UMC 0
+set CONFIG_SYN_TSMC90 0
+set tmpvar_1 "(not set)"
+set CONFIG_MEM_INFERRED 0
+set CONFIG_MEM_UMC 0
+set CONFIG_MEM_RHUMC 0
+set CONFIG_MEM_ARTISAN 0
+set CONFIG_MEM_CUSTOM1 0
+set CONFIG_MEM_VIRAGE 0
+set CONFIG_MEM_VIRAGE90 0
+set CONFIG_SYN_INFER_RAM 0
+set CONFIG_SYN_INFER_PADS 0
+set CONFIG_SYN_NO_ASYNC 0
+set CONFIG_SYN_SCAN 0
+set tmpvar_2 "(not set)"
+set CONFIG_FPGA_1500 0
+set CONFIG_FPGA_2000 0
+set tmpvar_3 "(not set)"
+set CONFIG_CLK_INFERRED 0
+set CONFIG_CLK_HCLKBUF 0
+set CONFIG_CLK_ALTDLL 0
+set CONFIG_CLK_LATDLL 0
+set CONFIG_CLK_PRO3PLL 0
+set CONFIG_CLK_LIB18T 0
+set CONFIG_CLK_RHUMC 0
+set CONFIG_CLK_CLKDLL 0
+set CONFIG_CLK_DCM 0
+set CONFIG_CLK_MUL 2
+set CONFIG_CLK_DIV 2
+set CONFIG_OCLK_DIV 2
+set CONFIG_PCI_CLKDLL 0
+set CONFIG_CLK_NOFB 0
+set CONFIG_PCI_SYSCLK 0
+set CONFIG_LEON3 0
+set CONFIG_PROC_NUM 1
+set CONFIG_IU_NWINDOWS 8
+set CONFIG_IU_V8MULDIV 0
+set tmpvar_4 "(not set)"
+set CONFIG_IU_MUL_LATENCY_2 0
+set CONFIG_IU_MUL_LATENCY_4 0
+set CONFIG_IU_MUL_LATENCY_5 0
+set CONFIG_IU_MUL_MAC 0
+set CONFIG_IU_BP 0
+set CONFIG_IU_SVT 0
+set CONFIG_IU_LDELAY 1
+set CONFIG_IU_WATCHPOINTS 0
+set CONFIG_PWD 0
+set CONFIG_IU_RSTADDR 00000
+set CONFIG_FPU_ENABLE 0
+set tmpvar_5 "(not set)"
+set CONFIG_FPU_GRFPU 0
+set CONFIG_FPU_GRFPULITE 0
+set CONFIG_FPU_MEIKO 0
+set tmpvar_6 "(not set)"
+set CONFIG_FPU_GRFPU_INFMUL 0
+set CONFIG_FPU_GRFPU_DWMUL 0
+set CONFIG_FPU_GRFPU_MODGEN 0
+set CONFIG_FPU_GRFPU_TECHSPEC 0
+set tmpvar_7 "(not set)"
+set CONFIG_FPU_GRFPC0 0
+set CONFIG_FPU_GRFPC1 0
+set CONFIG_FPU_GRFPC2 0
+set CONFIG_FPU_NETLIST 0
+set CONFIG_ICACHE_ENABLE 0
+set tmpvar_8 "(not set)"
+set CONFIG_ICACHE_ASSO1 0
+set CONFIG_ICACHE_ASSO2 0
+set CONFIG_ICACHE_ASSO3 0
+set CONFIG_ICACHE_ASSO4 0
+set tmpvar_9 "(not set)"
+set CONFIG_ICACHE_SZ1 0
+set CONFIG_ICACHE_SZ2 0
+set CONFIG_ICACHE_SZ4 0
+set CONFIG_ICACHE_SZ8 0
+set CONFIG_ICACHE_SZ16 0
+set CONFIG_ICACHE_SZ32 0
+set CONFIG_ICACHE_SZ64 0
+set CONFIG_ICACHE_SZ128 0
+set CONFIG_ICACHE_SZ256 0
+set tmpvar_10 "(not set)"
+set CONFIG_ICACHE_LZ16 0
+set CONFIG_ICACHE_LZ32 0
+set tmpvar_11 "(not set)"
+set CONFIG_ICACHE_ALGORND 0
+set CONFIG_ICACHE_ALGOLRR 0
+set CONFIG_ICACHE_ALGOLRU 0
+set CONFIG_ICACHE_LOCK 0
+set CONFIG_ICACHE_LRAM 0
+set tmpvar_12 "(not set)"
+set CONFIG_ICACHE_LRAM_SZ1 0
+set CONFIG_ICACHE_LRAM_SZ2 0
+set CONFIG_ICACHE_LRAM_SZ4 0
+set CONFIG_ICACHE_LRAM_SZ8 0
+set CONFIG_ICACHE_LRAM_SZ16 0
+set CONFIG_ICACHE_LRAM_SZ32 0
+set CONFIG_ICACHE_LRAM_SZ64 0
+set CONFIG_ICACHE_LRAM_SZ128 0
+set CONFIG_ICACHE_LRAM_SZ256 0
+set CONFIG_ICACHE_LRSTART 8e
+set CONFIG_DCACHE_ENABLE 0
+set tmpvar_13 "(not set)"
+set CONFIG_DCACHE_ASSO1 0
+set CONFIG_DCACHE_ASSO2 0
+set CONFIG_DCACHE_ASSO3 0
+set CONFIG_DCACHE_ASSO4 0
+set tmpvar_14 "(not set)"
+set CONFIG_DCACHE_SZ1 0
+set CONFIG_DCACHE_SZ2 0
+set CONFIG_DCACHE_SZ4 0
+set CONFIG_DCACHE_SZ8 0
+set CONFIG_DCACHE_SZ16 0
+set CONFIG_DCACHE_SZ32 0
+set CONFIG_DCACHE_SZ64 0
+set CONFIG_DCACHE_SZ128 0
+set CONFIG_DCACHE_SZ256 0
+set tmpvar_15 "(not set)"
+set CONFIG_DCACHE_LZ16 0
+set CONFIG_DCACHE_LZ32 0
+set tmpvar_16 "(not set)"
+set CONFIG_DCACHE_ALGORND 0
+set CONFIG_DCACHE_ALGOLRR 0
+set CONFIG_DCACHE_ALGOLRU 0
+set CONFIG_DCACHE_LOCK 0
+set CONFIG_DCACHE_SNOOP 0
+set CONFIG_DCACHE_SNOOP_FAST 0
+set CONFIG_DCACHE_SNOOP_SEPTAG 0
+set CONFIG_CACHE_FIXED 0
+set CONFIG_DCACHE_LRAM 0
+set tmpvar_17 "(not set)"
+set CONFIG_DCACHE_LRAM_SZ1 0
+set CONFIG_DCACHE_LRAM_SZ2 0
+set CONFIG_DCACHE_LRAM_SZ4 0
+set CONFIG_DCACHE_LRAM_SZ8 0
+set CONFIG_DCACHE_LRAM_SZ16 0
+set CONFIG_DCACHE_LRAM_SZ32 0
+set CONFIG_DCACHE_LRAM_SZ64 0
+set CONFIG_DCACHE_LRAM_SZ128 0
+set CONFIG_DCACHE_LRAM_SZ256 0
+set CONFIG_DCACHE_LRSTART 8f
+set CONFIG_MMU_ENABLE 0
+set tmpvar_18 "(not set)"
+set CONFIG_MMU_COMBINED 0
+set CONFIG_MMU_SPLIT 0
+set tmpvar_19 "(not set)"
+set CONFIG_MMU_REPARRAY 0
+set CONFIG_MMU_REPINCREMENT 0
+set tmpvar_20 "(not set)"
+set CONFIG_MMU_I2 0
+set CONFIG_MMU_I4 0
+set CONFIG_MMU_I8 0
+set CONFIG_MMU_I16 0
+set CONFIG_MMU_I32 0
+set tmpvar_21 "(not set)"
+set CONFIG_MMU_D2 0
+set CONFIG_MMU_D4 0
+set CONFIG_MMU_D8 0
+set CONFIG_MMU_D16 0
+set CONFIG_MMU_D32 0
+set CONFIG_MMU_FASTWB 0
+set tmpvar_22 "(not set)"
+set CONFIG_MMU_PAGE_4K 0
+set CONFIG_MMU_PAGE_8K 0
+set CONFIG_MMU_PAGE_16K 0
+set CONFIG_MMU_PAGE_32K 0
+set CONFIG_MMU_PAGE_PROG 0
+set CONFIG_DSU_ENABLE 0
+set CONFIG_DSU_ITRACE 0
+set tmpvar_23 "(not set)"
+set CONFIG_DSU_ITRACESZ1 0
+set CONFIG_DSU_ITRACESZ2 0
+set CONFIG_DSU_ITRACESZ4 0
+set CONFIG_DSU_ITRACESZ8 0
+set CONFIG_DSU_ITRACESZ16 0
+set CONFIG_DSU_ATRACE 0
+set tmpvar_24 "(not set)"
+set CONFIG_DSU_ATRACESZ1 0
+set CONFIG_DSU_ATRACESZ2 0
+set CONFIG_DSU_ATRACESZ4 0
+set CONFIG_DSU_ATRACESZ8 0
+set CONFIG_DSU_ATRACESZ16 0
+set CONFIG_IU_DISAS 0
+set CONFIG_IU_DISAS_NET 0
+set CONFIG_DEBUG_PC32 0
+set CONFIG_AHB_DEFMST 0
+set CONFIG_AHB_RROBIN 0
+set CONFIG_AHB_SPLIT 0
+set CONFIG_AHB_IOADDR FFF
+set CONFIG_APB_HADDR 800
+set CONFIG_AHB_MON 0
+set CONFIG_AHB_MONERR 0
+set CONFIG_AHB_MONWAR 0
+set CONFIG_DSU_UART 0
+set CONFIG_DSU_JTAG 0
+set CONFIG_GRUSB_DCL 0
+set tmpvar_26 "(not set)"
+set CONFIG_GRUSB_DCL_ULPI 0
+set CONFIG_GRUSB_DCL_UTMI8 0
+set CONFIG_GRUSB_DCL_UTMI16 0
+set CONFIG_DSU_ETH 0
+set tmpvar_27 "(not set)"
+set CONFIG_DSU_ETHSZ1 0
+set CONFIG_DSU_ETHSZ2 0
+set CONFIG_DSU_ETHSZ4 0
+set CONFIG_DSU_ETHSZ8 0
+set CONFIG_DSU_ETHSZ16 0
+set CONFIG_DSU_IPMSB C0A8
+set CONFIG_DSU_IPLSB 0033
+set CONFIG_DSU_ETHMSB 020000
+set CONFIG_DSU_ETHLSB 000000
+set CONFIG_DSU_ETH_PROG 0
+set CONFIG_MCTRL_LEON2 0
+set CONFIG_MCTRL_8BIT 0
+set CONFIG_MCTRL_16BIT 0
+set CONFIG_MCTRL_5CS 0
+set CONFIG_MCTRL_SDRAM 0
+set CONFIG_MCTRL_SDRAM_SEPBUS 0
+set CONFIG_MCTRL_SDRAM_BUS64 0
+set CONFIG_MCTRL_SDRAM_INVCLK 0
+set CONFIG_MCTRL_PAGE 0
+set CONFIG_MCTRL_PROGPAGE 0
+set CONFIG_AHBSTAT_ENABLE 0
+set CONFIG_AHBSTAT_NFTSLV 1
+set CONFIG_AHBROM_ENABLE 0
+set CONFIG_AHBROM_START 000
+set CONFIG_AHBROM_PIPE 0
+set CONFIG_AHBRAM_ENABLE 0
+set tmpvar_28 "(not set)"
+set CONFIG_AHBRAM_SZ1 0
+set CONFIG_AHBRAM_SZ2 0
+set CONFIG_AHBRAM_SZ4 0
+set CONFIG_AHBRAM_SZ8 0
+set CONFIG_AHBRAM_SZ16 0
+set CONFIG_AHBRAM_SZ32 0
+set CONFIG_AHBRAM_SZ64 0
+set CONFIG_AHBRAM_START A00
+set CONFIG_GRETH_ENABLE 0
+set CONFIG_GRETH_GIGA 0
+set tmpvar_29 "(not set)"
+set CONFIG_GRETH_FIFO4 0
+set CONFIG_GRETH_FIFO8 0
+set CONFIG_GRETH_FIFO16 0
+set CONFIG_GRETH_FIFO32 0
+set CONFIG_GRETH_FIFO64 0
+set CONFIG_ATA_ENABLE 0
+set CONFIG_ATAIO A00
+set CONFIG_ATAIRQ 10
+set CONFIG_ATA_MWDMA 0
+set CONFIG_ATA_FIFO 8
+set CONFIG_CAN_ENABLE 0
+set CONFIG_CAN_NUM 1
+set CONFIG_CANIO C00
+set CONFIG_CANIRQ 13
+set CONFIG_CANSEPIRQ 0
+set CONFIG_CAN_SYNCRST 0
+set CONFIG_CAN_FT 0
+set CONFIG_GRUSBDC_ENABLE 0
+set CONFIG_GRUSBDC_AIFACE 0
+set tmpvar_30 "(not set)"
+set CONFIG_GRUSBDC_ULPI 0
+set CONFIG_GRUSBDC_UTMI8 0
+set CONFIG_GRUSBDC_UTMI16 0
+set CONFIG_GRUSBDC_NEPI 1
+set CONFIG_GRUSBDC_NEPO 1
+set CONFIG_GRUSBDC_I0 1024
+set CONFIG_GRUSBDC_I1 1024
+set CONFIG_GRUSBDC_I2 1024
+set CONFIG_GRUSBDC_I3 1024
+set CONFIG_GRUSBDC_I4 1024
+set CONFIG_GRUSBDC_I5 1024
+set CONFIG_GRUSBDC_I6 1024
+set CONFIG_GRUSBDC_I7 1024
+set CONFIG_GRUSBDC_I8 1024
+set CONFIG_GRUSBDC_I9 1024
+set CONFIG_GRUSBDC_I10 1024
+set CONFIG_GRUSBDC_I11 1024
+set CONFIG_GRUSBDC_I12 1024
+set CONFIG_GRUSBDC_I13 1024
+set CONFIG_GRUSBDC_I14 1024
+set CONFIG_GRUSBDC_I15 1024
+set CONFIG_GRUSBDC_O0 1024
+set CONFIG_GRUSBDC_O1 1024
+set CONFIG_GRUSBDC_O2 1024
+set CONFIG_GRUSBDC_O3 1024
+set CONFIG_GRUSBDC_O4 1024
+set CONFIG_GRUSBDC_O5 1024
+set CONFIG_GRUSBDC_O6 1024
+set CONFIG_GRUSBDC_O7 1024
+set CONFIG_GRUSBDC_O8 1024
+set CONFIG_GRUSBDC_O9 1024
+set CONFIG_GRUSBDC_O10 1024
+set CONFIG_GRUSBDC_O11 1024
+set CONFIG_GRUSBDC_O12 1024
+set CONFIG_GRUSBDC_O13 1024
+set CONFIG_GRUSBDC_O14 1024
+set CONFIG_GRUSBDC_O15 1024
+set CONFIG_UART1_ENABLE 0
+set tmpvar_31 "(not set)"
+set CONFIG_UA1_FIFO1 0
+set CONFIG_UA1_FIFO2 0
+set CONFIG_UA1_FIFO4 0
+set CONFIG_UA1_FIFO8 0
+set CONFIG_UA1_FIFO16 0
+set CONFIG_UA1_FIFO32 0
+set CONFIG_UART2_ENABLE 0
+set tmpvar_32 "(not set)"
+set CONFIG_UA2_FIFO1 0
+set CONFIG_UA2_FIFO2 0
+set CONFIG_UA2_FIFO4 0
+set CONFIG_UA2_FIFO8 0
+set CONFIG_UA2_FIFO16 0
+set CONFIG_UA2_FIFO32 0
+set CONFIG_IRQ3_ENABLE 0
+set CONFIG_IRQ3_SEC 0
+set CONFIG_IRQ3_NSEC 12
+set CONFIG_GPT_ENABLE 0
+set CONFIG_GPT_NTIM 2
+set CONFIG_GPT_SW 8
+set CONFIG_GPT_TW 32
+set CONFIG_GPT_IRQ 8
+set CONFIG_GPT_SEPIRQ 0
+set CONFIG_GPT_WDOGEN 0
+set CONFIG_GPT_WDOG FFFF
+set CONFIG_GRGPIO_ENABLE 0
+set CONFIG_GRGPIO_WIDTH 8
+set CONFIG_GRGPIO_IMASK 0000
+set CONFIG_SPW_ENABLE 0
+set CONFIG_SPW_NUM 1
+set tmpvar_33 "(not set)"
+set CONFIG_SPW_AHBFIFO4 0
+set CONFIG_SPW_AHBFIFO8 0
+set CONFIG_SPW_AHBFIFO16 0
+set CONFIG_SPW_AHBFIFO32 0
+set tmpvar_34 "(not set)"
+set CONFIG_SPW_RXFIFO16 0
+set CONFIG_SPW_RXFIFO32 0
+set CONFIG_SPW_RXFIFO64 0
+set CONFIG_SPW_RMAP 0
+set tmpvar_35 "(not set)"
+set CONFIG_SPW_RMAPBUF2 0
+set CONFIG_SPW_RMAPBUF4 0
+set CONFIG_SPW_RMAPBUF6 0
+set CONFIG_SPW_RMAPBUF8 0
+set CONFIG_SPW_RMAPCRC 0
+set CONFIG_SPW_RXUNAL 0
+set CONFIG_SPW_FT 0
+set CONFIG_SPW_NETLIST 0
+set CONFIG_SPW_PORTS 1
+set tmpvar_36 "(not set)"
+set CONFIG_SPW_GRSPW1 0
+set CONFIG_SPW_GRSPW2 0
+set CONFIG_SPW_DMACHAN 1
+set CONFIG_SPW_RTSAME 0
+set tmpvar_37 "(not set)"
+set CONFIG_SPW_RX_SDR 0
+set CONFIG_SPW_RX_DDR 0
+set CONFIG_SPW_RX_XOR 0
+set CONFIG_SPW_RX_AFLEX 0
+set tmpvar_38 "(not set)"
+set CONFIG_SPW_TX_SDR 0
+set CONFIG_SPW_TX_DDR 0
+set CONFIG_SPW_TX_AFLEX 0
+set CONFIG_KBD_ENABLE 0
+set CONFIG_VGA_ENABLE 0
+set CONFIG_SVGA_ENABLE 0
+set CONFIG_DEBUG_UART 0
+set CONFIG_SYN_ARTISAN 4
+set CONFIG_PCI_ENABLE 4
+set CONFIG_HAS_SHARED_GRFPU 4
+set CONFIG_FPU_GRFPU_SH 4
+set CONFIG_LEON3FT_PRESENT 4
+set CONFIG_LEON3FT_EN 4
+set CONFIG_IUFT_NONE 4
+set CONFIG_IUFT_PAR 4
+set CONFIG_IUFT_DMR 4
+set CONFIG_IUFT_BCH 4
+set CONFIG_IUFT_TMR 4
+set CONFIG_FPUFT_EN 4
+set CONFIG_RF_ERRINJ 4
+set CONFIG_CACHE_FT_EN 4
+set CONFIG_CACHE_ERRINJ 4
+set CONFIG_LEON3_NETLIST 4
+set CONFIG_MODULES 4
+proc writeconfig {file1 file2} {
+ set cfg [open $file1 w]
+ set autocfg [open $file2 w]
+ set notmod 1
+ set notset 0
+ puts $cfg "#"
+ puts $cfg "# Automatically generated make config: don't edit"
+ puts $cfg "#"
+ puts $autocfg "/*"
+ puts $autocfg " * Automatically generated C config: don't edit"
+ puts $autocfg " */"
+ puts $autocfg "#define AUTOCONF_INCLUDED"
+ write_comment $cfg $autocfg "Synthesis "
+ global tmpvar_0
+
+ if { $tmpvar_0 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-Stratix" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-StratixII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-StratixIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-CycloneIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Altera-Others" } then { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-Axcelerator" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-Axcelerator-DSP" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXDSP 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXDSP 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-Proasic" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-ProasicPlus" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-Proasic3/E/L" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Actel-IGLOO/p/L" } then { write_tristate $cfg $autocfg CONFIG_SYN_IGLOO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IGLOO 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Aeroflex-UT025CRH" } then { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Atmel-ATC18" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Atmel-ATC18RHA" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "eASIC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "IHP25" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "IHP25RH" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Lattice-EC/ECP/XP" } then { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Quicklogic-Eclipse" } then { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Peregrine" } then { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "RH-LIB18T" } then { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "SMIC130" } then { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Spartan2" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Spartan3" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Spartan3E" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Spartan6" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN6 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-VirtexE" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex2" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex4" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex5" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "Xilinx-Virtex6" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX6 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "UMC180" } then { write_tristate $cfg $autocfg CONFIG_SYN_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UMC 0 [list $notmod] 2 }
+ if { $tmpvar_0 == "TSMC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 0 [list $notmod] 2 }
+ global tmpvar_1
+ global CONFIG_SYN_INFERRED
+ global CONFIG_SYN_CUSTOM1
+ global CONFIG_SYN_ATC18
+ global CONFIG_SYN_TSMC90
+ global CONFIG_SYN_UMC
+ global CONFIG_SYN_RHUMC
+ global CONFIG_SYN_ARTISAN
+ if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then {
+ if { $tmpvar_1 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "UMC18" } then { write_tristate $cfg $autocfg CONFIG_MEM_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_UMC 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "Artisan" } then { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "Virage" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 0 [list $notmod] 2 }
+ if { $tmpvar_1 == "Virage-TSMC90" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 0 [list $notmod] 2 }}
+ global CONFIG_SYN_INFER_RAM
+ if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_RAM $CONFIG_SYN_INFER_RAM [list $notmod] 2 }
+ global CONFIG_SYN_INFER_PADS
+ if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_PADS $CONFIG_SYN_INFER_PADS [list $notmod] 2 }
+ global CONFIG_SYN_NO_ASYNC
+ write_tristate $cfg $autocfg CONFIG_SYN_NO_ASYNC $CONFIG_SYN_NO_ASYNC [list $notmod] 2
+ global CONFIG_SYN_SCAN
+ write_tristate $cfg $autocfg CONFIG_SYN_SCAN $CONFIG_SYN_SCAN [list $notmod] 2
+ global tmpvar_2
+
+ if { $tmpvar_2 == "XC3S-1500" } then { write_tristate $cfg $autocfg CONFIG_FPGA_1500 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPGA_1500 0 [list $notmod] 2 }
+ if { $tmpvar_2 == "XC3S-2000" } then { write_tristate $cfg $autocfg CONFIG_FPGA_2000 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPGA_2000 0 [list $notmod] 2 }
+ write_comment $cfg $autocfg "Clock generation"
+ global tmpvar_3
+
+ if { $tmpvar_3 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "Actel-HCLKBUF" } then { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "Altera-ALTPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "Lattice-EXPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "Proasic3-PLLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "RH-LIB18T-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "DARE-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "Xilinx-CLKDLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 0 [list $notmod] 2 }
+ if { $tmpvar_3 == "Xilinx-DCM" } then { write_tristate $cfg $autocfg CONFIG_CLK_DCM 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_DCM 0 [list $notmod] 2 }
+ global CONFIG_CLK_MUL
+ global CONFIG_CLK_DCM
+ global CONFIG_CLK_ALTDLL
+ global CONFIG_CLK_LATDLL
+ global CONFIG_CLK_PRO3PLL
+ global CONFIG_CLK_CLKDLL
+ global CONFIG_CLK_LIB18T
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_MUL $CONFIG_CLK_MUL $notmod }
+ global CONFIG_CLK_DIV
+ if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_DIV $CONFIG_CLK_DIV $notmod }
+ global CONFIG_OCLK_DIV
+ if {($CONFIG_CLK_PRO3PLL == 1)} then {write_int $cfg $autocfg CONFIG_OCLK_DIV $CONFIG_OCLK_DIV $notmod }
+ global CONFIG_PCI_CLKDLL
+ if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_CLKDLL $CONFIG_PCI_CLKDLL [list $notmod] 2 }
+ global CONFIG_CLK_NOFB
+ if {($CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_CLK_NOFB $CONFIG_CLK_NOFB [list $notmod] 2 }
+ global CONFIG_PCI_SYSCLK
+ global CONFIG_PCI_ENABLE
+ if {($CONFIG_PCI_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SYSCLK $CONFIG_PCI_SYSCLK [list $notmod] 2 }
+ global CONFIG_LEON3
+ write_tristate $cfg $autocfg CONFIG_LEON3 $CONFIG_LEON3 [list $notmod] 2
+ global CONFIG_PROC_NUM
+ if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_PROC_NUM $CONFIG_PROC_NUM $notmod }
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Processor "}
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Integer unit "}
+ global CONFIG_IU_NWINDOWS
+ if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS $CONFIG_IU_NWINDOWS $notmod }
+ global CONFIG_IU_V8MULDIV
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONFIG_IU_V8MULDIV [list $notmod] 2 }
+ global tmpvar_4
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {
+ if { $tmpvar_4 == "2-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 0 [list $notmod] 2 }
+ if { $tmpvar_4 == "4-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 0 [list $notmod] 2 }
+ if { $tmpvar_4 == "5-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 0 [list $notmod] 2 }}
+ global CONFIG_IU_MUL_MAC
+ global CONFIG_IU_MUL_LATENCY_4
+ global CONFIG_IU_MUL_LATENCY_5
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_MAC $CONFIG_IU_MUL_MAC [list $notmod] 2 }
+ global CONFIG_IU_BP
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_BP $CONFIG_IU_BP [list $notmod] 2 }
+ global CONFIG_IU_SVT
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONFIG_IU_SVT [list $notmod] 2 }
+ global CONFIG_IU_LDELAY
+ if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY $CONFIG_IU_LDELAY $notmod }
+ global CONFIG_IU_WATCHPOINTS
+ if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS $CONFIG_IU_WATCHPOINTS $notmod }
+ global CONFIG_PWD
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONFIG_PWD [list $notmod] 2 }
+ global CONFIG_IU_RSTADDR
+ if {($CONFIG_LEON3 == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR $CONFIG_IU_RSTADDR $notmod }
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Floating-point unit"}
+ global CONFIG_FPU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONFIG_FPU_ENABLE [list $notmod] 2 }
+ global tmpvar_5
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {
+ if { $tmpvar_5 == "GRFPU" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 0 [list $notmod] 2 }
+ if { $tmpvar_5 == "GRFPU-LITE" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 0 [list $notmod] 2 }
+ if { $tmpvar_5 == "Meiko" } then { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 0 [list $notmod] 2 }}
+ global tmpvar_6
+ global CONFIG_FPU_GRFPU
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then {
+ if { $tmpvar_6 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 0 [list $notmod] 2 }
+ if { $tmpvar_6 == "DW" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 0 [list $notmod] 2 }
+ if { $tmpvar_6 == "ModGen" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 0 [list $notmod] 2 }
+ if { $tmpvar_6 == "TechSpec" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_TECHSPEC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_TECHSPEC 0 [list $notmod] 2 }}
+ global tmpvar_7
+ global CONFIG_FPU_GRFPULITE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then {
+ if { $tmpvar_7 == "Simple" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 0 [list $notmod] 2 }
+ if { $tmpvar_7 == "Data-forwarding" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 0 [list $notmod] 2 }
+ if { $tmpvar_7 == "Non-blocking" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 0 [list $notmod] 2 }}
+ global CONFIG_FPU_NETLIST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_NETLIST $CONFIG_FPU_NETLIST [list $notmod] 2 }
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Cache system"}
+ global CONFIG_ICACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONFIG_ICACHE_ENABLE [list $notmod] 2 }
+ global tmpvar_8
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {
+ if { $tmpvar_8 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "3" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 0 [list $notmod] 2 }
+ if { $tmpvar_8 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 0 [list $notmod] 2 }}
+ global tmpvar_9
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {
+ if { $tmpvar_9 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 0 [list $notmod] 2 }
+ if { $tmpvar_9 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 0 [list $notmod] 2 }}
+ global tmpvar_10
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {
+ if { $tmpvar_10 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 0 [list $notmod] 2 }
+ if { $tmpvar_10 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 0 [list $notmod] 2 }}
+ global tmpvar_11
+ global CONFIG_ICACHE_ASSO1
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {
+ if { $tmpvar_11 == "Random" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 0 [list $notmod] 2 }
+ if { $tmpvar_11 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 0 [list $notmod] 2 }}
+ global CONFIG_ICACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONFIG_ICACHE_LOCK [list $notmod] 2 }
+ global CONFIG_ICACHE_LRAM
+ global CONFIG_MMU_ENABLE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM $CONFIG_ICACHE_LRAM [list $notmod] 2 }
+ global tmpvar_12
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {
+ if { $tmpvar_12 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 0 [list $notmod] 2 }
+ if { $tmpvar_12 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 0 [list $notmod] 2 }}
+ global CONFIG_ICACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_ICACHE_LRSTART $CONFIG_ICACHE_LRSTART $notmod }
+ global CONFIG_DCACHE_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONFIG_DCACHE_ENABLE [list $notmod] 2 }
+ global tmpvar_13
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ if { $tmpvar_13 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "3" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 0 [list $notmod] 2 }
+ if { $tmpvar_13 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 0 [list $notmod] 2 }}
+ global tmpvar_14
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ if { $tmpvar_14 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 0 [list $notmod] 2 }
+ if { $tmpvar_14 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 0 [list $notmod] 2 }}
+ global tmpvar_15
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {
+ if { $tmpvar_15 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 0 [list $notmod] 2 }
+ if { $tmpvar_15 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 0 [list $notmod] 2 }}
+ global tmpvar_16
+ global CONFIG_DCACHE_ASSO1
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {
+ if { $tmpvar_16 == "Random" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 0 [list $notmod] 2 }
+ if { $tmpvar_16 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }}
+ global CONFIG_DCACHE_LOCK
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 }
+ global CONFIG_DCACHE_SNOOP
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 }
+ global CONFIG_DCACHE_SNOOP_FAST
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 }
+ global CONFIG_DCACHE_SNOOP_SEPTAG
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 }
+ global CONFIG_CACHE_FIXED
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod }
+ global CONFIG_DCACHE_LRAM
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 }
+ global tmpvar_17
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {
+ if { $tmpvar_17 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 0 [list $notmod] 2 }
+ if { $tmpvar_17 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 0 [list $notmod] 2 }}
+ global CONFIG_DCACHE_LRSTART
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_DCACHE_LRSTART $CONFIG_DCACHE_LRSTART $notmod }
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "MMU"}
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONFIG_MMU_ENABLE [list $notmod] 2 }
+ global tmpvar_18
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {
+ if { $tmpvar_18 == "combined" } then { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 0 [list $notmod] 2 }
+ if { $tmpvar_18 == "split" } then { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 0 [list $notmod] 2 }}
+ global tmpvar_19
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {
+ if { $tmpvar_19 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 0 [list $notmod] 2 }
+ if { $tmpvar_19 == "Increment" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 0 [list $notmod] 2 }}
+ global tmpvar_20
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {
+ if { $tmpvar_20 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_I2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I2 0 [list $notmod] 2 }
+ if { $tmpvar_20 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_I4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I4 0 [list $notmod] 2 }
+ if { $tmpvar_20 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_I8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I8 0 [list $notmod] 2 }
+ if { $tmpvar_20 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_I16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I16 0 [list $notmod] 2 }
+ if { $tmpvar_20 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_I32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I32 0 [list $notmod] 2 }}
+ global tmpvar_21
+ global CONFIG_MMU_SPLIT
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {
+ if { $tmpvar_21 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_D2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D2 0 [list $notmod] 2 }
+ if { $tmpvar_21 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_D4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D4 0 [list $notmod] 2 }
+ if { $tmpvar_21 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_D8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D8 0 [list $notmod] 2 }
+ if { $tmpvar_21 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_D16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D16 0 [list $notmod] 2 }
+ if { $tmpvar_21 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_D32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D32 0 [list $notmod] 2 }}
+ global CONFIG_MMU_FASTWB
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_FASTWB $CONFIG_MMU_FASTWB [list $notmod] 2 }
+ global tmpvar_22
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {
+ if { $tmpvar_22 == "4K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 0 [list $notmod] 2 }
+ if { $tmpvar_22 == "8K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 0 [list $notmod] 2 }
+ if { $tmpvar_22 == "16K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 0 [list $notmod] 2 }
+ if { $tmpvar_22 == "32K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 0 [list $notmod] 2 }
+ if { $tmpvar_22 == "Programmable" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 0 [list $notmod] 2 }}
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Debug Support Unit "}
+ global CONFIG_DSU_ENABLE
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONFIG_DSU_ENABLE [list $notmod] 2 }
+ global CONFIG_DSU_ITRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACE $CONFIG_DSU_ITRACE [list $notmod] 2 }
+ global tmpvar_23
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then {
+ if { $tmpvar_23 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 0 [list $notmod] 2 }
+ if { $tmpvar_23 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 0 [list $notmod] 2 }
+ if { $tmpvar_23 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 0 [list $notmod] 2 }
+ if { $tmpvar_23 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 0 [list $notmod] 2 }
+ if { $tmpvar_23 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 0 [list $notmod] 2 }}
+ global CONFIG_DSU_ATRACE
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ATRACE $CONFIG_DSU_ATRACE [list $notmod] 2 }
+ global tmpvar_24
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then {
+ if { $tmpvar_24 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 0 [list $notmod] 2 }
+ if { $tmpvar_24 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 0 [list $notmod] 2 }
+ if { $tmpvar_24 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 0 [list $notmod] 2 }
+ if { $tmpvar_24 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 0 [list $notmod] 2 }
+ if { $tmpvar_24 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 0 [list $notmod] 2 }}
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Fault-tolerance "}
+ if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "VHDL debug settings "}
+ global CONFIG_IU_DISAS
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS $CONFIG_IU_DISAS [list $notmod] 2 }
+ global CONFIG_IU_DISAS_NET
+ if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS_NET $CONFIG_IU_DISAS_NET [list $notmod] 2 }
+ global CONFIG_DEBUG_PC32
+ if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DEBUG_PC32 $CONFIG_DEBUG_PC32 [list $notmod] 2 }
+ write_comment $cfg $autocfg "AMBA configuration"
+ global CONFIG_AHB_DEFMST
+ write_int $cfg $autocfg CONFIG_AHB_DEFMST $CONFIG_AHB_DEFMST $notmod
+ global CONFIG_AHB_RROBIN
+ write_tristate $cfg $autocfg CONFIG_AHB_RROBIN $CONFIG_AHB_RROBIN [list $notmod] 2
+ global CONFIG_AHB_SPLIT
+ write_tristate $cfg $autocfg CONFIG_AHB_SPLIT $CONFIG_AHB_SPLIT [list $notmod] 2
+ global CONFIG_AHB_IOADDR
+ write_hex $cfg $autocfg CONFIG_AHB_IOADDR $CONFIG_AHB_IOADDR $notmod
+ global CONFIG_APB_HADDR
+ write_hex $cfg $autocfg CONFIG_APB_HADDR $CONFIG_APB_HADDR $notmod
+ global CONFIG_AHB_MON
+ write_tristate $cfg $autocfg CONFIG_AHB_MON $CONFIG_AHB_MON [list $notmod] 2
+ global CONFIG_AHB_MONERR
+ if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONERR $CONFIG_AHB_MONERR [list $notmod] 2 }
+ global CONFIG_AHB_MONWAR
+ if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONWAR $CONFIG_AHB_MONWAR [list $notmod] 2 }
+ write_comment $cfg $autocfg "Debug Link "
+ global CONFIG_DSU_UART
+ write_tristate $cfg $autocfg CONFIG_DSU_UART $CONFIG_DSU_UART [list $notmod] 2
+ global CONFIG_DSU_JTAG
+ write_tristate $cfg $autocfg CONFIG_DSU_JTAG $CONFIG_DSU_JTAG [list $notmod] 2
+ global CONFIG_GRUSB_DCL
+ write_tristate $cfg $autocfg CONFIG_GRUSB_DCL $CONFIG_GRUSB_DCL [list $notmod] 2
+ global tmpvar_26
+ if {($CONFIG_GRUSB_DCL == 1)} then {
+ if { $tmpvar_26 == "ULPI" } then { write_tristate $cfg $autocfg CONFIG_GRUSB_DCL_ULPI 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRUSB_DCL_ULPI 0 [list $notmod] 2 }
+ if { $tmpvar_26 == "UTMI/UTMI+8-bit" } then { write_tristate $cfg $autocfg CONFIG_GRUSB_DCL_UTMI8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRUSB_DCL_UTMI8 0 [list $notmod] 2 }
+ if { $tmpvar_26 == "UTMI/UTMI+16-bit" } then { write_tristate $cfg $autocfg CONFIG_GRUSB_DCL_UTMI16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRUSB_DCL_UTMI16 0 [list $notmod] 2 }}
+ global CONFIG_DSU_ETH
+ global CONFIG_GRETH_ENABLE
+ if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH $CONFIG_DSU_ETH [list $notmod] 2 }
+ global tmpvar_27
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {
+ if { $tmpvar_27 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 0 [list $notmod] 2 }
+ if { $tmpvar_27 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 0 [list $notmod] 2 }
+ if { $tmpvar_27 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 0 [list $notmod] 2 }
+ if { $tmpvar_27 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 0 [list $notmod] 2 }
+ if { $tmpvar_27 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 0 [list $notmod] 2 }}
+ global CONFIG_DSU_IPMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPMSB $CONFIG_DSU_IPMSB $notmod }
+ global CONFIG_DSU_IPLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPLSB $CONFIG_DSU_IPLSB $notmod }
+ global CONFIG_DSU_ETHMSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHMSB $CONFIG_DSU_ETHMSB $notmod }
+ global CONFIG_DSU_ETHLSB
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod }
+ global CONFIG_DSU_ETH_PROG
+ global CONFIG_GRETH_GIGA
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 }
+ write_comment $cfg $autocfg "Peripherals "
+ write_comment $cfg $autocfg "Memory controller "
+ write_comment $cfg $autocfg "Leon2 memory controller "
+ global CONFIG_MCTRL_LEON2
+ write_tristate $cfg $autocfg CONFIG_MCTRL_LEON2 $CONFIG_MCTRL_LEON2 [list $notmod] 2
+ global CONFIG_MCTRL_8BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_8BIT $CONFIG_MCTRL_8BIT [list $notmod] 2 }
+ global CONFIG_MCTRL_16BIT
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_16BIT $CONFIG_MCTRL_16BIT [list $notmod] 2 }
+ global CONFIG_MCTRL_5CS
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_5CS $CONFIG_MCTRL_5CS [list $notmod] 2 }
+ global CONFIG_MCTRL_SDRAM
+ if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM $CONFIG_MCTRL_SDRAM [list $notmod] 2 }
+ global CONFIG_MCTRL_SDRAM_SEPBUS
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_SEPBUS $CONFIG_MCTRL_SDRAM_SEPBUS [list $notmod] 2 }
+ global CONFIG_MCTRL_SDRAM_BUS64
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_BUS64 $CONFIG_MCTRL_SDRAM_BUS64 [list $notmod] 2 }
+ global CONFIG_MCTRL_SDRAM_INVCLK
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_INVCLK $CONFIG_MCTRL_SDRAM_INVCLK [list $notmod] 2 }
+ global CONFIG_MCTRL_PAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PAGE $CONFIG_MCTRL_PAGE [list $notmod] 2 }
+ global CONFIG_MCTRL_PROGPAGE
+ if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PROGPAGE $CONFIG_MCTRL_PROGPAGE [list $notmod] 2 }
+ global CONFIG_AHBSTAT_ENABLE
+ write_tristate $cfg $autocfg CONFIG_AHBSTAT_ENABLE $CONFIG_AHBSTAT_ENABLE [list $notmod] 2
+ global CONFIG_AHBSTAT_NFTSLV
+ if {($CONFIG_AHBSTAT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_AHBSTAT_NFTSLV $CONFIG_AHBSTAT_NFTSLV $notmod }
+ write_comment $cfg $autocfg "On-chip RAM/ROM "
+ global CONFIG_AHBROM_ENABLE
+ write_tristate $cfg $autocfg CONFIG_AHBROM_ENABLE $CONFIG_AHBROM_ENABLE [list $notmod] 2
+ global CONFIG_AHBROM_START
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBROM_START $CONFIG_AHBROM_START $notmod }
+ global CONFIG_AHBROM_PIPE
+ if {($CONFIG_AHBROM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBROM_PIPE $CONFIG_AHBROM_PIPE [list $notmod] 2 }
+ global CONFIG_AHBRAM_ENABLE
+ write_tristate $cfg $autocfg CONFIG_AHBRAM_ENABLE $CONFIG_AHBRAM_ENABLE [list $notmod] 2
+ global tmpvar_28
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {
+ if { $tmpvar_28 == "1" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "2" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "4" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "8" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "16" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "32" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 0 [list $notmod] 2 }
+ if { $tmpvar_28 == "64" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 0 [list $notmod] 2 }}
+ global CONFIG_AHBRAM_START
+ if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBRAM_START $CONFIG_AHBRAM_START $notmod }
+ write_comment $cfg $autocfg "Ethernet "
+ write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2
+ if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 }
+ global tmpvar_29
+ if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {
+ if { $tmpvar_29 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 0 [list $notmod] 2 }
+ if { $tmpvar_29 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 0 [list $notmod] 2 }
+ if { $tmpvar_29 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 0 [list $notmod] 2 }
+ if { $tmpvar_29 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 0 [list $notmod] 2 }
+ if { $tmpvar_29 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 0 [list $notmod] 2 }}
+ write_comment $cfg $autocfg "IDE Disk controller "
+ global CONFIG_ATA_ENABLE
+ write_tristate $cfg $autocfg CONFIG_ATA_ENABLE $CONFIG_ATA_ENABLE [list $notmod] 2
+ global CONFIG_ATAIO
+ if {($CONFIG_ATA_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_ATAIO $CONFIG_ATAIO $notmod }
+ global CONFIG_ATAIRQ
+ if {($CONFIG_ATA_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_ATAIRQ $CONFIG_ATAIRQ $notmod }
+ global CONFIG_ATA_MWDMA
+ if {($CONFIG_ATA_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_ATA_MWDMA $CONFIG_ATA_MWDMA [list $notmod] 2 }
+ global CONFIG_ATA_FIFO
+ if {($CONFIG_ATA_ENABLE == 1) && ($CONFIG_ATA_MWDMA == 1)} then {write_int $cfg $autocfg CONFIG_ATA_FIFO $CONFIG_ATA_FIFO $notmod }
+ write_comment $cfg $autocfg "CAN "
+ global CONFIG_CAN_ENABLE
+ write_tristate $cfg $autocfg CONFIG_CAN_ENABLE $CONFIG_CAN_ENABLE [list $notmod] 2
+ global CONFIG_CAN_NUM
+ if {($CONFIG_CAN_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_CAN_NUM $CONFIG_CAN_NUM $notmod }
+ global CONFIG_CANIO
+ if {($CONFIG_CAN_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CANIO $CONFIG_CANIO $notmod }
+ global CONFIG_CANIRQ
+ if {($CONFIG_CAN_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_CANIRQ $CONFIG_CANIRQ $notmod }
+ global CONFIG_CANSEPIRQ
+ if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CANSEPIRQ $CONFIG_CANSEPIRQ [list $notmod] 2 }
+ global CONFIG_CAN_SYNCRST
+ if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CAN_SYNCRST $CONFIG_CAN_SYNCRST [list $notmod] 2 }
+ global CONFIG_CAN_FT
+ if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CAN_FT $CONFIG_CAN_FT [list $notmod] 2 }
+ write_comment $cfg $autocfg "USB 2.0 Device Controller "
+ global CONFIG_GRUSBDC_ENABLE
+ write_tristate $cfg $autocfg CONFIG_GRUSBDC_ENABLE $CONFIG_GRUSBDC_ENABLE [list $notmod] 2
+ global CONFIG_GRUSBDC_AIFACE
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRUSBDC_AIFACE $CONFIG_GRUSBDC_AIFACE [list $notmod] 2 }
+ global tmpvar_30
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {
+ if { $tmpvar_30 == "ULPI" } then { write_tristate $cfg $autocfg CONFIG_GRUSBDC_ULPI 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRUSBDC_ULPI 0 [list $notmod] 2 }
+ if { $tmpvar_30 == "UTMI/UTMI+8-bit" } then { write_tristate $cfg $autocfg CONFIG_GRUSBDC_UTMI8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRUSBDC_UTMI8 0 [list $notmod] 2 }
+ if { $tmpvar_30 == "UTMI/UTMI+16-bit" } then { write_tristate $cfg $autocfg CONFIG_GRUSBDC_UTMI16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRUSBDC_UTMI16 0 [list $notmod] 2 }}
+ global CONFIG_GRUSBDC_NEPI
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_NEPI $CONFIG_GRUSBDC_NEPI $notmod }
+ global CONFIG_GRUSBDC_NEPO
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_NEPO $CONFIG_GRUSBDC_NEPO $notmod }
+ global CONFIG_GRUSBDC_I0
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I0 $CONFIG_GRUSBDC_I0 $notmod }
+ global CONFIG_GRUSBDC_I1
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I1 $CONFIG_GRUSBDC_I1 $notmod }
+ global CONFIG_GRUSBDC_I2
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I2 $CONFIG_GRUSBDC_I2 $notmod }
+ global CONFIG_GRUSBDC_I3
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I3 $CONFIG_GRUSBDC_I3 $notmod }
+ global CONFIG_GRUSBDC_I4
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I4 $CONFIG_GRUSBDC_I4 $notmod }
+ global CONFIG_GRUSBDC_I5
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I5 $CONFIG_GRUSBDC_I5 $notmod }
+ global CONFIG_GRUSBDC_I6
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I6 $CONFIG_GRUSBDC_I6 $notmod }
+ global CONFIG_GRUSBDC_I7
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I7 $CONFIG_GRUSBDC_I7 $notmod }
+ global CONFIG_GRUSBDC_I8
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I8 $CONFIG_GRUSBDC_I8 $notmod }
+ global CONFIG_GRUSBDC_I9
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I9 $CONFIG_GRUSBDC_I9 $notmod }
+ global CONFIG_GRUSBDC_I10
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I10 $CONFIG_GRUSBDC_I10 $notmod }
+ global CONFIG_GRUSBDC_I11
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I11 $CONFIG_GRUSBDC_I11 $notmod }
+ global CONFIG_GRUSBDC_I12
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I12 $CONFIG_GRUSBDC_I12 $notmod }
+ global CONFIG_GRUSBDC_I13
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I13 $CONFIG_GRUSBDC_I13 $notmod }
+ global CONFIG_GRUSBDC_I14
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I14 $CONFIG_GRUSBDC_I14 $notmod }
+ global CONFIG_GRUSBDC_I15
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_I15 $CONFIG_GRUSBDC_I15 $notmod }
+ global CONFIG_GRUSBDC_O0
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O0 $CONFIG_GRUSBDC_O0 $notmod }
+ global CONFIG_GRUSBDC_O1
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O1 $CONFIG_GRUSBDC_O1 $notmod }
+ global CONFIG_GRUSBDC_O2
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O2 $CONFIG_GRUSBDC_O2 $notmod }
+ global CONFIG_GRUSBDC_O3
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O3 $CONFIG_GRUSBDC_O3 $notmod }
+ global CONFIG_GRUSBDC_O4
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O4 $CONFIG_GRUSBDC_O4 $notmod }
+ global CONFIG_GRUSBDC_O5
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O5 $CONFIG_GRUSBDC_O5 $notmod }
+ global CONFIG_GRUSBDC_O6
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O6 $CONFIG_GRUSBDC_O6 $notmod }
+ global CONFIG_GRUSBDC_O7
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O7 $CONFIG_GRUSBDC_O7 $notmod }
+ global CONFIG_GRUSBDC_O8
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O8 $CONFIG_GRUSBDC_O8 $notmod }
+ global CONFIG_GRUSBDC_O9
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O9 $CONFIG_GRUSBDC_O9 $notmod }
+ global CONFIG_GRUSBDC_O10
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O10 $CONFIG_GRUSBDC_O10 $notmod }
+ global CONFIG_GRUSBDC_O11
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O11 $CONFIG_GRUSBDC_O11 $notmod }
+ global CONFIG_GRUSBDC_O12
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O12 $CONFIG_GRUSBDC_O12 $notmod }
+ global CONFIG_GRUSBDC_O13
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O13 $CONFIG_GRUSBDC_O13 $notmod }
+ global CONFIG_GRUSBDC_O14
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O14 $CONFIG_GRUSBDC_O14 $notmod }
+ global CONFIG_GRUSBDC_O15
+ if {($CONFIG_GRUSBDC_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRUSBDC_O15 $CONFIG_GRUSBDC_O15 $notmod }
+ write_comment $cfg $autocfg "UART, timer, I/O port and interrupt controller"
+ global CONFIG_UART1_ENABLE
+ write_tristate $cfg $autocfg CONFIG_UART1_ENABLE $CONFIG_UART1_ENABLE [list $notmod] 2
+ global tmpvar_31
+ if {($CONFIG_UART1_ENABLE == 1)} then {
+ if { $tmpvar_31 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 0 [list $notmod] 2 }
+ if { $tmpvar_31 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 0 [list $notmod] 2 }
+ if { $tmpvar_31 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 0 [list $notmod] 2 }
+ if { $tmpvar_31 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 0 [list $notmod] 2 }
+ if { $tmpvar_31 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 0 [list $notmod] 2 }
+ if { $tmpvar_31 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 0 [list $notmod] 2 }}
+ global CONFIG_UART2_ENABLE
+ if {($CONFIG_DSU_UART != 1)} then {write_tristate $cfg $autocfg CONFIG_UART2_ENABLE $CONFIG_UART2_ENABLE [list $notmod] 2 }
+ global tmpvar_32
+ if {($CONFIG_DSU_UART != 1) && ($CONFIG_UART2_ENABLE == 1)} then {
+ if { $tmpvar_32 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO1 0 [list $notmod] 2 }
+ if { $tmpvar_32 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO2 0 [list $notmod] 2 }
+ if { $tmpvar_32 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO4 0 [list $notmod] 2 }
+ if { $tmpvar_32 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO8 0 [list $notmod] 2 }
+ if { $tmpvar_32 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO16 0 [list $notmod] 2 }
+ if { $tmpvar_32 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO32 0 [list $notmod] 2 }}
+ global CONFIG_IRQ3_ENABLE
+ write_tristate $cfg $autocfg CONFIG_IRQ3_ENABLE $CONFIG_IRQ3_ENABLE [list $notmod] 2
+ global CONFIG_IRQ3_SEC
+ if {($CONFIG_IRQ3_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_IRQ3_SEC $CONFIG_IRQ3_SEC [list $notmod] 2 }
+ global CONFIG_IRQ3_NSEC
+ if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {write_int $cfg $autocfg CONFIG_IRQ3_NSEC $CONFIG_IRQ3_NSEC $notmod }
+ global CONFIG_GPT_ENABLE
+ write_tristate $cfg $autocfg CONFIG_GPT_ENABLE $CONFIG_GPT_ENABLE [list $notmod] 2
+ global CONFIG_GPT_NTIM
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_NTIM $CONFIG_GPT_NTIM $notmod }
+ global CONFIG_GPT_SW
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_SW $CONFIG_GPT_SW $notmod }
+ global CONFIG_GPT_TW
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_TW $CONFIG_GPT_TW $notmod }
+ global CONFIG_GPT_IRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_IRQ $CONFIG_GPT_IRQ $notmod }
+ global CONFIG_GPT_SEPIRQ
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_SEPIRQ $CONFIG_GPT_SEPIRQ [list $notmod] 2 }
+ global CONFIG_GPT_WDOGEN
+ if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_WDOGEN $CONFIG_GPT_WDOGEN [list $notmod] 2 }
+ global CONFIG_GPT_WDOG
+ if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {write_hex $cfg $autocfg CONFIG_GPT_WDOG $CONFIG_GPT_WDOG $notmod }
+ global CONFIG_GRGPIO_ENABLE
+ write_tristate $cfg $autocfg CONFIG_GRGPIO_ENABLE $CONFIG_GRGPIO_ENABLE [list $notmod] 2
+ global CONFIG_GRGPIO_WIDTH
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRGPIO_WIDTH $CONFIG_GRGPIO_WIDTH $notmod }
+ global CONFIG_GRGPIO_IMASK
+ if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_GRGPIO_IMASK $CONFIG_GRGPIO_IMASK $notmod }
+ write_comment $cfg $autocfg "Spacewire "
+ global CONFIG_SPW_ENABLE
+ write_tristate $cfg $autocfg CONFIG_SPW_ENABLE $CONFIG_SPW_ENABLE [list $notmod] 2
+ global CONFIG_SPW_NUM
+ if {($CONFIG_SPW_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPW_NUM $CONFIG_SPW_NUM $notmod }
+ global tmpvar_33
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ if { $tmpvar_33 == "4" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO4 0 [list $notmod] 2 }
+ if { $tmpvar_33 == "8" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO8 0 [list $notmod] 2 }
+ if { $tmpvar_33 == "16" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO16 0 [list $notmod] 2 }
+ if { $tmpvar_33 == "32" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO32 0 [list $notmod] 2 }}
+ global tmpvar_34
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ if { $tmpvar_34 == "16" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO16 0 [list $notmod] 2 }
+ if { $tmpvar_34 == "32" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO32 0 [list $notmod] 2 }
+ if { $tmpvar_34 == "64" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO64 0 [list $notmod] 2 }}
+ global CONFIG_SPW_RMAP
+ if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RMAP $CONFIG_SPW_RMAP [list $notmod] 2 }
+ global tmpvar_35
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_RMAP == 1)} then {
+ if { $tmpvar_35 == "64" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF2 0 [list $notmod] 2 }
+ if { $tmpvar_35 == "128" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF4 0 [list $notmod] 2 }
+ if { $tmpvar_35 == "192" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF6 0 [list $notmod] 2 }
+ if { $tmpvar_35 == "256" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF8 0 [list $notmod] 2 }}
+ global CONFIG_SPW_RMAPCRC
+ if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RMAPCRC $CONFIG_SPW_RMAPCRC [list $notmod] 2 }
+ global CONFIG_SPW_RXUNAL
+ if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RXUNAL $CONFIG_SPW_RXUNAL [list $notmod] 2 }
+ global CONFIG_SPW_FT
+ if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_FT $CONFIG_SPW_FT [list $notmod] 2 }
+ global CONFIG_SPW_NETLIST
+ if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_NETLIST $CONFIG_SPW_NETLIST [list $notmod] 2 }
+ global CONFIG_SPW_PORTS
+ if {($CONFIG_SPW_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPW_PORTS $CONFIG_SPW_PORTS $notmod }
+ global tmpvar_36
+ if {($CONFIG_SPW_ENABLE == 1)} then {
+ if { $tmpvar_36 == "1" } then { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW1 0 [list $notmod] 2 }
+ if { $tmpvar_36 == "2" } then { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW2 0 [list $notmod] 2 }}
+ global CONFIG_SPW_DMACHAN
+ global CONFIG_SPW_GRSPW2
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_int $cfg $autocfg CONFIG_SPW_DMACHAN $CONFIG_SPW_DMACHAN $notmod }
+ global CONFIG_SPW_RTSAME
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RTSAME $CONFIG_SPW_RTSAME [list $notmod] 2 }
+ global tmpvar_37
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {
+ if { $tmpvar_37 == "SDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_SDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_SDR 0 [list $notmod] 2 }
+ if { $tmpvar_37 == "DDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_DDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_DDR 0 [list $notmod] 2 }
+ if { $tmpvar_37 == "Xor" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_XOR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_XOR 0 [list $notmod] 2 }
+ if { $tmpvar_37 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_AFLEX 0 [list $notmod] 2 }}
+ global tmpvar_38
+ if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {
+ if { $tmpvar_38 == "SDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_SDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_SDR 0 [list $notmod] 2 }
+ if { $tmpvar_38 == "DDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_DDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_DDR 0 [list $notmod] 2 }
+ if { $tmpvar_38 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 0 [list $notmod] 2 }}
+ write_comment $cfg $autocfg "Keybord and VGA interface"
+ global CONFIG_KBD_ENABLE
+ write_tristate $cfg $autocfg CONFIG_KBD_ENABLE $CONFIG_KBD_ENABLE [list $notmod] 2
+ global CONFIG_VGA_ENABLE
+ write_tristate $cfg $autocfg CONFIG_VGA_ENABLE $CONFIG_VGA_ENABLE [list $notmod] 2
+ global CONFIG_SVGA_ENABLE
+ if {($CONFIG_VGA_ENABLE == 0)} then {write_tristate $cfg $autocfg CONFIG_SVGA_ENABLE $CONFIG_SVGA_ENABLE [list $notmod] 2 }
+ write_comment $cfg $autocfg "VHDL Debugging "
+ global CONFIG_DEBUG_UART
+ write_tristate $cfg $autocfg CONFIG_DEBUG_UART $CONFIG_DEBUG_UART [list $notmod] 2
+ close $cfg
+ close $autocfg
+}
+
+
+proc clear_choices { } {
+ global CONFIG_SYN_INFERRED; set CONFIG_SYN_INFERRED 0
+ global CONFIG_SYN_STRATIX; set CONFIG_SYN_STRATIX 0
+ global CONFIG_SYN_STRATIXII; set CONFIG_SYN_STRATIXII 0
+ global CONFIG_SYN_STRATIXIII; set CONFIG_SYN_STRATIXIII 0
+ global CONFIG_SYN_CYCLONEIII; set CONFIG_SYN_CYCLONEIII 0
+ global CONFIG_SYN_ALTERA; set CONFIG_SYN_ALTERA 0
+ global CONFIG_SYN_AXCEL; set CONFIG_SYN_AXCEL 0
+ global CONFIG_SYN_AXDSP; set CONFIG_SYN_AXDSP 0
+ global CONFIG_SYN_PROASIC; set CONFIG_SYN_PROASIC 0
+ global CONFIG_SYN_PROASICPLUS; set CONFIG_SYN_PROASICPLUS 0
+ global CONFIG_SYN_PROASIC3; set CONFIG_SYN_PROASIC3 0
+ global CONFIG_SYN_IGLOO; set CONFIG_SYN_IGLOO 0
+ global CONFIG_SYN_UT025CRH; set CONFIG_SYN_UT025CRH 0
+ global CONFIG_SYN_ATC18; set CONFIG_SYN_ATC18 0
+ global CONFIG_SYN_ATC18RHA; set CONFIG_SYN_ATC18RHA 0
+ global CONFIG_SYN_CUSTOM1; set CONFIG_SYN_CUSTOM1 0
+ global CONFIG_SYN_EASIC90; set CONFIG_SYN_EASIC90 0
+ global CONFIG_SYN_IHP25; set CONFIG_SYN_IHP25 0
+ global CONFIG_SYN_IHP25RH; set CONFIG_SYN_IHP25RH 0
+ global CONFIG_SYN_LATTICE; set CONFIG_SYN_LATTICE 0
+ global CONFIG_SYN_ECLIPSE; set CONFIG_SYN_ECLIPSE 0
+ global CONFIG_SYN_PEREGRINE; set CONFIG_SYN_PEREGRINE 0
+ global CONFIG_SYN_RH_LIB18T; set CONFIG_SYN_RH_LIB18T 0
+ global CONFIG_SYN_RHUMC; set CONFIG_SYN_RHUMC 0
+ global CONFIG_SYN_SMIC13; set CONFIG_SYN_SMIC13 0
+ global CONFIG_SYN_SPARTAN2; set CONFIG_SYN_SPARTAN2 0
+ global CONFIG_SYN_SPARTAN3; set CONFIG_SYN_SPARTAN3 0
+ global CONFIG_SYN_SPARTAN3E; set CONFIG_SYN_SPARTAN3E 0
+ global CONFIG_SYN_SPARTAN6; set CONFIG_SYN_SPARTAN6 0
+ global CONFIG_SYN_VIRTEX; set CONFIG_SYN_VIRTEX 0
+ global CONFIG_SYN_VIRTEXE; set CONFIG_SYN_VIRTEXE 0
+ global CONFIG_SYN_VIRTEX2; set CONFIG_SYN_VIRTEX2 0
+ global CONFIG_SYN_VIRTEX4; set CONFIG_SYN_VIRTEX4 0
+ global CONFIG_SYN_VIRTEX5; set CONFIG_SYN_VIRTEX5 0
+ global CONFIG_SYN_VIRTEX6; set CONFIG_SYN_VIRTEX6 0
+ global CONFIG_SYN_UMC; set CONFIG_SYN_UMC 0
+ global CONFIG_SYN_TSMC90; set CONFIG_SYN_TSMC90 0
+ global CONFIG_MEM_INFERRED; set CONFIG_MEM_INFERRED 0
+ global CONFIG_MEM_UMC; set CONFIG_MEM_UMC 0
+ global CONFIG_MEM_RHUMC; set CONFIG_MEM_RHUMC 0
+ global CONFIG_MEM_ARTISAN; set CONFIG_MEM_ARTISAN 0
+ global CONFIG_MEM_CUSTOM1; set CONFIG_MEM_CUSTOM1 0
+ global CONFIG_MEM_VIRAGE; set CONFIG_MEM_VIRAGE 0
+ global CONFIG_MEM_VIRAGE90; set CONFIG_MEM_VIRAGE90 0
+ global CONFIG_FPGA_1500; set CONFIG_FPGA_1500 0
+ global CONFIG_FPGA_2000; set CONFIG_FPGA_2000 0
+ global CONFIG_CLK_INFERRED; set CONFIG_CLK_INFERRED 0
+ global CONFIG_CLK_HCLKBUF; set CONFIG_CLK_HCLKBUF 0
+ global CONFIG_CLK_ALTDLL; set CONFIG_CLK_ALTDLL 0
+ global CONFIG_CLK_LATDLL; set CONFIG_CLK_LATDLL 0
+ global CONFIG_CLK_PRO3PLL; set CONFIG_CLK_PRO3PLL 0
+ global CONFIG_CLK_LIB18T; set CONFIG_CLK_LIB18T 0
+ global CONFIG_CLK_RHUMC; set CONFIG_CLK_RHUMC 0
+ global CONFIG_CLK_CLKDLL; set CONFIG_CLK_CLKDLL 0
+ global CONFIG_CLK_DCM; set CONFIG_CLK_DCM 0
+ global CONFIG_IU_MUL_LATENCY_2; set CONFIG_IU_MUL_LATENCY_2 0
+ global CONFIG_IU_MUL_LATENCY_4; set CONFIG_IU_MUL_LATENCY_4 0
+ global CONFIG_IU_MUL_LATENCY_5; set CONFIG_IU_MUL_LATENCY_5 0
+ global CONFIG_FPU_GRFPU; set CONFIG_FPU_GRFPU 0
+ global CONFIG_FPU_GRFPULITE; set CONFIG_FPU_GRFPULITE 0
+ global CONFIG_FPU_MEIKO; set CONFIG_FPU_MEIKO 0
+ global CONFIG_FPU_GRFPU_INFMUL; set CONFIG_FPU_GRFPU_INFMUL 0
+ global CONFIG_FPU_GRFPU_DWMUL; set CONFIG_FPU_GRFPU_DWMUL 0
+ global CONFIG_FPU_GRFPU_MODGEN; set CONFIG_FPU_GRFPU_MODGEN 0
+ global CONFIG_FPU_GRFPU_TECHSPEC; set CONFIG_FPU_GRFPU_TECHSPEC 0
+ global CONFIG_FPU_GRFPC0; set CONFIG_FPU_GRFPC0 0
+ global CONFIG_FPU_GRFPC1; set CONFIG_FPU_GRFPC1 0
+ global CONFIG_FPU_GRFPC2; set CONFIG_FPU_GRFPC2 0
+ global CONFIG_ICACHE_ASSO1; set CONFIG_ICACHE_ASSO1 0
+ global CONFIG_ICACHE_ASSO2; set CONFIG_ICACHE_ASSO2 0
+ global CONFIG_ICACHE_ASSO3; set CONFIG_ICACHE_ASSO3 0
+ global CONFIG_ICACHE_ASSO4; set CONFIG_ICACHE_ASSO4 0
+ global CONFIG_ICACHE_SZ1; set CONFIG_ICACHE_SZ1 0
+ global CONFIG_ICACHE_SZ2; set CONFIG_ICACHE_SZ2 0
+ global CONFIG_ICACHE_SZ4; set CONFIG_ICACHE_SZ4 0
+ global CONFIG_ICACHE_SZ8; set CONFIG_ICACHE_SZ8 0
+ global CONFIG_ICACHE_SZ16; set CONFIG_ICACHE_SZ16 0
+ global CONFIG_ICACHE_SZ32; set CONFIG_ICACHE_SZ32 0
+ global CONFIG_ICACHE_SZ64; set CONFIG_ICACHE_SZ64 0
+ global CONFIG_ICACHE_SZ128; set CONFIG_ICACHE_SZ128 0
+ global CONFIG_ICACHE_SZ256; set CONFIG_ICACHE_SZ256 0
+ global CONFIG_ICACHE_LZ16; set CONFIG_ICACHE_LZ16 0
+ global CONFIG_ICACHE_LZ32; set CONFIG_ICACHE_LZ32 0
+ global CONFIG_ICACHE_ALGORND; set CONFIG_ICACHE_ALGORND 0
+ global CONFIG_ICACHE_ALGOLRR; set CONFIG_ICACHE_ALGOLRR 0
+ global CONFIG_ICACHE_ALGOLRU; set CONFIG_ICACHE_ALGOLRU 0
+ global CONFIG_ICACHE_LRAM_SZ1; set CONFIG_ICACHE_LRAM_SZ1 0
+ global CONFIG_ICACHE_LRAM_SZ2; set CONFIG_ICACHE_LRAM_SZ2 0
+ global CONFIG_ICACHE_LRAM_SZ4; set CONFIG_ICACHE_LRAM_SZ4 0
+ global CONFIG_ICACHE_LRAM_SZ8; set CONFIG_ICACHE_LRAM_SZ8 0
+ global CONFIG_ICACHE_LRAM_SZ16; set CONFIG_ICACHE_LRAM_SZ16 0
+ global CONFIG_ICACHE_LRAM_SZ32; set CONFIG_ICACHE_LRAM_SZ32 0
+ global CONFIG_ICACHE_LRAM_SZ64; set CONFIG_ICACHE_LRAM_SZ64 0
+ global CONFIG_ICACHE_LRAM_SZ128; set CONFIG_ICACHE_LRAM_SZ128 0
+ global CONFIG_ICACHE_LRAM_SZ256; set CONFIG_ICACHE_LRAM_SZ256 0
+ global CONFIG_DCACHE_ASSO1; set CONFIG_DCACHE_ASSO1 0
+ global CONFIG_DCACHE_ASSO2; set CONFIG_DCACHE_ASSO2 0
+ global CONFIG_DCACHE_ASSO3; set CONFIG_DCACHE_ASSO3 0
+ global CONFIG_DCACHE_ASSO4; set CONFIG_DCACHE_ASSO4 0
+ global CONFIG_DCACHE_SZ1; set CONFIG_DCACHE_SZ1 0
+ global CONFIG_DCACHE_SZ2; set CONFIG_DCACHE_SZ2 0
+ global CONFIG_DCACHE_SZ4; set CONFIG_DCACHE_SZ4 0
+ global CONFIG_DCACHE_SZ8; set CONFIG_DCACHE_SZ8 0
+ global CONFIG_DCACHE_SZ16; set CONFIG_DCACHE_SZ16 0
+ global CONFIG_DCACHE_SZ32; set CONFIG_DCACHE_SZ32 0
+ global CONFIG_DCACHE_SZ64; set CONFIG_DCACHE_SZ64 0
+ global CONFIG_DCACHE_SZ128; set CONFIG_DCACHE_SZ128 0
+ global CONFIG_DCACHE_SZ256; set CONFIG_DCACHE_SZ256 0
+ global CONFIG_DCACHE_LZ16; set CONFIG_DCACHE_LZ16 0
+ global CONFIG_DCACHE_LZ32; set CONFIG_DCACHE_LZ32 0
+ global CONFIG_DCACHE_ALGORND; set CONFIG_DCACHE_ALGORND 0
+ global CONFIG_DCACHE_ALGOLRR; set CONFIG_DCACHE_ALGOLRR 0
+ global CONFIG_DCACHE_ALGOLRU; set CONFIG_DCACHE_ALGOLRU 0
+ global CONFIG_DCACHE_LRAM_SZ1; set CONFIG_DCACHE_LRAM_SZ1 0
+ global CONFIG_DCACHE_LRAM_SZ2; set CONFIG_DCACHE_LRAM_SZ2 0
+ global CONFIG_DCACHE_LRAM_SZ4; set CONFIG_DCACHE_LRAM_SZ4 0
+ global CONFIG_DCACHE_LRAM_SZ8; set CONFIG_DCACHE_LRAM_SZ8 0
+ global CONFIG_DCACHE_LRAM_SZ16; set CONFIG_DCACHE_LRAM_SZ16 0
+ global CONFIG_DCACHE_LRAM_SZ32; set CONFIG_DCACHE_LRAM_SZ32 0
+ global CONFIG_DCACHE_LRAM_SZ64; set CONFIG_DCACHE_LRAM_SZ64 0
+ global CONFIG_DCACHE_LRAM_SZ128; set CONFIG_DCACHE_LRAM_SZ128 0
+ global CONFIG_DCACHE_LRAM_SZ256; set CONFIG_DCACHE_LRAM_SZ256 0
+ global CONFIG_MMU_COMBINED; set CONFIG_MMU_COMBINED 0
+ global CONFIG_MMU_SPLIT; set CONFIG_MMU_SPLIT 0
+ global CONFIG_MMU_REPARRAY; set CONFIG_MMU_REPARRAY 0
+ global CONFIG_MMU_REPINCREMENT; set CONFIG_MMU_REPINCREMENT 0
+ global CONFIG_MMU_I2; set CONFIG_MMU_I2 0
+ global CONFIG_MMU_I4; set CONFIG_MMU_I4 0
+ global CONFIG_MMU_I8; set CONFIG_MMU_I8 0
+ global CONFIG_MMU_I16; set CONFIG_MMU_I16 0
+ global CONFIG_MMU_I32; set CONFIG_MMU_I32 0
+ global CONFIG_MMU_D2; set CONFIG_MMU_D2 0
+ global CONFIG_MMU_D4; set CONFIG_MMU_D4 0
+ global CONFIG_MMU_D8; set CONFIG_MMU_D8 0
+ global CONFIG_MMU_D16; set CONFIG_MMU_D16 0
+ global CONFIG_MMU_D32; set CONFIG_MMU_D32 0
+ global CONFIG_MMU_PAGE_4K; set CONFIG_MMU_PAGE_4K 0
+ global CONFIG_MMU_PAGE_8K; set CONFIG_MMU_PAGE_8K 0
+ global CONFIG_MMU_PAGE_16K; set CONFIG_MMU_PAGE_16K 0
+ global CONFIG_MMU_PAGE_32K; set CONFIG_MMU_PAGE_32K 0
+ global CONFIG_MMU_PAGE_PROG; set CONFIG_MMU_PAGE_PROG 0
+ global CONFIG_DSU_ITRACESZ1; set CONFIG_DSU_ITRACESZ1 0
+ global CONFIG_DSU_ITRACESZ2; set CONFIG_DSU_ITRACESZ2 0
+ global CONFIG_DSU_ITRACESZ4; set CONFIG_DSU_ITRACESZ4 0
+ global CONFIG_DSU_ITRACESZ8; set CONFIG_DSU_ITRACESZ8 0
+ global CONFIG_DSU_ITRACESZ16; set CONFIG_DSU_ITRACESZ16 0
+ global CONFIG_DSU_ATRACESZ1; set CONFIG_DSU_ATRACESZ1 0
+ global CONFIG_DSU_ATRACESZ2; set CONFIG_DSU_ATRACESZ2 0
+ global CONFIG_DSU_ATRACESZ4; set CONFIG_DSU_ATRACESZ4 0
+ global CONFIG_DSU_ATRACESZ8; set CONFIG_DSU_ATRACESZ8 0
+ global CONFIG_DSU_ATRACESZ16; set CONFIG_DSU_ATRACESZ16 0
+ global CONFIG_GRUSB_DCL_ULPI; set CONFIG_GRUSB_DCL_ULPI 0
+ global CONFIG_GRUSB_DCL_UTMI8; set CONFIG_GRUSB_DCL_UTMI8 0
+ global CONFIG_GRUSB_DCL_UTMI16; set CONFIG_GRUSB_DCL_UTMI16 0
+ global CONFIG_DSU_ETHSZ1; set CONFIG_DSU_ETHSZ1 0
+ global CONFIG_DSU_ETHSZ2; set CONFIG_DSU_ETHSZ2 0
+ global CONFIG_DSU_ETHSZ4; set CONFIG_DSU_ETHSZ4 0
+ global CONFIG_DSU_ETHSZ8; set CONFIG_DSU_ETHSZ8 0
+ global CONFIG_DSU_ETHSZ16; set CONFIG_DSU_ETHSZ16 0
+ global CONFIG_AHBRAM_SZ1; set CONFIG_AHBRAM_SZ1 0
+ global CONFIG_AHBRAM_SZ2; set CONFIG_AHBRAM_SZ2 0
+ global CONFIG_AHBRAM_SZ4; set CONFIG_AHBRAM_SZ4 0
+ global CONFIG_AHBRAM_SZ8; set CONFIG_AHBRAM_SZ8 0
+ global CONFIG_AHBRAM_SZ16; set CONFIG_AHBRAM_SZ16 0
+ global CONFIG_AHBRAM_SZ32; set CONFIG_AHBRAM_SZ32 0
+ global CONFIG_AHBRAM_SZ64; set CONFIG_AHBRAM_SZ64 0
+ global CONFIG_GRETH_FIFO4; set CONFIG_GRETH_FIFO4 0
+ global CONFIG_GRETH_FIFO8; set CONFIG_GRETH_FIFO8 0
+ global CONFIG_GRETH_FIFO16; set CONFIG_GRETH_FIFO16 0
+ global CONFIG_GRETH_FIFO32; set CONFIG_GRETH_FIFO32 0
+ global CONFIG_GRETH_FIFO64; set CONFIG_GRETH_FIFO64 0
+ global CONFIG_GRUSBDC_ULPI; set CONFIG_GRUSBDC_ULPI 0
+ global CONFIG_GRUSBDC_UTMI8; set CONFIG_GRUSBDC_UTMI8 0
+ global CONFIG_GRUSBDC_UTMI16; set CONFIG_GRUSBDC_UTMI16 0
+ global CONFIG_UA1_FIFO1; set CONFIG_UA1_FIFO1 0
+ global CONFIG_UA1_FIFO2; set CONFIG_UA1_FIFO2 0
+ global CONFIG_UA1_FIFO4; set CONFIG_UA1_FIFO4 0
+ global CONFIG_UA1_FIFO8; set CONFIG_UA1_FIFO8 0
+ global CONFIG_UA1_FIFO16; set CONFIG_UA1_FIFO16 0
+ global CONFIG_UA1_FIFO32; set CONFIG_UA1_FIFO32 0
+ global CONFIG_UA2_FIFO1; set CONFIG_UA2_FIFO1 0
+ global CONFIG_UA2_FIFO2; set CONFIG_UA2_FIFO2 0
+ global CONFIG_UA2_FIFO4; set CONFIG_UA2_FIFO4 0
+ global CONFIG_UA2_FIFO8; set CONFIG_UA2_FIFO8 0
+ global CONFIG_UA2_FIFO16; set CONFIG_UA2_FIFO16 0
+ global CONFIG_UA2_FIFO32; set CONFIG_UA2_FIFO32 0
+ global CONFIG_SPW_AHBFIFO4; set CONFIG_SPW_AHBFIFO4 0
+ global CONFIG_SPW_AHBFIFO8; set CONFIG_SPW_AHBFIFO8 0
+ global CONFIG_SPW_AHBFIFO16; set CONFIG_SPW_AHBFIFO16 0
+ global CONFIG_SPW_AHBFIFO32; set CONFIG_SPW_AHBFIFO32 0
+ global CONFIG_SPW_RXFIFO16; set CONFIG_SPW_RXFIFO16 0
+ global CONFIG_SPW_RXFIFO32; set CONFIG_SPW_RXFIFO32 0
+ global CONFIG_SPW_RXFIFO64; set CONFIG_SPW_RXFIFO64 0
+ global CONFIG_SPW_RMAPBUF2; set CONFIG_SPW_RMAPBUF2 0
+ global CONFIG_SPW_RMAPBUF4; set CONFIG_SPW_RMAPBUF4 0
+ global CONFIG_SPW_RMAPBUF6; set CONFIG_SPW_RMAPBUF6 0
+ global CONFIG_SPW_RMAPBUF8; set CONFIG_SPW_RMAPBUF8 0
+ global CONFIG_SPW_GRSPW1; set CONFIG_SPW_GRSPW1 0
+ global CONFIG_SPW_GRSPW2; set CONFIG_SPW_GRSPW2 0
+ global CONFIG_SPW_RX_SDR; set CONFIG_SPW_RX_SDR 0
+ global CONFIG_SPW_RX_DDR; set CONFIG_SPW_RX_DDR 0
+ global CONFIG_SPW_RX_XOR; set CONFIG_SPW_RX_XOR 0
+ global CONFIG_SPW_RX_AFLEX; set CONFIG_SPW_RX_AFLEX 0
+ global CONFIG_SPW_TX_SDR; set CONFIG_SPW_TX_SDR 0
+ global CONFIG_SPW_TX_DDR; set CONFIG_SPW_TX_DDR 0
+ global CONFIG_SPW_TX_AFLEX; set CONFIG_SPW_TX_AFLEX 0
+}
+
+
+proc update_choices { } {
+ global tmpvar_0
+ set tmpvar_0 "Inferred"
+ global CONFIG_SYN_INFERRED
+ if { $CONFIG_SYN_INFERRED == 1 } then { set tmpvar_0 "Inferred" }
+ global CONFIG_SYN_STRATIX
+ if { $CONFIG_SYN_STRATIX == 1 } then { set tmpvar_0 "Altera-Stratix" }
+ global CONFIG_SYN_STRATIXII
+ if { $CONFIG_SYN_STRATIXII == 1 } then { set tmpvar_0 "Altera-StratixII" }
+ global CONFIG_SYN_STRATIXIII
+ if { $CONFIG_SYN_STRATIXIII == 1 } then { set tmpvar_0 "Altera-StratixIII" }
+ global CONFIG_SYN_CYCLONEIII
+ if { $CONFIG_SYN_CYCLONEIII == 1 } then { set tmpvar_0 "Altera-CycloneIII" }
+ global CONFIG_SYN_ALTERA
+ if { $CONFIG_SYN_ALTERA == 1 } then { set tmpvar_0 "Altera-Others" }
+ global CONFIG_SYN_AXCEL
+ if { $CONFIG_SYN_AXCEL == 1 } then { set tmpvar_0 "Actel-Axcelerator" }
+ global CONFIG_SYN_AXDSP
+ if { $CONFIG_SYN_AXDSP == 1 } then { set tmpvar_0 "Actel-Axcelerator-DSP" }
+ global CONFIG_SYN_PROASIC
+ if { $CONFIG_SYN_PROASIC == 1 } then { set tmpvar_0 "Actel-Proasic" }
+ global CONFIG_SYN_PROASICPLUS
+ if { $CONFIG_SYN_PROASICPLUS == 1 } then { set tmpvar_0 "Actel-ProasicPlus" }
+ global CONFIG_SYN_PROASIC3
+ if { $CONFIG_SYN_PROASIC3 == 1 } then { set tmpvar_0 "Actel-Proasic3/E/L" }
+ global CONFIG_SYN_IGLOO
+ if { $CONFIG_SYN_IGLOO == 1 } then { set tmpvar_0 "Actel-IGLOO/p/L" }
+ global CONFIG_SYN_UT025CRH
+ if { $CONFIG_SYN_UT025CRH == 1 } then { set tmpvar_0 "Aeroflex-UT025CRH" }
+ global CONFIG_SYN_ATC18
+ if { $CONFIG_SYN_ATC18 == 1 } then { set tmpvar_0 "Atmel-ATC18" }
+ global CONFIG_SYN_ATC18RHA
+ if { $CONFIG_SYN_ATC18RHA == 1 } then { set tmpvar_0 "Atmel-ATC18RHA" }
+ global CONFIG_SYN_CUSTOM1
+ if { $CONFIG_SYN_CUSTOM1 == 1 } then { set tmpvar_0 "Custom1" }
+ global CONFIG_SYN_EASIC90
+ if { $CONFIG_SYN_EASIC90 == 1 } then { set tmpvar_0 "eASIC90" }
+ global CONFIG_SYN_IHP25
+ if { $CONFIG_SYN_IHP25 == 1 } then { set tmpvar_0 "IHP25" }
+ global CONFIG_SYN_IHP25RH
+ if { $CONFIG_SYN_IHP25RH == 1 } then { set tmpvar_0 "IHP25RH" }
+ global CONFIG_SYN_LATTICE
+ if { $CONFIG_SYN_LATTICE == 1 } then { set tmpvar_0 "Lattice-EC/ECP/XP" }
+ global CONFIG_SYN_ECLIPSE
+ if { $CONFIG_SYN_ECLIPSE == 1 } then { set tmpvar_0 "Quicklogic-Eclipse" }
+ global CONFIG_SYN_PEREGRINE
+ if { $CONFIG_SYN_PEREGRINE == 1 } then { set tmpvar_0 "Peregrine" }
+ global CONFIG_SYN_RH_LIB18T
+ if { $CONFIG_SYN_RH_LIB18T == 1 } then { set tmpvar_0 "RH-LIB18T" }
+ global CONFIG_SYN_RHUMC
+ if { $CONFIG_SYN_RHUMC == 1 } then { set tmpvar_0 "RH-UMC" }
+ global CONFIG_SYN_SMIC13
+ if { $CONFIG_SYN_SMIC13 == 1 } then { set tmpvar_0 "SMIC130" }
+ global CONFIG_SYN_SPARTAN2
+ if { $CONFIG_SYN_SPARTAN2 == 1 } then { set tmpvar_0 "Xilinx-Spartan2" }
+ global CONFIG_SYN_SPARTAN3
+ if { $CONFIG_SYN_SPARTAN3 == 1 } then { set tmpvar_0 "Xilinx-Spartan3" }
+ global CONFIG_SYN_SPARTAN3E
+ if { $CONFIG_SYN_SPARTAN3E == 1 } then { set tmpvar_0 "Xilinx-Spartan3E" }
+ global CONFIG_SYN_SPARTAN6
+ if { $CONFIG_SYN_SPARTAN6 == 1 } then { set tmpvar_0 "Xilinx-Spartan6" }
+ global CONFIG_SYN_VIRTEX
+ if { $CONFIG_SYN_VIRTEX == 1 } then { set tmpvar_0 "Xilinx-Virtex" }
+ global CONFIG_SYN_VIRTEXE
+ if { $CONFIG_SYN_VIRTEXE == 1 } then { set tmpvar_0 "Xilinx-VirtexE" }
+ global CONFIG_SYN_VIRTEX2
+ if { $CONFIG_SYN_VIRTEX2 == 1 } then { set tmpvar_0 "Xilinx-Virtex2" }
+ global CONFIG_SYN_VIRTEX4
+ if { $CONFIG_SYN_VIRTEX4 == 1 } then { set tmpvar_0 "Xilinx-Virtex4" }
+ global CONFIG_SYN_VIRTEX5
+ if { $CONFIG_SYN_VIRTEX5 == 1 } then { set tmpvar_0 "Xilinx-Virtex5" }
+ global CONFIG_SYN_VIRTEX6
+ if { $CONFIG_SYN_VIRTEX6 == 1 } then { set tmpvar_0 "Xilinx-Virtex6" }
+ global CONFIG_SYN_UMC
+ if { $CONFIG_SYN_UMC == 1 } then { set tmpvar_0 "UMC180" }
+ global CONFIG_SYN_TSMC90
+ if { $CONFIG_SYN_TSMC90 == 1 } then { set tmpvar_0 "TSMC90" }
+ global tmpvar_1
+ set tmpvar_1 "Inferred"
+ global CONFIG_MEM_INFERRED
+ if { $CONFIG_MEM_INFERRED == 1 } then { set tmpvar_1 "Inferred" }
+ global CONFIG_MEM_UMC
+ if { $CONFIG_MEM_UMC == 1 } then { set tmpvar_1 "UMC18" }
+ global CONFIG_MEM_RHUMC
+ if { $CONFIG_MEM_RHUMC == 1 } then { set tmpvar_1 "RH-UMC" }
+ global CONFIG_MEM_ARTISAN
+ if { $CONFIG_MEM_ARTISAN == 1 } then { set tmpvar_1 "Artisan" }
+ global CONFIG_MEM_CUSTOM1
+ if { $CONFIG_MEM_CUSTOM1 == 1 } then { set tmpvar_1 "Custom1" }
+ global CONFIG_MEM_VIRAGE
+ if { $CONFIG_MEM_VIRAGE == 1 } then { set tmpvar_1 "Virage" }
+ global CONFIG_MEM_VIRAGE90
+ if { $CONFIG_MEM_VIRAGE90 == 1 } then { set tmpvar_1 "Virage-TSMC90" }
+ global tmpvar_2
+ set tmpvar_2 "XC3S-1500"
+ global CONFIG_FPGA_1500
+ if { $CONFIG_FPGA_1500 == 1 } then { set tmpvar_2 "XC3S-1500" }
+ global CONFIG_FPGA_2000
+ if { $CONFIG_FPGA_2000 == 1 } then { set tmpvar_2 "XC3S-2000" }
+ global tmpvar_3
+ set tmpvar_3 "Inferred"
+ global CONFIG_CLK_INFERRED
+ if { $CONFIG_CLK_INFERRED == 1 } then { set tmpvar_3 "Inferred" }
+ global CONFIG_CLK_HCLKBUF
+ if { $CONFIG_CLK_HCLKBUF == 1 } then { set tmpvar_3 "Actel-HCLKBUF" }
+ global CONFIG_CLK_ALTDLL
+ if { $CONFIG_CLK_ALTDLL == 1 } then { set tmpvar_3 "Altera-ALTPLL" }
+ global CONFIG_CLK_LATDLL
+ if { $CONFIG_CLK_LATDLL == 1 } then { set tmpvar_3 "Lattice-EXPLL" }
+ global CONFIG_CLK_PRO3PLL
+ if { $CONFIG_CLK_PRO3PLL == 1 } then { set tmpvar_3 "Proasic3-PLLL" }
+ global CONFIG_CLK_LIB18T
+ if { $CONFIG_CLK_LIB18T == 1 } then { set tmpvar_3 "RH-LIB18T-PLL" }
+ global CONFIG_CLK_RHUMC
+ if { $CONFIG_CLK_RHUMC == 1 } then { set tmpvar_3 "DARE-PLL" }
+ global CONFIG_CLK_CLKDLL
+ if { $CONFIG_CLK_CLKDLL == 1 } then { set tmpvar_3 "Xilinx-CLKDLL" }
+ global CONFIG_CLK_DCM
+ if { $CONFIG_CLK_DCM == 1 } then { set tmpvar_3 "Xilinx-DCM" }
+ global tmpvar_4
+ set tmpvar_4 "5-cycles"
+ global CONFIG_IU_MUL_LATENCY_2
+ if { $CONFIG_IU_MUL_LATENCY_2 == 1 } then { set tmpvar_4 "2-cycles" }
+ global CONFIG_IU_MUL_LATENCY_4
+ if { $CONFIG_IU_MUL_LATENCY_4 == 1 } then { set tmpvar_4 "4-cycles" }
+ global CONFIG_IU_MUL_LATENCY_5
+ if { $CONFIG_IU_MUL_LATENCY_5 == 1 } then { set tmpvar_4 "5-cycles" }
+ global tmpvar_5
+ set tmpvar_5 "GRFPU"
+ global CONFIG_FPU_GRFPU
+ if { $CONFIG_FPU_GRFPU == 1 } then { set tmpvar_5 "GRFPU" }
+ global CONFIG_FPU_GRFPULITE
+ if { $CONFIG_FPU_GRFPULITE == 1 } then { set tmpvar_5 "GRFPU-LITE" }
+ global CONFIG_FPU_MEIKO
+ if { $CONFIG_FPU_MEIKO == 1 } then { set tmpvar_5 "Meiko" }
+ global tmpvar_6
+ set tmpvar_6 "Inferred"
+ global CONFIG_FPU_GRFPU_INFMUL
+ if { $CONFIG_FPU_GRFPU_INFMUL == 1 } then { set tmpvar_6 "Inferred" }
+ global CONFIG_FPU_GRFPU_DWMUL
+ if { $CONFIG_FPU_GRFPU_DWMUL == 1 } then { set tmpvar_6 "DW" }
+ global CONFIG_FPU_GRFPU_MODGEN
+ if { $CONFIG_FPU_GRFPU_MODGEN == 1 } then { set tmpvar_6 "ModGen" }
+ global CONFIG_FPU_GRFPU_TECHSPEC
+ if { $CONFIG_FPU_GRFPU_TECHSPEC == 1 } then { set tmpvar_6 "TechSpec" }
+ global tmpvar_7
+ set tmpvar_7 "Simple"
+ global CONFIG_FPU_GRFPC0
+ if { $CONFIG_FPU_GRFPC0 == 1 } then { set tmpvar_7 "Simple" }
+ global CONFIG_FPU_GRFPC1
+ if { $CONFIG_FPU_GRFPC1 == 1 } then { set tmpvar_7 "Data-forwarding" }
+ global CONFIG_FPU_GRFPC2
+ if { $CONFIG_FPU_GRFPC2 == 1 } then { set tmpvar_7 "Non-blocking" }
+ global tmpvar_8
+ set tmpvar_8 "1"
+ global CONFIG_ICACHE_ASSO1
+ if { $CONFIG_ICACHE_ASSO1 == 1 } then { set tmpvar_8 "1" }
+ global CONFIG_ICACHE_ASSO2
+ if { $CONFIG_ICACHE_ASSO2 == 1 } then { set tmpvar_8 "2" }
+ global CONFIG_ICACHE_ASSO3
+ if { $CONFIG_ICACHE_ASSO3 == 1 } then { set tmpvar_8 "3" }
+ global CONFIG_ICACHE_ASSO4
+ if { $CONFIG_ICACHE_ASSO4 == 1 } then { set tmpvar_8 "4" }
+ global tmpvar_9
+ set tmpvar_9 "4"
+ global CONFIG_ICACHE_SZ1
+ if { $CONFIG_ICACHE_SZ1 == 1 } then { set tmpvar_9 "1" }
+ global CONFIG_ICACHE_SZ2
+ if { $CONFIG_ICACHE_SZ2 == 1 } then { set tmpvar_9 "2" }
+ global CONFIG_ICACHE_SZ4
+ if { $CONFIG_ICACHE_SZ4 == 1 } then { set tmpvar_9 "4" }
+ global CONFIG_ICACHE_SZ8
+ if { $CONFIG_ICACHE_SZ8 == 1 } then { set tmpvar_9 "8" }
+ global CONFIG_ICACHE_SZ16
+ if { $CONFIG_ICACHE_SZ16 == 1 } then { set tmpvar_9 "16" }
+ global CONFIG_ICACHE_SZ32
+ if { $CONFIG_ICACHE_SZ32 == 1 } then { set tmpvar_9 "32" }
+ global CONFIG_ICACHE_SZ64
+ if { $CONFIG_ICACHE_SZ64 == 1 } then { set tmpvar_9 "64" }
+ global CONFIG_ICACHE_SZ128
+ if { $CONFIG_ICACHE_SZ128 == 1 } then { set tmpvar_9 "128" }
+ global CONFIG_ICACHE_SZ256
+ if { $CONFIG_ICACHE_SZ256 == 1 } then { set tmpvar_9 "256" }
+ global tmpvar_10
+ set tmpvar_10 "32"
+ global CONFIG_ICACHE_LZ16
+ if { $CONFIG_ICACHE_LZ16 == 1 } then { set tmpvar_10 "16" }
+ global CONFIG_ICACHE_LZ32
+ if { $CONFIG_ICACHE_LZ32 == 1 } then { set tmpvar_10 "32" }
+ global tmpvar_11
+ set tmpvar_11 "Random"
+ global CONFIG_ICACHE_ALGORND
+ if { $CONFIG_ICACHE_ALGORND == 1 } then { set tmpvar_11 "Random" }
+ global CONFIG_ICACHE_ALGOLRR
+ if { $CONFIG_ICACHE_ALGOLRR == 1 } then { set tmpvar_11 "LRR" }
+ global CONFIG_ICACHE_ALGOLRU
+ if { $CONFIG_ICACHE_ALGOLRU == 1 } then { set tmpvar_11 "LRU" }
+ global tmpvar_12
+ set tmpvar_12 "4"
+ global CONFIG_ICACHE_LRAM_SZ1
+ if { $CONFIG_ICACHE_LRAM_SZ1 == 1 } then { set tmpvar_12 "1" }
+ global CONFIG_ICACHE_LRAM_SZ2
+ if { $CONFIG_ICACHE_LRAM_SZ2 == 1 } then { set tmpvar_12 "2" }
+ global CONFIG_ICACHE_LRAM_SZ4
+ if { $CONFIG_ICACHE_LRAM_SZ4 == 1 } then { set tmpvar_12 "4" }
+ global CONFIG_ICACHE_LRAM_SZ8
+ if { $CONFIG_ICACHE_LRAM_SZ8 == 1 } then { set tmpvar_12 "8" }
+ global CONFIG_ICACHE_LRAM_SZ16
+ if { $CONFIG_ICACHE_LRAM_SZ16 == 1 } then { set tmpvar_12 "16" }
+ global CONFIG_ICACHE_LRAM_SZ32
+ if { $CONFIG_ICACHE_LRAM_SZ32 == 1 } then { set tmpvar_12 "32" }
+ global CONFIG_ICACHE_LRAM_SZ64
+ if { $CONFIG_ICACHE_LRAM_SZ64 == 1 } then { set tmpvar_12 "64" }
+ global CONFIG_ICACHE_LRAM_SZ128
+ if { $CONFIG_ICACHE_LRAM_SZ128 == 1 } then { set tmpvar_12 "128" }
+ global CONFIG_ICACHE_LRAM_SZ256
+ if { $CONFIG_ICACHE_LRAM_SZ256 == 1 } then { set tmpvar_12 "256" }
+ global tmpvar_13
+ set tmpvar_13 "1"
+ global CONFIG_DCACHE_ASSO1
+ if { $CONFIG_DCACHE_ASSO1 == 1 } then { set tmpvar_13 "1" }
+ global CONFIG_DCACHE_ASSO2
+ if { $CONFIG_DCACHE_ASSO2 == 1 } then { set tmpvar_13 "2" }
+ global CONFIG_DCACHE_ASSO3
+ if { $CONFIG_DCACHE_ASSO3 == 1 } then { set tmpvar_13 "3" }
+ global CONFIG_DCACHE_ASSO4
+ if { $CONFIG_DCACHE_ASSO4 == 1 } then { set tmpvar_13 "4" }
+ global tmpvar_14
+ set tmpvar_14 "4"
+ global CONFIG_DCACHE_SZ1
+ if { $CONFIG_DCACHE_SZ1 == 1 } then { set tmpvar_14 "1" }
+ global CONFIG_DCACHE_SZ2
+ if { $CONFIG_DCACHE_SZ2 == 1 } then { set tmpvar_14 "2" }
+ global CONFIG_DCACHE_SZ4
+ if { $CONFIG_DCACHE_SZ4 == 1 } then { set tmpvar_14 "4" }
+ global CONFIG_DCACHE_SZ8
+ if { $CONFIG_DCACHE_SZ8 == 1 } then { set tmpvar_14 "8" }
+ global CONFIG_DCACHE_SZ16
+ if { $CONFIG_DCACHE_SZ16 == 1 } then { set tmpvar_14 "16" }
+ global CONFIG_DCACHE_SZ32
+ if { $CONFIG_DCACHE_SZ32 == 1 } then { set tmpvar_14 "32" }
+ global CONFIG_DCACHE_SZ64
+ if { $CONFIG_DCACHE_SZ64 == 1 } then { set tmpvar_14 "64" }
+ global CONFIG_DCACHE_SZ128
+ if { $CONFIG_DCACHE_SZ128 == 1 } then { set tmpvar_14 "128" }
+ global CONFIG_DCACHE_SZ256
+ if { $CONFIG_DCACHE_SZ256 == 1 } then { set tmpvar_14 "256" }
+ global tmpvar_15
+ set tmpvar_15 "32"
+ global CONFIG_DCACHE_LZ16
+ if { $CONFIG_DCACHE_LZ16 == 1 } then { set tmpvar_15 "16" }
+ global CONFIG_DCACHE_LZ32
+ if { $CONFIG_DCACHE_LZ32 == 1 } then { set tmpvar_15 "32" }
+ global tmpvar_16
+ set tmpvar_16 "Random"
+ global CONFIG_DCACHE_ALGORND
+ if { $CONFIG_DCACHE_ALGORND == 1 } then { set tmpvar_16 "Random" }
+ global CONFIG_DCACHE_ALGOLRR
+ if { $CONFIG_DCACHE_ALGOLRR == 1 } then { set tmpvar_16 "LRR" }
+ global CONFIG_DCACHE_ALGOLRU
+ if { $CONFIG_DCACHE_ALGOLRU == 1 } then { set tmpvar_16 "LRU" }
+ global tmpvar_17
+ set tmpvar_17 "4"
+ global CONFIG_DCACHE_LRAM_SZ1
+ if { $CONFIG_DCACHE_LRAM_SZ1 == 1 } then { set tmpvar_17 "1" }
+ global CONFIG_DCACHE_LRAM_SZ2
+ if { $CONFIG_DCACHE_LRAM_SZ2 == 1 } then { set tmpvar_17 "2" }
+ global CONFIG_DCACHE_LRAM_SZ4
+ if { $CONFIG_DCACHE_LRAM_SZ4 == 1 } then { set tmpvar_17 "4" }
+ global CONFIG_DCACHE_LRAM_SZ8
+ if { $CONFIG_DCACHE_LRAM_SZ8 == 1 } then { set tmpvar_17 "8" }
+ global CONFIG_DCACHE_LRAM_SZ16
+ if { $CONFIG_DCACHE_LRAM_SZ16 == 1 } then { set tmpvar_17 "16" }
+ global CONFIG_DCACHE_LRAM_SZ32
+ if { $CONFIG_DCACHE_LRAM_SZ32 == 1 } then { set tmpvar_17 "32" }
+ global CONFIG_DCACHE_LRAM_SZ64
+ if { $CONFIG_DCACHE_LRAM_SZ64 == 1 } then { set tmpvar_17 "64" }
+ global CONFIG_DCACHE_LRAM_SZ128
+ if { $CONFIG_DCACHE_LRAM_SZ128 == 1 } then { set tmpvar_17 "128" }
+ global CONFIG_DCACHE_LRAM_SZ256
+ if { $CONFIG_DCACHE_LRAM_SZ256 == 1 } then { set tmpvar_17 "256" }
+ global tmpvar_18
+ set tmpvar_18 "combined"
+ global CONFIG_MMU_COMBINED
+ if { $CONFIG_MMU_COMBINED == 1 } then { set tmpvar_18 "combined" }
+ global CONFIG_MMU_SPLIT
+ if { $CONFIG_MMU_SPLIT == 1 } then { set tmpvar_18 "split" }
+ global tmpvar_19
+ set tmpvar_19 "Increment"
+ global CONFIG_MMU_REPARRAY
+ if { $CONFIG_MMU_REPARRAY == 1 } then { set tmpvar_19 "LRU" }
+ global CONFIG_MMU_REPINCREMENT
+ if { $CONFIG_MMU_REPINCREMENT == 1 } then { set tmpvar_19 "Increment" }
+ global tmpvar_20
+ set tmpvar_20 "8"
+ global CONFIG_MMU_I2
+ if { $CONFIG_MMU_I2 == 1 } then { set tmpvar_20 "2" }
+ global CONFIG_MMU_I4
+ if { $CONFIG_MMU_I4 == 1 } then { set tmpvar_20 "4" }
+ global CONFIG_MMU_I8
+ if { $CONFIG_MMU_I8 == 1 } then { set tmpvar_20 "8" }
+ global CONFIG_MMU_I16
+ if { $CONFIG_MMU_I16 == 1 } then { set tmpvar_20 "16" }
+ global CONFIG_MMU_I32
+ if { $CONFIG_MMU_I32 == 1 } then { set tmpvar_20 "32" }
+ global tmpvar_21
+ set tmpvar_21 "8"
+ global CONFIG_MMU_D2
+ if { $CONFIG_MMU_D2 == 1 } then { set tmpvar_21 "2" }
+ global CONFIG_MMU_D4
+ if { $CONFIG_MMU_D4 == 1 } then { set tmpvar_21 "4" }
+ global CONFIG_MMU_D8
+ if { $CONFIG_MMU_D8 == 1 } then { set tmpvar_21 "8" }
+ global CONFIG_MMU_D16
+ if { $CONFIG_MMU_D16 == 1 } then { set tmpvar_21 "16" }
+ global CONFIG_MMU_D32
+ if { $CONFIG_MMU_D32 == 1 } then { set tmpvar_21 "32" }
+ global tmpvar_22
+ set tmpvar_22 "4K"
+ global CONFIG_MMU_PAGE_4K
+ if { $CONFIG_MMU_PAGE_4K == 1 } then { set tmpvar_22 "4K" }
+ global CONFIG_MMU_PAGE_8K
+ if { $CONFIG_MMU_PAGE_8K == 1 } then { set tmpvar_22 "8K" }
+ global CONFIG_MMU_PAGE_16K
+ if { $CONFIG_MMU_PAGE_16K == 1 } then { set tmpvar_22 "16K" }
+ global CONFIG_MMU_PAGE_32K
+ if { $CONFIG_MMU_PAGE_32K == 1 } then { set tmpvar_22 "32K" }
+ global CONFIG_MMU_PAGE_PROG
+ if { $CONFIG_MMU_PAGE_PROG == 1 } then { set tmpvar_22 "Programmable" }
+ global tmpvar_23
+ set tmpvar_23 "1"
+ global CONFIG_DSU_ITRACESZ1
+ if { $CONFIG_DSU_ITRACESZ1 == 1 } then { set tmpvar_23 "1" }
+ global CONFIG_DSU_ITRACESZ2
+ if { $CONFIG_DSU_ITRACESZ2 == 1 } then { set tmpvar_23 "2" }
+ global CONFIG_DSU_ITRACESZ4
+ if { $CONFIG_DSU_ITRACESZ4 == 1 } then { set tmpvar_23 "4" }
+ global CONFIG_DSU_ITRACESZ8
+ if { $CONFIG_DSU_ITRACESZ8 == 1 } then { set tmpvar_23 "8" }
+ global CONFIG_DSU_ITRACESZ16
+ if { $CONFIG_DSU_ITRACESZ16 == 1 } then { set tmpvar_23 "16" }
+ global tmpvar_24
+ set tmpvar_24 "1"
+ global CONFIG_DSU_ATRACESZ1
+ if { $CONFIG_DSU_ATRACESZ1 == 1 } then { set tmpvar_24 "1" }
+ global CONFIG_DSU_ATRACESZ2
+ if { $CONFIG_DSU_ATRACESZ2 == 1 } then { set tmpvar_24 "2" }
+ global CONFIG_DSU_ATRACESZ4
+ if { $CONFIG_DSU_ATRACESZ4 == 1 } then { set tmpvar_24 "4" }
+ global CONFIG_DSU_ATRACESZ8
+ if { $CONFIG_DSU_ATRACESZ8 == 1 } then { set tmpvar_24 "8" }
+ global CONFIG_DSU_ATRACESZ16
+ if { $CONFIG_DSU_ATRACESZ16 == 1 } then { set tmpvar_24 "16" }
+ global tmpvar_26
+ set tmpvar_26 "ULPI"
+ global CONFIG_GRUSB_DCL_ULPI
+ if { $CONFIG_GRUSB_DCL_ULPI == 1 } then { set tmpvar_26 "ULPI" }
+ global CONFIG_GRUSB_DCL_UTMI8
+ if { $CONFIG_GRUSB_DCL_UTMI8 == 1 } then { set tmpvar_26 "UTMI/UTMI+8-bit" }
+ global CONFIG_GRUSB_DCL_UTMI16
+ if { $CONFIG_GRUSB_DCL_UTMI16 == 1 } then { set tmpvar_26 "UTMI/UTMI+16-bit" }
+ global tmpvar_27
+ set tmpvar_27 "2"
+ global CONFIG_DSU_ETHSZ1
+ if { $CONFIG_DSU_ETHSZ1 == 1 } then { set tmpvar_27 "1" }
+ global CONFIG_DSU_ETHSZ2
+ if { $CONFIG_DSU_ETHSZ2 == 1 } then { set tmpvar_27 "2" }
+ global CONFIG_DSU_ETHSZ4
+ if { $CONFIG_DSU_ETHSZ4 == 1 } then { set tmpvar_27 "4" }
+ global CONFIG_DSU_ETHSZ8
+ if { $CONFIG_DSU_ETHSZ8 == 1 } then { set tmpvar_27 "8" }
+ global CONFIG_DSU_ETHSZ16
+ if { $CONFIG_DSU_ETHSZ16 == 1 } then { set tmpvar_27 "16" }
+ global tmpvar_28
+ set tmpvar_28 "4"
+ global CONFIG_AHBRAM_SZ1
+ if { $CONFIG_AHBRAM_SZ1 == 1 } then { set tmpvar_28 "1" }
+ global CONFIG_AHBRAM_SZ2
+ if { $CONFIG_AHBRAM_SZ2 == 1 } then { set tmpvar_28 "2" }
+ global CONFIG_AHBRAM_SZ4
+ if { $CONFIG_AHBRAM_SZ4 == 1 } then { set tmpvar_28 "4" }
+ global CONFIG_AHBRAM_SZ8
+ if { $CONFIG_AHBRAM_SZ8 == 1 } then { set tmpvar_28 "8" }
+ global CONFIG_AHBRAM_SZ16
+ if { $CONFIG_AHBRAM_SZ16 == 1 } then { set tmpvar_28 "16" }
+ global CONFIG_AHBRAM_SZ32
+ if { $CONFIG_AHBRAM_SZ32 == 1 } then { set tmpvar_28 "32" }
+ global CONFIG_AHBRAM_SZ64
+ if { $CONFIG_AHBRAM_SZ64 == 1 } then { set tmpvar_28 "64" }
+ global tmpvar_29
+ set tmpvar_29 "8"
+ global CONFIG_GRETH_FIFO4
+ if { $CONFIG_GRETH_FIFO4 == 1 } then { set tmpvar_29 "4" }
+ global CONFIG_GRETH_FIFO8
+ if { $CONFIG_GRETH_FIFO8 == 1 } then { set tmpvar_29 "8" }
+ global CONFIG_GRETH_FIFO16
+ if { $CONFIG_GRETH_FIFO16 == 1 } then { set tmpvar_29 "16" }
+ global CONFIG_GRETH_FIFO32
+ if { $CONFIG_GRETH_FIFO32 == 1 } then { set tmpvar_29 "32" }
+ global CONFIG_GRETH_FIFO64
+ if { $CONFIG_GRETH_FIFO64 == 1 } then { set tmpvar_29 "64" }
+ global tmpvar_30
+ set tmpvar_30 "ULPI"
+ global CONFIG_GRUSBDC_ULPI
+ if { $CONFIG_GRUSBDC_ULPI == 1 } then { set tmpvar_30 "ULPI" }
+ global CONFIG_GRUSBDC_UTMI8
+ if { $CONFIG_GRUSBDC_UTMI8 == 1 } then { set tmpvar_30 "UTMI/UTMI+8-bit" }
+ global CONFIG_GRUSBDC_UTMI16
+ if { $CONFIG_GRUSBDC_UTMI16 == 1 } then { set tmpvar_30 "UTMI/UTMI+16-bit" }
+ global tmpvar_31
+ set tmpvar_31 "1"
+ global CONFIG_UA1_FIFO1
+ if { $CONFIG_UA1_FIFO1 == 1 } then { set tmpvar_31 "1" }
+ global CONFIG_UA1_FIFO2
+ if { $CONFIG_UA1_FIFO2 == 1 } then { set tmpvar_31 "2" }
+ global CONFIG_UA1_FIFO4
+ if { $CONFIG_UA1_FIFO4 == 1 } then { set tmpvar_31 "4" }
+ global CONFIG_UA1_FIFO8
+ if { $CONFIG_UA1_FIFO8 == 1 } then { set tmpvar_31 "8" }
+ global CONFIG_UA1_FIFO16
+ if { $CONFIG_UA1_FIFO16 == 1 } then { set tmpvar_31 "16" }
+ global CONFIG_UA1_FIFO32
+ if { $CONFIG_UA1_FIFO32 == 1 } then { set tmpvar_31 "32" }
+ global tmpvar_32
+ set tmpvar_32 "1"
+ global CONFIG_UA2_FIFO1
+ if { $CONFIG_UA2_FIFO1 == 1 } then { set tmpvar_32 "1" }
+ global CONFIG_UA2_FIFO2
+ if { $CONFIG_UA2_FIFO2 == 1 } then { set tmpvar_32 "2" }
+ global CONFIG_UA2_FIFO4
+ if { $CONFIG_UA2_FIFO4 == 1 } then { set tmpvar_32 "4" }
+ global CONFIG_UA2_FIFO8
+ if { $CONFIG_UA2_FIFO8 == 1 } then { set tmpvar_32 "8" }
+ global CONFIG_UA2_FIFO16
+ if { $CONFIG_UA2_FIFO16 == 1 } then { set tmpvar_32 "16" }
+ global CONFIG_UA2_FIFO32
+ if { $CONFIG_UA2_FIFO32 == 1 } then { set tmpvar_32 "32" }
+ global tmpvar_33
+ set tmpvar_33 "16"
+ global CONFIG_SPW_AHBFIFO4
+ if { $CONFIG_SPW_AHBFIFO4 == 1 } then { set tmpvar_33 "4" }
+ global CONFIG_SPW_AHBFIFO8
+ if { $CONFIG_SPW_AHBFIFO8 == 1 } then { set tmpvar_33 "8" }
+ global CONFIG_SPW_AHBFIFO16
+ if { $CONFIG_SPW_AHBFIFO16 == 1 } then { set tmpvar_33 "16" }
+ global CONFIG_SPW_AHBFIFO32
+ if { $CONFIG_SPW_AHBFIFO32 == 1 } then { set tmpvar_33 "32" }
+ global tmpvar_34
+ set tmpvar_34 "16"
+ global CONFIG_SPW_RXFIFO16
+ if { $CONFIG_SPW_RXFIFO16 == 1 } then { set tmpvar_34 "16" }
+ global CONFIG_SPW_RXFIFO32
+ if { $CONFIG_SPW_RXFIFO32 == 1 } then { set tmpvar_34 "32" }
+ global CONFIG_SPW_RXFIFO64
+ if { $CONFIG_SPW_RXFIFO64 == 1 } then { set tmpvar_34 "64" }
+ global tmpvar_35
+ set tmpvar_35 "64"
+ global CONFIG_SPW_RMAPBUF2
+ if { $CONFIG_SPW_RMAPBUF2 == 1 } then { set tmpvar_35 "64" }
+ global CONFIG_SPW_RMAPBUF4
+ if { $CONFIG_SPW_RMAPBUF4 == 1 } then { set tmpvar_35 "128" }
+ global CONFIG_SPW_RMAPBUF6
+ if { $CONFIG_SPW_RMAPBUF6 == 1 } then { set tmpvar_35 "192" }
+ global CONFIG_SPW_RMAPBUF8
+ if { $CONFIG_SPW_RMAPBUF8 == 1 } then { set tmpvar_35 "256" }
+ global tmpvar_36
+ set tmpvar_36 "2"
+ global CONFIG_SPW_GRSPW1
+ if { $CONFIG_SPW_GRSPW1 == 1 } then { set tmpvar_36 "1" }
+ global CONFIG_SPW_GRSPW2
+ if { $CONFIG_SPW_GRSPW2 == 1 } then { set tmpvar_36 "2" }
+ global tmpvar_37
+ set tmpvar_37 "DDR"
+ global CONFIG_SPW_RX_SDR
+ if { $CONFIG_SPW_RX_SDR == 1 } then { set tmpvar_37 "SDR" }
+ global CONFIG_SPW_RX_DDR
+ if { $CONFIG_SPW_RX_DDR == 1 } then { set tmpvar_37 "DDR" }
+ global CONFIG_SPW_RX_XOR
+ if { $CONFIG_SPW_RX_XOR == 1 } then { set tmpvar_37 "Xor" }
+ global CONFIG_SPW_RX_AFLEX
+ if { $CONFIG_SPW_RX_AFLEX == 1 } then { set tmpvar_37 "Aeroflex" }
+ global tmpvar_38
+ set tmpvar_38 "SDR"
+ global CONFIG_SPW_TX_SDR
+ if { $CONFIG_SPW_TX_SDR == 1 } then { set tmpvar_38 "SDR" }
+ global CONFIG_SPW_TX_DDR
+ if { $CONFIG_SPW_TX_DDR == 1 } then { set tmpvar_38 "DDR" }
+ global CONFIG_SPW_TX_AFLEX
+ if { $CONFIG_SPW_TX_AFLEX == 1 } then { set tmpvar_38 "Aeroflex" }
+}
+
+
+proc update_define_mainmenu {} {
+ global CONFIG_MODULES
+}
+
+
+# FILE: tail.tk
+# This file is boilerplate TCL/TK function definitions for 'make xconfig'.
+#
+# CHANGES
+# =======
+#
+# 8 January 1998, Michael Elizabeth Chastain, <mec@shout.net>
+# Arrange buttons in three columns for better screen fitting.
+#
+
+#
+# Read the user's settings from .config. These will override whatever is
+# in config.in. Don't do this if the user specified a -D to force
+# the defaults.
+#
+
+set defaults defconfig
+
+if { [file readable .config] == 1} then {
+ if { $argc > 0 } then {
+ if { [lindex $argv 0] != "-D" } then {
+ read_config .config
+ }
+ else
+ {
+ read_config $defaults
+ }
+ } else {
+ read_config .config
+ }
+} else {
+ read_config $defaults
+}
+
+update_define 1 $total_menus 0
+update_mainmenu
+
+button .f0.right.save -anchor w -text "Save and Exit" -underline 0\
+ -command { catch {exec cp -f .config .config.old}; \
+ writeconfig .config config.h; wrapup .wrap }
+
+button .f0.right.quit -anchor w -text "Quit Without Saving" -underline 0\
+ -command { maybe_exit .maybe }
+
+button .f0.right.load -anchor w -text "Load Configuration from File" \
+ -command { load_configfile .load "Load Configuration from file" read_config_file
+}
+
+button .f0.right.store -anchor w -text "Store Configuration to File" \
+ -command { load_configfile .load "Store Configuration to file" write_config_file }
+
+#
+# Now pack everything.
+#
+
+pack .f0.right.store .f0.right.load .f0.right.quit .f0.right.save \
+ -padx 0 -pady 0 -side bottom -fill x
+pack .f0.left .f0.middle .f0.right -side left -padx 5 -pady 0 -fill y
+pack .f0 -padx 5 -pady 5
+
+update idletasks
+set winy [expr 10 + [winfo reqheight .f0]]
+set scry [lindex [wm maxsize .] 1]
+set winx [expr 10 + [winfo reqwidth .f0]]
+set scrx [lindex [wm maxsize .] 0]
+if {$winx < $scrx} then {set maxx -1} else {set maxx $winx}
+if {$winy < $scry} then {set maxy -1} else {set maxy $winy}
+.f0 configure -width $winx -height $winy
+wm maxsize . $maxx $maxy
+
+#
+# If we cannot write our config files, disable the write button.
+#
+if { [file exists .config] == 1 } then {
+ if { [file writable .config] == 0 } then {
+ .f0.right.save configure -state disabled
+ }
+ } else {
+ if { [file writable .] == 0 } then {
+ .f0.right.save configure -state disabled
+ }
+ }
+
+#if { [file exists include/linux/autoconf.h] == 1 } then {
+# if { [file writable include/linux/autoconf.h] == 0 } then {
+# .f0.right.save configure -state disabled
+# }
+# } else {
+# if { [file writable include/linux/] == 0 } then {
+# .f0.right.save configure -state disabled
+# }
+# }
--- /dev/null
+#modified version for gr-xc3s-1550-fg456 board
+
+CONFIG stepping="0";
+
+NET clk period = 20.000 ;
+OFFSET = out : 20.000 : AFTER clk ;
+OFFSET = in : 8.000 : BEFORE clk ;
+
+NET clk3 period = 40.000 ;
+
+NET erx_clk PERIOD = 40.000 ;
+OFFSET = in : 10.000 : BEFORE erx_clk ;
+NET etx_clk PERIOD = 40.000 ;
+OFFSET = out : 20.000 : AFTER etx_clk ;
+OFFSET = in : 10.000 : BEFORE etx_clk ;
+
+NET usb_clkout period = 16.667;
+OFFSET = out : 10.000 : AFTER usb_clkout ;
+OFFSET = in : 8.000 : BEFORE usb_clkout ;
+
+NET "clkm" TNM_NET = "clkm";
+
+
+##################################################################
+# Enable these is you have enabled the SVGA clock generator
+
+NET vid_clock period = 15.000 ;
+NET "clk50" TNM_NET = "clk50";
+NET "video_clk" TNM_NET = "video_clk";
+TIMESPEC "TS_clkm_vidclk" = FROM "clkm" TO "video_clk" TIG;
+TIMESPEC "TS_clk50_vidclk" = FROM "clk50" TO "video_clk" TIG;
+TIMESPEC "TS_vidclk_clkm" = FROM "video_clk" TO "clkm" TIG;
+
+##################################################################
+
+INST "clkgen0_xc3s_v_dll0" LOC = DCM_X1Y0;
+INST "clkgen0_xc3s_v_sd0_dll1" LOC = DCM_X0Y0;
+INST "clkgen0_v_dll0" LOC = DCM_X1Y0;
+INST "clkgen0_v_dll1" LOC = DCM_X0Y0;
+INST "clkgen0/v/dll0" LOC = DCM_X1Y0;
+INST "clkgen0/v/dll1" LOC = DCM_X0Y0;
+INST "clkgen0/xc3s.v/dll0" LOC = DCM_X1Y0;
+INST "clkgen0/xc3s.v/sd0.dll1" LOC = DCM_X0Y0;
+INST "clkgen0.xc3s.v.dll0" LOC = DCM_X1Y0;
+INST "clkgen0.xc3s.v.sd0.dll1" LOC = DCM_X0Y0;
+
+# ISE/XST constraints
+#NET "spw.swloop[0].sw0/rxclki" PERIOD = 10.0 ;
+#NET "spw.swloop[1].sw0/rxclki" PERIOD = 10.0 ;
+#NET "spw.swloop[2].sw0/rxclki" PERIOD = 10.0 ;
+
+# ISE/SYNPLIFY constraints
+#NET "spw.swloop.0.sw0/rxclki" PERIOD = 10.0 ;
+#NET "spw.swloop.1.sw0/rxclki" PERIOD = 10.0 ;
+#NET "spw.swloop.2.sw0/rxclki" PERIOD = 10.0 ;
+
+INST "spw.swloop.0.sw0/grspwc0/rxclko" LOC = "SLICE_X0Y62";
+INST "spw.swloop[0].sw0/grspwc0/rxclko" LOC = "SLICE_X0Y62";
+INST "spw.swloop.1.sw0/grspwc0/rxclko" LOC = "SLICE_X0Y48";
+INST "spw.swloop[1].sw0/grspwc0/rxclko" LOC = "SLICE_X0Y48";
+INST "spw.swloop.2.sw0/grspwc0/rxclko" LOC = "SLICE_X0Y24";
+INST "spw.swloop[2].sw0/grspwc0/rxclko" LOC = "SLICE_X0Y24";
+INST "sw00/grspwc0/rxclko" LOC = SLICE_X0Y62;
+INST "sw01/grspwc0/rxclko" LOC = SLICE_X0Y48;
+INST "sw02/grspwc0/rxclko" LOC = SLICE_X0Y24;
+
+NET "address(0)" LOC = "u16" | IOSTANDARD = LVTTL;
+NET "address(1)" LOC = "u17" | IOSTANDARD = LVTTL;
+NET "address(10)" LOC = "y22" | IOSTANDARD = LVTTL;
+NET "address(11)" LOC = "v19" | IOSTANDARD = LVTTL;
+NET "address(12)" LOC = "w19" | IOSTANDARD = LVTTL;
+NET "address(13)" LOC = "w21" | IOSTANDARD = LVTTL;
+NET "address(14)" LOC = "w20" | IOSTANDARD = LVTTL;
+NET "address(15)" LOC = "u19" | IOSTANDARD = LVTTL;
+NET "address(16)" LOC = "v20" | IOSTANDARD = LVTTL;
+NET "address(17)" LOC = "v22" | IOSTANDARD = LVTTL;
+NET "address(18)" LOC = "v21" | IOSTANDARD = LVTTL;
+NET "address(19)" LOC = "t17" | IOSTANDARD = LVTTL;
+NET "address(2)" LOC = "aa20" | IOSTANDARD = LVTTL;
+NET "address(20)" LOC = "u18" | IOSTANDARD = LVTTL;
+NET "address(21)" LOC = "w13" | IOSTANDARD = LVTTL;
+NET "address(22)" LOC = "w14" | IOSTANDARD = LVTTL;
+NET "address(23)" LOC = "u14" | IOSTANDARD = LVTTL;
+NET "address(24)" LOC = "v14" | IOSTANDARD = LVTTL;
+NET "address(25)" LOC = "u13" | IOSTANDARD = LVTTL;
+NET "address(26)" LOC = "v13" | IOSTANDARD = LVTTL;
+NET "address(27)" LOC = "y13" | IOSTANDARD = LVTTL;
+NET "address(3)" LOC = "ab20" | IOSTANDARD = LVTTL;
+NET "address(4)" LOC = "aa19" | IOSTANDARD = LVTTL;
+NET "address(5)" LOC = "ab19" | IOSTANDARD = LVTTL;
+NET "address(6)" LOC = "y21" | IOSTANDARD = LVTTL;
+NET "address(7)" LOC = "y20" | IOSTANDARD = LVTTL;
+NET "address(8)" LOC = "y19" | IOSTANDARD = LVTTL;
+NET "address(9)" LOC = "w22" | IOSTANDARD = LVTTL;
+NET "bexcn" LOC = "aa7" | IOSTANDARD = LVTTL;
+NET "brdyn" LOC = "ab7" | IOSTANDARD = LVTTL;
+NET "clk" LOC = "aa12" | IOSTANDARD = LVTTL;
+NET "clk2" LOC = "ab12" | IOSTANDARD = LVTTL;
+NET "clk3" LOC = "a11" | IOSTANDARD = LVTTL;
+NET "ctsn1" LOC = "l5" | IOSTANDARD = LVTTL;
+NET "ctsn2" LOC = "k3" | IOSTANDARD = LVTTL;
+NET "data(0)" LOC = "n18" | IOSTANDARD = LVTTL;
+NET "data(1)" LOC = "p21" | IOSTANDARD = LVTTL;
+NET "data(10)" LOC = "t22" | IOSTANDARD = LVTTL;
+NET "data(11)" LOC = "t19" | IOSTANDARD = LVTTL;
+NET "data(12)" LOC = "t20" | IOSTANDARD = LVTTL;
+NET "data(13)" LOC = "t18" | IOSTANDARD = LVTTL;
+NET "data(14)" LOC = "r18" | IOSTANDARD = LVTTL;
+NET "data(15)" LOC = "u20" | IOSTANDARD = LVTTL;
+NET "data(16)" LOC = "aa18" | IOSTANDARD = LVTTL;
+NET "data(17)" LOC = "ab18" | IOSTANDARD = LVTTL;
+NET "data(18)" LOC = "ab16" | IOSTANDARD = LVTTL;
+NET "data(19)" LOC = "aa15" | IOSTANDARD = LVTTL;
+NET "data(2)" LOC = "p22" | IOSTANDARD = LVTTL;
+NET "data(20)" LOC = "ab15" | IOSTANDARD = LVTTL;
+NET "data(21)" LOC = "ab14" | IOSTANDARD = LVTTL;
+NET "data(22)" LOC = "aa13" | IOSTANDARD = LVTTL;
+NET "data(23)" LOC = "ab13" | IOSTANDARD = LVTTL;
+NET "data(24)" LOC = "aa16" | IOSTANDARD = LVTTL;
+NET "data(25)" LOC = "w16" | IOSTANDARD = LVTTL;
+NET "data(26)" LOC = "v16" | IOSTANDARD = LVTTL;
+NET "data(27)" LOC = "aa17" | IOSTANDARD = LVTTL;
+NET "data(28)" LOC = "w17" | IOSTANDARD = LVTTL;
+NET "data(29)" LOC = "v17" | IOSTANDARD = LVTTL;
+NET "data(3)" LOC = "p17" | IOSTANDARD = LVTTL;
+NET "data(30)" LOC = "w18" | IOSTANDARD = LVTTL;
+NET "data(31)" LOC = "y18" | IOSTANDARD = LVTTL;
+NET "data(4)" LOC = "p18" | IOSTANDARD = LVTTL;
+NET "data(5)" LOC = "r19" | IOSTANDARD = LVTTL;
+NET "data(6)" LOC = "p19" | IOSTANDARD = LVTTL;
+NET "data(7)" LOC = "r21" | IOSTANDARD = LVTTL;
+NET "data(8)" LOC = "r22" | IOSTANDARD = LVTTL;
+NET "data(9)" LOC = "t21" | IOSTANDARD = LVTTL;
+NET "emdint" LOC = "c2" | IOSTANDARD = LVTTL | PULLUP;
+NET "emdio" LOC = "c4" | IOSTANDARD = LVTTL | PULLUP;
+NET "erx_clk" LOC = "y11" | IOSTANDARD = LVTTL;
+NET "erx_col" LOC = "f3" | IOSTANDARD = LVTTL;
+NET "erx_crs" LOC = "f4" | IOSTANDARD = LVTTL;
+NET "erx_dv" LOC = "e3" | IOSTANDARD = LVTTL;
+NET "erx_er" LOC = "f2" | IOSTANDARD = LVTTL;
+NET "erxd(0)" LOC = "e4" | IOSTANDARD = LVTTL;
+NET "erxd(1)" LOC = "d4" | IOSTANDARD = LVTTL;
+NET "erxd(2)" LOC = "d3" | IOSTANDARD = LVTTL;
+NET "erxd(3)" LOC = "d2" | IOSTANDARD = LVTTL;
+NET "emdc" LOC = "c3" | IOSTANDARD = LVTTL;
+NET "etx_clk" LOC = "aa11" | IOSTANDARD = LVTTL;
+NET "etx_en" LOC = "f5" | IOSTANDARD = LVTTL;
+NET "etx_er" LOC = "g6" | IOSTANDARD = LVTTL;
+NET "etxd(0)" LOC = "e1" | IOSTANDARD = LVTTL;
+NET "etxd(1)" LOC = "e2" | IOSTANDARD = LVTTL;
+NET "etxd(2)" LOC = "d1" | IOSTANDARD = LVTTL;
+NET "etxd(3)" LOC = "c1" | IOSTANDARD = LVTTL;
+NET "genio(0)" LOC = "m6" | IOSTANDARD = LVTTL;
+NET "genio(1)" LOC = "m5" | IOSTANDARD = LVTTL;
+NET "genio(10)" LOC = "t6" | IOSTANDARD = LVTTL;
+NET "genio(11)" LOC = "t5" | IOSTANDARD = LVTTL;
+NET "genio(12)" LOC = "v5" | IOSTANDARD = LVTTL;
+NET "genio(13)" LOC = "u5" | IOSTANDARD = LVTTL;
+NET "genio(14)" LOC = "w4" | IOSTANDARD = LVTTL;
+NET "genio(15)" LOC = "w3" | IOSTANDARD = LVTTL;
+NET "genio(16)" LOC = "y3" | IOSTANDARD = LVTTL;
+NET "genio(17)" LOC = "y2" | IOSTANDARD = LVTTL;
+NET "genio(18)" LOC = "y1" | IOSTANDARD = LVTTL;
+NET "genio(19)" LOC = "u6" | IOSTANDARD = LVTTL;
+NET "genio(2)" LOC = "n6" | IOSTANDARD = LVTTL;
+NET "genio(20)" LOC = "d22" | IOSTANDARD = LVTTL;
+NET "genio(21)" LOC = "g17" | IOSTANDARD = LVTTL;
+NET "genio(22)" LOC = "e21" | IOSTANDARD = LVTTL;
+NET "genio(23)" LOC = "g22" | IOSTANDARD = LVTTL;
+NET "genio(24)" LOC = "g21" | IOSTANDARD = LVTTL;
+NET "genio(25)" LOC = "g19" | IOSTANDARD = LVTTL;
+NET "genio(26)" LOC = "h22" | IOSTANDARD = LVTTL;
+NET "genio(27)" LOC = "g18" | IOSTANDARD = LVTTL;
+NET "genio(28)" LOC = "j18" | IOSTANDARD = LVTTL;
+NET "genio(29)" LOC = "j21" | IOSTANDARD = LVTTL;
+NET "genio(3)" LOC = "n5" | IOSTANDARD = LVTTL;
+NET "genio(30)" LOC = "j22" | IOSTANDARD = LVTTL;
+NET "genio(31)" LOC = "h21" | IOSTANDARD = LVTTL;
+NET "genio(32)" LOC = "k22" | IOSTANDARD = LVTTL;
+NET "genio(33)" LOC = "k21" | IOSTANDARD = LVTTL;
+NET "genio(34)" LOC = "k18" | IOSTANDARD = LVTTL;
+NET "genio(35)" LOC = "l19" | IOSTANDARD = LVTTL;
+NET "genio(36)" LOC = "l18" | IOSTANDARD = LVTTL;
+NET "genio(37)" LOC = "k17" | IOSTANDARD = LVTTL;
+NET "genio(38)" LOC = "l17" | IOSTANDARD = LVTTL;
+NET "genio(39)" LOC = "j17" | IOSTANDARD = LVTTL;
+NET "genio(4)" LOC = "r5" | IOSTANDARD = LVTTL;
+NET "genio(40)" LOC = "e19" | IOSTANDARD = LVTTL;
+NET "genio(41)" LOC = "f18" | IOSTANDARD = LVTTL;
+NET "genio(42)" LOC = "e20" | IOSTANDARD = LVTTL;
+NET "genio(43)" LOC = "f19" | IOSTANDARD = LVTTL;
+NET "genio(44)" LOC = "f20" | IOSTANDARD = LVTTL;
+NET "genio(45)" LOC = "f21" | IOSTANDARD = LVTTL;
+NET "genio(46)" LOC = "e22" | IOSTANDARD = LVTTL;
+NET "genio(47)" LOC = "e18" | IOSTANDARD = LVTTL;
+NET "genio(48)" LOC = "g20" | IOSTANDARD = LVTTL;
+NET "genio(49)" LOC = "h19" | IOSTANDARD = LVTTL;
+NET "genio(5)" LOC = "p6" | IOSTANDARD = LVTTL;
+NET "genio(50)" LOC = "h18" | IOSTANDARD = LVTTL;
+NET "genio(51)" LOC = "j19" | IOSTANDARD = LVTTL;
+NET "genio(52)" LOC = "k20" | IOSTANDARD = LVTTL;
+NET "genio(53)" LOC = "k19" | IOSTANDARD = LVTTL;
+NET "genio(54)" LOC = "l20" | IOSTANDARD = LVTTL;
+NET "genio(55)" LOC = "l21" | IOSTANDARD = LVTTL;
+NET "genio(56)" LOC = "m20" | IOSTANDARD = LVTTL;
+NET "genio(57)" LOC = "m19" | IOSTANDARD = LVTTL;
+NET "genio(58)" LOC = "m22" | IOSTANDARD = LVTTL;
+NET "genio(59)" LOC = "m21" | IOSTANDARD = LVTTL;
+NET "genio(6)" LOC = "t2" | IOSTANDARD = LVTTL;
+NET "genio(7)" LOC = "t1" | IOSTANDARD = LVTTL;
+NET "genio(8)" LOC = "u4" | IOSTANDARD = LVTTL;
+NET "genio(9)" LOC = "t4" | IOSTANDARD = LVTTL;
+NET "iosn" LOC = "u12" | IOSTANDARD = LVTTL;
+#NET "led(0)" LOC = "f11" | IOSTANDARD = LVTTL;
+#NET "led(1)" LOC = "e11" | IOSTANDARD = LVTTL;
+#NET "led(2)" LOC = "d11" | IOSTANDARD = LVTTL;
+#NET "led(3)" LOC = "c11" | IOSTANDARD = LVTTL;
+#NET "lvdsion(0)" LOC = "m2" | IOSTANDARD = LVTTL;
+#NET "lvdsion(1)" LOC = "m1" | IOSTANDARD = LVTTL;
+#NET "lvdsion(10)" LOC = "w2" | IOSTANDARD = LVTTL;
+#NET "lvdsion(11)" LOC = "w1" | IOSTANDARD = LVTTL;
+#NET "lvdsion(2)" LOC = "v4" | IOSTANDARD = LVTTL;
+#NET "lvdsion(3)" LOC = "v3" | IOSTANDARD = LVTTL;
+#NET "lvdsion(4)" LOC = "m4" | IOSTANDARD = LVTTL;
+#NET "lvdsion(5)" LOC = "m3" | IOSTANDARD = LVTTL;
+#NET "lvdsion(6)" LOC = "n2" | IOSTANDARD = LVTTL;
+#NET "lvdsion(7)" LOC = "n1" | IOSTANDARD = LVTTL;
+#NET "lvdsion(8)" LOC = "n4" | IOSTANDARD = LVTTL;
+#NET "lvdsion(9)" LOC = "n3" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(0)" LOC = "p2" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(1)" LOC = "p1" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(10)" LOC = "p5" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(11)" LOC = "p4" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(2)" LOC = "r2" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(3)" LOC = "r1" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(4)" LOC = "t3" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(5)" LOC = "r4" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(6)" LOC = "v2" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(7)" LOC = "v1" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(8)" LOC = "u3" | IOSTANDARD = LVTTL;
+#NET "lvdsiop(9)" LOC = "u2" | IOSTANDARD = LVTTL;
+NET "oen" LOC = "ab4" | IOSTANDARD = LVTTL;
+NET "pio(0)" LOC = "h5" | IOSTANDARD = LVTTL;
+NET "pio(1)" LOC = "g5" | IOSTANDARD = LVTTL;
+NET "pio(10)" LOC = "j5" | IOSTANDARD = LVTTL;
+NET "pio(11)" LOC = "j6" | IOSTANDARD = LVTTL;
+NET "pio(12)" LOC = "j1" | IOSTANDARD = LVTTL;
+NET "pio(13)" LOC = "j2" | IOSTANDARD = LVTTL;
+NET "pio(14)" LOC = "k5" | IOSTANDARD = LVTTL;
+NET "pio(15)" LOC = "k6" | IOSTANDARD = LVTTL;
+NET "pio(2)" LOC = "g3" | IOSTANDARD = LVTTL;
+NET "pio(3)" LOC = "g4" | IOSTANDARD = LVTTL;
+NET "pio(4)" LOC = "g1" | IOSTANDARD = LVTTL;
+NET "pio(5)" LOC = "g2" | IOSTANDARD = LVTTL;
+NET "pio(6)" LOC = "h1" | IOSTANDARD = LVTTL;
+NET "pio(7)" LOC = "h2" | IOSTANDARD = LVTTL;
+NET "pio(8)" LOC = "j4" | IOSTANDARD = LVTTL;
+NET "pio(9)" LOC = "h4" | IOSTANDARD = LVTTL;
+NET "pllref" LOC = "v8" | IOSTANDARD = LVTTL;# sdclkfb
+NET "ps2clk(0)" LOC = "b10" | IOSTANDARD = LVTTL;
+NET "ps2clk(1)" LOC = "e10" | IOSTANDARD = LVTTL;
+NET "ps2data(0)" LOC = "c10" | IOSTANDARD = LVTTL;
+NET "ps2data(1)" LOC = "f10" | IOSTANDARD = LVTTL;
+NET "ramoen(0)" LOC = "u10" | IOSTANDARD = LVTTL;
+NET "ramoen(1)" LOC = "u11" | IOSTANDARD = LVTTL;
+NET "ramoen(2)" LOC = "v10" | IOSTANDARD = LVTTL;
+NET "ramoen(3)" LOC = "u9" | IOSTANDARD = LVTTL;
+NET "ramoen(4)" LOC = "u7" | IOSTANDARD = LVTTL;
+NET "ramsn(0)" LOC = "aa4" | IOSTANDARD = LVTTL;
+NET "ramsn(1)" LOC = "y5" | IOSTANDARD = LVTTL;
+NET "ramsn(2)" LOC = "w5" | IOSTANDARD = LVTTL;
+NET "ramsn(3)" LOC = "ab5" | IOSTANDARD = LVTTL;
+NET "ramsn(4)" LOC = "aa5" | IOSTANDARD = LVTTL;
+NET "read" LOC = "v12" | IOSTANDARD = LVTTL;
+NET "resetn" LOC = "l2" | IOSTANDARD = LVTTL;
+NET "romsn(0)" LOC = "y4" | IOSTANDARD = LVTTL;
+NET "romsn(1)" LOC = "v7" | IOSTANDARD = LVTTL;
+NET "rtsn1" LOC = "l6" | IOSTANDARD = LVTTL;
+NET "rtsn2" LOC = "k4" | IOSTANDARD = LVTTL;
+NET "rwen(0)" LOC = "aa6" | IOSTANDARD = LVTTL;
+NET "rwen(1)" LOC = "y7" | IOSTANDARD = LVTTL;
+NET "rwen(2)" LOC = "y6" | IOSTANDARD = LVTTL;
+NET "rwen(3)" LOC = "w7" | IOSTANDARD = LVTTL;
+NET "rxd1" LOC = "l3" | IOSTANDARD = LVTTL;
+NET "rxd2" LOC = "k1" | IOSTANDARD = LVTTL;
+NET "sdcasn" LOC = "ab9" | IOSTANDARD = LVTTL;
+NET "sdclk" LOC = "w8" | IOSTANDARD = LVTTL;
+NET "sdcsn(0)" LOC = "ab8" | IOSTANDARD = LVTTL;
+NET "sdcsn(1)" LOC = "w9" | IOSTANDARD = LVTTL;
+NET "sddqm(0)" LOC = "aa8" | IOSTANDARD = LVTTL;
+NET "sddqm(1)" LOC = "v11" | IOSTANDARD = LVTTL;
+NET "sddqm(2)" LOC = "ab10" | IOSTANDARD = LVTTL;
+NET "sddqm(3)" LOC = "w10" | IOSTANDARD = LVTTL;
+NET "sdrasn" LOC = "aa9" | IOSTANDARD = LVTTL;
+NET "sdwen" LOC = "aa10" | IOSTANDARD = LVTTL;
+
+NET "spw_rxdp(0)" LOC = "m1";# | IOSTANDARD = LVDS_25;
+NET "spw_rxdn(0)" LOC = "m2";# | IOSTANDARD = LVDS_25;
+NET "spw_rxsp(0)" LOC = "m3";# | IOSTANDARD = LVDS_25;
+NET "spw_rxsn(0)" LOC = "m4";# | IOSTANDARD = LVDS_25;
+NET "spw_txdp(0)" LOC = "n1";# | IOSTANDARD = LVDS_25;
+NET "spw_txdn(0)" LOC = "n2";# | IOSTANDARD = LVDS_25;
+NET "spw_txsp(0)" LOC = "n3";# | IOSTANDARD = LVDS_25;
+NET "spw_txsn(0)" LOC = "n4";# | IOSTANDARD = LVDS_25;
+NET "spw_rxdp(1)" LOC = "p1";# | IOSTANDARD = LVDS_25;
+NET "spw_rxdn(1)" LOC = "p2";# | IOSTANDARD = LVDS_25;
+NET "spw_rxsp(1)" LOC = "p4";# | IOSTANDARD = LVDS_25;
+NET "spw_rxsn(1)" LOC = "p5";# | IOSTANDARD = LVDS_25;
+NET "spw_txdp(1)" LOC = "r1";# | IOSTANDARD = LVDS_25;
+NET "spw_txdn(1)" LOC = "r2";# | IOSTANDARD = LVDS_25;
+NET "spw_txsp(1)" LOC = "r4";# | IOSTANDARD = LVDS_25;
+NET "spw_txsn(1)" LOC = "t3";# | IOSTANDARD = LVDS_25;
+NET "spw_rxdp(2)" LOC = "v1";# | IOSTANDARD = LVDS_25;
+NET "spw_rxdn(2)" LOC = "v2";# | IOSTANDARD = LVDS_25;
+NET "spw_rxsp(2)" LOC = "u2";# | IOSTANDARD = LVDS_25;
+NET "spw_rxsn(2)" LOC = "u3";# | IOSTANDARD = LVDS_25;
+NET "spw_txdp(2)" LOC = "w1";# | IOSTANDARD = LVDS_25;
+NET "spw_txdn(2)" LOC = "w2";# | IOSTANDARD = LVDS_25;
+NET "spw_txsp(2)" LOC = "v3";# | IOSTANDARD = LVDS_25;
+NET "spw_txsn(2)" LOC = "v4";# | IOSTANDARD = LVDS_25;
+
+NET "switch(0)" LOC = "f16" | IOSTANDARD = LVTTL;
+NET "switch(1)" LOC = "f13" | IOSTANDARD = LVTTL;
+#NET "pio(0)" LOC = "f16" | IOSTANDARD = LVTTL;
+#NET "pio(1)" LOC = "f13" | IOSTANDARD = LVTTL;
+NET "switch(2)" LOC = "f12" | IOSTANDARD = LVTTL;
+NET "switch(3)" LOC = "e16" | IOSTANDARD = LVTTL;
+NET "switch(4)" LOC = "c22" | IOSTANDARD = LVTTL;
+NET "switch(5)" LOC = "c20" | IOSTANDARD = LVTTL;
+NET "switch(6)" LOC = "c21" | IOSTANDARD = LVTTL;
+#NET "switch(7)" LOC = "d20" | IOSTANDARD = LVTTL;
+NET "switch(8)" LOC = "d19" | IOSTANDARD = LVTTL;
+#NET "switch(9)" LOC = "d21" | IOSTANDARD = LVTTL;
+NET "txd1" LOC = "l4" | IOSTANDARD = LVTTL;
+NET "txd2" LOC = "k2" | IOSTANDARD = LVTTL;
+NET "usb_clkout" LOC = "c12" | IOSTANDARD = LVTTL;
+NET "usb_clock" LOC = "b12" | IOSTANDARD = LVTTL;
+NET "usb_d(0)" LOC = "c13" | IOSTANDARD = LVTTL;
+NET "usb_d(1)" LOC = "b14" | IOSTANDARD = LVTTL;
+NET "usb_d(10)" LOC = "a16" | IOSTANDARD = LVTTL;
+NET "usb_d(11)" LOC = "d16" | IOSTANDARD = LVTTL;
+NET "usb_d(12)" LOC = "c16" | IOSTANDARD = LVTTL;
+NET "usb_d(13)" LOC = "c17" | IOSTANDARD = LVTTL;
+NET "usb_d(14)" LOC = "b17" | IOSTANDARD = LVTTL;
+NET "usb_d(15)" LOC = "e17" | IOSTANDARD = LVTTL;
+NET "usb_d(2)" LOC = "a14" | IOSTANDARD = LVTTL;
+NET "usb_d(3)" LOC = "e14" | IOSTANDARD = LVTTL;
+NET "usb_d(4)" LOC = "d14" | IOSTANDARD = LVTTL;
+NET "usb_d(5)" LOC = "a15" | IOSTANDARD = LVTTL;
+NET "usb_d(6)" LOC = "b15" | IOSTANDARD = LVTTL;
+NET "usb_d(7)" LOC = "e15" | IOSTANDARD = LVTTL;
+NET "usb_d(8)" LOC = "d15" | IOSTANDARD = LVTTL;
+NET "usb_d(9)" LOC = "b16" | IOSTANDARD = LVTTL;
+NET "usb_enablen" LOC = "b18" | IOSTANDARD = LVTTL;
+NET "usb_faultn" LOC = "c19" | IOSTANDARD = LVTTL;
+NET "usb_linestate(0)" LOC = "a19" | IOSTANDARD = LVTTL;
+NET "usb_linestate(1)" LOC = "b19" | IOSTANDARD = LVTTL;
+NET "usb_opmode(0)" LOC = "d18" | IOSTANDARD = LVTTL;
+NET "usb_opmode(1)" LOC = "c18" | IOSTANDARD = LVTTL;
+NET "usb_reset" LOC = "b20" | IOSTANDARD = LVTTL;
+NET "usb_rxactive" LOC = "b13" | IOSTANDARD = LVTTL;
+NET "usb_rxerror" LOC = "a13" | IOSTANDARD = LVTTL;
+NET "usb_rxvalid" LOC = "f17" | IOSTANDARD = LVTTL;
+NET "usb_suspend" LOC = "a18" | IOSTANDARD = LVTTL;
+NET "usb_termsel" LOC = "d13" | IOSTANDARD = LVTTL;
+NET "usb_txready" LOC = "e13" | IOSTANDARD = LVTTL;
+NET "usb_txvalid" LOC = "f14" | IOSTANDARD = LVTTL;
+NET "usb_validh" LOC = "e12" | IOSTANDARD = LVTTL;
+NET "usb_vbus" LOC = "a12" | IOSTANDARD = LVTTL;
+NET "usb_xcvrsel" LOC = "d12" | IOSTANDARD = LVTTL;
+NET "vid_b(0)" LOC = "a7" | IOSTANDARD = LVTTL;
+NET "vid_b(1)" LOC = "e8" | IOSTANDARD = LVTTL;
+NET "vid_b(2)" LOC = "d8" | IOSTANDARD = LVTTL;
+NET "vid_b(3)" LOC = "b8" | IOSTANDARD = LVTTL;
+NET "vid_b(4)" LOC = "a8" | IOSTANDARD = LVTTL;
+NET "vid_b(5)" LOC = "f9" | IOSTANDARD = LVTTL;
+NET "vid_b(6)" LOC = "e9" | IOSTANDARD = LVTTL;
+NET "vid_b(7)" LOC = "b9" | IOSTANDARD = LVTTL;
+NET "vid_blankn" LOC = "b7" | IOSTANDARD = LVTTL;
+NET "vid_clock" LOC = "b11" | IOSTANDARD = LVTTL;
+NET "vid_g(0)" LOC = "b5" | IOSTANDARD = LVTTL;
+NET "vid_g(1)" LOC = "a5" | IOSTANDARD = LVTTL;
+NET "vid_g(2)" LOC = "e6" | IOSTANDARD = LVTTL;
+NET "vid_g(3)" LOC = "d6" | IOSTANDARD = LVTTL;
+NET "vid_g(4)" LOC = "c6" | IOSTANDARD = LVTTL;
+NET "vid_g(5)" LOC = "b6" | IOSTANDARD = LVTTL;
+NET "vid_g(6)" LOC = "e7" | IOSTANDARD = LVTTL;
+NET "vid_g(7)" LOC = "d7" | IOSTANDARD = LVTTL;
+NET "vid_hsync" LOC = "c7" | IOSTANDARD = LVTTL;
+NET "vid_r(0)" LOC = "a10" | IOSTANDARD = LVTTL;
+NET "vid_r(1)" LOC = "d10" | IOSTANDARD = LVTTL;
+NET "vid_r(2)" LOC = "d9" | IOSTANDARD = LVTTL;
+NET "vid_r(3)" LOC = "f6" | IOSTANDARD = LVTTL;
+NET "vid_r(4)" LOC = "b4" | IOSTANDARD = LVTTL;
+NET "vid_r(5)" LOC = "a4" | IOSTANDARD = LVTTL;
+NET "vid_r(6)" LOC = "d5" | IOSTANDARD = LVTTL;
+NET "vid_r(7)" LOC = "c5" | IOSTANDARD = LVTTL;
+NET "vid_sda" LOC = "a3" | IOSTANDARD = LVTTL;
+NET "vid_sdc" LOC = "a9" | IOSTANDARD = LVTTL;
+NET "vid_syncn" LOC = "f7" | IOSTANDARD = LVTTL;
+NET "vid_vsync" LOC = "e5" | IOSTANDARD = LVTTL;
+NET "wdogn" LOC = "l1" | IOSTANDARD = LVTTL;
+NET "writen" LOC = "aa3" | IOSTANDARD = LVTTL;
+
+#NET "dsutx" LOC = "l4" | IOSTANDARD = LVTTL ;#txd1
+#NET "dsurx" LOC = "l3" | IOSTANDARD = LVTTL ;#rxd1
+NET "dsuen" LOC = "d20" | IOSTANDARD = LVTTL ;#switch(7)
+NET "dsubre" LOC = "d21" | IOSTANDARD = LVTTL ;#switch(9)
+NET "dsuact" LOC = "e11" | IOSTANDARD = LVTTL ;#led(1)
+NET "errorn" LOC = "f11" | IOSTANDARD = LVTTL ; #led(0)
+NET "pio(16)" LOC = "d11" | IOSTANDARD = LVTTL; # led(2)
+NET "pio(17)" LOC = "c11" | IOSTANDARD = LVTTL; # led(3)
+
+#NET "can_stb(2)" LOC = "h5" | IOSTANDARD = LVTTL; #pio(0)
+#NET "can_rxd(2)" LOC = "g5" | IOSTANDARD = LVTTL; #pio(1)
+#NET "can_txd(2)" LOC = "g3" | IOSTANDARD = LVTTL; #pio(2)
+#NET "can_stb(1)" LOC = "g4" | IOSTANDARD = LVTTL; #pio(3)
+#NET "can_rxd(1)" LOC = "g1" | IOSTANDARD = LVTTL; #pio(4)
+#NET "can_txd(1)" LOC = "g2" | IOSTANDARD = LVTTL; #pio(5)
+
+NET "ata_rstn" LOC = "d22" | IOSTANDARD = LVTTL; #genio(20)
+NET "ata_data(7)" LOC = "g17" | IOSTANDARD = LVTTL; #genio(21)
+NET "ata_data(6)" LOC = "e21" | IOSTANDARD = LVTTL; #genio(22)
+NET "ata_data(5)" LOC = "g22" | IOSTANDARD = LVTTL; #genio(23)
+NET "ata_data(4)" LOC = "g21" | IOSTANDARD = LVTTL; #genio(24)
+NET "ata_data(3)" LOC = "g19" | IOSTANDARD = LVTTL; #genio(25)
+NET "ata_data(2)" LOC = "h22" | IOSTANDARD = LVTTL; #genio(26)
+NET "ata_data(1)" LOC = "g18" | IOSTANDARD = LVTTL; #genio(27)
+NET "ata_data(0)" LOC = "j18" | IOSTANDARD = LVTTL; #genio(28)
+#NET "genio(29)" LOC = "j21" | IOSTANDARD = LVTTL; #genio(29) / not used
+NET "ata_dmarq" LOC = "j22" | IOSTANDARD = LVTTL | PULLDOWN; #genio(30) / DMARQ
+NET "ata_diow" LOC = "h21" | IOSTANDARD = LVTTL; #genio(31) / nDIOW
+NET "ata_dior" LOC = "k22" | IOSTANDARD = LVTTL; #genio(32) / DIOR
+NET "ata_iordy" LOC = "k21" | IOSTANDARD = LVTTL | PULLUP; #genio(33) / IORDY
+NET "ata_dmack" LOC = "k18" | IOSTANDARD = LVTTL; #genio(34) / nDMACK
+NET "ata_intrq" LOC = "l19" | IOSTANDARD = LVTTL | PULLDOWN; #genio(35) / INTRQ
+NET "ata_da(1)" LOC = "l18" | IOSTANDARD = LVTTL; #genio(36) / DA1
+NET "ata_da(0)" LOC = "k17" | IOSTANDARD = LVTTL; #genio(37) / DA0
+NET "ata_cs0" LOC = "l17" | IOSTANDARD = LVTTL; #genio(38) / nCS0
+NET "ata_dasp" LOC = "j17" | IOSTANDARD = LVTTL; #genio(39) / nDASP
+
+#NET "genio(40)" LOC = "e19" | IOSTANDARD = LVTTL; #genio(40) / not used
+NET "ata_data(8)" LOC = "f18" | IOSTANDARD = LVTTL; #genio(41)
+NET "ata_data(9)" LOC = "e20" | IOSTANDARD = LVTTL; #genio(42)
+NET "ata_data(10)" LOC = "f19" | IOSTANDARD = LVTTL; #genio(43)
+NET "ata_data(11)" LOC = "f20" | IOSTANDARD = LVTTL; #genio(44)
+NET "ata_data(12)" LOC = "f21" | IOSTANDARD = LVTTL; #genio(45)
+NET "ata_data(13)" LOC = "e22" | IOSTANDARD = LVTTL; #genio(46)
+NET "ata_data(14)" LOC = "e18" | IOSTANDARD = LVTTL; #genio(47)
+NET "ata_data(15)" LOC = "g20" | IOSTANDARD = LVTTL; #genio(48)
+#NET "genio(49)" LOC = "h19" | IOSTANDARD = LVTTL; #genio(49) / not used
+#NET "genio(50)" LOC = "h18" | IOSTANDARD = LVTTL; #genio(50) / not used
+#NET "genio(51)" LOC = "j19" | IOSTANDARD = LVTTL; #genio(51) / not used
+#NET "genio(52)" LOC = "k20" | IOSTANDARD = LVTTL; #genio(52) / not used
+NET "ata_csel" LOC = "k19" | IOSTANDARD = LVTTL; #genio(53) / Cable SEL
+#NET "genio(54)" LOC = "l20" | IOSTANDARD = LVTTL; #genio(54) / not used
+#NET "genio(55)" LOC = "l21" | IOSTANDARD = LVTTL; #genio(55) / not used
+#NET "genio(56)" LOC = "m20" | IOSTANDARD = LVTTL; #genio(56) / nPDIAG
+NET "ata_da(2)" LOC = "m19" | IOSTANDARD = LVTTL; #genio(57)
+NET "ata_cs1" LOC = "m22" | IOSTANDARD = LVTTL; #genio(58)
+#NET "genio(59)" LOC = "m21" | IOSTANDARD = LVTTL; #genio(59)
+
+
+CONFIG PROHIBIT = "aa14"; #"fpgadata"
+CONFIG PROHIBIT = "w12"; #"fpgainit"
+
+
+
--- /dev/null
+-w
+-g DebugBitstream:No
+-d
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g Persist:No
+-m
+-g ReadBack
+-g DonePipe:No
+-g DriveDone:Yes
--- /dev/null
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design
+-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib, techmap;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use techmap.gencomp.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+use gaisler.can.all;
+use gaisler.net.all;
+use gaisler.jtag.all;
+use gaisler.spacewire.all;
+use gaisler.grusb.all;
+use gaisler.ata.all;
+
+library esa;
+use esa.memoryctrl.all;
+
+library kuri;
+use kuri.mjpeg.all;
+
+use work.config.all;
+
+entity leon3mp is
+ generic (
+ fabtech : integer := CFG_FABTECH;
+ memtech : integer := CFG_MEMTECH;
+ padtech : integer := CFG_PADTECH;
+ clktech : integer := CFG_CLKTECH;
+ disas : integer := CFG_DISAS; -- Enable disassembly to console
+ dbguart : integer := CFG_DUART; -- Print UART on console
+ pclow : integer := CFG_PCLOW
+ );
+ port (
+ resetn : in std_ulogic;
+ clk : in std_ulogic; -- 50 MHz main clock
+ clk3 : in std_ulogic; -- 25 MHz ethernet clock
+ pllref : in std_ulogic;
+ errorn : out std_ulogic;
+ wdogn : out std_ulogic;
+ address : out std_logic_vector(27 downto 0);
+ data : inout std_logic_vector(31 downto 0);
+ ramsn : out std_logic_vector (4 downto 0);
+ ramoen : out std_logic_vector (4 downto 0);
+ rwen : out std_logic_vector (3 downto 0);
+ oen : out std_ulogic;
+ writen : out std_ulogic;
+ read : out std_ulogic;
+ iosn : out std_ulogic;
+ bexcn : in std_ulogic; -- DSU rx data
+ brdyn : in std_ulogic; -- DSU rx data
+ romsn : out std_logic_vector (1 downto 0);
+ sdclk : out std_ulogic;
+ sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
+ sdwen : out std_ulogic; -- sdram write enable
+ sdrasn : out std_ulogic; -- sdram ras
+ sdcasn : out std_ulogic; -- sdram cas
+ sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
+
+ dsuen : in std_ulogic;
+ dsubre : in std_ulogic;
+ dsuact : out std_ulogic;
+
+ txd1 : out std_ulogic; -- UART1 tx data
+ rxd1 : in std_ulogic; -- UART1 rx data
+ ctsn1 : in std_ulogic; -- UART1 rx data
+ rtsn1 : out std_ulogic; -- UART1 rx data
+ txd2 : out std_ulogic; -- UART2 tx data
+ rxd2 : in std_ulogic; -- UART2 rx data
+ ctsn2 : in std_ulogic; -- UART1 rx data
+ rtsn2 : out std_ulogic; -- UART1 rx data
+
+ pio : inout std_logic_vector(17 downto 0); -- I/O port
+
+ emdio : inout std_logic; -- ethernet PHY interface
+ etx_clk : in std_ulogic;
+ erx_clk : in std_ulogic;
+ erxd : in std_logic_vector(3 downto 0);
+ erx_dv : in std_ulogic;
+ erx_er : in std_ulogic;
+ erx_col : in std_ulogic;
+ erx_crs : in std_ulogic;
+ emdint : in std_ulogic;
+ etxd : out std_logic_vector(3 downto 0);
+ etx_en : out std_ulogic;
+ etx_er : out std_ulogic;
+ emdc : out std_ulogic;
+
+ ps2clk : inout std_logic_vector(1 downto 0);
+ ps2data : inout std_logic_vector(1 downto 0);
+
+ vid_clock : out std_ulogic;
+ vid_blankn : out std_ulogic;
+ vid_syncn : out std_ulogic;
+ vid_hsync : out std_ulogic;
+ vid_vsync : out std_ulogic;
+ vid_r : out std_logic_vector(7 downto 0);
+ vid_g : out std_logic_vector(7 downto 0);
+ vid_b : out std_logic_vector(7 downto 0);
+
+ spw_clk : in std_ulogic;
+ spw_rxdp : in std_logic_vector(0 to 2);
+ spw_rxdn : in std_logic_vector(0 to 2);
+ spw_rxsp : in std_logic_vector(0 to 2);
+ spw_rxsn : in std_logic_vector(0 to 2);
+ spw_txdp : out std_logic_vector(0 to 2);
+ spw_txdn : out std_logic_vector(0 to 2);
+ spw_txsp : out std_logic_vector(0 to 2);
+ spw_txsn : out std_logic_vector(0 to 2);
+
+ usb_clkout : in std_ulogic;
+ usb_d : inout std_logic_vector(15 downto 0);
+ usb_linestate : in std_logic_vector(1 downto 0);
+ usb_opmode : out std_logic_vector(1 downto 0);
+ usb_reset : out std_ulogic;
+ usb_rxactive : in std_ulogic;
+ usb_rxerror : in std_ulogic;
+ usb_rxvalid : in std_ulogic;
+ usb_suspend : out std_ulogic;
+ usb_termsel : out std_ulogic;
+ usb_txready : in std_ulogic;
+ usb_txvalid : out std_ulogic;
+ usb_validh : inout std_ulogic;
+ usb_xcvrsel : out std_ulogic;
+ usb_vbus : in std_ulogic;
+
+ ata_rstn : out std_logic;
+ ata_data : inout std_logic_vector(15 downto 0);
+ ata_da : out std_logic_vector(2 downto 0);
+ ata_cs0 : out std_logic;
+ ata_cs1 : out std_logic;
+ ata_dior : out std_logic;
+ ata_diow : out std_logic;
+ ata_iordy : in std_logic;
+ ata_intrq : in std_logic;
+ ata_dmarq : in std_logic;
+ ata_dmack : out std_logic;
+ --ata_dasp : in std_logic
+ ata_csel : out std_logic
+
+ );
+end;
+
+architecture rtl of leon3mp is
+
+attribute syn_netlist_hierarchy : boolean;
+attribute syn_netlist_hierarchy of rtl : architecture is false;
+
+constant blength : integer := 12;
+constant fifodepth : integer := 8;
+constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
+ CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
+ CFG_ATA+CFG_GRUSBDC+1;
+
+signal vcc, gnd : std_logic_vector(4 downto 0);
+signal memi : memory_in_type;
+signal memo : memory_out_type;
+signal wpo : wprot_out_type;
+signal sdi : sdctrl_in_type;
+signal sdo : sdram_out_type;
+signal sdo2, sdo3 : sdctrl_out_type;
+
+signal apbi : apb_slv_in_type;
+signal apbo : apb_slv_out_vector := (others => apb_none);
+signal ahbsi : ahb_slv_in_type;
+signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+signal ahbmi : ahb_mst_in_type;
+signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+signal clkm, rstn, rstraw, sdclkl : std_ulogic;
+signal cgi, cgi2 : clkgen_in_type;
+signal cgo, cgo2 : clkgen_out_type;
+signal u1i, u2i, dui : uart_in_type;
+signal u1o, u2o, duo : uart_out_type;
+
+signal irqi : irq_in_vector(0 to CFG_NCPU-1);
+signal irqo : irq_out_vector(0 to CFG_NCPU-1);
+
+signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
+signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
+
+signal dsui : dsu_in_type;
+signal dsuo : dsu_out_type;
+
+signal ethi, ethi1, ethi2 : eth_in_type;
+signal etho, etho1, etho2 : eth_out_type;
+
+signal gpti : gptimer_in_type;
+signal gpto : gptimer_out_type;
+
+signal gpioi : gpio_in_type;
+signal gpioo : gpio_out_type;
+
+signal can_lrx, can_ltx : std_logic_vector(0 to 7);
+
+signal lclk, rst, ndsuact, wdogl : std_ulogic;
+signal tck, tckn, tms, tdi, tdo : std_ulogic;
+
+signal ethclk : std_ulogic;
+
+signal kbdi : ps2_in_type;
+signal kbdo : ps2_out_type;
+signal moui : ps2_in_type;
+signal mouo : ps2_out_type;
+signal vgao : apbvga_out_type;
+
+constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
+constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
+constant IOAEN : integer := CFG_CAN + CFG_ATA + CFG_GRUSBDC;
+
+signal spwi : grspw_in_type_vector(0 to 2);
+signal spwo : grspw_out_type_vector(0 to 2);
+signal dtmp : std_logic_vector(2 downto 0);
+signal stmp : std_logic_vector(2 downto 0);
+signal spw_clkl : std_ulogic;
+signal spw_clkln : std_ulogic;
+signal rxclko : std_logic_vector(CFG_SPW_NUM-1 downto 0);
+signal stati : ahbstat_in_type;
+
+signal uclk : std_ulogic;
+signal usbi : grusb_in_type;
+signal usbo : grusb_out_type;
+
+signal idei : ata_in_type;
+signal ideo : ata_out_type;
+
+constant SPW_LOOP_BACK : integer := 0;
+
+signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
+signal clk_sel : std_logic_vector(1 downto 0);
+
+attribute keep : boolean;
+attribute syn_keep : boolean;
+attribute syn_preserve : boolean;
+attribute syn_keep of clk50 : signal is true;
+attribute syn_preserve of clk50 : signal is true;
+attribute keep of clk50 : signal is true;
+attribute syn_keep of video_clk : signal is true;
+attribute syn_preserve of video_clk : signal is true;
+attribute keep of video_clk : signal is true;
+
+begin
+
+----------------------------------------------------------------------
+--- Reset and Clock generation -------------------------------------
+----------------------------------------------------------------------
+
+ vcc <= (others => '1'); gnd <= (others => '0');
+ cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
+
+ pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
+ ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
+ clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
+ clkgen0 : clkgen -- clock generator
+ generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
+ CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
+ port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
+
+ sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
+ port map (sdclk, sdclkl);
+
+ resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
+ rst0 : rstgen -- reset generator
+ port map (rst, clkm, cgo.clklock, rstn, rstraw);
+
+----------------------------------------------------------------------
+--- AHB CONTROLLER --------------------------------------------------
+----------------------------------------------------------------------
+
+ ahb0 : ahbctrl -- AHB arbiter/multiplexer
+ generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+ rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
+ ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
+ port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
+
+----------------------------------------------------------------------
+--- LEON3 processor and DSU -----------------------------------------
+----------------------------------------------------------------------
+
+ l3 : if CFG_LEON3 = 1 generate
+ cpu : for i in 0 to CFG_NCPU-1 generate
+ u0 : leon3s -- LEON3 processor
+ generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
+ 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
+ CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
+ CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
+ CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
+ CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
+ CFG_MMU_PAGE, CFG_BP)
+ port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
+ irqi(i), irqo(i), dbgi(i), dbgo(i));
+ end generate;
+ errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
+
+ dsugen : if CFG_DSU = 1 generate
+ dsu0 : dsu3 -- LEON3 Debug Support Unit
+ generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
+ ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
+ port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
+ dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
+ dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
+ dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
+ ndsuact <= not dsuo.active;
+ end generate;
+ end generate;
+ nodsu : if CFG_DSU = 0 generate
+ dsuo.tstop <= '0'; dsuo.active <= '0';
+ end generate;
+
+ dcomgen : if CFG_AHB_UART = 1 generate
+ dcom0: ahbuart -- Debug UART
+ generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
+ port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
+ dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
+ dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
+ end generate;
+ nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
+
+ ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
+ ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
+ port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
+ open, open, open, open, open, open, open, gnd(0));
+ end generate;
+
+----------------------------------------------------------------------
+--- Memory controllers ----------------------------------------------
+----------------------------------------------------------------------
+
+ memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
+ brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
+ bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
+
+ mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
+ paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
+ ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
+ invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
+ pageburst => CFG_MCTRL_PAGE)
+ port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
+ sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
+ sdwen_pad : outpad generic map (tech => padtech)
+ port map (sdwen, sdo.sdwen);
+ sdras_pad : outpad generic map (tech => padtech)
+ port map (sdrasn, sdo.rasn);
+ sdcas_pad : outpad generic map (tech => padtech)
+ port map (sdcasn, sdo.casn);
+ sddqm_pad : outpadv generic map (width =>4, tech => padtech)
+ port map (sddqm, sdo.dqm(3 downto 0));
+ end generate;
+ sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
+ port map (sdcsn, sdo.sdcsn);
+
+ addr_pad : outpadv generic map (width => 28, tech => padtech)
+ port map (address, memo.address(27 downto 0));
+ rams_pad : outpadv generic map (width => 5, tech => padtech)
+ port map (ramsn, memo.ramsn(4 downto 0));
+ roms_pad : outpadv generic map (width => 2, tech => padtech)
+ port map (romsn, memo.romsn(1 downto 0));
+ oen_pad : outpad generic map (tech => padtech)
+ port map (oen, memo.oen);
+ rwen_pad : outpadv generic map (width => 4, tech => padtech)
+ port map (rwen, memo.wrn);
+ roen_pad : outpadv generic map (width => 5, tech => padtech)
+ port map (ramoen, memo.ramoen(4 downto 0));
+ wri_pad : outpad generic map (tech => padtech)
+ port map (writen, memo.writen);
+ read_pad : outpad generic map (tech => padtech)
+ port map (read, memo.read);
+ iosn_pad : outpad generic map (tech => padtech)
+ port map (iosn, memo.iosn);
+ bdr : for i in 0 to 3 generate
+ data_pad : iopadv generic map (tech => padtech, width => 8)
+ port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
+ memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
+ end generate;
+
+----------------------------------------------------------------------
+--- APB Bridge and various periherals -------------------------------
+----------------------------------------------------------------------
+
+ bpromgen : if CFG_AHBROMEN /= 0 generate
+ brom : entity work.ahbrom
+ generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
+ port map ( rstn, clkm, ahbsi, ahbso(6));
+ end generate;
+
+----------------------------------------------------------------------
+--- APB Bridge and various periherals -------------------------------
+----------------------------------------------------------------------
+
+ apb0 : apbctrl -- AHB/APB bridge
+ generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
+ port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
+
+ ua1 : if CFG_UART1_ENABLE /= 0 generate
+ uart1 : apbuart -- UART 1
+ generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
+ fifosize => CFG_UART1_FIFO)
+ port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
+ u1i.extclk <= '0';
+ rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
+ txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
+ cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
+ rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
+ end generate;
+ noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
+
+ ua2 : if CFG_UART2_ENABLE /= 0 generate
+ uart2 : apbuart -- UART 2
+ generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
+ port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
+ u2i.extclk <= '0';
+ rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
+ txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
+ cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
+ rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
+ end generate;
+ noua1 : if CFG_UART2_ENABLE = 0 generate
+ apbo(9) <= apb_none; rtsn2 <= '0';
+ end generate;
+
+ irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
+ irqctrl0 : irqmp -- interrupt controller
+ generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
+ port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
+ end generate;
+ irq3 : if CFG_IRQ3_ENABLE = 0 generate
+ x : for i in 0 to CFG_NCPU-1 generate
+ irqi(i).irl <= "0000";
+ end generate;
+ apbo(2) <= apb_none;
+ end generate;
+
+ gpt : if CFG_GPT_ENABLE /= 0 generate
+ timer0 : gptimer -- timer unit
+ generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
+ sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
+ nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
+ port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
+ gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
+ end generate;
+ wden : if CFG_GPT_WDOGEN /= 0 generate
+ wdogl <= gpto.wdogn or not rstn;
+ wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
+ end generate;
+ wddis : if CFG_GPT_WDOGEN = 0 generate
+ wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
+ end generate;
+
+ nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
+
+ kbd : if CFG_KBD_ENABLE /= 0 generate
+ ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
+ port map(rstn, clkm, apbi, apbo(4), moui, mouo);
+ ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
+ port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
+ end generate;
+ nokbd : if CFG_KBD_ENABLE = 0 generate
+ apbo(4) <= apb_none; mouo <= ps2o_none;
+ apbo(5) <= apb_none; kbdo <= ps2o_none;
+ end generate;
+ kbdclk_pad : iopad generic map (tech => padtech)
+ port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
+ kbdata_pad : iopad generic map (tech => padtech)
+ port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
+ mouclk_pad : iopad generic map (tech => padtech)
+ port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
+ mouata_pad : iopad generic map (tech => padtech)
+ port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
+
+ vga : if CFG_VGA_ENABLE /= 0 generate
+ vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
+ port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
+ video_clock_pad : outpad generic map ( tech => padtech)
+ port map (vid_clock, video_clk);
+ video_clk <= not ethclk;
+ end generate;
+
+ svga : if CFG_SVGA_ENABLE /= 0 generate
+ svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
+ clk0 => 40000, clk1 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
+ clk2 => 20000, clk3 => 15385, burstlen => 6)
+ port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
+ ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
+ vgaclk0 : entity work.vga_clkgen
+ port map (rstn, clk_sel, ethclk, clkm, clk50, video_clk);
+ dac_clk <= not video_clk;
+ video_clock_pad : outpad generic map ( tech => padtech)
+ port map (vid_clock, dac_clk);
+ end generate;
+
+ novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
+ apbo(6) <= apb_none; vgao <= vgao_none;
+ video_clk <= not clkm;
+ video_clock_pad : outpad generic map ( tech => padtech)
+ port map (vid_clock, video_clk);
+ end generate;
+
+ blank_pad : outpad generic map (tech => padtech)
+ port map (vid_blankn, vgao.blank);
+ comp_sync_pad : outpad generic map (tech => padtech)
+ port map (vid_syncn, vgao.comp_sync);
+ vert_sync_pad : outpad generic map (tech => padtech)
+ port map (vid_vsync, vgao.vsync);
+ horiz_sync_pad : outpad generic map (tech => padtech)
+ port map (vid_hsync, vgao.hsync);
+ video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
+ port map (vid_r, vgao.video_out_r);
+ video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
+ port map (vid_g, vgao.video_out_g);
+ video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
+ port map (vid_b, vgao.video_out_b);
+
+ gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
+ grgpio0: grgpio
+ generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
+ port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
+ gpioi => gpioi, gpioo => gpioo);
+ p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
+ pio_pads : for i in 1 to 2 generate
+ pio_pad : iopad generic map (tech => padtech)
+ port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
+ end generate;
+ end generate;
+ p1 : if (CFG_CAN = 0) generate
+ pio_pads : for i in 4 to 5 generate
+ pio_pad : iopad generic map (tech => padtech)
+ port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
+ end generate;
+ end generate;
+ pio_pad0 : iopad generic map (tech => padtech)
+ port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
+ pio_pad1 : iopad generic map (tech => padtech)
+ port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
+ pio_pads : for i in 6 to 17 generate
+ pio_pad : iopad generic map (tech => padtech)
+ port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
+ end generate;
+
+ end generate;
+
+ ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
+ ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
+ nftslv => CFG_AHBSTATN)
+ port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
+ end generate;
+
+-----------------------------------------------------------------------
+--- ETHERNET ---------------------------------------------------------
+-----------------------------------------------------------------------
+
+ eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
+ e1 : grethm generic map(
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
+ pindex => 13, paddr => 13, pirq => 13, memtech => memtech,
+ mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
+ nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
+ macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
+ ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
+ port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
+ ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
+ apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
+ end generate;
+
+ ethpads : if (CFG_GRETH = 1) generate -- eth pads
+ emdio_pad : iopad generic map (tech => padtech)
+ port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
+ etxc_pad : clkpad generic map (tech => padtech, arch => 2)
+ port map (etx_clk, ethi.tx_clk);
+ erxc_pad : clkpad generic map (tech => padtech, arch => 2)
+ port map (erx_clk, ethi.rx_clk);
+ erxd_pad : inpadv generic map (tech => padtech, width => 4)
+ port map (erxd, ethi.rxd(3 downto 0));
+ erxdv_pad : inpad generic map (tech => padtech)
+ port map (erx_dv, ethi.rx_dv);
+ erxer_pad : inpad generic map (tech => padtech)
+ port map (erx_er, ethi.rx_er);
+ erxco_pad : inpad generic map (tech => padtech)
+ port map (erx_col, ethi.rx_col);
+ erxcr_pad : inpad generic map (tech => padtech)
+ port map (erx_crs, ethi.rx_crs);
+ emdint_pad : inpad generic map (tech => padtech)
+ port map (emdint, ethi.mdint);
+
+ etxd_pad : outpadv generic map (tech => padtech, width => 4)
+ port map (etxd, etho.txd(3 downto 0));
+ etxen_pad : outpad generic map (tech => padtech)
+ port map ( etx_en, etho.tx_en);
+ etxer_pad : outpad generic map (tech => padtech)
+ port map (etx_er, etho.tx_er);
+ emdc_pad : outpad generic map (tech => padtech)
+ port map (emdc, etho.mdc);
+ end generate;
+
+-----------------------------------------------------------------------
+--- AHB RAM ----------------------------------------------------------
+-----------------------------------------------------------------------
+
+ ocram : if CFG_AHBRAMEN = 1 generate
+ ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
+ tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
+ port map ( rstn, clkm, ahbsi, ahbso(7));
+ end generate;
+
+-----------------------------------------------------------------------
+--- Multi-core CAN ---------------------------------------------------
+-----------------------------------------------------------------------
+
+ can0 : if CFG_CAN = 1 generate
+ can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
+ iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
+ ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
+ port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
+ can_tx_pad1 : iopad generic map (tech => padtech)
+ port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
+ can_rx_pad1 : iopad generic map (tech => padtech)
+ port map (pio(4), gnd(0), vcc(0), can_lrx(0));
+ canpas : if CFG_CAN_NUM = 2 generate
+ can_tx_pad2 : iopad generic map (tech => padtech)
+ port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
+ can_rx_pad2 : iopad generic map (tech => padtech)
+ port map (pio(1), gnd(0), vcc(0), can_lrx(1));
+ end generate;
+ end generate;
+
+ -- standby controlled by pio(3) and pio(0)
+
+-----------------------------------------------------------------------
+--- SPACEWIRE -------------------------------------------------------
+-----------------------------------------------------------------------
+
+ spw : if CFG_SPW_EN > 0 generate
+ core0: if CFG_SPW_GRSPW = 1 generate
+ spw_clkl <= clkm;
+ end generate;
+
+ core1 : if CFG_SPW_GRSPW = 2 generate
+ cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
+ clkgen_spw_rx : clkgen -- clock generator
+ generic map (clktech, 12, 2, 0,
+ 1, 0, 0, 0, 25000)
+ port map (clk3, clk3, spw_clkl, spw_clkln, open, open, open, cgi2, cgo2, open, open);
+ end generate;
+
+ swloop : for i in 0 to CFG_SPW_NUM-1 generate
+ core1 : if CFG_SPW_GRSPW = 2 generate
+ spw_phy0 : grspw2_phy
+ generic map(
+ scantest => 0,
+ tech => memtech,
+ input_type => CFG_SPW_INPUT)
+ port map(
+ rstn => rstn,
+ rxclki => spw_clkl,
+ rxclkin => spw_clkln,
+ nrxclki => spw_clkl,
+ di => dtmp(i),
+ si => stmp(i),
+ do => spwi(i).d(1 downto 0),
+ dov => spwi(i).dv(1 downto 0),
+ dconnect => spwi(i).dconnect(1 downto 0),
+ rxclko => rxclko(i));
+ end generate;
+
+ sw0 : grspwm generic map(tech => memtech,
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i,
+ sysfreq => CPU_FREQ, usegen => 1,
+ pindex => 10+i, paddr => 10+i, pirq => 10+i,
+ nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
+ rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
+ fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
+ rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
+ spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
+ rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
+ output_type => CFG_SPW_OUTPUT)
+ port map(rstn, clkm, rxclko(i), rxclko(i), spw_clkl, spw_clkl, ahbmi,
+ ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i),
+ apbi, apbo(10+i), spwi(i), spwo(i));
+ spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
+ spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
+ else conv_std_logic_vector((25*12/20)-1, 8);
+
+ spwlb0 : if SPW_LOOP_BACK = 1 generate
+ core0 : if CFG_SPW_GRSPW = 1 generate
+ spwi(i).d(0) <= spwo(i).d(0); spwi(i).s(0) <= spwo(i).s(0);
+ end generate;
+ core1 : if CFG_SPW_GRSPW = 2 generate
+ dtmp(i) <= spwo(i).d(0); stmp(i) <= spwo(i).s(0);
+ end generate;
+ end generate;
+
+ nospwlb0 : if SPW_LOOP_BACK = 0 generate
+ core0 : if CFG_SPW_GRSPW = 1 generate
+ spwi(i).d(0) <= dtmp(i); spwi(i).s(0) <= stmp(i);
+ end generate;
+ spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
+ port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
+ spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
+ port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
+ spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
+ port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
+ spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
+ port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
+ end generate;
+ end generate;
+ end generate;
+
+-------------------------------------------------------------------------------
+--- USB -----------------------------------------------------------------------
+-------------------------------------------------------------------------------
+ -- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
+ -- time (board has only one USB transceiver), therefore they share AHB
+ -- master/slave indexes
+ -----------------------------------------------------------------------------
+ -- Shared pads
+ -----------------------------------------------------------------------------
+ usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
+ usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
+ port map (usb_clkout, uclk);
+
+ usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
+ port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
+
+ usb_txready_pad : inpad generic map (tech => padtech)
+ port map (usb_txready,usbi.txready);
+ usb_rxvalid_pad : inpad generic map (tech => padtech)
+ port map (usb_rxvalid,usbi.rxvalid);
+ usb_rxerror_pad : inpad generic map (tech => padtech)
+ port map (usb_rxerror,usbi.rxerror);
+ usb_rxactive_pad : inpad generic map (tech => padtech)
+ port map (usb_rxactive,usbi.rxactive);
+ usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
+ port map (usb_linestate,usbi.linestate);
+ usb_vbus_pad : inpad generic map (tech => padtech)
+ port map (usb_vbus, usbi.vbusvalid);
+
+ usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
+ port map (usb_reset,usbo.reset);
+ usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
+ port map (usb_suspend,usbo.suspendm);
+ usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
+ port map (usb_termsel,usbo.termselect);
+ usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
+ port map (usb_xcvrsel,usbo.xcvrselect(0));
+ usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
+ port map (usb_txvalid,usbo.txvalid);
+ usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
+ port map (usb_opmode,usbo.opmode);
+
+ usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
+ port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
+
+ end generate;
+
+ -----------------------------------------------------------------------------
+ -- USB 2.0 Device Controller
+ -----------------------------------------------------------------------------
+ usbdc0: if CFG_GRUSBDC = 1 generate
+ usbdc0: grusbdc
+ generic map(
+ hsindex => 5, hirq => 9, haddr => 16#004#, hmask => 16#FFC#,
+ hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
+ aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
+ nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
+ i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
+ i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
+ i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
+ i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
+ i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
+ i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
+ i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
+ i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
+ o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
+ o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
+ o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
+ o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
+ o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
+ o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
+ o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
+ o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
+ memtech => memtech)
+ port map(
+ uclk => uclk,
+ usbi => usbi,
+ usbo => usbo,
+ hclk => clkm,
+ hrst => rstn,
+ ahbmi => ahbmi,
+ ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
+ ahbsi => ahbsi,
+ ahbso => ahbso(5)
+ );
+ end generate usbdc0;
+
+ -----------------------------------------------------------------------------
+ -- USB DCL
+ -----------------------------------------------------------------------------
+ usb_dcl0: if CFG_GRUSB_DCL = 1 generate
+ usb_dcl0: grusb_dcl
+ generic map (
+ hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
+ memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
+ port map (
+ uclk, usbi, usbo, clkm, rstn, ahbmi,
+ ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
+ CFG_SPW_NUM*CFG_SPW_EN));
+ end generate usb_dcl0;
+
+-----------------------------------------------------------------------
+--- AHB ATA ----------------------------------------------------------
+-----------------------------------------------------------------------
+
+ ata0 : if CFG_ATA = 1 generate
+ atac0 : atactrl
+ generic map(
+ tech => 0, fdepth => CFG_ATAFIFO,
+ mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
+ CFG_GRUSBDC,
+ shindex => 3, haddr => 16#A00#, hmask => 16#fff#, pirq => CFG_ATAIRQ,
+ mwdma => CFG_ATADMA, TWIDTH => 8,
+ -- PIO mode 0 settings (@100MHz clock)
+ PIO_mode0_T1 => 6, -- 70ns
+ PIO_mode0_T2 => 28, -- 290ns
+ PIO_mode0_T4 => 2, -- 30ns
+ PIO_mode0_Teoc => 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
+ )
+ port map(
+ rst => rstn, arst => vcc(0), clk => clkm, ahbmi => ahbmi,
+ ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+
+ CFG_GRUSB_DCL+CFG_GRUSBDC),
+ ahbsi => ahbsi, ahbso => ahbso(3), atai => idei, atao => ideo);
+
+ ata_rstn_pad : outpad generic map (tech => padtech)
+ port map (ata_rstn, ideo.rstn);
+ ata_data_pad : iopadv generic map (tech => padtech, width => 16, oepol => 1)
+ port map (ata_data, ideo.ddo, ideo.oen, idei.ddi);
+ ata_da_pad : outpadv generic map (tech => padtech, width => 3)
+ port map (ata_da, ideo.da);
+ ata_cs0_pad : outpad generic map (tech => padtech)
+ port map (ata_cs0, ideo.cs0);
+ ata_cs1_pad : outpad generic map (tech => padtech)
+ port map (ata_cs1, ideo.cs1);
+ ata_dior_pad : outpad generic map (tech => padtech)
+ port map (ata_dior, ideo.dior);
+ ata_diow_pad : outpad generic map (tech => padtech)
+ port map (ata_diow, ideo.diow);
+ iordy_pad : inpad generic map (tech => padtech)
+ port map (ata_iordy, idei.iordy);
+ intrq_pad : inpad generic map (tech => padtech)
+ port map (ata_intrq, idei.intrq);
+ dmarq_pad : inpad generic map (tech => padtech)
+ port map (ata_dmarq, idei.dmarq);
+ dmack_pad : outpad generic map (tech => padtech)
+ port map (ata_dmack, ideo.dmack);
+ ata_csel <= '0';
+ end generate;
+
+
+-------------------------------------------------------------------------------
+-- YCC-RGB translation module ---------------------------------------
+-------------------------------------------------------------------------------
+ jpgycc : yccrgbs
+ generic map(shindex => 4, haddr => 16#A00#, hirq => 10, pindex => 12,
+ paddr => 12, mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
+ CFG_GRUSBDC+CFG_ATA )
+ port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
+ ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
+ CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
+ CFG_GRUSBDC+CFG_ATA), ahbsi => ahbsi, ahbso => ahbso(4),
+ apbi => apbi, apbo => apbo(12)
+ );
+
+
+
+-----------------------------------------------------------------------
+--- Drive unused bus elements ---------------------------------------
+-----------------------------------------------------------------------
+
+-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
+-- ahbmo(i) <= ahbm_none;
+-- end generate;
+-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
+-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
+
+-----------------------------------------------------------------------
+--- Boot message ----------------------------------------------------
+-----------------------------------------------------------------------
+
+-- pragma translate_off
+ x : report_version
+ generic map (
+ msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
+ msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
+ & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
+ msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
+ mdel => 1
+ );
+-- pragma translate_on
+end;
--- /dev/null
+
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 20.00 ns HIGH 50 %;
+
+#NET "spw.swloop[0].sw0/rxclki" PERIOD = 10.0 ;
+#NET "spw.swloop[1].sw0/rxclki" PERIOD = 10.0 ;
+#NET "spw.swloop[2].sw0/rxclki" PERIOD = 10.0 ;
+
--- /dev/null
+/* linkcmds
+ *
+ * $Id: linkcmds,v 1.8.2.1 2000/05/24 17:06:38 joel Exp $
+ */
+
+OUTPUT_ARCH(sparc)
+__DYNAMIC = 0;
+
+/*
+ * The memory map looks like this:
+ * +--------------------+ <- low memory
+ * | .text |
+ * | etext |
+ * | ctor list | the ctor and dtor lists are for
+ * | dtor list | C++ support
+ * | _endtext |
+ * +--------------------+
+ * | .data | initialized data goes here
+ * | _sdata |
+ * | _edata |
+ * +--------------------+
+ * | .bss |
+ * | __bss_start | start of bss, cleared by crt0
+ * | _end | start of heap, used by sbrk()
+ * +--------------------+
+ * | heap space |
+ * | _ENDHEAP |
+ * | stack space |
+ * | __stack | top of stack
+ * +--------------------+ <- high memory
+ */
+
+
+/* Default values, can be overridden */
+
+_PROM_SIZE = 2M;
+_RAM_SIZE = 4M;
+
+_RAM_START = 0x02000000;
+_RAM_END = _RAM_START + _RAM_SIZE;
+
+_PROM_START = 0x00000000;
+_PROM_END = _PROM_START + _PROM_SIZE;
+
+/*
+ * Alternate names without leading _.
+ */
+
+PROM_START = _PROM_START;
+PROM_SIZE = _PROM_SIZE;
+PROM_END = _PROM_END;
+
+RAM_START = _RAM_START;
+RAM_SIZE = _RAM_SIZE;
+RAM_END = _RAM_END;
+
+_LEON_REG = 0x80000000;
+LEON_REG = 0x80000000;
+
+/* these are the maximum values */
+
+MEMORY
+{
+ rom : ORIGIN = 0x00000000, LENGTH = 16M
+ ram : ORIGIN = 0x40000000, LENGTH = 1024M
+}
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ text_start = .;
+ _text_start = .;
+ *(.text)
+ . = ALIGN (16);
+
+ *(.eh_frame)
+ . = ALIGN (16);
+
+ *(.gnu.linkonce.t*)
+
+ /*
+ * C++ constructors
+ */
+ __CTOR_LIST__ = .;
+ LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+ *(.ctors)
+ LONG(0)
+ __CTOR_END__ = .;
+ __DTOR_LIST__ = .;
+ LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+ *(.dtors)
+ LONG(0)
+ __DTOR_END__ = .;
+
+ _rodata_start = . ;
+ *(.rodata*)
+ *(.gnu.linkonce.r*)
+ _erodata = ALIGN( 0x10 ) ;
+
+ etext = ALIGN(0x10);
+ _etext = .;
+ *(.init)
+ *(.fini)
+ *(.lit)
+ *(.shdata)
+ . = ALIGN (16);
+ _endtext = .;
+ } > rom
+ .dynamic : { *(.dynamic) } >ram
+ .got : { *(.got) } >ram
+ .plt : { *(.plt) } >ram
+ .hash : { *(.hash) } >ram
+ .dynrel : { *(.dynrel) } >ram
+ .dynsym : { *(.dynsym) } >ram
+ .dynstr : { *(.dynstr) } >ram
+ .hash : { *(.hash) } >ram
+ .data :
+ {
+ data_start = .;
+ _data_start = .;
+ _sdata = . ;
+ *(.data)
+ *(.gnu.linkonce.d*)
+ *(.gcc_except_table)
+ . = ALIGN(0x10);
+ edata = .;
+ _edata = .;
+ } > ram
+ .shbss :
+ {
+ *(.shbss)
+ } > ram
+ .bss :
+ {
+ __bss_start = ALIGN(0x8);
+ _bss_start = .;
+ bss_start = .;
+ *(.bss)
+ *(COMMON)
+ end = .;
+ _end = ALIGN(0x8);
+ __end = ALIGN(0x8);
+ } > ram
+ .jcr . (NOLOAD) : { *(.jcr) }
+ .stab . (NOLOAD) :
+ {
+ [ .stab ]
+ }
+ .stabstr . (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+../../../snapgear-2.6-p42/user/jpeg-6b-host/out_yccrgbs.txt
\ No newline at end of file
--- /dev/null
+#define MCFG1 0x10380033
+#define MCFG2 0xe6B86e60
+#define MCFG3 0x000ff000
+#define ASDCFG 0x80000000
+#define DSDCFG 0xe6A06e60
+#define L2MCTRLIO 0x80000000
+#define IRQCTRL 0x80000200
+#define RAMSTART 0x40000000
+#define RAMSIZE 0x00100000
+
--- /dev/null
+S00C000070726F6D2E737265635A\r
+S113000081D8200003000004821060E08188400051\r
+S1130010819000008198000081800000A180000090\r
+S113002001000000030020408210600FC2A00040C5\r
+S11300308410000001000000010000000100000025\r
+S11300400100000001000000801080020100000097\r
+S11300500100000001000000010000000100000098\r
+S1130060874440008608E01F881000008A100000C2\r
+S11300708C1000008E100000A0100000A2100000E0\r
+S1130080A4100000A6100000A8100000AA10000090\r
+S1130090AC100000AE1000009010000092100000A0\r
+S11300A09410000096100000981000009A100000B0\r
+S11300B09C1000009E10000086A0E00116BFFFEF18\r
+S11300C081E00000821020028190400003000004BF\r
+S11300D0821060E0818840000100000001000000FF\r
+S11300E001000000834800008330600C80886001B8\r
+S11300F00280002401000000070000008610E1785F\r
+S1130100C108C000C118C000C518C000C918C0008B\r
+S1130110CD18C000D118C000D518C000D918C0002F\r
+S1130120DD18C000E118C000E518C000E918C000DF\r
+S1130130ED18C000F118C000F518C000F918C0008F\r
+S1130140FD18C000010000000100000001000000D3\r
+S1130150010000000100000089A008420100000025\r
+S113016001000000010000000100000010800005F3\r
+S11301700100000001000000000000000000000079\r
+S1130180874440008730E01C8688E00F1280001509\r
+S11301900320000005040E008410A033C420400096\r
+S11301A00539AE1B8410A260C4206004050003FC62\r
+S11301B0C420600882103860C40040008530A00C60\r
+S11301C0030000048210600980A040021280000530\r
+S11301D0032000000539A81B8410A260C42040003D\r
+S11301E0050000808210000080A0E000028000056D\r
+S11301F0010000008200400210BFFFFC8620E001E5\r
+S11302003D1003FFBC17A3E0BC2780019C27A0601E\r
+S11302100310000081C04000010000000100000044\r
+S113022000000000000000000000000000000000CA\r
+S9030000FC\r
--- /dev/null
+S00D0000736472616D2E7372656300\r
+S31540000000881000000910004981C121DC0100000070\r
+S31540000010A1480000A75000001080203BAC102001F2\r
+S3154000002091D0200001000000010000000100000006\r
+S3154000003091D02000010000000100000001000000F6\r
+S31540000040A14800002910004981C521140100000083\r
+S31540000050A14800002910004781C520380100000052\r
+S31540000060A14800002910004781C520A401000000D6\r
+S3154000007091D02000010000000100000001000000B6\r
+S3154000008091D02000010000000100000001000000A6\r
+S31540000090A1480000A75000001080201BAC1020098A\r
+S315400000A091D0200001000000010000000100000086\r
+S315400000B091D0200001000000010000000100000076\r
+S315400000C091D0200001000000010000000100000066\r
+S315400000D091D0200001000000010000000100000056\r
+S315400000E091D0200001000000010000000100000046\r
+S315400000F091D0200001000000010000000100000036\r
+S3154000010091D0200001000000010000000100000025\r
+S31540000110AE102001A14800001080478FA750000074\r
+S31540000120AE102002A14800001080478BA750000067\r
+S31540000130AE102003A148000010804787A75000005A\r
+S31540000140AE102004A148000010804783A75000004D\r
+S31540000150AE102005A14800001080477FA750000040\r
+S31540000160AE102006A14800001080477BA750000033\r
+S31540000170AE102007A148000010804777A750000026\r
+S31540000180AE102008A148000010804773A750000019\r
+S31540000190AE102009A14800001080476FA75000000C\r
+S315400001A0AE10200AA14800001080476BA7500000FF\r
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--- /dev/null
+//#define NORMALTEST
+//#define IP_CONNECT
+#define BOARD_TEST
+
+main()
+{
+#ifdef NORMALTEST
+ report_start();
+ base_test();
+ greth_test(0x80000d00);
+ report_end();
+#endif
+
+#ifdef IP_CONNECT
+ yccrgbs_connect();
+#endif
+
+#ifdef BOARD_TEST
+ yccrgbs_pic();
+#endif
+
+}
--- /dev/null
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench
+-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.sim.all;
+library techmap;
+use techmap.gencomp.all;
+library micron;
+use micron.components.all;
+use work.debug.all;
+
+use work.config.all; -- configuration
+
+entity testbench is
+ generic (
+ fabtech : integer := CFG_FABTECH;
+ memtech : integer := CFG_MEMTECH;
+ padtech : integer := CFG_PADTECH;
+ clktech : integer := CFG_CLKTECH;
+ disas : integer := CFG_DISAS; -- Enable disassembly to console
+ dbguart : integer := CFG_DUART; -- Print UART on console
+ pclow : integer := CFG_PCLOW;
+
+ clkperiod : integer := 20; -- system clock period
+ romwidth : integer := 32; -- rom data width (8/32)
+ romdepth : integer := 16; -- rom address depth
+ sramwidth : integer := 32; -- ram data width (8/16/32)
+ sramdepth : integer := 18; -- ram address depth
+ srambanks : integer := 2 -- number of ram banks
+ );
+end;
+
+architecture behav of testbench is
+
+constant promfile : string := "prom.srec"; -- rom contents
+constant sramfile : string := "sram.srec"; -- ram contents
+constant sdramfile : string := "sdram.srec"; -- sdram contents
+
+component leon3mp
+ generic (
+ fabtech : integer := CFG_FABTECH;
+ memtech : integer := CFG_MEMTECH;
+ padtech : integer := CFG_PADTECH;
+ clktech : integer := CFG_CLKTECH;
+ disas : integer := CFG_DISAS; -- Enable disassembly to console
+ dbguart : integer := CFG_DUART; -- Print UART on console
+ pclow : integer := CFG_PCLOW
+ );
+ port (
+ resetn : in std_ulogic;
+ clk : in std_ulogic;
+ clk3 : in std_ulogic;
+ pllref : in std_ulogic;
+ errorn : out std_ulogic;
+ wdogn : out std_ulogic;
+
+ address : out std_logic_vector(27 downto 0);
+ data : inout std_logic_vector(31 downto 0);
+ ramsn : out std_logic_vector (4 downto 0);
+ ramoen : out std_logic_vector (4 downto 0);
+ rwen : out std_logic_vector (3 downto 0);
+ oen : out std_ulogic;
+ writen : out std_ulogic;
+ read : out std_ulogic;
+ iosn : out std_ulogic;
+ bexcn : in std_ulogic; -- DSU rx data
+ brdyn : in std_ulogic; -- DSU rx data
+ romsn : out std_logic_vector (1 downto 0);
+ sdclk : out std_ulogic;
+ sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
+ sdwen : out std_ulogic; -- sdram write enable
+ sdrasn : out std_ulogic; -- sdram ras
+ sdcasn : out std_ulogic; -- sdram cas
+ sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
+
+ dsuen : in std_ulogic;
+ dsubre : in std_ulogic;
+ dsuact : out std_ulogic;
+
+ txd1 : out std_ulogic; -- UART1 tx data
+ rxd1 : in std_ulogic; -- UART1 rx data
+ ctsn1 : in std_ulogic; -- UART1 rx data
+ rtsn1 : out std_ulogic; -- UART1 rx data
+ txd2 : out std_ulogic; -- UART2 tx data
+ rxd2 : in std_ulogic; -- UART2 rx data
+ ctsn2 : in std_ulogic; -- UART1 rx data
+ rtsn2 : out std_ulogic; -- UART1 rx data
+
+ pio : inout std_logic_vector(17 downto 0); -- I/O port
+
+ emdio : inout std_logic; -- ethernet PHY interface
+ etx_clk : in std_ulogic;
+ erx_clk : in std_ulogic;
+ erxd : in std_logic_vector(3 downto 0);
+ erx_dv : in std_ulogic;
+ erx_er : in std_ulogic;
+ erx_col : in std_ulogic;
+ erx_crs : in std_ulogic;
+ emdint : in std_ulogic;
+ etxd : out std_logic_vector(3 downto 0);
+ etx_en : out std_ulogic;
+ etx_er : out std_ulogic;
+ emdc : out std_ulogic;
+
+ ps2clk : inout std_logic_vector(1 downto 0);
+ ps2data : inout std_logic_vector(1 downto 0);
+
+ vid_clock : out std_ulogic;
+ vid_blankn : out std_ulogic;
+ vid_syncn : out std_ulogic;
+ vid_hsync : out std_ulogic;
+ vid_vsync : out std_ulogic;
+ vid_r : out std_logic_vector(7 downto 0);
+ vid_g : out std_logic_vector(7 downto 0);
+ vid_b : out std_logic_vector(7 downto 0);
+
+ spw_clk : in std_ulogic;
+ spw_rxdp : in std_logic_vector(0 to 2);
+ spw_rxdn : in std_logic_vector(0 to 2);
+ spw_rxsp : in std_logic_vector(0 to 2);
+ spw_rxsn : in std_logic_vector(0 to 2);
+ spw_txdp : out std_logic_vector(0 to 2);
+ spw_txdn : out std_logic_vector(0 to 2);
+ spw_txsp : out std_logic_vector(0 to 2);
+ spw_txsn : out std_logic_vector(0 to 2);
+
+ usb_clkout : in std_ulogic;
+ usb_d : inout std_logic_vector(15 downto 0);
+ usb_linestate : in std_logic_vector(1 downto 0);
+ usb_opmode : out std_logic_vector(1 downto 0);
+ usb_reset : out std_ulogic;
+ usb_rxactive : in std_ulogic;
+ usb_rxerror : in std_ulogic;
+ usb_rxvalid : in std_ulogic;
+ usb_suspend : out std_ulogic;
+ usb_termsel : out std_ulogic;
+ usb_txready : in std_ulogic;
+ usb_txvalid : out std_ulogic;
+ usb_validh : inout std_ulogic;
+ usb_xcvrsel : out std_ulogic;
+ usb_vbus : in std_ulogic;
+
+ ata_rstn : out std_logic;
+ ata_data : inout std_logic_vector(15 downto 0);
+ ata_da : out std_logic_vector(2 downto 0);
+ ata_cs0 : out std_logic;
+ ata_cs1 : out std_logic;
+ ata_dior : out std_logic;
+ ata_diow : out std_logic;
+ ata_iordy : in std_logic;
+ ata_intrq : in std_logic;
+ ata_dmarq : in std_logic;
+ ata_dmack : out std_logic;
+ --ata_dasp : in std_logic;
+ ata_csel : out std_logic
+
+ );
+
+end component;
+
+signal clk : std_logic := '0';
+signal Rst : std_logic := '0'; -- Reset
+constant ct : integer := clkperiod/2;
+
+signal address : std_logic_vector(27 downto 0);
+signal data : std_logic_vector(31 downto 0);
+signal pio : std_logic_vector(17 downto 0);
+signal romsn : std_logic_vector(1 downto 0);
+signal ramsn : std_logic_vector(4 downto 0);
+signal ramoen : std_logic_vector(4 downto 0);
+signal rwen : std_logic_vector(3 downto 0);
+signal oen : std_ulogic;
+signal writen : std_ulogic;
+signal read : std_ulogic;
+signal iosn : std_ulogic;
+signal bexcn : std_ulogic;
+signal brdyn : std_ulogic;
+signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
+signal dsurst : std_ulogic;
+signal GND : std_ulogic := '0';
+signal VCC : std_ulogic := '1';
+signal NC : std_ulogic := 'Z';
+signal clk2 : std_ulogic := '1';
+signal wdogn : std_logic;
+
+signal sdcke : std_ulogic; -- clk en
+signal sdcsn : std_logic_vector ( 1 downto 0);
+signal sdwen : std_ulogic; -- write en
+signal sdrasn : std_ulogic; -- row addr stb
+signal sdcasn : std_ulogic; -- col addr stb
+signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
+signal sdclk : std_ulogic;
+signal pllref : std_ulogic;
+signal txd1, rxd1 : std_logic;
+signal txd2, rxd2 : std_logic;
+signal ctsn1, rtsn1 : std_ulogic;
+signal ctsn2, rtsn2 : std_ulogic;
+signal errorn : std_logic;
+
+signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
+signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
+signal erxdt, etxdt : std_logic_vector(7 downto 0);
+signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
+signal eth_macclk : std_ulogic := '0';
+signal emdint : std_ulogic;
+
+signal ps2clk : std_logic_vector(1 downto 0);
+signal ps2data : std_logic_vector(1 downto 0);
+
+signal vid_clock : std_ulogic;
+signal vid_blankn : std_ulogic;
+signal vid_syncn : std_ulogic;
+signal vid_hsync : std_ulogic;
+signal vid_vsync : std_ulogic;
+signal vid_r : std_logic_vector(7 downto 0);
+signal vid_g : std_logic_vector(7 downto 0);
+signal vid_b : std_logic_vector(7 downto 0);
+signal clk3 : std_ulogic := '0';
+
+signal spw_clk : std_ulogic := '0';
+signal spw_rxdp : std_logic_vector(0 to 2) := "000";
+signal spw_rxdn : std_logic_vector(0 to 2) := "000";
+signal spw_rxsp : std_logic_vector(0 to 2) := "000";
+signal spw_rxsn : std_logic_vector(0 to 2) := "000";
+signal spw_txdp : std_logic_vector(0 to 2);
+signal spw_txdn : std_logic_vector(0 to 2);
+signal spw_txsp : std_logic_vector(0 to 2);
+signal spw_txsn : std_logic_vector(0 to 2);
+
+signal usb_clkout : std_ulogic := '0';
+signal usb_d : std_logic_vector(15 downto 0);
+signal usb_linestate : std_logic_vector(1 downto 0);
+signal usb_opmode : std_logic_vector(1 downto 0);
+signal usb_reset : std_ulogic;
+signal usb_rxactive : std_ulogic;
+signal usb_rxerror : std_ulogic;
+signal usb_rxvalid : std_ulogic;
+signal usb_suspend : std_ulogic;
+signal usb_termsel : std_ulogic;
+signal usb_txready : std_ulogic;
+signal usb_txvalid : std_ulogic;
+signal usb_validh : std_logic;
+signal usb_xcvrsel : std_ulogic;
+signal usb_vbus : std_ulogic;
+signal rhvalid : std_ulogic;
+
+signal ata_data : std_logic_vector(15 downto 0);
+signal ata_da : std_logic_vector(2 downto 0);
+signal ata_cs0 : std_logic;
+signal ata_cs1 : std_logic;
+signal ata_dior : std_logic;
+signal ata_diow : std_logic;
+signal ata_iordy : std_logic;
+signal ata_intrq : std_logic;
+signal ata_dmarq : std_logic;
+signal ata_dmack : std_logic;
+signal ata_rstn : std_logic;
+signal ata_csel : std_logic;
+
+signal from_ata : ata_out_type := ATAO_RESET_VECTOR;
+signal to_ata : ata_in_type := ATAI_RESET_VECTOR;
+
+constant lresp : boolean := false;
+
+begin
+
+-- clock and reset
+
+ clk <= not clk after ct * 1 ns;
+ clk3 <= not clk3 after 20 ns;
+ rst <= dsurst and wdogn;
+ dsuen <= '1'; dsubre <= '0';
+ rxd1 <= 'H'; ctsn1 <= '0';
+ rxd2 <= 'H'; ctsn2 <= '0'; pllref <= sdclk;
+ ps2clk <= "HH"; ps2data <= "HH";
+-- pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
+ wdogn <= 'H';
+ usb_clkout <= not usb_clkout after 8.33 ns; -- ~60MHz
+
+ spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
+ spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
+
+ ata_iordy <= 'H'; ata_intrq <= 'H'; ata_dmarq <= 'H';
+ ata_data <= (others => 'H');
+
+ cpu : leon3mp
+ generic map ( fabtech, memtech, padtech, clktech,
+ disas, dbguart, pclow )
+ port map (rst, clk, clk3, pllref, errorn, wdogn, address(27 downto 0), data,
+ ramsn, ramoen, rwen, oen, writen, read, iosn, bexcn, brdyn, romsn,
+ sdclk, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
+ dsuen, dsubre, dsuact,
+ txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio,
+ emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs, emdint,
+ etxd, etx_en, etx_er, emdc, ps2clk, ps2data, vid_clock, vid_blankn, vid_syncn,
+ vid_hsync, vid_vsync, vid_r, vid_g, vid_b, spw_clk, spw_rxdp, spw_rxdn,
+ spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn, usb_clkout,
+ usb_d, usb_linestate, usb_opmode, usb_reset, usb_rxactive, usb_rxerror,
+ usb_rxvalid, usb_suspend, usb_termsel, usb_txready, usb_txvalid, usb_validh,
+ usb_xcvrsel, usb_vbus, ata_rstn, ata_data, ata_da, ata_cs0, ata_cs1,
+ ata_dior, ata_diow, ata_iordy, ata_intrq, ata_dmarq, ata_dmack, ata_csel
+ );
+
+ u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
+ PORT MAP(
+ Dq => data(31 downto 16), Addr => address(14 downto 2),
+ Ba => address(16 downto 15), Clk => sdclk, Cke => vcc,
+ Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
+ Dqm => sddqm(3 downto 2));
+ u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
+ PORT MAP(
+ Dq => data(15 downto 0), Addr => address(14 downto 2),
+ Ba => address(16 downto 15), Clk => sdclk, Cke => vcc,
+ Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
+ Dqm => sddqm(1 downto 0));
+
+ prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
+ port map (address(romdepth-1 downto 0), data(31 downto 24), romsn(0),
+ writen, oen);
+
+ disk: ata_device
+ generic map( sector_length => 512, log2_size => 14)
+ port map( clk => clk, rst => rst, d => ata_data, atai => to_ata,
+ atao => from_ata
+ );
+ to_ata.cs(0)<=ata_cs0; to_ata.cs(1)<=ata_cs1;
+ to_ata.da<=ata_da; to_ata.dmack<=ata_dmack;
+ to_ata.dior<=ata_dior; to_ata.diow<=ata_diow; to_ata.reset<=ata_rstn;
+ ata_dmarq<=from_ata.dmarq; ata_intrq<=from_ata.intrq; ata_iordy<=from_ata.iordy;
+
+
+ phy0 : if (CFG_GRETH = 1) generate
+ emdio <= 'H';
+ erxd <= erxdt(3 downto 0);
+ etxdt <= "0000" & etxd;
+ p0: phy
+ generic map(base1000_t_fd => 0, base1000_t_hd => 0)
+ port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
+ erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
+ end generate;
+
+ ps2devs: for i in 0 to 1 generate
+ ps2_device(ps2clk(i), ps2data(i));
+ end generate ps2devs;
+
+ errorn <= 'H'; -- ERROR pull-up
+
+ iuerr : process
+ begin
+ wait for 5000 ns;
+ if to_x01(errorn) = '1' then wait on errorn; end if;
+ assert (to_x01(errorn) = '1')
+ report "*** IU in error mode, simulation halted ***"
+ severity failure ;
+ end process;
+
+ test0 : grtestmod
+ port map ( rst, clk, errorn, address(21 downto 2), data,
+ iosn, oen, writen, brdyn);
+
+
+ data <= buskeep(data) after 5 ns;
+
+ dsucom : process
+ procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
+ variable w32 : std_logic_vector(31 downto 0);
+ variable c8 : std_logic_vector(7 downto 0);
+ constant txp : time := 320 * 1 ns;
+ begin
+ dsutx <= '1';
+ dsurst <= '0';
+ wait for 2500 ns;
+ dsurst <= '1';
+ wait;
+ wait for 5000 ns;
+ txc(dsutx, 16#55#, txp); -- sync uart
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
+
+ wait for 25000 ns;
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
+ txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
+
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
+
+ txc(dsutx, 16#80#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
+
+ wait;
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
+ txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
+ txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
+
+
+
+
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
+
+ txc(dsutx, 16#c0#, txp);
+ txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
+ txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
+
+ txc(dsutx, 16#80#, txp);
+ txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
+ rxi(dsurx, w32, txp, lresp);
+
+ txc(dsutx, 16#a0#, txp);
+ txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
+ rxi(dsurx, w32, txp, lresp);
+
+ end;
+
+ begin
+
+ dsucfg(txd2, rxd2);
+
+ wait;
+ end process;
+end ;
+
--- /dev/null
+#if defined CONFIG_SYN_INFERRED
+#define CONFIG_SYN_TECH inferred
+#elif defined CONFIG_SYN_UMC
+#define CONFIG_SYN_TECH umc
+#elif defined CONFIG_SYN_RHUMC
+#define CONFIG_SYN_TECH rhumc
+#elif defined CONFIG_SYN_ATC18
+#define CONFIG_SYN_TECH atc18s
+#elif defined CONFIG_SYN_ATC18RHA
+#define CONFIG_SYN_TECH atc18rha
+#elif defined CONFIG_SYN_AXCEL
+#define CONFIG_SYN_TECH axcel
+#elif defined CONFIG_SYN_AXDSP
+#define CONFIG_SYN_TECH axdsp
+#elif defined CONFIG_SYN_PROASICPLUS
+#define CONFIG_SYN_TECH proasic
+#elif defined CONFIG_SYN_ALTERA
+#define CONFIG_SYN_TECH altera
+#elif defined CONFIG_SYN_STRATIX
+#define CONFIG_SYN_TECH stratix1
+#elif defined CONFIG_SYN_STRATIXII
+#define CONFIG_SYN_TECH stratix2
+#elif defined CONFIG_SYN_STRATIXIII
+#define CONFIG_SYN_TECH stratix3
+#elif defined CONFIG_SYN_CYCLONEIII
+#define CONFIG_SYN_TECH cyclone3
+#elif defined CONFIG_SYN_EASIC90
+#define CONFIG_SYN_TECH easic90
+#elif defined CONFIG_SYN_IHP25
+#define CONFIG_SYN_TECH ihp25
+#elif defined CONFIG_SYN_IHP25RH
+#define CONFIG_SYN_TECH ihp25rh
+#elif defined CONFIG_SYN_LATTICE
+#define CONFIG_SYN_TECH lattice
+#elif defined CONFIG_SYN_ECLIPSE
+#define CONFIG_SYN_TECH eclipse
+#elif defined CONFIG_SYN_PEREGRINE
+#define CONFIG_SYN_TECH peregrine
+#elif defined CONFIG_SYN_PROASIC
+#define CONFIG_SYN_TECH proasic
+#elif defined CONFIG_SYN_PROASIC3
+#define CONFIG_SYN_TECH apa3
+#elif defined CONFIG_SYN_IGLOO
+#define CONFIG_SYN_TECH apa3
+#elif defined CONFIG_SYN_SPARTAN2
+#define CONFIG_SYN_TECH virtex
+#elif defined CONFIG_SYN_VIRTEX
+#define CONFIG_SYN_TECH virtex
+#elif defined CONFIG_SYN_VIRTEXE
+#define CONFIG_SYN_TECH virtex
+#elif defined CONFIG_SYN_SPARTAN3
+#define CONFIG_SYN_TECH spartan3
+#elif defined CONFIG_SYN_SPARTAN3E
+#define CONFIG_SYN_TECH spartan3e
+#elif defined CONFIG_SYN_SPARTAN6
+#define CONFIG_SYN_TECH spartan6
+#elif defined CONFIG_SYN_VIRTEX2
+#define CONFIG_SYN_TECH virtex2
+#elif defined CONFIG_SYN_VIRTEX4
+#define CONFIG_SYN_TECH virtex4
+#elif defined CONFIG_SYN_VIRTEX5
+#define CONFIG_SYN_TECH virtex5
+#elif defined CONFIG_SYN_VIRTEX6
+#define CONFIG_SYN_TECH virtex6
+#elif defined CONFIG_SYN_RH_LIB18T
+#define CONFIG_SYN_TECH rhlib18t
+#elif defined CONFIG_SYN_SMIC13
+#define CONFIG_SYN_TECH smic013
+#elif defined CONFIG_SYN_UT025CRH
+#define CONFIG_SYN_TECH ut25
+#elif defined CONFIG_SYN_TSMC90
+#define CONFIG_SYN_TECH tsmc90
+#elif defined CONFIG_SYN_CUSTOM1
+#define CONFIG_SYN_TECH custom1
+#else
+#error "unknown target technology"
+#endif
+
+#if defined CONFIG_SYN_INFER_RAM
+#define CFG_RAM_TECH inferred
+#elif defined CONFIG_MEM_UMC
+#define CFG_RAM_TECH umc
+#elif defined CONFIG_MEM_RHUMC
+#define CFG_RAM_TECH rhumc
+#elif defined CONFIG_MEM_VIRAGE
+#define CFG_RAM_TECH memvirage
+#elif defined CONFIG_MEM_ARTISAN
+#define CFG_RAM_TECH memartisan
+#elif defined CONFIG_MEM_CUSTOM1
+#define CFG_RAM_TECH custom1
+#elif defined CONFIG_MEM_VIRAGE90
+#define CFG_RAM_TECH memvirage90
+#elif defined CONFIG_MEM_INFERRED
+#define CFG_RAM_TECH inferred
+#else
+#define CFG_RAM_TECH CONFIG_SYN_TECH
+#endif
+
+#if defined CONFIG_SYN_INFER_PADS
+#define CFG_PAD_TECH inferred
+#else
+#define CFG_PAD_TECH CONFIG_SYN_TECH
+#endif
+
+#ifndef CONFIG_SYN_NO_ASYNC
+#define CONFIG_SYN_NO_ASYNC 0
+#endif
+
+#ifndef CONFIG_SYN_SCAN
+#define CONFIG_SYN_SCAN 0
+#endif
+
+
+#if defined CONFIG_CLK_ALTDLL
+#define CFG_CLK_TECH CONFIG_SYN_TECH
+#elif defined CONFIG_CLK_HCLKBUF
+#define CFG_CLK_TECH axcel
+#elif defined CONFIG_CLK_LATDLL
+#define CFG_CLK_TECH lattice
+#elif defined CONFIG_CLK_PRO3PLL
+#define CFG_CLK_TECH apa3
+#elif defined CONFIG_CLK_CLKDLL
+#define CFG_CLK_TECH virtex
+#elif defined CONFIG_CLK_DCM
+#define CFG_CLK_TECH CONFIG_SYN_TECH
+#elif defined CONFIG_CLK_LIB18T
+#define CFG_CLK_TECH rhlib18t
+#elif defined CONFIG_CLK_RHUMC
+#define CFG_CLK_TECH rhumc
+#else
+#define CFG_CLK_TECH inferred
+#endif
+
+#ifndef CONFIG_CLK_MUL
+#define CONFIG_CLK_MUL 2
+#endif
+
+#ifndef CONFIG_CLK_DIV
+#define CONFIG_CLK_DIV 2
+#endif
+
+#ifndef CONFIG_OCLK_DIV
+#define CONFIG_OCLK_DIV 2
+#endif
+
+#ifndef CONFIG_PCI_CLKDLL
+#define CONFIG_PCI_CLKDLL 0
+#endif
+
+#ifndef CONFIG_PCI_SYSCLK
+#define CONFIG_PCI_SYSCLK 0
+#endif
+
+#ifndef CONFIG_CLK_NOFB
+#define CONFIG_CLK_NOFB 0
+#endif
+#ifndef CONFIG_LEON3
+#define CONFIG_LEON3 0
+#endif
+
+#ifndef CONFIG_PROC_NUM
+#define CONFIG_PROC_NUM 1
+#endif
+
+#ifndef CONFIG_IU_NWINDOWS
+#define CONFIG_IU_NWINDOWS 8
+#endif
+
+#ifndef CONFIG_IU_RSTADDR
+#define CONFIG_IU_RSTADDR 8
+#endif
+
+#ifndef CONFIG_IU_LDELAY
+#define CONFIG_IU_LDELAY 1
+#endif
+
+#ifndef CONFIG_IU_WATCHPOINTS
+#define CONFIG_IU_WATCHPOINTS 0
+#endif
+
+#ifdef CONFIG_IU_V8MULDIV
+#ifdef CONFIG_IU_MUL_LATENCY_4
+#define CFG_IU_V8 1
+#elif defined CONFIG_IU_MUL_LATENCY_5
+#define CFG_IU_V8 2
+#elif defined CONFIG_IU_MUL_LATENCY_2
+#define CFG_IU_V8 16#32#
+#endif
+#else
+#define CFG_IU_V8 0
+#endif
+
+#ifndef CONFIG_PWD
+#define CONFIG_PWD 0
+#endif
+
+#ifndef CONFIG_IU_MUL_MAC
+#define CONFIG_IU_MUL_MAC 0
+#endif
+
+#ifndef CONFIG_IU_BP
+#define CONFIG_IU_BP 0
+#endif
+
+#ifndef CONFIG_IU_SVT
+#define CONFIG_IU_SVT 0
+#endif
+
+#if defined CONFIG_FPU_GRFPC1
+#define CONFIG_FPU_GRFPC 1
+#elif defined CONFIG_FPU_GRFPC2
+#define CONFIG_FPU_GRFPC 2
+#else
+#define CONFIG_FPU_GRFPC 0
+#endif
+
+#if defined CONFIG_FPU_GRFPU_INFMUL
+#define CONFIG_FPU_GRFPU_MUL 0
+#elif defined CONFIG_FPU_GRFPU_DWMUL
+#define CONFIG_FPU_GRFPU_MUL 1
+#elif defined CONFIG_FPU_GRFPU_MODGEN
+#define CONFIG_FPU_GRFPU_MUL 2
+#elif defined CONFIG_FPU_GRFPU_TECHSPEC
+#define CONFIG_FPU_GRFPU_MUL 3
+#else
+#define CONFIG_FPU_GRFPU_MUL 0
+#endif
+
+#if defined CONFIG_FPU_GRFPU_SH
+#define CONFIG_FPU_GRFPU_SHARED 1
+#else
+#define CONFIG_FPU_GRFPU_SHARED 0
+#endif
+
+#if defined CONFIG_FPU_GRFPU
+#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
+#elif defined CONFIG_FPU_MEIKO
+#define CONFIG_FPU 15
+#elif defined CONFIG_FPU_GRFPULITE
+#define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
+#else
+#define CONFIG_FPU 0
+#endif
+
+#ifndef CONFIG_FPU_NETLIST
+#define CONFIG_FPU_NETLIST 0
+#endif
+
+#ifndef CONFIG_ICACHE_ENABLE
+#define CONFIG_ICACHE_ENABLE 0
+#endif
+
+#if defined CONFIG_ICACHE_ASSO1
+#define CFG_IU_ISETS 1
+#elif defined CONFIG_ICACHE_ASSO2
+#define CFG_IU_ISETS 2
+#elif defined CONFIG_ICACHE_ASSO3
+#define CFG_IU_ISETS 3
+#elif defined CONFIG_ICACHE_ASSO4
+#define CFG_IU_ISETS 4
+#else
+#define CFG_IU_ISETS 1
+#endif
+
+#if defined CONFIG_ICACHE_SZ1
+#define CFG_ICACHE_SZ 1
+#elif defined CONFIG_ICACHE_SZ2
+#define CFG_ICACHE_SZ 2
+#elif defined CONFIG_ICACHE_SZ4
+#define CFG_ICACHE_SZ 4
+#elif defined CONFIG_ICACHE_SZ8
+#define CFG_ICACHE_SZ 8
+#elif defined CONFIG_ICACHE_SZ16
+#define CFG_ICACHE_SZ 16
+#elif defined CONFIG_ICACHE_SZ32
+#define CFG_ICACHE_SZ 32
+#elif defined CONFIG_ICACHE_SZ64
+#define CFG_ICACHE_SZ 64
+#elif defined CONFIG_ICACHE_SZ128
+#define CFG_ICACHE_SZ 128
+#elif defined CONFIG_ICACHE_SZ256
+#define CFG_ICACHE_SZ 256
+#else
+#define CFG_ICACHE_SZ 1
+#endif
+
+#ifdef CONFIG_ICACHE_LZ16
+#define CFG_ILINE_SZ 4
+#else
+#define CFG_ILINE_SZ 8
+#endif
+
+#if defined CONFIG_ICACHE_ALGORND
+#define CFG_ICACHE_ALGORND 2
+#elif defined CONFIG_ICACHE_ALGOLRR
+#define CFG_ICACHE_ALGORND 1
+#else
+#define CFG_ICACHE_ALGORND 0
+#endif
+
+#ifndef CONFIG_ICACHE_LOCK
+#define CONFIG_ICACHE_LOCK 0
+#endif
+
+#ifndef CONFIG_ICACHE_LRAM
+#define CONFIG_ICACHE_LRAM 0
+#endif
+
+#ifndef CONFIG_ICACHE_LRSTART
+#define CONFIG_ICACHE_LRSTART 8E
+#endif
+
+#if defined CONFIG_ICACHE_LRAM_SZ2
+#define CFG_ILRAM_SIZE 2
+#elif defined CONFIG_ICACHE_LRAM_SZ4
+#define CFG_ILRAM_SIZE 4
+#elif defined CONFIG_ICACHE_LRAM_SZ8
+#define CFG_ILRAM_SIZE 8
+#elif defined CONFIG_ICACHE_LRAM_SZ16
+#define CFG_ILRAM_SIZE 16
+#elif defined CONFIG_ICACHE_LRAM_SZ32
+#define CFG_ILRAM_SIZE 32
+#elif defined CONFIG_ICACHE_LRAM_SZ64
+#define CFG_ILRAM_SIZE 64
+#elif defined CONFIG_ICACHE_LRAM_SZ128
+#define CFG_ILRAM_SIZE 128
+#elif defined CONFIG_ICACHE_LRAM_SZ256
+#define CFG_ILRAM_SIZE 256
+#else
+#define CFG_ILRAM_SIZE 1
+#endif
+
+
+#ifndef CONFIG_DCACHE_ENABLE
+#define CONFIG_DCACHE_ENABLE 0
+#endif
+
+#if defined CONFIG_DCACHE_ASSO1
+#define CFG_IU_DSETS 1
+#elif defined CONFIG_DCACHE_ASSO2
+#define CFG_IU_DSETS 2
+#elif defined CONFIG_DCACHE_ASSO3
+#define CFG_IU_DSETS 3
+#elif defined CONFIG_DCACHE_ASSO4
+#define CFG_IU_DSETS 4
+#else
+#define CFG_IU_DSETS 1
+#endif
+
+#if defined CONFIG_DCACHE_SZ1
+#define CFG_DCACHE_SZ 1
+#elif defined CONFIG_DCACHE_SZ2
+#define CFG_DCACHE_SZ 2
+#elif defined CONFIG_DCACHE_SZ4
+#define CFG_DCACHE_SZ 4
+#elif defined CONFIG_DCACHE_SZ8
+#define CFG_DCACHE_SZ 8
+#elif defined CONFIG_DCACHE_SZ16
+#define CFG_DCACHE_SZ 16
+#elif defined CONFIG_DCACHE_SZ32
+#define CFG_DCACHE_SZ 32
+#elif defined CONFIG_DCACHE_SZ64
+#define CFG_DCACHE_SZ 64
+#elif defined CONFIG_DCACHE_SZ128
+#define CFG_DCACHE_SZ 128
+#elif defined CONFIG_DCACHE_SZ256
+#define CFG_DCACHE_SZ 256
+#else
+#define CFG_DCACHE_SZ 1
+#endif
+
+#ifdef CONFIG_DCACHE_LZ16
+#define CFG_DLINE_SZ 4
+#else
+#define CFG_DLINE_SZ 8
+#endif
+
+#if defined CONFIG_DCACHE_ALGORND
+#define CFG_DCACHE_ALGORND 2
+#elif defined CONFIG_DCACHE_ALGOLRR
+#define CFG_DCACHE_ALGORND 1
+#else
+#define CFG_DCACHE_ALGORND 0
+#endif
+
+#ifndef CONFIG_DCACHE_LOCK
+#define CONFIG_DCACHE_LOCK 0
+#endif
+
+#ifndef CONFIG_DCACHE_SNOOP
+#define CONFIG_DCACHE_SNOOP 0
+#endif
+
+#ifndef CONFIG_DCACHE_SNOOP_FAST
+#define CONFIG_DCACHE_SNOOP_FAST 0
+#endif
+
+#ifndef CONFIG_DCACHE_SNOOP_SEPTAG
+#define CONFIG_DCACHE_SNOOP_SEPTAG 0
+#endif
+
+#ifndef CONFIG_CACHE_FIXED
+#define CONFIG_CACHE_FIXED 0
+#endif
+
+#ifndef CONFIG_DCACHE_LRAM
+#define CONFIG_DCACHE_LRAM 0
+#endif
+
+#ifndef CONFIG_DCACHE_LRSTART
+#define CONFIG_DCACHE_LRSTART 8F
+#endif
+
+#if defined CONFIG_DCACHE_LRAM_SZ2
+#define CFG_DLRAM_SIZE 2
+#elif defined CONFIG_DCACHE_LRAM_SZ4
+#define CFG_DLRAM_SIZE 4
+#elif defined CONFIG_DCACHE_LRAM_SZ8
+#define CFG_DLRAM_SIZE 8
+#elif defined CONFIG_DCACHE_LRAM_SZ16
+#define CFG_DLRAM_SIZE 16
+#elif defined CONFIG_DCACHE_LRAM_SZ32
+#define CFG_DLRAM_SIZE 32
+#elif defined CONFIG_DCACHE_LRAM_SZ64
+#define CFG_DLRAM_SIZE 64
+#elif defined CONFIG_DCACHE_LRAM_SZ128
+#define CFG_DLRAM_SIZE 128
+#elif defined CONFIG_DCACHE_LRAM_SZ256
+#define CFG_DLRAM_SIZE 256
+#else
+#define CFG_DLRAM_SIZE 1
+#endif
+
+#if defined CONFIG_MMU_PAGE_4K
+#define CONFIG_MMU_PAGE 0
+#elif defined CONFIG_MMU_PAGE_8K
+#define CONFIG_MMU_PAGE 1
+#elif defined CONFIG_MMU_PAGE_16K
+#define CONFIG_MMU_PAGE 2
+#elif defined CONFIG_MMU_PAGE_32K
+#define CONFIG_MMU_PAGE 3
+#elif defined CONFIG_MMU_PAGE_PROG
+#define CONFIG_MMU_PAGE 4
+#else
+#define CONFIG_MMU_PAGE 0
+#endif
+
+#ifdef CONFIG_MMU_ENABLE
+#define CONFIG_MMUEN 1
+
+#ifdef CONFIG_MMU_SPLIT
+#define CONFIG_TLB_TYPE 0
+#endif
+#ifdef CONFIG_MMU_COMBINED
+#define CONFIG_TLB_TYPE 1
+#endif
+
+#ifdef CONFIG_MMU_REPARRAY
+#define CONFIG_TLB_REP 0
+#endif
+#ifdef CONFIG_MMU_REPINCREMENT
+#define CONFIG_TLB_REP 1
+#endif
+
+#ifdef CONFIG_MMU_I2
+#define CONFIG_ITLBNUM 2
+#endif
+#ifdef CONFIG_MMU_I4
+#define CONFIG_ITLBNUM 4
+#endif
+#ifdef CONFIG_MMU_I8
+#define CONFIG_ITLBNUM 8
+#endif
+#ifdef CONFIG_MMU_I16
+#define CONFIG_ITLBNUM 16
+#endif
+#ifdef CONFIG_MMU_I32
+#define CONFIG_ITLBNUM 32
+#endif
+
+#define CONFIG_DTLBNUM 2
+#ifdef CONFIG_MMU_D2
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 2
+#endif
+#ifdef CONFIG_MMU_D4
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 4
+#endif
+#ifdef CONFIG_MMU_D8
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 8
+#endif
+#ifdef CONFIG_MMU_D16
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 16
+#endif
+#ifdef CONFIG_MMU_D32
+#undef CONFIG_DTLBNUM
+#define CONFIG_DTLBNUM 32
+#endif
+#ifdef CONFIG_MMU_FASTWB
+#define CFG_MMU_FASTWB 1
+#else
+#define CFG_MMU_FASTWB 0
+#endif
+
+#else
+#define CONFIG_MMUEN 0
+#define CONFIG_ITLBNUM 2
+#define CONFIG_DTLBNUM 2
+#define CONFIG_TLB_TYPE 1
+#define CONFIG_TLB_REP 1
+#define CFG_MMU_FASTWB 0
+#endif
+
+#ifndef CONFIG_DSU_ENABLE
+#define CONFIG_DSU_ENABLE 0
+#endif
+
+#if defined CONFIG_DSU_ITRACESZ1
+#define CFG_DSU_ITB 1
+#elif CONFIG_DSU_ITRACESZ2
+#define CFG_DSU_ITB 2
+#elif CONFIG_DSU_ITRACESZ4
+#define CFG_DSU_ITB 4
+#elif CONFIG_DSU_ITRACESZ8
+#define CFG_DSU_ITB 8
+#elif CONFIG_DSU_ITRACESZ16
+#define CFG_DSU_ITB 16
+#else
+#define CFG_DSU_ITB 0
+#endif
+
+#if defined CONFIG_DSU_ATRACESZ1
+#define CFG_DSU_ATB 1
+#elif CONFIG_DSU_ATRACESZ2
+#define CFG_DSU_ATB 2
+#elif CONFIG_DSU_ATRACESZ4
+#define CFG_DSU_ATB 4
+#elif CONFIG_DSU_ATRACESZ8
+#define CFG_DSU_ATB 8
+#elif CONFIG_DSU_ATRACESZ16
+#define CFG_DSU_ATB 16
+#else
+#define CFG_DSU_ATB 0
+#endif
+
+#ifndef CONFIG_LEON3FT_EN
+#define CONFIG_LEON3FT_EN 0
+#endif
+
+#if defined CONFIG_IUFT_PAR
+#define CONFIG_IUFT_EN 1
+#elif defined CONFIG_IUFT_DMR
+#define CONFIG_IUFT_EN 2
+#elif defined CONFIG_IUFT_BCH
+#define CONFIG_IUFT_EN 3
+#elif defined CONFIG_IUFT_TMR
+#define CONFIG_IUFT_EN 4
+#else
+#define CONFIG_IUFT_EN 0
+#endif
+#ifndef CONFIG_RF_ERRINJ
+#define CONFIG_RF_ERRINJ 0
+#endif
+
+#ifndef CONFIG_FPUFT_EN
+#define CONFIG_FPUFT 0
+#else
+#ifdef CONFIG_FPU_GRFPU
+#define CONFIG_FPUFT 2
+#else
+#define CONFIG_FPUFT 1
+#endif
+#endif
+
+#ifndef CONFIG_CACHE_FT_EN
+#define CONFIG_CACHE_FT_EN 0
+#endif
+#ifndef CONFIG_CACHE_ERRINJ
+#define CONFIG_CACHE_ERRINJ 0
+#endif
+
+#ifndef CONFIG_LEON3_NETLIST
+#define CONFIG_LEON3_NETLIST 0
+#endif
+
+#ifdef CONFIG_DEBUG_PC32
+#define CFG_DEBUG_PC32 0
+#else
+#define CFG_DEBUG_PC32 2
+#endif
+#ifndef CONFIG_IU_DISAS
+#define CONFIG_IU_DISAS 0
+#endif
+#ifndef CONFIG_IU_DISAS_NET
+#define CONFIG_IU_DISAS_NET 0
+#endif
+
+
+#ifndef CONFIG_AHB_SPLIT
+#define CONFIG_AHB_SPLIT 0
+#endif
+
+#ifndef CONFIG_AHB_RROBIN
+#define CONFIG_AHB_RROBIN 0
+#endif
+
+#ifndef CONFIG_AHB_IOADDR
+#define CONFIG_AHB_IOADDR FFF
+#endif
+
+#ifndef CONFIG_APB_HADDR
+#define CONFIG_APB_HADDR 800
+#endif
+
+#ifndef CONFIG_AHB_MON
+#define CONFIG_AHB_MON 0
+#endif
+
+#ifndef CONFIG_AHB_MONERR
+#define CONFIG_AHB_MONERR 0
+#endif
+
+#ifndef CONFIG_AHB_MONWAR
+#define CONFIG_AHB_MONWAR 0
+#endif
+
+#ifndef CONFIG_DSU_UART
+#define CONFIG_DSU_UART 0
+#endif
+
+
+#ifndef CONFIG_DSU_JTAG
+#define CONFIG_DSU_JTAG 0
+#endif
+
+#ifndef CONFIG_GRUSB_DCL
+#define CONFIG_GRUSB_DCL 0
+#endif
+
+#if defined CONFIG_GRUSB_DCL_UTMI16
+#define CONFIG_GRUSB_DCL_UIFACE 0
+#define CONFIG_GRUSB_DCL_DW 16
+#elif defined CONFIG_GRUSB_DCL_UTMI8
+#define CONFIG_GRUSB_DCL_UIFACE 0
+#define CONFIG_GRUSB_DCL_DW 8
+#else
+#define CONFIG_GRUSB_DCL_UIFACE 1
+#define CONFIG_GRUSB_DCL_DW 8
+#endif
+#ifndef CONFIG_DSU_ETH
+#define CONFIG_DSU_ETH 0
+#endif
+
+#ifndef CONFIG_DSU_IPMSB
+#define CONFIG_DSU_IPMSB C0A8
+#endif
+
+#ifndef CONFIG_DSU_IPLSB
+#define CONFIG_DSU_IPLSB 0033
+#endif
+
+#ifndef CONFIG_DSU_ETHMSB
+#define CONFIG_DSU_ETHMSB 020000
+#endif
+
+#ifndef CONFIG_DSU_ETHLSB
+#define CONFIG_DSU_ETHLSB 000009
+#endif
+
+#if defined CONFIG_DSU_ETHSZ1
+#define CFG_DSU_ETHB 1
+#elif CONFIG_DSU_ETHSZ2
+#define CFG_DSU_ETHB 2
+#elif CONFIG_DSU_ETHSZ4
+#define CFG_DSU_ETHB 4
+#elif CONFIG_DSU_ETHSZ8
+#define CFG_DSU_ETHB 8
+#elif CONFIG_DSU_ETHSZ16
+#define CFG_DSU_ETHB 16
+#elif CONFIG_DSU_ETHSZ32
+#define CFG_DSU_ETHB 32
+#else
+#define CFG_DSU_ETHB 1
+#endif
+
+#ifndef CONFIG_DSU_ETH_PROG
+#define CONFIG_DSU_ETH_PROG 0
+#endif
+
+#ifndef CONFIG_MCTRL_LEON2
+#define CONFIG_MCTRL_LEON2 0
+#endif
+
+#ifndef CONFIG_MCTRL_SDRAM
+#define CONFIG_MCTRL_SDRAM 0
+#endif
+
+#ifndef CONFIG_MCTRL_SDRAM_SEPBUS
+#define CONFIG_MCTRL_SDRAM_SEPBUS 0
+#endif
+
+#ifndef CONFIG_MCTRL_SDRAM_INVCLK
+#define CONFIG_MCTRL_SDRAM_INVCLK 0
+#endif
+
+#ifndef CONFIG_MCTRL_SDRAM_BUS64
+#define CONFIG_MCTRL_SDRAM_BUS64 0
+#endif
+
+#ifndef CONFIG_MCTRL_8BIT
+#define CONFIG_MCTRL_8BIT 0
+#endif
+
+#ifndef CONFIG_MCTRL_16BIT
+#define CONFIG_MCTRL_16BIT 0
+#endif
+
+#ifndef CONFIG_MCTRL_5CS
+#define CONFIG_MCTRL_5CS 0
+#endif
+
+#ifndef CONFIG_MCTRL_EDAC
+#define CONFIG_MCTRL_EDAC 0
+#endif
+
+#ifndef CONFIG_MCTRL_PAGE
+#define CONFIG_MCTRL_PAGE 0
+#endif
+
+#ifndef CONFIG_MCTRL_PROGPAGE
+#define CONFIG_MCTRL_PROGPAGE 0
+#endif
+
+#ifndef CONFIG_AHBSTAT_ENABLE
+#define CONFIG_AHBSTAT_ENABLE 0
+#endif
+
+#ifndef CONFIG_AHBSTAT_NFTSLV
+#define CONFIG_AHBSTAT_NFTSLV 1
+#endif
+
+#ifndef CONFIG_AHBROM_ENABLE
+#define CONFIG_AHBROM_ENABLE 0
+#endif
+
+#ifndef CONFIG_AHBROM_START
+#define CONFIG_AHBROM_START 000
+#endif
+
+#ifndef CONFIG_AHBROM_PIPE
+#define CONFIG_AHBROM_PIPE 0
+#endif
+
+#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
+#define CONFIG_ROM_START 100
+#else
+#define CONFIG_ROM_START 000
+#endif
+
+
+#ifndef CONFIG_AHBRAM_ENABLE
+#define CONFIG_AHBRAM_ENABLE 0
+#endif
+
+#ifndef CONFIG_AHBRAM_START
+#define CONFIG_AHBRAM_START A00
+#endif
+
+#if defined CONFIG_AHBRAM_SZ1
+#define CFG_AHBRAMSZ 1
+#elif CONFIG_AHBRAM_SZ2
+#define CFG_AHBRAMSZ 2
+#elif CONFIG_AHBRAM_SZ4
+#define CFG_AHBRAMSZ 4
+#elif CONFIG_AHBRAM_SZ8
+#define CFG_AHBRAMSZ 8
+#elif CONFIG_AHBRAM_SZ16
+#define CFG_AHBRAMSZ 16
+#elif CONFIG_AHBRAM_SZ32
+#define CFG_AHBRAMSZ 32
+#elif CONFIG_AHBRAM_SZ64
+#define CFG_AHBRAMSZ 64
+#else
+#define CFG_AHBRAMSZ 1
+#endif
+
+#ifndef CONFIG_GRETH_ENABLE
+#define CONFIG_GRETH_ENABLE 0
+#endif
+
+#ifndef CONFIG_GRETH_GIGA
+#define CONFIG_GRETH_GIGA 0
+#endif
+
+#if defined CONFIG_GRETH_FIFO4
+#define CFG_GRETH_FIFO 4
+#elif defined CONFIG_GRETH_FIFO8
+#define CFG_GRETH_FIFO 8
+#elif defined CONFIG_GRETH_FIFO16
+#define CFG_GRETH_FIFO 16
+#elif defined CONFIG_GRETH_FIFO32
+#define CFG_GRETH_FIFO 32
+#elif defined CONFIG_GRETH_FIFO64
+#define CFG_GRETH_FIFO 64
+#else
+#define CFG_GRETH_FIFO 8
+#endif
+
+#ifndef CONFIG_ATA_ENABLE
+#define CONFIG_ATA_ENABLE 0
+#endif
+
+#ifndef CONFIG_ATAIO
+#define CONFIG_ATAIO 0
+#endif
+
+#ifndef CONFIG_ATAIRQ
+#define CONFIG_ATAIRQ 0
+#endif
+
+#ifndef CONFIG_ATA_MWDMA
+#define CONFIG_ATA_MWDMA 0
+#endif
+
+#ifndef CONFIG_ATA_FIFO
+#define CONFIG_ATA_FIFO 8
+#endif
+#ifndef CONFIG_CAN_ENABLE
+#define CONFIG_CAN_ENABLE 0
+#endif
+
+#ifndef CONFIG_CAN_NUM
+#define CONFIG_CAN_NUM 1
+#endif
+
+#ifndef CONFIG_CANIO
+#define CONFIG_CANIO 0
+#endif
+
+#ifndef CONFIG_CANIRQ
+#define CONFIG_CANIRQ 0
+#endif
+
+#ifndef CONFIG_CANSEPIRQ
+#define CONFIG_CANSEPIRQ 0
+#endif
+
+#ifndef CONFIG_CAN_SYNCRST
+#define CONFIG_CAN_SYNCRST 0
+#endif
+
+#ifndef CONFIG_CAN_FT
+#define CONFIG_CAN_FT 0
+#endif
+
+#ifndef CONFIG_GRUSBDC_ENABLE
+#define CONFIG_GRUSBDC_ENABLE 0
+#endif
+
+#ifndef CONFIG_GRUSBDC_AIFACE
+#define CONFIG_GRUSBDC_AIFACE 0
+#endif
+
+#if defined CONFIG_GRUSBDC_UTMI16
+#define CONFIG_GRUSBDC_UIFACE 0
+#define CONFIG_GRUSBDC_DW 16
+#elif defined CONFIG_GRUSBDC_UTMI8
+#define CONFIG_GRUSBDC_UIFACE 0
+#define CONFIG_GRUSBDC_DW 8
+#else
+#define CONFIG_GRUSBDC_UIFACE 1
+#define CONFIG_GRUSBDC_DW 8
+#endif
+
+#ifndef CONFIG_GRUSBDC_NEPI
+#define CONFIG_GRUSBDC_NEPI 1
+#endif
+
+#ifndef CONFIG_GRUSBDC_NEPO
+#define CONFIG_GRUSBDC_NEPO 1
+#endif
+
+#ifndef CONFIG_GRUSBDC_I0
+#define CONFIG_GRUSBDC_I0 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I1
+#define CONFIG_GRUSBDC_I1 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I2
+#define CONFIG_GRUSBDC_I2 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I3
+#define CONFIG_GRUSBDC_I3 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I4
+#define CONFIG_GRUSBDC_I4 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I5
+#define CONFIG_GRUSBDC_I5 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I6
+#define CONFIG_GRUSBDC_I6 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I7
+#define CONFIG_GRUSBDC_I7 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I8
+#define CONFIG_GRUSBDC_I8 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I9
+#define CONFIG_GRUSBDC_I9 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I10
+#define CONFIG_GRUSBDC_I10 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I11
+#define CONFIG_GRUSBDC_I11 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I12
+#define CONFIG_GRUSBDC_I12 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I13
+#define CONFIG_GRUSBDC_I13 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I14
+#define CONFIG_GRUSBDC_I14 1024
+#endif
+#ifndef CONFIG_GRUSBDC_I15
+#define CONFIG_GRUSBDC_I15 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O0
+#define CONFIG_GRUSBDC_O0 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O1
+#define CONFIG_GRUSBDC_O1 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O2
+#define CONFIG_GRUSBDC_O2 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O3
+#define CONFIG_GRUSBDC_O3 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O4
+#define CONFIG_GRUSBDC_O4 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O5
+#define CONFIG_GRUSBDC_O5 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O6
+#define CONFIG_GRUSBDC_O6 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O7
+#define CONFIG_GRUSBDC_O7 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O8
+#define CONFIG_GRUSBDC_O8 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O9
+#define CONFIG_GRUSBDC_O9 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O10
+#define CONFIG_GRUSBDC_O10 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O11
+#define CONFIG_GRUSBDC_O11 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O12
+#define CONFIG_GRUSBDC_O12 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O13
+#define CONFIG_GRUSBDC_O13 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O14
+#define CONFIG_GRUSBDC_O14 1024
+#endif
+#ifndef CONFIG_GRUSBDC_O15
+#define CONFIG_GRUSBDC_O15 1024
+#endif
+#ifndef CONFIG_UART1_ENABLE
+#define CONFIG_UART1_ENABLE 0
+#endif
+
+#if defined CONFIG_UA1_FIFO1
+#define CFG_UA1_FIFO 1
+#elif defined CONFIG_UA1_FIFO2
+#define CFG_UA1_FIFO 2
+#elif defined CONFIG_UA1_FIFO4
+#define CFG_UA1_FIFO 4
+#elif defined CONFIG_UA1_FIFO8
+#define CFG_UA1_FIFO 8
+#elif defined CONFIG_UA1_FIFO16
+#define CFG_UA1_FIFO 16
+#elif defined CONFIG_UA1_FIFO32
+#define CFG_UA1_FIFO 32
+#else
+#define CFG_UA1_FIFO 1
+#endif
+
+#ifndef CONFIG_UART2_ENABLE
+#define CONFIG_UART2_ENABLE 0
+#endif
+
+#if defined CONFIG_UA2_FIFO1
+#define CFG_UA2_FIFO 1
+#elif defined CONFIG_UA2_FIFO2
+#define CFG_UA2_FIFO 2
+#elif defined CONFIG_UA2_FIFO4
+#define CFG_UA2_FIFO 4
+#elif defined CONFIG_UA2_FIFO8
+#define CFG_UA2_FIFO 8
+#elif defined CONFIG_UA2_FIFO16
+#define CFG_UA2_FIFO 16
+#elif defined CONFIG_UA2_FIFO32
+#define CFG_UA2_FIFO 32
+#else
+#define CFG_UA2_FIFO 1
+#endif
+
+#ifndef CONFIG_IRQ3_ENABLE
+#define CONFIG_IRQ3_ENABLE 0
+#endif
+#ifndef CONFIG_IRQ3_NSEC
+#define CONFIG_IRQ3_NSEC 0
+#endif
+#ifndef CONFIG_GPT_ENABLE
+#define CONFIG_GPT_ENABLE 0
+#endif
+
+#ifndef CONFIG_GPT_NTIM
+#define CONFIG_GPT_NTIM 1
+#endif
+
+#ifndef CONFIG_GPT_SW
+#define CONFIG_GPT_SW 8
+#endif
+
+#ifndef CONFIG_GPT_TW
+#define CONFIG_GPT_TW 8
+#endif
+
+#ifndef CONFIG_GPT_IRQ
+#define CONFIG_GPT_IRQ 8
+#endif
+
+#ifndef CONFIG_GPT_SEPIRQ
+#define CONFIG_GPT_SEPIRQ 0
+#endif
+#ifndef CONFIG_GPT_ENABLE
+#define CONFIG_GPT_ENABLE 0
+#endif
+
+#ifndef CONFIG_GPT_NTIM
+#define CONFIG_GPT_NTIM 1
+#endif
+
+#ifndef CONFIG_GPT_SW
+#define CONFIG_GPT_SW 8
+#endif
+
+#ifndef CONFIG_GPT_TW
+#define CONFIG_GPT_TW 8
+#endif
+
+#ifndef CONFIG_GPT_IRQ
+#define CONFIG_GPT_IRQ 8
+#endif
+
+#ifndef CONFIG_GPT_SEPIRQ
+#define CONFIG_GPT_SEPIRQ 0
+#endif
+
+#ifndef CONFIG_GPT_WDOGEN
+#define CONFIG_GPT_WDOGEN 0
+#endif
+
+#ifndef CONFIG_GPT_WDOG
+#define CONFIG_GPT_WDOG 0
+#endif
+
+#ifndef CONFIG_GRGPIO_ENABLE
+#define CONFIG_GRGPIO_ENABLE 0
+#endif
+#ifndef CONFIG_GRGPIO_IMASK
+#define CONFIG_GRGPIO_IMASK 0000
+#endif
+#ifndef CONFIG_GRGPIO_WIDTH
+#define CONFIG_GRGPIO_WIDTH 1
+#endif
+
+#ifndef CONFIG_SPW_ENABLE
+#define CONFIG_SPW_ENABLE 0
+#endif
+
+#ifndef CONFIG_SPW_NUM
+#define CONFIG_SPW_NUM 1
+#endif
+
+#if defined CONFIG_SPW_AHBFIFO4
+#define CONFIG_SPW_AHBFIFO 4
+#elif defined CONFIG_SPW_AHBFIFO8
+#define CONFIG_SPW_AHBFIFO 8
+#elif defined CONFIG_SPW_AHBFIFO16
+#define CONFIG_SPW_AHBFIFO 16
+#elif defined CONFIG_SPW_AHBFIFO32
+#define CONFIG_SPW_AHBFIFO 32
+#elif defined CONFIG_SPW_AHBFIFO64
+#define CONFIG_SPW_AHBFIFO 64
+#else
+#define CONFIG_SPW_AHBFIFO 4
+#endif
+
+#if defined CONFIG_SPW_RXFIFO16
+#define CONFIG_SPW_RXFIFO 16
+#elif defined CONFIG_SPW_RXFIFO32
+#define CONFIG_SPW_RXFIFO 32
+#elif defined CONFIG_SPW_RXFIFO64
+#define CONFIG_SPW_RXFIFO 64
+#else
+#define CONFIG_SPW_RXFIFO 16
+#endif
+
+#ifndef CONFIG_SPW_RMAP
+#define CONFIG_SPW_RMAP 0
+#endif
+
+#if defined CONFIG_SPW_RMAPBUF2
+#define CONFIG_SPW_RMAPBUF 2
+#elif defined CONFIG_SPW_RMAPBUF4
+#define CONFIG_SPW_RMAPBUF 4
+#elif defined CONFIG_SPW_RMAPBUF6
+#define CONFIG_SPW_RMAPBUF 6
+#elif defined CONFIG_SPW_RMAPBUF8
+#define CONFIG_SPW_RMAPBUF 8
+#else
+#define CONFIG_SPW_RMAPBUF 4
+#endif
+
+#ifndef CONFIG_SPW_RMAPCRC
+#define CONFIG_SPW_RMAPCRC 0
+#endif
+
+#ifndef CONFIG_SPW_RXUNAL
+#define CONFIG_SPW_RXUNAL 0
+#endif
+
+#ifndef CONFIG_SPW_NETLIST
+#define CONFIG_SPW_NETLIST 0
+#endif
+
+#ifndef CONFIG_SPW_FT
+#define CONFIG_SPW_FT 0
+#endif
+
+#if defined CONFIG_SPW_GRSPW1
+#define CONFIG_SPW_GRSPW 1
+#else
+#define CONFIG_SPW_GRSPW 2
+#endif
+
+#ifndef CONFIG_SPW_DMACHAN
+#define CONFIG_SPW_DMACHAN 1
+#endif
+
+#ifndef CONFIG_SPW_PORTS
+#define CONFIG_SPW_PORTS 1
+#endif
+
+#if defined CONFIG_SPW_RX_SDR
+#define CONFIG_SPW_INPUT 2
+#elif defined CONFIG_SPW_RX_DDR
+#define CONFIG_SPW_INPUT 3
+#elif defined CONFIG_SPW_RX_XOR
+#define CONFIG_SPW_INPUT 0
+#elif defined CONFIG_SPW_RX_AFLEX
+#define CONFIG_SPW_INPUT 1
+#else
+#define CONFIG_SPW_INPUT 2
+#endif
+
+#if defined CONFIG_SPW_TX_SDR
+#define CONFIG_SPW_OUTPUT 0
+#elif defined CONFIG_SPW_TX_DDR
+#define CONFIG_SPW_OUTPUT 1
+#elif defined CONFIG_SPW_TX_AFLEX
+#define CONFIG_SPW_OUTPUT 2
+#else
+#define CONFIG_SPW_OUTPUT 0
+#endif
+
+#ifndef CONFIG_SPW_RTSAME
+#define CONFIG_SPW_RTSAME 0
+#endif
+#ifndef CONFIG_VGA_ENABLE
+#define CONFIG_VGA_ENABLE 0
+#endif
+#ifndef CONFIG_SVGA_ENABLE
+#define CONFIG_SVGA_ENABLE 0
+#endif
+#ifndef CONFIG_KBD_ENABLE
+#define CONFIG_KBD_ENABLE 0
+#endif
+
+
+#ifndef CONFIG_DEBUG_UART
+#define CONFIG_DEBUG_UART 0
+#endif
--- /dev/null
+------------------------------------------------------------------------------
+-- This file is a part of the GRLIB VHDL IP LIBRARY
+-- Copyright (C) 2003 - 2008, Gaisler Research
+-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+library ieee;
+use ieee.std_logic_1164.all;
+-- pragma translate_off
+library unisim;
+use unisim.BUFG;
+-- pragma translate_on
+library techmap;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+
+
+entity vga_clkgen is
+ port (
+ resetn : in std_logic;
+ sel : in std_logic_vector(1 downto 0);
+ clk25 : in std_logic;
+ clkm : in std_logic;
+ clk50 : in std_logic;
+ clkout : out std_logic
+ );
+end;
+
+architecture struct of vga_clkgen is
+component BUFG port ( O : out std_logic; I : in std_logic); end component;
+signal clk65, clksel : std_logic;
+
+begin
+
+ -- 65 MHz clock generator
+
+ clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
+
+ clk_select : process (clk25, clk50, clk65, sel)
+ begin
+ case sel is
+ when "00" => clksel <= clk25;
+ when "01" => clksel <= clkm;
+ when "10" => clksel <= clk50;
+ when "11" => clksel <= clk65;
+ when others => clksel <= '0';
+ end case;
+ end process;
+
+ bufg1 : BUFG port map (I => clksel, O => clkout);
+
+end;
--- /dev/null
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /testbench/clk
+add wave -noupdate -format Logic /testbench/rst
+add wave -noupdate -format Logic /testbench/errorn
+add wave -noupdate -format Literal -radix hexadecimal /testbench/address
+add wave -noupdate -format Literal -radix hexadecimal /testbench/data
+add wave -noupdate -format Literal /testbench/ramsn
+add wave -noupdate -format Literal /testbench/ramoen
+add wave -noupdate -format Literal /testbench/rwen
+add wave -noupdate -format Literal /testbench/romsn
+add wave -noupdate -format Logic /testbench/iosn
+add wave -noupdate -format Logic /testbench/oen
+add wave -noupdate -format Logic /testbench/read
+add wave -noupdate -format Logic /testbench/writen
+add wave -noupdate -format Literal /testbench/sdcke
+add wave -noupdate -format Literal /testbench/sdcsn
+add wave -noupdate -format Logic /testbench/sdwen
+add wave -noupdate -format Logic /testbench/sdrasn
+add wave -noupdate -format Logic /testbench/sdcasn
+add wave -noupdate -format Literal /testbench/sddqm
+add wave -noupdate -format Logic /testbench/sdclk
+add wave -noupdate -format Logic /testbench/dsuen
+add wave -noupdate -format Logic /testbench/dsubre
+add wave -noupdate -format Logic /testbench/dsuact
+add wave -noupdate -divider {CPU 1}
+add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/apbi
+add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/apbo
+add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbsi
+add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbso
+add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbmi
+add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbmo
+add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/dcomgen/dcom0/dcom_uart0/r
+add wave -noupdate -format Literal -radix hexadecimal /testbench/from_ata
+add wave -noupdate -format Literal -radix hexadecimal /testbench/to_ata
+add wave -noupdate -format Logic /testbench/cpu/spw_clk
+add wave -noupdate -format Literal /testbench/cpu/spw_rxdp
+add wave -noupdate -format Literal /testbench/cpu/spw_rxdn
+add wave -noupdate -format Literal /testbench/cpu/spw_rxsp
+add wave -noupdate -format Literal /testbench/cpu/spw_rxsn
+add wave -noupdate -format Literal /testbench/cpu/spw_txdp
+add wave -noupdate -format Literal /testbench/cpu/spw_txdn
+add wave -noupdate -format Literal /testbench/cpu/spw_txsp
+add wave -noupdate -format Literal /testbench/cpu/spw_txsn
+add wave -noupdate -format Logic /testbench/wdogn
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {869597000 ps} 0}
+configure wave -namecolwidth 162
+configure wave -valuecolwidth 110
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {805588699 ps} {850580882 ps}
GRLIB=../..
-TOP=leon3mp
+TOP=bus_yccrgbs
BOARD=altera-ep3c25-eek
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
EFFORT=std
XSTOPT=
SYNPOPT="set_option -pipe 1; set_option -retiming 1"
-VHDLSYNFILES=config.vhd ahbrom.vhd serializer.vhd altera_eek_clkgen.vhd \
- leon3mp.vhd
-VHDLSIMFILES=testbench.vhd
-SIMTOP=testbench
+VHDLSYNFILES=config.vhd bus_yccrgbs.vhd
+VHDLSIMFILES=sim_yccrgbs.vhd
+SIMTOP=sim_yccrgbs
SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
CLEAN=soft-clean
TECHLIBS = altera altera_mf cycloneiii
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
- tmtc openchip ihp gleichmann stratixii stratixiii usbhc spw
-DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
- grusbhc spacewire hcan
-FILESKIP = grcan.vhd
+ tmtc openchip hynix cypress ihp gleichmann opencores micron\
+ stratixii stratixiii usbhc spw \
+ eth fmf spansion gsi
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft can \
+ grusbhc spacewire hcan ddr net greth haps leon3 ata usb uart jtag arith
+FILESKIP = grcan.vhd i2cmst.vhd
include $(GRLIB)/software/leon3/Makefile
include $(GRLIB)/bin/Makefile
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2010, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library grlib,techmap;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use techmap.gencomp.all;
+library gaisler;
+use gaisler.misc.all;
+--use gaisler.ambatest.all;
+use gaisler.ahbtbp.all;
+library kuri;
+use kuri.mjpeg.all;
+
+use work.config.all;
+
+entity bus_yccrgbs is
+ port (
+ rstn : in std_ulogic;
+ clk : in std_ulogic;
+ ctrl_in1 : in ahbtbm_ctrl_in_type;
+ ctrl_out1 : out ahbtbm_ctrl_out_type);
+end;
+
+architecture rtl of bus_yccrgbs is
+
+
+ signal apbi : apb_slv_in_type;
+ signal apbo : apb_slv_out_vector := (others => apb_none);
+ signal ahbsi : ahb_slv_in_type;
+ signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+ signal ahbmi : ahb_mst_in_type;
+ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+-- signal rst : std_ulogic;
+
+
+
+begin -- rtl
+
+
+-- rst <= not rstn;
+
+ yccinst : yccrgbs
+ generic map(shindex => 2, haddr => 16#900#, pindex => 2, paddr => 2, mhindex => 3, hirq => 2)
+ port map (rstn, clk, ahbmi, ahbmo(3), ahbsi, ahbso(2), apbi, apbo(2));
+
+ apb0 : apbctrl
+ generic map (hindex => 4, haddr => 16#800#)
+ port map(rstn, clk, ahbsi, ahbso(4), apbi, apbo);
+
+ ahbcontroller : ahbctrl -- AHB arbiter/multiplexer
+ generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+ enbusmon => 0,rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO)
+ port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
+
+ ram0 : ahbram
+ generic map (hindex => 7, haddr => 16#a00#, tech => CFG_MEMTECH, kbytes => 24)
+ port map (rstn, clk, ahbsi, ahbso(7));
+
+ mast_em : ahbtbm
+ generic map(hindex => 0)
+ port map (rstn, clk, ctrl_in1, ctrl_out1, ahbmi, ahbmo(0));
+
+
+
+-- mast_em2 : ahbtbm
+-- generic map(hindex => 1)
+-- port map (rstn, clk, ctrl_in2, ctrl_out2, ahbmi, ahbmo(1));
+
+end rtl;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2010, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library grlib,techmap;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use techmap.gencomp.all;
+library gaisler;
+use gaisler.misc.all;
+--use gaisler.ambatest.all;
+use gaisler.ahbtbp.all;
+library kuri;
+use kuri.mjpeg.all;
+
+use work.config.all;
+
+entity bus_ycc is
+ port (
+ rstn : in std_ulogic;
+ clk : in std_ulogic;
+ ctrl_in1 : in ahbtbm_ctrl_in_type;
+ ctrl_out1 : out ahbtbm_ctrl_out_type);
+end;
+
+architecture rtl of bus_ycc is
+
+
+ signal apbi : apb_slv_in_type;
+ signal apbo : apb_slv_out_vector := (others => apb_none);
+ signal ahbsi : ahb_slv_in_type;
+ signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+ signal ahbmi : ahb_mst_in_type;
+ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+-- signal rst : std_ulogic;
+
+
+
+begin -- rtl
+
+
+-- rst <= not rstn;
+
+ yccinst : yccrgbs
+ generic map(shindex => 2, haddr => 16#900#, pindex => 2, paddr => 2, mhindex => 3, hirq => 2)
+ port map (rstn, clk, ahbmi, ahbmo(3), ahbsi, ahbso(2), apbi, apbo(2));
+
+ apb0 : apbctrl
+ generic map (hindex => 4, haddr => 16#800#)
+ port map(rstn, clk, ahbsi, ahbso(4), apbi, apbo);
+
+ ahbcontroller : ahbctrl -- AHB arbiter/multiplexer
+ generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+ enbusmon => 0,rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO)
+ port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
+
+ ram0 : ahbram
+ generic map (hindex => 7, haddr => 16#a00#, tech => CFG_MEMTECH, kbytes => 24)
+ port map (rstn, clk, ahbsi, ahbso(7));
+
+ mast_em : ahbtbm
+ generic map(hindex => 0)
+ port map (rstn, clk, ctrl_in1, ctrl_out1, ahbmi, ahbmo(0));
+
+
+
+-- mast_em2 : ahbtbm
+-- generic map(hindex => 1)
+-- port map (rstn, clk, ctrl_in2, ctrl_out2, ahbmi, ahbmo(1));
+
+end rtl;
+
--- /dev/null
+../../../snapgear-2.6-p42/user/jpeg-6b-host/in_yccrgbs.txt
\ No newline at end of file
--- /dev/null
+../../../snapgear-2.6-p42/user/jpeg-6b-host/out_yccrgbs.txt
\ No newline at end of file
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2010, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+--use ieee.numeric_std.all;
+
+
+library gaisler;
+use gaisler.sim.all;
+use gaisler.ambatest.all;
+use gaisler.ahbtbp.all;
+library techmap;
+use techmap.gencomp.all;
+library grlib;
+use grlib.stdlib.all;
+library kuri;
+use kuri.mjpeg.all;
+
+use work.debug.all;
+use work.config.all;
+
+
+
+entity sim_yccrgbs is
+
+ generic (
+ clkperiod : integer := 20);
+
+end ;
+
+architecture behav of sim_yccrgbs is
+
+
+
+ component bus_yccrgbs
+ port(
+ rstn : in std_ulogic;
+ clk : in std_ulogic;
+ ctrl_in1 : in ahbtbm_ctrl_in_type;
+ ctrl_out1 : out ahbtbm_ctrl_out_type
+ );
+
+ end component;
+
+signal clk : std_ulogic := '0';
+signal rst : std_ulogic := '0';
+signal ctrl1 : ahbtb_ctrl_type;
+-- signal data_in : std_logic_vector(31 downto 0);
+
+file in_file : text open read_mode is "in_yccrgbs.txt";
+file compare_file : text open read_mode is "out_yccrgbs.txt";
+
+begin -- behav
+
+ b0 : bus_yccrgbs
+ port map (rst,clk,ctrl1.i,ctrl1.o);
+
+ tictak : process
+ begin
+ clk <= '0';
+ wait for 10 ns;
+ clk <= '1';
+ wait for 10 ns;
+ end process;
+
+ stim: process
+ variable li : line;
+ variable lc : line;
+ variable i,j : integer;
+ -- variable ycc : std_logic_vector(23 downto 0);
+ variable indata : std_logic_vector(31 downto 0);
+ variable radd : std_logic_vector(31 downto 0);
+ -- variable cdata1, cdata2 : std_logic_vector(15 downto 0);
+ variable cdata32 : std_logic_vector(31 downto 0);
+
+ begin
+
+ report " stimulus process start ";
+
+ rst <= '0';
+ wait for 100 ns;
+ rst <= '1';
+
+ -- initialize
+ ahbtbminit(ctrl1);
+
+-- Write Control registers through APB bus
+
+ahbwrite(x"80000200", x"a0000000", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000204", x"028001e0", "10", "10", '1', 2, false , ctrl1);
+--ahbwrite(x"80000204", x"00500050", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000208", x"00000000", "10", "10", '1', 2, false , ctrl1);
+--ahbwrite(x"80000208", x"00000460", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"8000020c", x"00000000", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"8000020c", x"ffffffff", "10", "10", '1', 2, false , ctrl1);
+
+-- Write YCC data for IP core
+-- for i in 0 to 33821 loop
+ for i in 0 to 3999 loop
+ readline(in_file,li);
+ hread(li, indata);
+ ahbwrite(x"90000000", indata, "10", "10", '1', 2, false , ctrl1);
+ ahbtbmidle(true, ctrl1);
+ wait for 20 ns;
+ end loop;
+
+ radd := x"a0000000";
+-- for i in 0 to 16910 loop
+ for i in 0 to 1999 loop
+ readline(compare_file, lc);
+ hread(lc, cdata32);
+ ahbread(radd, cdata32, "10", 2, false, ctrl1);
+ radd := radd + x"004";
+ end loop;
+
+ ahbtbmidle(true,ctrl1);
+ wait for 100 ns;
+
+
+ ahbtbmdone(0, ctrl1);
+ wait for 300 ns;
+
+ report "stimulus process end" severity failure;
+ wait;
+ end process;
+
+end behav;
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2010, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+--use ieee.numeric_std.all;
+
+
+library gaisler;
+use gaisler.sim.all;
+use gaisler.ambatest.all;
+use gaisler.ahbtbp.all;
+library techmap;
+use techmap.gencomp.all;
+library grlib;
+use grlib.stdlib.all;
+library kuri;
+use kuri.mjpeg.all;
+
+use work.debug.all;
+use work.config.all;
+
+
+
+entity sim_yccrgbs is
+
+ generic (
+ clkperiod : integer := 20);
+
+end ;
+
+architecture behav of sim_yccrgbs is
+
+
+
+ component bus_yccrgbs
+ port(
+ rstn : in std_ulogic;
+ clk : in std_ulogic;
+ ctrl_in1 : in ahbtbm_ctrl_in_type;
+ ctrl_out1 : out ahbtbm_ctrl_out_type
+ );
+
+ end component;
+
+signal clk : std_ulogic := '0';
+signal rst : std_ulogic := '0';
+signal ctrl1 : ahbtb_ctrl_type;
+-- signal data_in : std_logic_vector(31 downto 0);
+
+file in_file : text open read_mode is "in_yccrgbs.txt";
+file compare_file : text open read_mode is "out_yccrgbs.txt";
+
+begin -- behav
+
+ b0 : bus_yccrgbs
+ port map (rst,clk,ctrl1.i,ctrl1.o);
+
+ tictak : process
+ begin
+ clk <= '0';
+ wait for 10 ns;
+ clk <= '1';
+ wait for 10 ns;
+ end process;
+
+ stim: process
+ variable li : line;
+ variable lc : line;
+ variable i,j : integer;
+ -- variable ycc : std_logic_vector(23 downto 0);
+ variable indata : std_logic_vector(31 downto 0);
+ variable radd : std_logic_vector(31 downto 0);
+ -- variable cdata1, cdata2 : std_logic_vector(15 downto 0);
+ variable cdata32 : std_logic_vector(31 downto 0);
+
+ begin
+
+ report " stimulus process start ";
+
+ rst <= '0';
+ wait for 100 ns;
+ rst <= '1';
+
+ -- initialize
+ ahbtbminit(ctrl1);
+
+-- Write Control registers through APB bus
+
+ahbwrite(x"80000200", x"a0000000", "10", "10", '1', 2, false , ctrl1);
+--ahbwrite(x"80000204", x"028001e0", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000204", x"00500050", "10", "10", '1', 2, false , ctrl1);
+--ahbwrite(x"80000208", x"00000000", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"80000208", x"00000460", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"8000020c", x"00000000", "10", "10", '1', 2, false , ctrl1);
+ahbwrite(x"8000020c", x"ffffffff", "10", "10", '1', 2, false , ctrl1);
+
+-- Write YCC data for IP core
+-- for i in 0 to 33821 loop
+ for i in 0 to 3999 loop
+ readline(in_file,li);
+ hread(li, indata);
+ ahbwrite(x"90000000", indata, "10", "10", '1', 2, false , ctrl1);
+ ahbtbmidle(true, ctrl1);
+ wait for 20 ns;
+ end loop;
+
+ radd := x"a0000000";
+-- for i in 0 to 16910 loop
+ for i in 0 to 1999 loop
+ readline(compare_file, lc);
+ hread(lc, cdata32);
+ ahbread(radd, cdata32, "10", 2, false, ctrl1);
+ radd := radd + x"004";
+ end loop;
+
+ ahbtbmidle(true,ctrl1);
+ wait for 100 ns;
+
+
+ ahbtbmdone(0, ctrl1);
+ wait for 300 ns;
+
+ report "stimulus process end" severity failure;
+ wait;
+ end process;
+
+end behav;
yc_datapath(r.hreg.ycc(23 downto 16), r.hreg.ycc(15 downto 8),r.hreg.ycc(7 downto 0), red,green,blue);
-- Fifo part
- write_point := to_integer(unsigned(r.creg.fifo_wp));
- read_point := to_integer(unsigned(r.creg.fifo_rp));
+ write_point := 0;
+ if notx(r.creg.fifo_wp) then write_point := to_integer(unsigned(r.creg.fifo_wp)); end if;
+ read_point := 0;
+ if notx(r.creg.fifo_rp) then read_point := to_integer(unsigned(r.creg.fifo_rp)); end if;
if write_point >= read_point then
num_ele := write_point - read_point;
else
mhaddr := mhaddr + "100";
end if;
end if;
-
- if vstart = '1' then
- mhaddr := r.preg.fb_add;
- x := (others => '0');
- y := (others => '0');
- end if;
-
- v.creg.gen_add := mhaddr;
- v.creg.xpoint := x;
- v.creg.ypoint := y;
+
+
-- read_en_fifo <= fifo_read;
read_en_fifo <= '1';
vmhwdata := data_out_fifo;
end if;
+-- soft reest
+ if vstart = '1' then
+ mhaddr := r.preg.fb_add;
+ x := (others => '0');
+ y := (others => '0');
+ v.hreg.written := '0';
+ v.creg.fifo_state := ready;
+ v.creg.fifo_rp := (others => '0');
+ v.creg.fifo_wp := (others => '0');
+ v.creg.mstate := idle;
+ end if;
+
+ v.creg.gen_add := mhaddr;
+ v.creg.xpoint := x;
+ v.creg.ypoint := y;
+
+
-- reset part
if rst = '0' then
v.hreg.ycc := (others => '0');
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+entity yccrgbs is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ fifo_depth : integer := 32;
+ burst_num : integer := 16;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type
+ );
+end;
+
+architecture rtl of yccrgbs is
+
+constant shconfig : ahb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, hirq),
+ 4 => ahb_membar(haddr, '0', '0', hmask),
+ others => zero32);
+
+constant mhconfig : ahb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
+ others => zero32);
+
+constant pconfig : apb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
+ 1 => apb_iobar(paddr, pmask));
+
+function stdv2str(vec:std_logic_vector) return string is
+ variable str : string(vec'length downto 1);
+ begin
+ for i in vec'length-1 downto 0 loop
+ if(vec(i)='U') then
+ str(i+1) := 'U';
+ elsif(vec(i)='X') then
+ str(i+1) := 'X';
+ elsif(vec(i)='0') then
+ str(i+1) := '0';
+ elsif(vec(i)='1') then
+ str(i+1) := '1';
+ elsif(vec(i)='Z') then
+ str(i+1) := 'Z';
+ elsif(vec(i)='W') then
+ str(i+1) := 'W';
+ elsif(vec(i)='L') then
+ str(i+1) := 'L';
+ elsif(vec(i)='H') then
+ str(i+1) := 'H';
+ else
+ str(i+1) := '-';
+ end if;
+ end loop;
+ return str;
+end;
+
+function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
+variable z : std_logic_vector(a'length + b'length -1 downto 0);
+begin
+ z := std_logic_vector(signed(a) * signed(b));
+ return(z);
+end;
+
+
+function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
+variable ex_a : std_logic_vector(a'length downto 0);
+variable ex_b : std_logic_vector(b'length downto 0);
+variable z1 : std_logic_vector(a'length downto 0);
+variable z2 : std_logic_vector(b'length downto 0);
+begin
+ ex_a := a(a'left) & a;
+ ex_b := b(b'left) & b;
+ if( a'length > b'length)then
+ z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z1);
+ else
+ z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z2);
+ end if;
+end;
+
+procedure yc_datapath(
+ yin : in std_logic_vector(7 downto 0);
+ cbin : in std_logic_vector(7 downto 0);
+ crin : in std_logic_vector(7 downto 0);
+ rout : out std_logic_vector(4 downto 0);
+ gout : out std_logic_vector(5 downto 0);
+ bout : out std_logic_vector(4 downto 0)) is
+ variable node1 : std_logic_vector(9 downto 0);
+ variable node2 : std_logic_vector(9 downto 0);
+ variable node3 : std_logic_vector(15 downto 0);
+ variable node4 : std_logic_vector(15 downto 0);
+ variable node5 : std_logic_vector(15 downto 0);
+ variable node6 : std_logic_vector(15 downto 0);
+ variable node7 : std_logic_vector(9 downto 0);
+ variable node8 : std_logic_vector(8 downto 0);
+ variable node9 : std_logic_vector(9 downto 0);
+ variable node10 : std_logic_vector(9 downto 0);
+begin
+ node1 := mysigned_add(('0' & cbin), "110000000");
+ node2 := mysigned_add(('0' & crin), "110000000");
+ node3 := mysigned_mul("01011010", node2(7 downto 0));
+ node4 := mysigned_mul("11101010", node1(7 downto 0));
+ node5 := mysigned_mul("11010010", node2(7 downto 0));
+ node6 := mysigned_mul("01110001", node1(7 downto 0));
+ node7 := mysigned_add(('0' & yin), (node3(14 downto 7) & '0'));
+ node8 := mysigned_add((node4(13 downto 7) & '0'), (node5(13 downto 7) & '0'));
+ node9 := mysigned_add(('0' & yin), ( node6(14 downto 7) & '0'));
+ node10 := mysigned_add(('0' & yin), node8);
+ if(node7(9) = '1') then
+ rout := "00000";
+ elsif(node7(8) = '1') then
+ rout := "11111";
+ else
+ rout := node7(7 downto 3);
+ end if;
+
+ if(node10(9) = '1') then
+ gout := "000000";
+ elsif(node10(8) = '1') then
+ gout := "111111";
+ else
+ gout := node10(7 downto 2);
+ end if;
+
+ if(node9(9) = '1') then
+ bout := "00000";
+ elsif(node9(8) = '1') then
+ bout := "11111";
+ else
+ bout := node9(7 downto 3);
+ end if;
+end;
+
+type fstate_type is (ready, stuck);
+type mstate_type is (idle, busreq, grant, nonseq, seq);
+
+type ahbs_reg is record
+ get : std_logic;
+ ycc : std_logic_vector(23 downto 0);
+ written : std_ulogic;
+end record;
+
+type apbs_reg is record
+ fb_add : std_logic_vector(31 downto 0);
+ size_info : std_logic_vector(31 downto 0);
+ inc_add : std_logic_vector(11 downto 0);
+end record;
+
+type control_reg is record
+ fifo_state : fstate_type;
+ fifo_rp : std_logic_vector(7 downto 0);
+ fifo_wp : std_logic_vector(7 downto 0);
+ gen_add : std_logic_vector(31 downto 0);
+ temp_data : std_logic_vector(15 downto 0);
+ mstate : mstate_type;
+ xpoint : std_logic_vector(15 downto 0);
+ ypoint : std_logic_vector(15 downto 0);
+ bst_cnt : integer;
+ keep_data : std_logic_vector(31 downto 0);
+ dhready : std_logic;
+end record;
+
+type all_reg is record
+ hreg : ahbs_reg;
+ preg : apbs_reg;
+ creg : control_reg;
+end record;
+
+
+
+signal r, rin : all_reg;
+signal read_en_fifo, write_en_fifo : std_logic;
+signal read_pointer_fifo : std_logic_vector(5 downto 0);
+signal write_pointer_fifo : std_logic_vector(5 downto 0);
+signal data_out_fifo : std_logic_vector(31 downto 0);
+signal data_in_fifo : std_logic_vector(31 downto 0);
+
+begin
+ram0 : syncram_2p generic map(tech => memtech, abits => 6, dbits => 32,
+ sepclk => 0)
+ port map( clk, read_en_fifo, read_pointer_fifo, data_out_fifo,
+ clk, write_en_fifo, write_pointer_fifo, data_in_fifo);
+
+comb : process (r, rst, ahbsi, ahbmi, apbi, data_out_fifo)
+ variable v : all_reg;
+ variable apbwrite : std_logic;
+ variable vprdata : std_logic_vector(31 downto 0);
+ variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
+ variable vsready : std_logic;
+ variable red : std_logic_vector(4 downto 0);
+ variable green : std_logic_vector(5 downto 0);
+ variable blue : std_logic_vector(4 downto 0);
+ variable fifo_write : std_logic;
+ variable fifo_read :std_logic;
+ variable write_point : integer;
+ variable read_point : integer;
+ variable num_ele : integer;
+ variable mhaddr : std_logic_vector(31 downto 0);
+ variable mhtrans : std_logic_vector(1 downto 0);
+ variable mhbusreq : std_ulogic;
+ variable mhwdata : std_logic_vector(31 downto 0);
+ variable mhprot : std_logic_vector(3 downto 0);
+ variable add_inc : std_logic;
+ variable x : std_logic_vector(15 downto 0);
+ variable y : std_logic_vector(15 downto 0);
+ variable maxx,maxy : std_logic_vector(15 downto 0);
+ variable vstart : std_logic;
+ variable vmhwdata : std_logic_vector(31 downto 0);
+
+
+ begin
+
+ v := r;
+ vprdata := (others => '0');
+ virq := (others => '0');
+ mhprot := conv_std_logic_vector(chprot,4);
+ v.hreg.written := '0';
+ fifo_write := '0';
+ vsready := '1';
+ vstart := '0';
+ mhbusreq := '0';
+ mhtrans := HTRANS_IDLE;
+
+-- apb controle part
+ apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
+ vprdata := (others => '0');
+ case apbi.paddr(5 downto 2) is
+ when "0000" =>
+ if apbwrite = '1' then
+ v.preg.fb_add := apbi.pwdata(31 downto 0);
+ end if;
+ vprdata := v.preg.fb_add(31 downto 0);
+ when "0001" =>
+ if apbwrite = '1' then
+ v.preg.size_info := apbi.pwdata(31 downto 0);
+ end if;
+ vprdata := v.preg.size_info(31 downto 0);
+ when "0010" =>
+ if apbwrite = '1' then
+ v.preg.inc_add := apbi.pwdata(11 downto 0);
+ end if;
+ vprdata := "00000000000000000000" & v.preg.inc_add(11 downto 0);
+ when "0011" =>
+ if apbwrite = '1' then
+ if apbi.pwdata(0) = '1' then
+ vstart := '1';
+ end if;
+ end if;
+ vprdata := (others => '0');
+ when others =>
+ end case;
+
+
+ v.hreg.get := '0';
+-- ahb slave input part
+ if (ahbsi.hready = '1') and (ahbsi.hsel(shindex) = '1') then
+ if (ahbsi.haddr(15 downto 0) = "0000000000000000") and (ahbsi.hwrite = '1') and (ahbsi.htrans = HTRANS_NONSEQ) then
+ v.hreg.get := '1';
+ end if;
+ end if;
+ if r.hreg.get = '1' then
+ v.hreg.ycc(23 downto 0) := ahbsi.hwdata(23 downto 0);
+ v.hreg.written := '1';
+ end if;
+
+
+-- register write
+ yc_datapath(r.hreg.ycc(23 downto 16), r.hreg.ycc(15 downto 8),r.hreg.ycc(7 downto 0), red,green,blue);
+
+-- Fifo part
+ write_point := 0;
+ if notx(r.creg.fifo_wp) then write_point := to_integer(unsigned(r.creg.fifo_wp));
+ read_point := 0;
+ if notx(r.creg.fifo_rp) then read_point := to_integer(unsigned(r.creg.fifo_rp));
+ if write_point >= read_point then
+ num_ele := write_point - read_point;
+ else
+ num_ele := fifo_depth - read_point + write_point;
+ end if;
+ if num_ele > fifo_depth/2 then
+ vsready := '0';
+ end if;
+ if (num_ele = fifo_depth/2) and ( r.hreg.written = '1' or r.creg.fifo_state = stuck) then
+ vsready := '0';
+ end if;
+
+ case r.creg.fifo_state is
+ when ready =>
+ if r.hreg.written = '1' then
+ v.creg.temp_data := red & green & blue;
+ v.creg.fifo_state := stuck;
+ end if;
+ when stuck =>
+ if r.hreg.written = '1' then
+ fifo_write := '1';
+ write_point := write_point + 1;
+ if write_point = fifo_depth then
+ write_point := 0;
+ end if;
+ v.creg.fifo_state := ready;
+ end if;
+ end case;
+
+-- data_in_fifo <= red & green & blue & r.creg.temp_data;
+ data_in_fifo <= r.creg.temp_data &red & green & blue;
+ write_en_fifo <= fifo_write;
+ v.creg.fifo_wp := std_logic_vector(to_unsigned(write_point,8));
+
+-- AHB master part
+ fifo_read := '0';
+ add_inc := '0';
+ maxx := "0" & r.preg.size_info(31 downto 17);
+ maxy := r.preg.size_info(15 downto 0);
+
+ case r.creg.mstate is
+ when idle =>
+ mhbusreq := '0';
+ mhtrans := HTRANS_IDLE;
+ v.creg.bst_cnt := burst_num;
+ if (num_ele >= burst_num) then
+ v.creg.mstate := busreq;
+ end if;
+ when busreq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_NONSEQ;
+ if (ahbmi.hready = '1') and (ahbmi.hgrant(mhindex) = '1') then
+ v.creg.mstate := nonseq;
+ end if;
+ when nonseq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_NONSEQ;
+ if ahbmi.hready = '1' then
+ fifo_read := '1';
+ add_inc := '1';
+ if r.creg.xpoint = maxx -1 then
+ v.creg.mstate := idle;
+ else
+ v.creg.mstate := seq;
+ v.creg.bst_cnt := v.creg.bst_cnt - 1;
+ end if;
+ end if;
+ when seq =>
+ mhbusreq := '1';
+ mhtrans := HTRANS_SEQ;
+ if ahbmi.hready = '1' then
+ fifo_read := '1';
+ add_inc := '1';
+ v.creg.bst_cnt := v.creg.bst_cnt - 1;
+ if (v.creg.bst_cnt = 0) or (r.creg.xpoint = maxx -1) then
+ v.creg.mstate := idle;
+ end if;
+ end if;
+ when others =>
+ end case;
+
+ mhaddr := r.creg.gen_add;
+ x := r.creg.xpoint;
+ y := r.creg.ypoint;
+
+ -- x loop 0 - (maxx-1)
+ if add_inc = '1' then
+ if x = maxx -1 then
+ if y = maxy -1 then
+ x := "0000000000000000";
+ y := "0000000000000000";
+ mhaddr := r.preg.fb_add;
+ else
+ x := "0000000000000000";
+ y := y + '1';
+ mhaddr := mhaddr + "100" + r.preg.inc_add;
+ end if;
+ else
+ x := x + '1';
+ mhaddr := mhaddr + "100";
+ end if;
+ end if;
+
+
+
+-- read_en_fifo <= fifo_read;
+ read_en_fifo <= '1';
+ if fifo_read = '1' then
+ read_point := read_point + 1;
+ if read_point = fifo_depth then
+ read_point := 0;
+ end if;
+ end if;
+ v.creg.fifo_rp := std_logic_vector(to_unsigned(read_point,8));
+
+-- for the hready assert
+ v.creg.dhready := ahbmi.hready;
+
+ if (ahbmi.hready = '1') or (ahbmi.hgrant(mhindex) = '0') then
+ v.creg.keep_data := data_out_fifo;
+ end if;
+
+ if (r.creg.dhready = '0') and (ahbmi.hgrant(mhindex) = '1') then
+ vmhwdata := r.creg.keep_data;
+ else
+ vmhwdata := data_out_fifo;
+ end if;
+
+-- soft reest
+ if vstart = '1' then
+ mhaddr := r.preg.fb_add;
+ x := (others => '0');
+ y := (others => '0');
+ v.hreg.written := '0';
+ v.creg.fifo_state := ready;
+ v.creg.fifo_rp := (others => '0');
+ v.creg.fifo_wp := (others => '0');
+ v.creg.mstate := idle;
+ end if;
+
+ v.creg.gen_add := mhaddr;
+ v.creg.xpoint := x;
+ v.creg.ypoint := y;
+
+
+-- reset part
+ if rst = '0' then
+ v.hreg.ycc := (others => '0');
+ v.hreg.written := '0';
+ v.creg.fifo_state := ready;
+ v.creg.fifo_rp := (others => '0');
+ v.creg.fifo_wp := (others => '0');
+ v.creg.mstate := idle;
+ v.creg.xpoint := (others => '0');
+ v.creg.ypoint := (others => '0');
+ v.creg.temp_data := (others => '0');
+ v.creg.gen_add := (others => '0');
+ end if;
+
+-- signal
+
+ rin <= v;
+ apbo.prdata <= vprdata;
+ ahbso.hirq <= virq;
+ ahbso.hrdata <= vsready & "0000000" & r.hreg.ycc;
+ write_pointer_fifo <= r.creg.fifo_wp(5 downto 0);
+ read_pointer_fifo <= r.creg.fifo_rp(5 downto 0);
+ ahbmo.haddr <= r.creg.gen_add;
+ ahbmo.htrans <= mhtrans;
+ ahbmo.hbusreq <= mhbusreq;
+ ahbmo.hprot <= mhprot;
+ ahbmo.hwdata <= vmhwdata;
+
+end process;
+
+ apbo.pirq <= (others => '0');
+ apbo.pindex <= pindex;
+ apbo.pconfig <= pconfig;
+ ahbso.hconfig <= shconfig;
+ ahbso.hresp <= "00";
+ ahbso.hsplit <= (others => '0');
+ ahbso.hcache <= '0';
+ ahbso.hready <= '1';
+ ahbso.hindex <= shindex;
+ ahbmo.hconfig <= mhconfig;
+ ahbmo.hlock <= '0';
+ ahbmo.hwrite <= '1';
+ ahbmo.hsize <= "010";
+ ahbmo.hburst <= HBURST_INCR;
+ ahbmo.hirq <= (others => '0');
+ ahbmo.hindex <= mhindex;
+
+
+-- registers
+reg : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
+
+
+end;
+
base_test grfpu_test can_oc mmu mmu_asm pcitest greth atactrl \
amba dsu3 greth_api grcan \
spictrl i2cmst misc spimctrl svgactrl apbps2 \
- i2cslv i2c $(EXTRA_PROGS)
+ i2cslv i2c yccrgbs_connect yccrgbs_pic yccrgbs_connect_neek \
+ yccrgbs_pic_neek $(EXTRA_PROGS)
OFILES = $(PROGS:%=%.o)
--- /dev/null
+0x00317d85,0x00317d85,0x00307d85,0x00307d85,0x002f7f84,0x002e7f84,0x002d8083,0x002d8082,
+0x002e8182,0x002e8181,0x002e8280,0x002e8280,0x002d827f,0x002c827f,0x002b827f,0x002b8280,
+0x002b8283,0x002b8284,0x002b8284,0x002b8284,0x002b8183,0x002b8183,0x002b8082,0x002b8082,
+0x002e8082,0x002e8082,0x002e7f81,0x002e7f81,0x002f7e81,0x002f7e81,0x002f7e80,0x002f7f80,
+0x002e8082,0x002e8182,0x002e8082,0x002e8082,0x002e7f83,0x002e7f83,0x002e7e84,0x002e7e84,
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+0x00337d87,0x00327c83,0x00337c82,0x00357a86,0x00387a8e,0x003d7996,0x0042789f,0x004578a3
--- /dev/null
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\ No newline at end of file
--- /dev/null
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,0x00fc7f82,0x00fa8082,0x00fb8082,0x00fd8081,0x00fe8081,0x00ff8081,0x00fe8081,0x00fd7f82,0x00fe7e82,0x00fe7e84,0x00fa7c85,0x00ef7b86,0x00e87a87,0x00ed7988,0x00f77b86,0x00fd8084,0x00fe8182,0x00fe8081,0x00ff7f80,0x00ff7e80,0x00fe7e7f,0x00fe807f,0x00fd817f,0x00fd827f,0x00fe827f,0x00ff8281,0x00ff7f81,0x00fe7b83,0x00fc7783,0x00fa7385,0x00f87284,0x00fb7484,0x00fe7483,0x00e17484,0x00867384,0x004b7285,0x004d7185,0x004c7086,0x004d7086,0x004c6f86,0x004d6f86,0x004f7085,0x004f7085,0x004f7184,0x004d7184,0x004b7283,0x004a7283,0x004a7284,0x004a7283,0x004a7383,0x004a7381,0x004b7481,0x004c747f,0x004c757f,0x004d757e,0x004f747e,0x004c737e,0x004d737e,0x0052717e,0x0054717f,0x0055707f,0x005d6f80,0x00676e7f,0x00886b7c,0x009a6a7a,0x00a66b7b,0x00a16d7c,0x00986f7c,0x008c707d,0x0075727e,0x005d737f,0x004c7480,0x004a7481,0x00497582,0x00477583,0x00487583,0x004a7484,0x004d7485,0x004f7485,0x00507485,0x004f7485,0x004d7684,0x004b7684,0x00487883,0x00467982,0x00447a82,0x00437b80,0x003d7c80,0x003d7c7e,0x003d7c7e,0x003d7c7d,0x003d7b7c,0x003d7b7c,0x003d7a7b,0x003d7a7b,0x003f7c7d,0x003f7c7d,0x003e7c7d,0x003d7c7d,0x003d7c7d,0x003e7c7d,0x003f7c7d,0x003f7c7d,0x003f7c7d,0x003f7c7d,0x003f7c7d,0x003f7c7d,0x00407c7d,0x00417c7d,0x00427c7d,0x00437c7c,0x00437e7c,0x00437d7b,0x00437c7c,0x00437a7c},
+{0x00427a7d,0x00417a7d,0x00407b7e,0x00407d7e,0x003e7e7d,0x003d7e7c,0x003b7d7c,0x003c7a7a,0x0041767a,0x004c7279,0x00596f78,0x00626c77,0x00656b74,0x00646c73,0x005f6f75,0x00547375,0x00467777,0x003a7977,0x00357a79,0x00357979,0x003b7879,0x00467679,0x00527579,0x005a7479,0x005d7578,0x00597578,0x004d7777,0x00407878,0x00327c7c,0x002f7d7d,0x002b7d7d,34
\ No newline at end of file
--- /dev/null
+../../../snapgear-2.6-p42/user/jpeg-6b-host/in_yccrgbs.txt
\ No newline at end of file
--- /dev/null
+#!/usr/local/bin/perl
+
+while($_ = <STDIN>){
+ print "0x";
+ print $_;
+ print ",";
+}
--- /dev/null
+#!/usr/local/bin/perl
+
+$xx = 0;
+$yy = 1;
+print "{";
+
+while($_ = <STDIN>){
+ if($_ =~ /([A-Za-z0-9]*)\n/){
+ print "0x";
+ print $1;
+
+ if($xx==1023){
+ print "},\n{";
+ $xx = 0;
+ $yy++;
+ }else{
+ print ",";
+ $xx++;
+ }
+ }
+}
+print $yy;
--- /dev/null
+#include "testmod.h"
+#include <stdio.h>
+
+// You must set the following AHB address according to your system
+// This sample address is for leon3-gr-xc3s-1500-mjpeg
+#define HSADDR 0xa0000000
+#define HPADDR 0x80000c00
+#define IOADDR 0x80000800
+
+static unsigned int indata[80] ={
+0x00317d85,0x00317d85,0x00307d85,0x00307d85,0x002f7f84,0x002e7f84,0x002d8083,0x002d8082,
+0x002e8182,0x002e8181,0x002e8280,0x002e8280,0x002d827f,0x002c827f,0x002b827f,0x002b8280,
+0x002b8283,0x002b8284,0x002b8284,0x002b8284,0x002b8183,0x002b8183,0x002b8082,0x002b8082,
+0x002e8082,0x002e8082,0x002e7f81,0x002e7f81,0x002f7e81,0x002f7e81,0x002f7e80,0x002f7f80,
+0x002e8082,0x002e8182,0x002e8082,0x002e8082,0x002e7f83,0x002e7f83,0x002e7e84,0x002e7e84,
+0x00307d85,0x00317c85,0x00317c86,0x00337b86,0x00347a86,0x00357a86,0x00367a87,0x00367a86,
+0x00377c85,0x00387c84,0x00397b84,0x00397b84,0x00387b85,0x00377b85,0x00357b86,0x00347b86,
+0x00347b86,0x00347b86,0x00337b86,0x00327b86,0x00327c86,0x00337c86,0x00347d86,0x00347c85,
+0x00387b85,0x00357a87,0x00387b8d,0x00397b92,0x00357c96,0x00357c96,0x00357d93,0x00317d8d,
+0x00337d87,0x00327c83,0x00337c82,0x00357a86,0x00387a8e,0x003d7996,0x0042789f,0x004578a3
+};
+
+struct yrsreg {
+ volatile unsigned int fbadd;
+ volatile unsigned int sizeinfo;
+ volatile unsigned int incadd;
+ volatile unsigned int reset;
+}
+
+ yccrgbs_connect(){
+ struct yrsreg *sreg = (struct yrsreg *) HPADDR;
+ volatile unsigned int *dataad = (unsigned int *)HSADDR;
+ unsigned int rdata;
+ volatile unsigned int *raddr;
+ int i,j;
+ unsigned int *allocadd;
+ volatile unsigned int *ioaddr = (unsigned int *)IOADDR;
+ unsigned int iodata;
+
+ allocadd = (unsigned int *)memalign(1024, 2*640*480);
+ if (allocadd == NULL) fail(0);
+
+ sreg->fbadd = (unsigned int) allocadd;
+ sreg->sizeinfo = 0x028001e0;
+ sreg->incadd = 0x0;
+ sreg->reset = 0xffffffff;
+
+ for(i=0;i<80;i++){
+ *dataad = indata[i];
+ }
+
+ for(i=0; i<300; i++){}
+
+ raddr = allocadd;
+ *(ioaddr + 2) = 0xffffffff;
+ *(ioaddr + 3) = 0x00000000;
+ *(ioaddr + 1) = 0x0000aaaa;
+
+ for(i=0;i<40;i++){
+ rdata = *raddr;
+ iodata = (rdata & 0x0000ffff) | 0x00010000;
+ *(ioaddr + 1) = iodata;
+ *(ioaddr + 1) = 0x0000aaaa;
+ iodata = (rdata & 0xffff0000) >> 16;
+ iodata = iodata | 0x00010000;
+ // iodata = rdata;
+ *(ioaddr + 1) = iodata;
+ *(ioaddr + 1) = 0x0000aaaa;
+ raddr++;
+ }
+ }
--- /dev/null
+#include "testmod.h"
+#include <stdio.h>
+
+// You must set the following AHB address according to your system
+// This sample address is for leon3-gr-xc3s-1500-mjpeg
+#define HSADDR 0xb0000000
+#define HPADDR 0x80000700
+#define IOADDR 0x80000500
+
+static unsigned int indata[80] ={
+0x00317d85,0x00317d85,0x00307d85,0x00307d85,0x002f7f84,0x002e7f84,0x002d8083,0x002d8082,
+0x002e8182,0x002e8181,0x002e8280,0x002e8280,0x002d827f,0x002c827f,0x002b827f,0x002b8280,
+0x002b8283,0x002b8284,0x002b8284,0x002b8284,0x002b8183,0x002b8183,0x002b8082,0x002b8082,
+0x002e8082,0x002e8082,0x002e7f81,0x002e7f81,0x002f7e81,0x002f7e81,0x002f7e80,0x002f7f80,
+0x002e8082,0x002e8182,0x002e8082,0x002e8082,0x002e7f83,0x002e7f83,0x002e7e84,0x002e7e84,
+0x00307d85,0x00317c85,0x00317c86,0x00337b86,0x00347a86,0x00357a86,0x00367a87,0x00367a86,
+0x00377c85,0x00387c84,0x00397b84,0x00397b84,0x00387b85,0x00377b85,0x00357b86,0x00347b86,
+0x00347b86,0x00347b86,0x00337b86,0x00327b86,0x00327c86,0x00337c86,0x00347d86,0x00347c85,
+0x00387b85,0x00357a87,0x00387b8d,0x00397b92,0x00357c96,0x00357c96,0x00357d93,0x00317d8d,
+0x00337d87,0x00327c83,0x00337c82,0x00357a86,0x00387a8e,0x003d7996,0x0042789f,0x004578a3
+};
+
+struct yrsreg {
+ volatile unsigned int fbadd;
+ volatile unsigned int sizeinfo;
+ volatile unsigned int incadd;
+ volatile unsigned int reset;
+}
+
+ yccrgbs_connect_neek(){
+ struct yrsreg *sreg = (struct yrsreg *) HPADDR;
+ volatile unsigned int *dataad = (unsigned int *)HSADDR;
+ unsigned int rdata;
+ volatile unsigned int *raddr;
+ int i,j;
+ unsigned int *allocadd;
+ volatile unsigned int *ioaddr = (unsigned int *)IOADDR;
+ unsigned int iodata;
+
+ allocadd = (unsigned int *)memalign(1024, 2*640*480);
+ if (allocadd == NULL) fail(0);
+
+ sreg->fbadd = (unsigned int) allocadd;
+ sreg->sizeinfo = 0x028001e0;
+ sreg->incadd = 0x0;
+ sreg->reset = 0xffffffff;
+
+ for(i=0;i<80;i++){
+ *dataad = indata[i];
+ }
+
+ for(i=0; i<300; i++){}
+
+ raddr = allocadd;
+ *(ioaddr + 2) = 0xffffffff;
+ *(ioaddr + 3) = 0x00000000;
+ *(ioaddr + 1) = 0x0000aaaa;
+
+ for(i=0;i<40;i++){
+ rdata = *raddr;
+ iodata = (rdata & 0x0000ffff) | 0x00010000;
+ *(ioaddr + 1) = iodata;
+ *(ioaddr + 1) = 0x0000aaaa;
+ iodata = (rdata & 0xffff0000) >> 16;
+ iodata = iodata | 0x00010000;
+ // iodata = rdata;
+ *(ioaddr + 1) = iodata;
+ *(ioaddr + 1) = 0x0000aaaa;
+ raddr++;
+ }
+ }
--- /dev/null
+#include "testmod.h"\r
+#include <stdio.h>\r
+\r
+// You must set the following AHB address according to your system\r
+// This sample address is for leon3-gr-xc3s-1500-mjpeg\r
+#define HSADDR 0xa0000000\r
+#define HPADDR 0x80000c00\r
+#define SVGAADDR 0x80000600\r
+\r
+static unsigned int indata[6][1024] = {\r
+{0x00317d85,0x00317d85,0x00307d85,0x00307d85,0x002f7f84,0x002e7f84,0x002d8083,0x002d8082,0x002e8182,0x002e8181,0x002e8280,0x002e8280,0x002d827f,0x002c827f,0x002b827f,0x002b8280,0x002b8283,0x002b8284,0x002b8284,0x002b8284,0x002b8183,0x002b8183,0x002b8082,0x002b8082,0x002e8082,0x002e8082,0x002e7f81,0x002e7f81,0x002f7e81,0x002f7e81,0x002f7e80,0x002f7f80,0x002e8082,0x002e8182,0x002e8082,0x002e8082,0x002e7f83,0x002e7f83,0x002e7e84,0x002e7e84,0x00307d85,0x00317c85,0x00317c86,0x00337b86,0x00347a86,0x00357a86,0x00367a87,0x00367a86,0x00377c85,0x00387c84,0x00397b84,0x00397b84,0x00387b85,0x00377b85,0x00357b86,0x00347b86,0x00347b86,0x00347b86,0x00337b86,0x00327b86,0x00327c86,0x00337c86,0x00347d86,0x00347c85,0x00387b85,0x00357a87,0x00387b8d,0x00397b92,0x00357c96,0x00357c96,0x00357d93,0x00317d8d,0x00337d87,0x00327c83,0x00337c82,0x00357a86,0x00387a8e,0x003d7996,0x0042789f,0x004578a3,0x00337d85,0x00337d85,0x00327d85,0x00327d85,0x00317e84,0x00307f84,0x002f8083,0x002f8083,0x00308182,0x00308181,0x00308181,0x002f8180,0x002f8280,0x002e817f,0x002d8280,0x002d8181,0x002d8283,0x002d8184,0x002d8284,0x002d8184,0x002d8183,0x002d8083,0x002d8082,0x002d8082,0x002f8082,0x002f7f82,0x002f7f81,0x002f7f81,0x00307e81,0x00307e81,0x00307e80,0x00317e81,0x00308082,0x00308082,0x00308082,0x00307f82,0x00307f83,0x002f7e83,0x002f7e84,0x002f7d84,0x00327d85,0x00337c85,0x00337b86,0x00357a86,0x00367a86,0x00377a86,0x00387a87,0x00387a86,0x00397b85,0x003a7b84,0x003a7b84,0x003a7b84,0x003a7b85,0x00387b85,0x00377b86,0x00367b86,0x00357b86,0x00357b86,0x00347b86,0x00337b86,0x00337c86,0x00347c86,0x00357d86,0x00357c86,0x00367b87,0x00347a8a,0x00367b8f,0x00377b93,0x00357c96,0x00367c96,0x00387d93,0x00357d8e,0x00357d88,0x00347c84,0x00347b84,0x00347a87,0x0036798d,0x00397894,0x003c789c,0x003e779f,0x00367d85,0x00367d85,0x00357d84,0x00357d84,0x00347e84,0x00337e84,0x00327f83,0x00327f83,0x00328082,0x00328082,0x00328082,0x00328081,0x00328181,0x00318080,0x00308181,0x002f8081,0x002f8183,0x002f8084,0x002f8184,0x002f8084,0x002f8083,0x002f8083,0x002f8083,0x002f7f83,0x00307f82,0x00307f82,0x00307f81,0x00317e81,0x00327e81,0x00327e81,0x00327d81,0x00337e81,0x00338082,0x00328082,0x00328082,0x00327f82,0x00327f83,0x00327e83,0x00327e84,0x00327d84,0x00357d85,0x00357c85,0x00367b86,0x00377a86,0x00397a86,0x003a7986,0x003b7987,0x003b7a86,0x003c7a85,0x003c7a85,0x003d7a85,0x003d7a85,0x003c7a86,0x003a7a86,0x00397b86,0x00387b86,0x00377b86,0x00367b86,0x00357c86,0x00357c86,0x00357d85,0x00357d85,0x00367d85,0x00377c87,0x003a7b8c,0x00397b8f,0x00387b92,0x00377b95,0x00367c96,0x00367c96,0x00367c93,0x00367c8f,0x00397c8b,0x00397b88,0x00387a86,0x00387988,0x0039788c,0x003a7791,0x003b7795,0x003c7698,0x00397d85,0x00397d85,0x00387d84,0x00377d84,0x00367e84,0x00367e84,0x00357e83,0x00357f83,0x00357f83,0x00357f82,0x00357f83,0x00357f82,0x00347f82,0x00337f82,0x00327f82,0x00327f82,0x00308084,0x00307f84,0x00308084,0x00307f84,0x00308083,0x00307f83,0x00307f83,0x00307e83,0x00317f82,0x00317e82,0x00317e81,0x00327e81,0x00337e81,0x00337d81,0x00347d81,0x00347d81,0x00337f82,0x00347f82,0x00347f82,0x00347e82,0x00357e83,0x00367d83,0x00367d84,0x00367c84,0x00377c85,0x00387b85,0x00397a86,0x003a7986,0x003b7986,0x003c7986,0x003d7987,0x003e7987,0x003e7986,0x003f7a85,0x003e7a86,0x003e7a86,0x003d7a86,0x003c7a86,0x003a7b86,0x003a7b86,0x00387b86,0x00387b86,0x00377c86,0x00367c85,0x00367d85,0x00377d85,0x00387d85,0x00387c87,0x003a7c8c,0x003c7b8f,0x003b7b91,0x003a7b92,0x003c7c93,0x003a7c92,0x00387c91,0x003a7b8e,0x00387b8c,0x00387a89,0x00387988,0x00387889,0x0039778b,0x003a768d,0x003b7690,0x003b7591,0x003b7d84,0x003b7d84,0x003b7d84,0x003a7d84,0x00397d84,0x00387d84,0x00387d84,0x00377e84,0x00377e84,0x00377e83,0x00377e84,0x00377e83,0x00367e83,0x00357e83,0x00357e83,0x00347e84,0x00317f84,0x00317e85,0x00317f84,0x00317e84,0x00317f84,0x00317e84,0x00317e83,0x00317d83,0x00327e82,0x00327d82,0x00327d82,0x00337d82,0x00337d81,0x00347d81,0x00347d81,0x00347d81,0x00337e82,0x00347e82,0x00357e82,0x00367e82,0x00377e83,0x00397d83,0x003a7d84,0x003a7c84,0x00397b85,0x00397a85,0x003a7a86,0x003c7986,0x003d7987,0x003e7887,0x003f7887,0x003f7887,0x00407887,0x00407986,0x003f7987,0x003e7987,0x003d7987,0x003c7987,0x003b7a86,0x003a7a86,0x003a7b85,0x00397b85,0x00387c85,0x00387c85,0x00387d85,0x00387d84,0x00397d84,0x003a7c85,0x00357c87,0x003b7b89,0x003a7b8a,0x003b7b8b,0x00417b8b,0x00407b8c,0x003c7b8c,0x00407a8b,0x003c798b,0x003c788a,0x003c7789,0x003d7689,0x003d758a,0x003e748a,0x003f748b,0x0040748b,0x003e7d84,0x003e7d84,0x003d7d84,0x003d7d84,0x003c7d84,0x003b7d84,0x003a7d84,0x003a7c84,0x003a7d84,0x003a7c84,0x003a7d84,0x00397c84,0x00397d84,0x00387d84,0x00377d85,0x00377d85,0x00347d85,0x00347d85,0x00347d84,0x00347d84,0x00347d84,0x00347d84,0x00347d83,0x00347d83,0x00337d83,0x00337d82,0x00347d82,0x00347d82,0x00347d81,0x00347d81,0x00347c81,0x00347c81,0x00337d82,0x00347e82,0x00357e82,0x00377d82,0x00397d83,0x003a7c83,0x003b7c84,0x003c7b84,0x003b7a85,0x003b7985,0x003c7986,0x003d7886,0x003e7887,0x00407787,0x00407787,0x00417787,0x00427788,0x00417888,0x00407888,0x003f7987,0x003e7987,0x003d7987,0x00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,0x005d7888,0x005e7789,0x005e7689,0x00607588,0x00607587,0x005f7487,0x005e7488,0x005f7389,0x0062728c,0x0064718f,0x00636f95,0x006b6d9c,0x00676ba5,0x006569ae,0x006767b8,0x006866c1,0x006664c8,0x006363ce,0x006362d1,0x006761d3,0x006861d4,0x006960d5,0x00695fd5,0x00675fd5,0x00655dd4,0x00655dd3,0x00665cd1,0x00645ccf,0x00645cce,0x00645dcd,0x00655dcd,0x00655ecf,0x00665fd0,0x006660d1,0x006661ce,0x006262c7,0x005d62c3,0x005762c2,0x005762c1,0x005d62c0,0x006362c1,0x006462c3,0x006162c6,0x006d62c9,0x008e62cb,0x007162cc,0x006362cb,0x006962c9,0x005762c6,0x005862c3,0x005d62c1,0x00597883,0x00597a83,0x005b7e83,0x00608282,0x00698882,0x00748d81,0x007f9281,0x00859680,0x008b9980,0x008c9a7f,0x008b9a7f,0x0087997f,0x00819780,0x007a9580,0x00749480,0x0071927f,0x0074907e,0x00768f7d,0x00788d7e,0x00798b7f,0x00778980,0x00748681,0x006f8482,0x006c8183,0x00647e84,0x00627c85,0x00607a86,0x005f7887,0x005f7788,0x00607789,0x0061768a,0x0061768a,0x00607589,0x00617589,0x00607589,0x005e748a,0x0061738c,0x00667290,0x00677195,0x00656f9b,0x006f6da3,0x00686bac,0x006169b5,0x006066bd,0x006065c4,0x006063ca,0x006261ce,0x006461d1,0x006a61d3,0x006961d4,0x006860d5,0x00675fd5,0x00675fd5,0x00675dd4,0x00645dd2,0x00625cd0,0x00645cce,0x00645ccd,0x00655dcc,0x00655dcc,0x00655ecd,0x00665fce,0x006660d0,0x006661cc}\r
+};\r
+\r
+struct yrsreg {\r
+ volatile unsigned int fbadd;\r
+ volatile unsigned int size_info;\r
+ volatile unsigned int incadd;\r
+ volatile unsigned int reset;\r
+}\r
+\r
+ yccrgbs_pic(){\r
+ struct yrsreg *sreg = (struct yrsreg *) HPADDR;\r
+ volatile unsigned int *dataad = (unsigned int *)HSADDR;\r
+ unsigned int rdata;\r
+ volatile unsigned int *raddr; \r
+ int i,j,k;\r
+ unsigned int *allocadd;\r
+ volatile unsigned int *svaddr = (unsigned int *)SVGAADDR;\r
+\r
+ allocadd = (unsigned int *)memalign(1024, 2*640*480);\r
+ if (allocadd == NULL) fail(0);\r
+\r
+ sreg->fbadd = (unsigned int) allocadd;\r
+ sreg->size_info = 0x00500050;\r
+ sreg->incadd = 0x00000460;\r
+ sreg->reset = 0x00000000;\r
+ sreg->reset = 0xffffffff;\r
+\r
+ /* For checking data*/\r
+\r
+ *(svaddr + 1) = 0x01df027f;\r
+ *(svaddr + 2) = 0x000b0010;\r
+ *(svaddr + 3) = 0x00020060;\r
+ *(svaddr + 4) = 0x020b031f;\r
+ *(svaddr + 5) = (unsigned int) allocadd;\r
+ *(svaddr + 6) = 0x00009c40;\r
+ *(svaddr + 7) = 0x000061a8;\r
+ *(svaddr + 8) = 0x00004e20;\r
+ *(svaddr + 9) = 0x00003c19;\r
+ *(svaddr + 10) = 0x00000000;\r
+\r
+ *svaddr = 0x00000021;\r
+ for(i=0;i<480;i++){\r
+ for(j=0;j<320;j++){\r
+ *(allocadd + i*320 +j) = 0x0;\r
+ }\r
+ }\r
+ for(i=0;i<6;i++){\r
+ for(j=0;j<1024;j++){\r
+ *dataad = indata[i][j];\r
+ // for(k=0;k<100000;k++);\r
+ }\r
+ }\r
+ }\r
+\r
+\r
+\r
+ \r
+\r
--- /dev/null
+#include "testmod.h"\r
+#include <stdio.h>\r
+\r
+// You must set the following AHB address according to your system\r
+// This sample address is for leon3-gr-xc3s-1500-mjpeg\r
+#define HSADDR 0xb0000000\r
+#define HPADDR 0x80000700\r
+#define SVGAADDR 0x80000b00\r
+\r
+static unsigned int indata[6][1024] = {\r
+{0x00317d85,0x00317d85,0x00307d85,0x00307d85,0x002f7f84,0x002e7f84,0x002d8083,0x002d8082,0x002e8182,0x002e8181,0x002e8280,0x002e8280,0x002d827f,0x002c827f,0x002b827f,0x002b8280,0x002b8283,0x002b8284,0x002b8284,0x002b8284,0x002b8183,0x002b8183,0x002b8082,0x002b8082,0x002e8082,0x002e8082,0x002e7f81,0x002e7f81,0x002f7e81,0x002f7e81,0x002f7e80,0x002f7f80,0x002e8082,0x002e8182,0x002e8082,0x002e8082,0x002e7f83,0x002e7f83,0x002e7e84,0x002e7e84,0x00307d85,0x00317c85,0x00317c86,0x00337b86,0x00347a86,0x00357a86,0x00367a87,0x00367a86,0x00377c85,0x00387c84,0x00397b84,0x00397b84,0x00387b85,0x00377b85,0x00357b86,0x00347b86,0x00347b86,0x00347b86,0x00337b86,0x00327b86,0x00327c86,0x00337c86,0x00347d86,0x00347c85,0x00387b85,0x00357a87,0x00387b8d,0x00397b92,0x00357c96,0x00357c96,0x00357d93,0x00317d8d,0x00337d87,0x00327c83,0x00337c82,0x00357a86,0x00387a8e,0x003d7996,0x0042789f,0x004578a3,0x00337d85,0x00337d85,0x00327d85,0x00327d85,0x00317e84,0x00307f84,0x002f8083,0x002f8083,0x00308182,0x00308181,0x00308181,0x002f8180,0x002f8280,0x002e817f,0x002d8280,0x002d8181,0x002d8283,0x002d8184,0x002d8284,0x002d8184,0x002d8183,0x002d8083,0x002d8082,0x002d8082,0x002f8082,0x002f7f82,0x002f7f81,0x002f7f81,0x00307e81,0x00307e81,0x00307e80,0x00317e81,0x00308082,0x00308082,0x00308082,0x00307f82,0x00307f83,0x002f7e83,0x002f7e84,0x002f7d84,0x00327d85,0x00337c85,0x00337b86,0x00357a86,0x00367a86,0x00377a86,0x00387a87,0x00387a86,0x00397b85,0x003a7b84,0x003a7b84,0x003a7b84,0x003a7b85,0x00387b85,0x00377b86,0x00367b86,0x00357b86,0x00357b86,0x00347b86,0x00337b86,0x00337c86,0x00347c86,0x00357d86,0x00357c86,0x00367b87,0x00347a8a,0x00367b8f,0x00377b93,0x00357c96,0x00367c96,0x00387d93,0x00357d8e,0x00357d88,0x00347c84,0x00347b84,0x00347a87,0x0036798d,0x00397894,0x003c789c,0x003e779f,0x00367d85,0x00367d85,0x00357d84,0x00357d84,0x00347e84,0x00337e84,0x00327f83,0x00327f83,0x00328082,0x00328082,0x00328082,0x00328081,0x00328181,0x00318080,0x00308181,0x002f8081,0x002f8183,0x002f8084,0x002f8184,0x002f8084,0x002f8083,0x002f8083,0x002f8083,0x002f7f83,0x00307f82,0x00307f82,0x00307f81,0x00317e81,0x00327e81,0x00327e81,0x00327d81,0x00337e81,0x00338082,0x00328082,0x00328082,0x00327f82,0x00327f83,0x00327e83,0x00327e84,0x00327d84,0x00357d85,0x00357c85,0x00367b86,0x00377a86,0x00397a86,0x003a7986,0x003b7987,0x003b7a86,0x003c7a85,0x003c7a85,0x003d7a85,0x003d7a85,0x003c7a86,0x003a7a86,0x00397b86,0x00387b86,0x00377b86,0x00367b86,0x00357c86,0x00357c86,0x00357d85,0x00357d85,0x00367d85,0x00377c87,0x003a7b8c,0x00397b8f,0x00387b92,0x00377b95,0x00367c96,0x00367c96,0x00367c93,0x00367c8f,0x00397c8b,0x00397b88,0x00387a86,0x00387988,0x0039788c,0x003a7791,0x003b7795,0x003c7698,0x00397d85,0x00397d85,0x00387d84,0x00377d84,0x00367e84,0x00367e84,0x00357e83,0x00357f83,0x00357f83,0x00357f82,0x00357f83,0x00357f82,0x00347f82,0x00337f82,0x00327f82,0x00327f82,0x00308084,0x00307f84,0x00308084,0x00307f84,0x00308083,0x00307f83,0x00307f83,0x00307e83,0x00317f82,0x00317e82,0x00317e81,0x00327e81,0x00337e81,0x00337d81,0x00347d81,0x00347d81,0x00337f82,0x00347f82,0x00347f82,0x00347e82,0x00357e83,0x00367d83,0x00367d84,0x00367c84,0x00377c85,0x00387b85,0x00397a86,0x003a7986,0x003b7986,0x003c7986,0x003d7987,0x003e7987,0x003e7986,0x003f7a85,0x003e7a86,0x003e7a86,0x003d7a86,0x003c7a86,0x003a7b86,0x003a7b86,0x00387b86,0x00387b86,0x00377c86,0x00367c85,0x00367d85,0x00377d85,0x00387d85,0x00387c87,0x003a7c8c,0x003c7b8f,0x003b7b91,0x003a7b92,0x003c7c93,0x003a7c92,0x00387c91,0x003a7b8e,0x00387b8c,0x00387a89,0x00387988,0x00387889,0x0039778b,0x003a768d,0x003b7690,0x003b7591,0x003b7d84,0x003b7d84,0x003b7d84,0x003a7d84,0x00397d84,0x00387d84,0x00387d84,0x00377e84,0x00377e84,0x00377e83,0x00377e84,0x00377e83,0x00367e83,0x00357e83,0x00357e83,0x00347e84,0x00317f84,0x00317e85,0x00317f84,0x00317e84,0x00317f84,0x00317e84,0x00317e83,0x00317d83,0x00327e82,0x00327d82,0x00327d82,0x00337d82,0x00337d81,0x00347d81,0x00347d81,0x00347d81,0x00337e82,0x00347e82,0x00357e82,0x00367e82,0x00377e83,0x00397d83,0x003a7d84,0x003a7c84,0x00397b85,0x00397a85,0x003a7a86,0x003c7986,0x003d7987,0x003e7887,0x003f7887,0x003f7887,0x00407887,0x00407986,0x003f7987,0x003e7987,0x003d7987,0x003c7987,0x003b7a86,0x003a7a86,0x003a7b85,0x00397b85,0x00387c85,0x00387c85,0x00387d85,0x00387d84,0x00397d84,0x003a7c85,0x00357c87,0x003b7b89,0x003a7b8a,0x003b7b8b,0x00417b8b,0x00407b8c,0x003c7b8c,0x00407a8b,0x003c798b,0x003c788a,0x003c7789,0x003d7689,0x003d758a,0x003e748a,0x003f748b,0x0040748b,0x003e7d84,0x003e7d84,0x003d7d84,0x003d7d84,0x003c7d84,0x003b7d84,0x003a7d84,0x003a7c84,0x003a7d84,0x003a7c84,0x003a7d84,0x00397c84,0x00397d84,0x00387d84,0x00377d85,0x00377d85,0x00347d85,0x00347d85,0x00347d84,0x00347d84,0x00347d84,0x00347d84,0x00347d83,0x00347d83,0x00337d83,0x00337d82,0x00347d82,0x00347d82,0x00347d81,0x00347d81,0x00347c81,0x00347c81,0x00337d82,0x00347e82,0x00357e82,0x00377d82,0x00397d83,0x003a7c83,0x003b7c84,0x003c7b84,0x003b7a85,0x003b7985,0x003c7986,0x003d7886,0x003e7887,0x00407787,0x00407787,0x00417787,0x00427788,0x00417888,0x00407888,0x003f7987,0x003e7987,0x003d7987,0x00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+};\r
+\r
+struct yrsreg {\r
+ volatile unsigned int fbadd;\r
+ volatile unsigned int size_info;\r
+ volatile unsigned int incadd;\r
+ volatile unsigned int reset;\r
+}\r
+\r
+ yccrgbs_pic_neek(){\r
+ struct yrsreg *sreg = (struct yrsreg *) HPADDR;\r
+ volatile unsigned int *dataad = (unsigned int *)HSADDR;\r
+ unsigned int rdata;\r
+ volatile unsigned int *raddr; \r
+ int i,j,k;\r
+ unsigned int *allocadd;\r
+ volatile unsigned int *svaddr = (unsigned int *)SVGAADDR;\r
+\r
+ allocadd = (unsigned int *)memalign(1024, 2*800*480);\r
+ if (allocadd == NULL) fail(0);\r
+\r
+ sreg->fbadd = (unsigned int) allocadd;\r
+ sreg->size_info = 0x00500050;\r
+ sreg->incadd = 0x000005a0;\r
+ sreg->reset = 0x00000000;\r
+ sreg->reset = 0xffffffff;\r
+\r
+ /* For checking data*/\r
+\r
+ *(svaddr + 1) = 0x01df031f;\r
+ *(svaddr + 2) = 0x000a0010;\r
+ *(svaddr + 3) = 0x00030030;\r
+ *(svaddr + 4) = 0x020f0437;\r
+ *(svaddr + 5) = (unsigned int) allocadd;\r
+ *(svaddr + 6) = 0x000075a8;\r
+ *(svaddr + 7) = 0x00000000;\r
+ *(svaddr + 8) = 0x00000000;\r
+ *(svaddr + 9) = 0x00000000;\r
+ *(svaddr + 10) = 0x00000000;\r
+\r
+ *svaddr = 0x00000021;\r
+ for(i=0;i<480;i++){\r
+ for(j=0;j<400;j++){\r
+ *(allocadd + i*400 +j) = 0x0;\r
+ }\r
+ }\r
+ for(i=0;i<6;i++){\r
+ for(j=0;j<1024;j++){\r
+ *dataad = indata[i][j];\r
+ // for(k=0;k<100000;k++);\r
+ }\r
+ }\r
+ }\r
+\r
+\r
+\r
+ \r
+\r
-002f7f81
-002f7f81
-00307f81
-00317f81
-00327e82
-00327e82
-00337e82
-00337e82
-00347d83
-00347d83
-00347c84
-00347c84
-00347c84
-00347c84
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