This patch implements trap instructions for mips. The test cases are added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index 28abb7e..b05363d 100644 (file)
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -479,6 +479,17 @@ class TEQ_FM<bits<6> funct> {
   let Inst{5-0}   = funct;
 }
 
+class TEQI_FM<bits<5> funct> {
+  bits<5> rs;
+  bits<16> imm16;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 1;
+  let Inst{25-21} = rs;
+  let Inst{20-16}   = funct;
+  let Inst{15-0}  = imm16;
+}
 //===----------------------------------------------------------------------===//
 //  System calls format <op|code_|funct>
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 3c90e75..94f9ee6 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -630,6 +630,9 @@ class TEQ_FT<string opstr, RegisterOperand RO> :
   InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
          !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
 
+class TEQI_FT<string opstr, RegisterOperand RO> :
+  InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
+         !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
 // Mul, Div
 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
            list<Register> DefRegs> :
@@ -914,6 +917,18 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
 
 def SYNC : SYNC_FT, SYNC_FM;
 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
+def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
+def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
+def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
+def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
+def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
+
+def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
+def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
+def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
+def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
+def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
+def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
 
 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
@@ -1093,6 +1108,13 @@ def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
 def : InstAlias<"break", (BREAK 0, 0), 1>;
 def : InstAlias<"ei", (EI ZERO), 1>;
 def : InstAlias<"di", (DI ZERO), 1>;
+
+def  : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def  : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def  : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def  : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def  : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def  : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//

diff --git a/test/MC/Mips/mips-control-instructions.s b/test/MC/Mips/mips-control-instructions.s
index 825f349..4a16c53 100644 (file)
--- a/test/MC/Mips/mips-control-instructions.s
+++ b/test/MC/Mips/mips-control-instructions.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 | \
 # RUN: FileCheck -check-prefix=CHECK32  %s
-# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips64r2 | \
-# RUN: FileCheck -check-prefix=CHECK64  %s
+# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64r2 \
+# RUN: | FileCheck -check-prefix=CHECK64  %s
 
 # CHECK32:    break                      # encoding: [0x00,0x00,0x00,0x0d]
 # CHECK32:    break   7, 0               # encoding: [0x00,0x07,0x00,0x0d]
@@ -17,6 +17,24 @@
 # CHECK32:    ei                         # encoding: [0x41,0x60,0x60,0x20]
 # CHECK32:    ei      $10                # encoding: [0x41,0x6a,0x60,0x20]
 # CHECK32:    wait                       # encoding: [0x42,0x00,0x00,0x20]
+# CHECK32:    teq     $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+# CHECK32:    teq     $zero, $3, 1       # encoding: [0x00,0x03,0x00,0x74]
+# CHECK32:    teqi    $3, 1              # encoding: [0x04,0x6c,0x00,0x01]
+# CHECK32:    tge     $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
+# CHECK32:    tge     $zero, $3, 3       # encoding: [0x00,0x03,0x00,0xf0]
+# CHECK32:    tgei    $3, 3              # encoding: [0x04,0x68,0x00,0x03]
+# CHECK32:    tgeu    $zero, $3          # encoding: [0x00,0x03,0x00,0x31]
+# CHECK32:    tgeu    $zero, $3, 7       # encoding: [0x00,0x03,0x01,0xf1]
+# CHECK32:    tgeiu   $3, 7              # encoding: [0x04,0x69,0x00,0x07]
+# CHECK32:    tlt     $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
+# CHECK32:    tlt     $zero, $3, 31      # encoding: [0x00,0x03,0x07,0xf2]
+# CHECK32:    tlti    $3, 31             # encoding: [0x04,0x6a,0x00,0x1f]
+# CHECK32:    tltu    $zero, $3          # encoding: [0x00,0x03,0x00,0x33]
+# CHECK32:    tltu    $zero, $3, 255     # encoding: [0x00,0x03,0x3f,0xf3]
+# CHECK32:    tltiu   $3, 255            # encoding: [0x04,0x6b,0x00,0xff]
+# CHECK32:    tne     $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
+# CHECK32:    tne     $zero, $3, 1023    # encoding: [0x00,0x03,0xff,0xf6]
+# CHECK32:    tnei    $3, 1023           # encoding: [0x04,0x6e,0x03,0xff]
 
 # CHECK64:    break                      # encoding: [0x00,0x00,0x00,0x0d]
 # CHECK64:    break   7, 0               # encoding: [0x00,0x07,0x00,0x0d]
@@ -32,6 +50,25 @@
 # CHECK64:    ei                         # encoding: [0x41,0x60,0x60,0x20]
 # CHECK64:    ei      $10                # encoding: [0x41,0x6a,0x60,0x20]
 # CHECK64:    wait                       # encoding: [0x42,0x00,0x00,0x20]
+# CHECK64:    teq     $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+# CHECK64:    teq     $zero, $3, 1       # encoding: [0x00,0x03,0x00,0x74]
+# CHECK64:    teqi    $3, 1              # encoding: [0x04,0x6c,0x00,0x01]
+# CHECK64:    tge     $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
+# CHECK64:    tge     $zero, $3, 3       # encoding: [0x00,0x03,0x00,0xf0]
+# CHECK64:    tgei    $3, 3              # encoding: [0x04,0x68,0x00,0x03]
+# CHECK64:    tgeu    $zero, $3          # encoding: [0x00,0x03,0x00,0x31]
+# CHECK64:    tgeu    $zero, $3, 7       # encoding: [0x00,0x03,0x01,0xf1]
+# CHECK64:    tgeiu   $3, 7              # encoding: [0x04,0x69,0x00,0x07]
+# CHECK64:    tlt     $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
+# CHECK64:    tlt     $zero, $3, 31      # encoding: [0x00,0x03,0x07,0xf2]
+# CHECK64:    tlti    $3, 31             # encoding: [0x04,0x6a,0x00,0x1f]
+# CHECK64:    tltu    $zero, $3          # encoding: [0x00,0x03,0x00,0x33]
+# CHECK64:    tltu    $zero, $3, 255     # encoding: [0x00,0x03,0x3f,0xf3]
+# CHECK64:    tltiu   $3, 255            # encoding: [0x04,0x6b,0x00,0xff]
+# CHECK64:    tne     $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
+# CHECK64:    tne     $zero, $3, 1023    # encoding: [0x00,0x03,0xff,0xf6]
+# CHECK64:    tnei    $3, 1023           # encoding: [0x04,0x6e,0x03,0xff]
+
     break
     break 7
     break 7,5
@@ -48,3 +85,22 @@
     ei  $10
 
     wait
+
+    teq   $0,$3
+    teq   $0,$3,1
+    teqi  $3,1
+    tge   $0,$3
+    tge   $0,$3,3
+    tgei  $3,3
+    tgeu  $0,$3
+    tgeu  $0,$3,7
+    tgeiu $3,7
+    tlt   $0,$3
+    tlt   $0,$3,31
+    tlti  $3,31
+    tltu  $0,$3
+    tltu  $0,$3,255
+    tltiu $3,255
+    tne   $0,$3
+    tne   $0,$3,1023
+    tnei  $3,1023