2004-07-20 Dave Brolley <brolley@redhat.com>

        * cacheutil.cxx (find): Make sure cache line is valid before returning
        it.
        * cache.cxx (write_any): Move call to addr_to_tag to a later point when
        the result is actually needed. Make sure cache line is valid before
        flushing it.
        (read_any): Make sure cache line is valid before flushing it.

diff --git a/sid/component/cache/ChangeLog b/sid/component/cache/ChangeLog
index 181ae61..90840ac 100644 (file)
--- a/sid/component/cache/ChangeLog
+++ b/sid/component/cache/ChangeLog
@@ -1,3 +1,12 @@
+2004-07-20  Dave Brolley  <brolley@redhat.com>
+
+       * cacheutil.cxx (find): Make sure cache line is valid before returning
+       it.
+       * cache.cxx (write_any): Move call to addr_to_tag to a later point when
+       the result is actually needed. Make sure cache line is valid before
+       flushing it.
+       (read_any): Make sure cache line is valid before flushing it.
+
 2004-07-01  Dave Brolley  <brolley@redhat.com>
 
        * cache.cxx (write_any): Allow misaligned access. Return

diff --git a/sid/component/cache/cache.cxx b/sid/component/cache/cache.cxx
index 932e4c7..cb5e2de 100644 (file)
--- a/sid/component/cache/cache.cxx
+++ b/sid/component/cache/cache.cxx
@@ -180,7 +180,6 @@ cache_component::write_any (host_int_4 addr, DataType data)
   if (LIKELY (collect_p))
     stats.writes++;
 
-  cache_tag tag = acache.addr_to_tag (addr);
   if (UNLIKELY (addr % sizeof (data) != 0))
     {
       if (LIKELY (collect_p))
@@ -191,6 +190,7 @@ cache_component::write_any (host_int_4 addr, DataType data)
   if (UNLIKELY (addr % line_size + sizeof (data) > line_size))
     return bus::misaligned;
 
+  cache_tag tag = acache.addr_to_tag (addr);
   cache_line* line = acache.find (tag);
   if (LIKELY (line))
     {
@@ -215,7 +215,7 @@ cache_component::write_any (host_int_4 addr, DataType data)
 
          if (! write_through_p)
            {
-             if (expelled_line->dirty_p ())
+             if (expelled_line->valid_p () && expelled_line->dirty_p ())
                {
                  // flush a dirty line being replaced
                  if ((st = write_line (*expelled_line)) != bus::ok)
@@ -291,7 +291,7 @@ cache_component::read_any (host_int_4 addr, DataType& data)
          
          cache_line *expelled_line = acache.expell_line (tag);
          assert (expelled_line);
-         if (expelled_line->dirty_p ())
+         if (expelled_line->valid_p () && expelled_line->dirty_p ())
            {
              // flush a dirty line being replaced
              if ((st = write_line (*expelled_line)) != bus::ok)

diff --git a/sid/component/cache/cacheutil.cxx b/sid/component/cache/cacheutil.cxx
index 9f3d75c..b950a29 100644 (file)
--- a/sid/component/cache/cacheutil.cxx
+++ b/sid/component/cache/cacheutil.cxx
@@ -173,7 +173,7 @@ cache_set::find (const cache_tag& tag)
   // order of associativity will be small.
 
   for (const_iterator_t it = lines.begin (); it != lines.end (); it++)
-    if (tag == *(*it))
+    if (tag == *(*it) && (*it)->valid_p ())
       {
        replacer.update (*this, *(*it));
        return *it;