FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
FIELD(MSR, IR, MSR_IR, 1)
+FIELD(MSR, DR, MSR_DR, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
#define msr_de ((env->msr >> MSR_DE) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ep ((env->msr >> MSR_EP) & 1)
-#define msr_dr ((env->msr >> MSR_DR) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
" nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
" ir=%d dr=%d pr=%d %d t=%d\n",
eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr,
- (int)FIELD_EX64(env->msr, MSR, IR), (int)msr_dr, pr ? 1 : 0,
+ (int)FIELD_EX64(env->msr, MSR, IR),
+ (int)FIELD_EX64(env->msr, MSR, DR), pr ? 1 : 0,
access_type == MMU_DATA_STORE, type);
pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
hash = vsid ^ pgidx;
/* Check the address space */
if ((access_type == MMU_INST_FETCH ?
- FIELD_EX64(env->msr, MSR, IR) : msr_dr) != (tlb->attr & 1)) {
+ FIELD_EX64(env->msr, MSR, IR) :
+ FIELD_EX64(env->msr, MSR, DR)) != (tlb->attr & 1)) {
qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
return -1;
}
int mmu_idx)
{
int ret = -1;
- bool real_mode = (type == ACCESS_CODE && !FIELD_EX64(env->msr, MSR, IR))
- || (type != ACCESS_CODE && msr_dr == 0);
+ bool real_mode = (type == ACCESS_CODE && !FIELD_EX64(env->msr, MSR, IR)) ||
+ (type != ACCESS_CODE && !FIELD_EX64(env->msr, MSR, DR));
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx: