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igc: Remove unused registers
authorSasha Neftin <sasha.neftin@intel.com>
Sun, 12 Apr 2020 14:21:58 +0000 (17:21 +0300)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Tue, 19 May 2020 23:00:00 +0000 (16:00 -0700)
Tx data FIFO Head/Tail, Saved and Packet Count registers
not applicable for i225 LAN controller.
This patch comes to clean up these registers.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/igc/igc_dump.c
drivers/net/ethernet/intel/igc/igc_regs.h

index 4ad32d9..4b9ec7d 100644 (file)
@@ -35,10 +35,6 @@ static const struct igc_reg_info igc_reg_info_tbl[] = {
        {IGC_TDH(0), "TDH"},
        {IGC_TDT(0), "TDT"},
        {IGC_TXDCTL(0), "TXDCTL"},
-       {IGC_TDFH, "TDFH"},
-       {IGC_TDFT, "TDFT"},
-       {IGC_TDFHS, "TDFHS"},
-       {IGC_TDFPC, "TDFPC"},
 
        /* List Terminator */
        {}
index 763a24d..61db951 100644 (file)
 /* Internal Packet Buffer Size Registers */
 #define IGC_RXPBS              0x02404  /* Rx Packet Buffer Size - RW */
 #define IGC_TXPBS              0x03404  /* Tx Packet Buffer Size - RW */
-#define IGC_TDFH               0x03410  /* Tx Data FIFO Head - RW */
-#define IGC_TDFT               0x03418  /* Tx Data FIFO Tail - RW */
-#define IGC_TDFHS              0x03420  /* Tx Data FIFO Head Saved - RW */
-#define IGC_TDFTS              0x03428  /* Tx Data FIFO Tail Saved - RW */
-#define IGC_TDFPC              0x03430  /* Tx Data FIFO Packet Count - RW */
 
 /* NVM  Register Descriptions */
 #define IGC_EERD               0x12014  /* EEprom mode read - RW */