git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276011
91177308-0d34-0410-b5e6-
96231b3b80d8
assert(Reg && "NoRegister does not have a register bank");
const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
- if (RegClassOrBank.is<const RegisterBank *>())
- return RegClassOrBank.get<const RegisterBank *>();
- const TargetRegisterClass *RC =
- RegClassOrBank.get<const TargetRegisterClass *>();
- if (RC)
+ if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
+ return RB;
+ if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
return &getRegBankFromRegClass(*RC);
return nullptr;
}