--- /dev/null
+/*\r
+ * Copyright (c) 2008 Siarhei Siamashka <ssvb@users.sourceforge.net>\r
+ *\r
+ * This file is part of FFmpeg.\r
+ *\r
+ * FFmpeg is free software; you can redistribute it and/or\r
+ * modify it under the terms of the GNU Lesser General Public\r
+ * License as published by the Free Software Foundation; either\r
+ * version 2.1 of the License, or (at your option) any later version.\r
+ *\r
+ * FFmpeg is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+ * Lesser General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU Lesser General Public\r
+ * License along with FFmpeg; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\r
+ */\r
+\r
+#include "libavcodec/dsputil.h"\r
+\r
+/*\r
+ * VFP is a floating point coprocessor used in some ARM cores. VFP11 has 1 cycle\r
+ * throughput for almost all the instructions (except for double precision\r
+ * arithmetics), but rather high latency. Latency is 4 cycles for loads and 8 cycles\r
+ * for arithmetic operations. Scheduling code to avoid pipeline stalls is very\r
+ * important for performance. One more interesting feature is that VFP has\r
+ * independent load/store and arithmetics pipelines, so it is possible to make\r
+ * them work simultaneously and get more than 1 operation per cycle. Load/store\r
+ * pipeline can process 2 single precision floating point values per cycle and\r
+ * supports bulk loads and stores for large sets of registers. Arithmetic operations\r
+ * can be done on vectors, which allows to keep the arithmetics pipeline busy,\r
+ * while the processor may issue and execute other instructions. Detailed\r
+ * optimization manuals can be found at http://www.arm.com\r
+ */\r
+\r
+/**\r
+ * ARM VFP optimized implementation of 'vector_fmul_c' function.\r
+ * Assume that len is a positive number and is multiple of 8\r
+ */\r
+static void vector_fmul_vfp(float *dst, const float *src, int len)\r
+{\r
+ int tmp;\r
+ asm volatile(\r
+ "fmrx %[tmp], fpscr\n\t"\r
+ "orr %[tmp], %[tmp], #(3 << 16)\n\t" /* set vector size to 4 */\r
+ "fmxr fpscr, %[tmp]\n\t"\r
+\r
+ "fldmias %[dst_r]!, {s0-s3}\n\t"\r
+ "fldmias %[src]!, {s8-s11}\n\t"\r
+ "fldmias %[dst_r]!, {s4-s7}\n\t"\r
+ "fldmias %[src]!, {s12-s15}\n\t"\r
+ "fmuls s8, s0, s8\n\t"\r
+ "1:\n\t"\r
+ "subs %[len], %[len], #16\n\t"\r
+ "fmuls s12, s4, s12\n\t"\r
+ "fldmiasge %[dst_r]!, {s16-s19}\n\t"\r
+ "fldmiasge %[src]!, {s24-s27}\n\t"\r
+ "fldmiasge %[dst_r]!, {s20-s23}\n\t"\r
+ "fldmiasge %[src]!, {s28-s31}\n\t"\r
+ "fmulsge s24, s16, s24\n\t"\r
+ "fstmias %[dst_w]!, {s8-s11}\n\t"\r
+ "fstmias %[dst_w]!, {s12-s15}\n\t"\r
+ "fmulsge s28, s20, s28\n\t"\r
+ "fldmiasgt %[dst_r]!, {s0-s3}\n\t"\r
+ "fldmiasgt %[src]!, {s8-s11}\n\t"\r
+ "fldmiasgt %[dst_r]!, {s4-s7}\n\t"\r
+ "fldmiasgt %[src]!, {s12-s15}\n\t"\r
+ "fmulsge s8, s0, s8\n\t"\r
+ "fstmiasge %[dst_w]!, {s24-s27}\n\t"\r
+ "fstmiasge %[dst_w]!, {s28-s31}\n\t"\r
+ "bgt 1b\n\t"\r
+\r
+ "bic %[tmp], %[tmp], #(7 << 16)\n\t" /* set vector size back to 1 */\r
+ "fmxr fpscr, %[tmp]\n\t"\r
+ : [dst_w] "+&r" (dst), [dst_r] "+&r" (dst), [src] "+&r" (src), [len] "+&r" (len), [tmp] "=&r" (tmp)\r
+ :\r
+ : "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",\r
+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",\r
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",\r
+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",\r
+ "cc", "memory");\r
+}\r
+\r
+/**\r
+ * ARM VFP optimized implementation of 'vector_fmul_reverse_c' function.\r
+ * Assume that len is a positive number and is multiple of 8\r
+ */\r
+static void vector_fmul_reverse_vfp(float *dst, const float *src0, const float *src1, int len)\r
+{\r
+ src1 += len;\r
+ asm volatile(\r
+ "fldmdbs %[src1]!, {s0-s3}\n\t"\r
+ "fldmias %[src0]!, {s8-s11}\n\t"\r
+ "fldmdbs %[src1]!, {s4-s7}\n\t"\r
+ "fldmias %[src0]!, {s12-s15}\n\t"\r
+ "fmuls s8, s3, s8\n\t"\r
+ "fmuls s9, s2, s9\n\t"\r
+ "fmuls s10, s1, s10\n\t"\r
+ "fmuls s11, s0, s11\n\t"\r
+ "1:\n\t"\r
+ "subs %[len], %[len], #16\n\t"\r
+ "fldmdbsge %[src1]!, {s16-s19}\n\t"\r
+ "fmuls s12, s7, s12\n\t"\r
+ "fldmiasge %[src0]!, {s24-s27}\n\t"\r
+ "fmuls s13, s6, s13\n\t"\r
+ "fldmdbsge %[src1]!, {s20-s23}\n\t"\r
+ "fmuls s14, s5, s14\n\t"\r
+ "fldmiasge %[src0]!, {s28-s31}\n\t"\r
+ "fmuls s15, s4, s15\n\t"\r
+ "fmulsge s24, s19, s24\n\t"\r
+ "fldmdbsgt %[src1]!, {s0-s3}\n\t"\r
+ "fmulsge s25, s18, s25\n\t"\r
+ "fstmias %[dst]!, {s8-s13}\n\t"\r
+ "fmulsge s26, s17, s26\n\t"\r
+ "fldmiasgt %[src0]!, {s8-s11}\n\t"\r
+ "fmulsge s27, s16, s27\n\t"\r
+ "fmulsge s28, s23, s28\n\t"\r
+ "fldmdbsgt %[src1]!, {s4-s7}\n\t"\r
+ "fmulsge s29, s22, s29\n\t"\r
+ "fstmias %[dst]!, {s14-s15}\n\t"\r
+ "fmulsge s30, s21, s30\n\t"\r
+ "fmulsge s31, s20, s31\n\t"\r
+ "fmulsge s8, s3, s8\n\t"\r
+ "fldmiasgt %[src0]!, {s12-s15}\n\t"\r
+ "fmulsge s9, s2, s9\n\t"\r
+ "fmulsge s10, s1, s10\n\t"\r
+ "fstmiasge %[dst]!, {s24-s27}\n\t"\r
+ "fmulsge s11, s0, s11\n\t"\r
+ "fstmiasge %[dst]!, {s28-s31}\n\t"\r
+ "bgt 1b\n\t"\r
+\r
+ : [dst] "+&r" (dst), [src0] "+&r" (src0), [src1] "+&r" (src1), [len] "+&r" (len)\r
+ :\r
+ : "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",\r
+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",\r
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",\r
+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",\r
+ "cc", "memory");\r
+}\r
+\r
+#ifdef HAVE_ARMV6\r
+/**\r
+ * ARM VFP optimized float to int16 conversion.\r
+ * Assume that len is a positive number and is multiple of 8, destination\r
+ * buffer is at least 4 bytes aligned (8 bytes alignment is better for\r
+ * performance), little endian byte sex\r
+ */\r
+void float_to_int16_vfp(int16_t *dst, const float *src, int len)\r
+{\r
+ asm volatile(\r
+ "fldmias %[src]!, {s16-s23}\n\t"\r
+ "ftosis s0, s16\n\t"\r
+ "ftosis s1, s17\n\t"\r
+ "ftosis s2, s18\n\t"\r
+ "ftosis s3, s19\n\t"\r
+ "ftosis s4, s20\n\t"\r
+ "ftosis s5, s21\n\t"\r
+ "ftosis s6, s22\n\t"\r
+ "ftosis s7, s23\n\t"\r
+ "1:\n\t"\r
+ "subs %[len], %[len], #8\n\t"\r
+ "fmrrs r3, r4, {s0, s1}\n\t"\r
+ "fmrrs r5, r6, {s2, s3}\n\t"\r
+ "fmrrs r7, r8, {s4, s5}\n\t"\r
+ "fmrrs ip, lr, {s6, s7}\n\t"\r
+ "fldmiasgt %[src]!, {s16-s23}\n\t"\r
+ "ssat r4, #16, r4\n\t"\r
+ "ssat r3, #16, r3\n\t"\r
+ "ssat r6, #16, r6\n\t"\r
+ "ssat r5, #16, r5\n\t"\r
+ "pkhbt r3, r3, r4, lsl #16\n\t"\r
+ "pkhbt r4, r5, r6, lsl #16\n\t"\r
+ "ftosisgt s0, s16\n\t"\r
+ "ftosisgt s1, s17\n\t"\r
+ "ftosisgt s2, s18\n\t"\r
+ "ftosisgt s3, s19\n\t"\r
+ "ftosisgt s4, s20\n\t"\r
+ "ftosisgt s5, s21\n\t"\r
+ "ftosisgt s6, s22\n\t"\r
+ "ftosisgt s7, s23\n\t"\r
+ "ssat r8, #16, r8\n\t"\r
+ "ssat r7, #16, r7\n\t"\r
+ "ssat lr, #16, lr\n\t"\r
+ "ssat ip, #16, ip\n\t"\r
+ "pkhbt r5, r7, r8, lsl #16\n\t"\r
+ "pkhbt r6, ip, lr, lsl #16\n\t"\r
+ "stmia %[dst]!, {r3-r6}\n\t"\r
+ "bgt 1b\n\t"\r
+\r
+ : [dst] "+&r" (dst), [src] "+&r" (src), [len] "+&r" (len)\r
+ :\r
+ : "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",\r
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",\r
+ "r3", "r4", "r5", "r6", "r7", "r8", "ip", "lr",\r
+ "cc", "memory");\r
+}\r
+#endif\r
+\r
+void ff_float_init_arm_vfp(DSPContext* c, AVCodecContext *avctx)\r
+{\r
+ c->vector_fmul = vector_fmul_vfp;\r
+ c->vector_fmul_reverse = vector_fmul_reverse_vfp;\r
+#ifdef HAVE_ARMV6\r
+ c->float_to_int16 = float_to_int16_vfp;\r
+#endif\r
+}\r
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