[Target/ARM] Only enable OptimizeBarrierPass at -O1 and above.

Ideally this is going to be and LLVM IR pass (shared, among others
with AArch64), but for the time being just enable it if consumers
ask us for optimization and not unconditionally.

Discussed with Tim Northover on IRC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237837 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index bd29a05..e794fb7 100644 (file)
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -402,6 +402,9 @@ void ARMPassConfig::addPreEmitPass() {
   if (getARMSubtarget().isThumb2())
     addPass(&UnpackMachineBundlesID);
 
-  addPass(createARMOptimizeBarriersPass());
+  // Don't optimize barriers at -O0.
+  if (getOptLevel() != CodeGenOpt::None)
+    addPass(createARMOptimizeBarriersPass());
+
   addPass(createARMConstantIslandPass());
 }

diff --git a/test/CodeGen/ARM/noopt-dmb-v7.ll b/test/CodeGen/ARM/noopt-dmb-v7.ll
new file mode 100644 (file)
index 0000000..56a29c8
--- /dev/null
+++ b/test/CodeGen/ARM/noopt-dmb-v7.ll
@@ -0,0 +1,15 @@
+; Ensure that adjacent duplicated barriers are not removed at -O0.
+; RUN: llc -O0 < %s -mtriple=armv7 -mattr=+db | FileCheck %s
+
+define i32 @t1() {
+entry:
+  fence seq_cst
+  fence seq_cst
+  fence seq_cst
+  ret i32 0
+}
+
+; CHECK: @ BB#0: @ %entry
+; CHECK-NEXT: dmb ish
+; CHECK-NEXT: dmb ish
+; CHECK-NEXT: dmb ish

diff --git a/test/CodeGen/ARM/optimize-dmbs-v7.ll b/test/CodeGen/ARM/optimize-dmbs-v7.ll
index 64f5e20..34a55aa 100644 (file)
--- a/test/CodeGen/ARM/optimize-dmbs-v7.ll
+++ b/test/CodeGen/ARM/optimize-dmbs-v7.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=armv7 -mattr=+db | FileCheck %s
+; RUN: llc -O1 < %s -mtriple=armv7 -mattr=+db | FileCheck %s
 
 @x1 = global i32 0, align 4
 @x2 = global i32 0, align 4