This patch is a follow up for D61391 to add lround/llround
support for float16.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362698
91177308-0d34-0410-b5e6-
96231b3b80d8
defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
+let Predicates = [HasFullFP16] in {
+ def : Pat<(i32 (lround f16:$Rn)),
+ (!cast<Instruction>(FCVTASUWHr) f16:$Rn)>;
+ def : Pat<(i64 (lround f16:$Rn)),
+ (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
+ def : Pat<(i64 (llround f16:$Rn)),
+ (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
+}
def : Pat<(i32 (lround f32:$Rn)),
(!cast<Instruction>(FCVTASUWSr) f32:$Rn)>;
def : Pat<(i32 (lround f64:$Rn)),
--- /dev/null
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK: fcvtas x0, h0
+; CHECK: ret
+define i16 @testmhhs(half %x) {
+entry:
+ %0 = tail call i64 @llvm.llround.i64.f16(half %x)
+ %conv = trunc i64 %0 to i16
+ ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK: fcvtas x0, h0
+; CHECK: ret
+define i32 @testmhws(half %x) {
+entry:
+ %0 = tail call i64 @llvm.llround.i64.f16(half %x)
+ %conv = trunc i64 %0 to i32
+ ret i32 %conv
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK: fcvtas x0, h0
+; CHECK-NEXT: ret
+define i64 @testmhxs(half %x) {
+entry:
+ %0 = tail call i64 @llvm.llround.i64.f16(half %x)
+ ret i64 %0
+}
+
+declare i64 @llvm.llround.i64.f16(half) nounwind readnone
--- /dev/null
+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK: fcvtas w0, h0
+; CHECK: ret
+define i16 @testmhhs(half %x) {
+entry:
+ %0 = tail call i32 @llvm.lround.i32.f16(half %x)
+ %conv = trunc i32 %0 to i16
+ ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK: fcvtas w0, h0
+; CHECK: ret
+define i32 @testmhws(half %x) {
+entry:
+ %0 = tail call i32 @llvm.lround.i32.f16(half %x)
+ ret i32 %0
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK: fcvtas w8, h0
+; CHECK-NEXT: sxtw x0, w8
+; CHECK-NEXT: ret
+define i64 @testmhxs(half %x) {
+entry:
+ %0 = tail call i32 @llvm.lround.i32.f16(half %x)
+ %conv = sext i32 %0 to i64
+ ret i64 %conv
+}
+
+declare i32 @llvm.lround.i32.f16(half) nounwind readnone
--- /dev/null
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK: fcvtas x0, h0
+; CHECK: ret
+define i16 @testmhhs(half %x) {
+entry:
+ %0 = tail call i64 @llvm.lround.i64.f16(half %x)
+ %conv = trunc i64 %0 to i16
+ ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK: fcvtas x0, h0
+; CHECK: ret
+define i32 @testmhws(half %x) {
+entry:
+ %0 = tail call i64 @llvm.lround.i64.f16(half %x)
+ %conv = trunc i64 %0 to i32
+ ret i32 %conv
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK: fcvtas x0, h0
+; CHECK-NEXT: ret
+define i64 @testmhxs(half %x) {
+entry:
+ %0 = tail call i64 @llvm.lround.i64.f16(half %x)
+ ret i64 %0
+}
+
+declare i64 @llvm.lround.i64.f16(half) nounwind readnone