ARM: dts: sun9i: Add GMAC clock node

The A80 has the same DWMAC hardware as on earlier Allwinner SoCs. The
accompanying GMAC clock register has been moved into the "System
Control" area.

Add a clock node for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d9532fb..724ca3b 100644 (file)
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -183,6 +183,37 @@
                        clock-output-names = "osc32k";
                };
 
+               /*
+                * The following two are dummy clocks, placeholders
+                * used in the gmac_tx clock. The gmac driver will
+                * choose one parent depending on the PHY interface
+                * mode, using clk_set_rate auto-reparenting.
+                *
+                * The actual TX clock rate is not controlled by the
+                * gmac_tx clock.
+                */
+               mii_phy_tx_clk: mii_phy_tx_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <25000000>;
+                       clock-output-names = "mii_phy_tx";
+               };
+
+               gmac_int_tx_clk: gmac_int_tx_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <125000000>;
+                       clock-output-names = "gmac_int_tx";
+               };
+
+               gmac_tx_clk: clk@800030 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun7i-a20-gmac-clk";
+                       reg = <0x00800030 0x4>;
+                       clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+                       clock-output-names = "gmac_tx";
+               };
+
                cpus_clk: clk@8001410 {
                        compatible = "allwinner,sun9i-a80-cpus-clk";
                        reg = <0x08001410 0x4>;