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clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2ch
author
zhangqing
<zhangqing@rock-chips.com>
Mon, 25 Jan 2016 16:56:02 +0000
(08:56 -0800)
committer
Heiko Stuebner
<heiko@sntech.de>
Mon, 25 Jan 2016 10:06:54 +0000
(11:06 +0100)
I2S_2CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3368.c
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diff --git
a/drivers/clk/rockchip/clk-rk3368.c
b/drivers/clk/rockchip/clk-rk3368.c
index
caf0b94
..
e90abe8
100644
(file)
--- a/
drivers/clk/rockchip/clk-rk3368.c
+++ b/
drivers/clk/rockchip/clk-rk3368.c
@@
-362,7
+362,7
@@
static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(54), 0,
RK3368_CLKGATE_CON(5), 14, GFLAGS),
- COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p,
0
,
+ COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p,
CLK_SET_RATE_PARENT
,
RK3368_CLKSEL_CON(53), 8, 2, MFLAGS,
RK3368_CLKGATE_CON(5), 15, GFLAGS),