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MIPS: mm: Fix definition of R6 cache instruction
author
Matt Redfearn
<matt.redfearn@imgtec.com>
Tue, 14 Jun 2016 13:59:38 +0000
(14:59 +0100)
committer
Greg Kroah-Hartman
<gregkh@linuxfoundation.org>
Sat, 20 Aug 2016 16:09:26 +0000
(18:09 +0200)
commit
4f53989b0652ffe2605221c81ca8ffcfc90aed2a
upstream.
Commit
a168b8f1cde6
("MIPS: mm: Add MIPS R6 instruction encodings") added
an incorrect definition of the redefined MIPSr6 cache instruction.
Executing any kernel code including this instuction results in a
reserved instruction exception and kernel panic.
Fix the instruction definition.
Fixes:
a168b8f1cde6588ff7a67699fa11e01bc77a5ddd
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13663/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/mips/mm/uasm-mips.c
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diff --git
a/arch/mips/mm/uasm-mips.c
b/arch/mips/mm/uasm-mips.c
index
b4a8378
..
5abe51c
100644
(file)
--- a/
arch/mips/mm/uasm-mips.c
+++ b/
arch/mips/mm/uasm-mips.c
@@
-65,7
+65,7
@@
static struct insn insn_table[] = {
#ifndef CONFIG_CPU_MIPSR6
{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
#else
- { insn_cache, M6(
cache
_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 },
+ { insn_cache, M6(
spec3
_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 },
#endif
{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },