drm/amd/display: update dio for two pixel per container case

[why]
Processing rate of the DP encoder, must be programmed to be the same as
DIG_FIFO_OUTPUT_ PROCESSING_MODE in DP mode
0: 1 pixel per cycle
1: 2 pixel per cycle

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
index c724481..89de64f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
@@ -286,6 +286,7 @@ static void enc32_stream_encoder_dp_unblank(
                uint32_t n_vid = 0x8000;
                uint32_t m_vid;
                uint32_t n_multiply = 0;
+               uint32_t pix_per_cycle = 0;
                uint64_t m_vid_l = n_vid;
 
                /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
@@ -320,6 +321,10 @@ static void enc32_stream_encoder_dp_unblank(
                REG_UPDATE_2(DP_VID_TIMING,
                                DP_VID_M_N_GEN_EN, 1,
                                DP_VID_N_MUL, n_multiply);
+
+               REG_UPDATE(DP_PIXEL_FORMAT,
+                               DP_PIXEL_PER_CYCLE_PROCESSING_MODE,
+                               pix_per_cycle);
        }
 
        /* make sure stream is disabled before resetting steer fifo */