de1 integration. failed to display..

diff --git a/de0_cv_nes/de0_cv_nes.qsf b/de0_cv_nes/de0_cv_nes.qsf
index be9933b..3a8760e 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.qsf
+++ b/de0_cv_nes/de0_cv_nes.qsf
@@ -115,7 +115,7 @@ set_global_assignment -name VHDL_FILE ../de1_nes/cpu/mos6502.vhd
 set_global_assignment -name VHDL_FILE de0_cv_nes.vhd\r
 \r
 ##timing definition...\r
-set_global_assignment -name SDC_FILE ../de1_nesmos6502-timing.sdc\r
+set_global_assignment -name SDC_FILE ../de1_nes/mos6502-timing.sdc\r
 \r
 ##for signal trap ii setting...\r
 set_global_assignment -name ENABLE_SIGNALTAP ON\r
@@ -620,5 +620,5 @@ set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -t
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "counter_register:clock_counter_inst|\\clk_p:q_out[8]" -section_id auto_signaltap_0\r
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "counter_register:clock_counter_inst|\\clk_p:q_out[9]" -section_id auto_signaltap_0\r
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=65505" -section_id auto_signaltap_0\r
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top\r
-set_global_assignment -name SLD_FILE "D:/daisuke/nes/repo/motonesfpga/de0_cv_nes/de0-cv-analyze-all_auto_stripped.stp"
\ No newline at end of file
+set_global_assignment -name SLD_FILE "de0-cv-analyze-all_auto_stripped.stp"\r
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd
index d6261f7..c55e285 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.vhd
+++ b/de0_cv_nes/de0_cv_nes.vhd
@@ -156,6 +156,7 @@ architecture rtl of de0_cv_nes is
         signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);
         signal dbg_s_oam_addr_cpy               : out std_logic_vector (4 downto 0);
 
+                cpu_clk     : in std_logic;
                 dl_cpu_clk  : in std_logic;
                 ppu_clk     : in std_logic;
                 vga_clk     : in std_logic;
@@ -382,6 +383,7 @@ begin
         dbg_s_oam_data                  ,
         dbg_s_oam_addr_cpy              ,
 
+                cpu_clk     ,
                 cpu_mem_clk     ,
                 ppu_clk         ,
                 vga_clk     ,