PLANE_PROP_ROTATION,
PLANE_PROP_BLEND_OP,
PLANE_PROP_SRC_CONFIG,
+ PLANE_PROP_FB_TRANSLATION_MODE,
/* total # of properties */
PLANE_PROP_COUNT
CRTC_PROP_CORE_CLK,
CRTC_PROP_CORE_AB,
CRTC_PROP_CORE_IB,
+ CRTC_PROP_SECURITY_LEVEL,
/* total # of properties */
CRTC_PROP_COUNT
struct drm_device *dev;
struct sde_kms_info *info;
struct sde_kms *sde_kms;
+ static const struct drm_prop_enum_list e_secure_level[] = {
+ {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
+ {SDE_DRM_SEC_ONLY, "sec_only"},
+ };
SDE_DEBUG("\n");
msm_property_install_blob(&sde_crtc->property_info, "capabilities",
DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
+
+ msm_property_install_enum(&sde_crtc->property_info, "security_level",
+ 0x0, 0, e_secure_level,
+ ARRAY_SIZE(e_secure_level),
+ CRTC_PROP_SECURITY_LEVEL);
+
sde_kms_info_reset(info);
sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
static const struct drm_prop_enum_list e_src_config[] = {
{SDE_DRM_DEINTERLACE, "deinterlace"}
};
+ static const struct drm_prop_enum_list e_fb_translation_mode[] = {
+ {SDE_DRM_FB_NON_SEC, "non_sec"},
+ {SDE_DRM_FB_SEC, "sec"},
+ {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
+ {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
+ };
const struct sde_format_extended *format_list;
struct sde_kms_info *info;
struct sde_plane *psde = to_sde_plane(plane);
msm_property_install_blob(&psde->property_info, feature_name, 0,
PLANE_PROP_FOLIAGE_COLOR);
}
+
+ msm_property_install_enum(&psde->property_info, "fb_translation_mode",
+ 0x0,
+ 0, e_fb_translation_mode,
+ ARRAY_SIZE(e_fb_translation_mode),
+ PLANE_PROP_FB_TRANSLATION_MODE);
}
static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
#define SDE_DRM_BITMASK_COUNT 64
/**
+ * Framebuffer modes for "fb_translation_mode" PLANE property
+ *
+ * @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode
+ * is non-secure domain and requires
+ * both stage I and stage II translations when
+ * this buffer is accessed by the display HW.
+ * This is the default mode of all frambuffers.
+ * @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode
+ * is secure domain and requires
+ * both stage I and stage II translations when
+ * this buffer is accessed by the display HW.
+ * @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
+ * is non-secure domain and requires
+ * only stage II translation when
+ * this buffer is accessed by the display HW.
+ * @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
+ * is secure domain and requires
+ * only stage II translation when
+ * this buffer is accessed by the display HW.
+*/
+
+#define SDE_DRM_FB_NON_SEC 0
+#define SDE_DRM_FB_SEC 1
+#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2
+#define SDE_DRM_FB_SEC_DIR_TRANS 3
+
+/**
+ * Secure levels for "security_level" CRTC property.
+ * CRTC property which specifies what plane types
+ * can be attached to this CRTC. Plane component
+ * derives the plane type based on the FB_MODE.
+ * @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be
+ * attached to this CRTC. This is the default state of
+ * the CRTC.
+ * @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a
+ * CRTC is instructed to be in this mode it follows the
+ * platform dependent restrictions.
+ */
+#define SDE_DRM_SEC_NON_SEC 0
+#define SDE_DRM_SEC_ONLY 1
+
+/**
* struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure
* @num_ext_pxls_lr: Number of total horizontal pixels
* @num_ext_pxls_tb: Number of total vertical lines