// Promote the value if needed.
switch (VA.getLocInfo()) {
default:
- // Loc info must be one of Full, SExt, ZExt, or AExt.
+ // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
llvm_unreachable("Unknown loc info!");
- case CCValAssign::BCvt:
case CCValAssign::Full:
break;
+ case CCValAssign::BCvt:
+ Arg = DAG.getBitcast(VA.getLocVT(), Arg);
+ break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
break;
unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
+ if (VA.getLocInfo() == CCValAssign::BCvt)
+ RegVT = VA.getValVT();
SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
// Treat values of type MVT::i1 specially: they are passed in
// registers of type i32, but they need to remain as values of
unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
+ if (VA.getLocInfo() == CCValAssign::BCvt)
+ RegVT = VA.getValVT();
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
// Single Vector
--- /dev/null
+; RUN: llc -march=hexagon -debug-only=isel < %s 2>/dev/null
+; REQUIRES: asserts
+
+; Make sure that this doesn't crash. Debug option enabled a failing assertion
+; about type mismatch in formal arguments.
+; CHECK: vaddub
+
+define i1 @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
+entry:
+ %0 = add <4 x i8> %a, %b
+ %1 = bitcast <4 x i8> %0 to <32 x i1>
+ %2 = extractelement <32 x i1> %1, i32 0
+ ret i1 %2
+}