0x20 (RW) : status register, bitwise OR
0x01 -- computing factorial (RO)
- 0x80 -- raise interrupt 0x01 after finishing factorial computation
+ 0x80 -- raise interrupt after finishing factorial computation
0x24 (RO) : interrupt status register
It contains values which raised the interrupt (see interrupt raise
appears in interrupt status register when the interrupt is raised and has to
be written to the interrupt acknowledge register to lower it.
+The device supports both INTx and MSI interrupt. By default, INTx is
+used. Even if the driver disabled INTx and only uses MSI, it still
+needs to update the acknowledge register at the end of the IRQ handler
+routine.
+
DMA controller
--------------
One has to specify, source, destination, size, and start the transfer. One
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
+#include "hw/pci/msi.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h" /* iothread mutex */
#include "qapi/visitor.h"
uint64_t dma_mask;
} EduState;
+static bool edu_msi_enabled(EduState *edu)
+{
+ return msi_enabled(&edu->pdev);
+}
+
static void edu_raise_irq(EduState *edu, uint32_t val)
{
edu->irq_status |= val;
if (edu->irq_status) {
- pci_set_irq(&edu->pdev, 1);
+ if (edu_msi_enabled(edu)) {
+ msi_notify(&edu->pdev, 0);
+ } else {
+ pci_set_irq(&edu->pdev, 1);
+ }
}
}
{
edu->irq_status &= ~val;
- if (!edu->irq_status) {
+ if (!edu->irq_status && !edu_msi_enabled(edu)) {
pci_set_irq(&edu->pdev, 0);
}
}
pci_config_set_interrupt_pin(pci_conf, 1);
+ if (msi_init(pdev, 0, 1, true, false, errp)) {
+ return;
+ }
+
memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
"edu-mmio", 1 << 20);
pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);