drm/amd/pm: correct the requirement for umc cdr workaround

The workaround can be applied only with UCLK DPM enabled.
And expand the workaround to more Navi10 SKUs and also
Navi14.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 5c6243d..64166b2 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2185,19 +2185,18 @@ static int navi10_run_btc(struct smu_context *smu)
        return ret;
 }
 
-static inline bool navi10_need_umc_cdr_12gbps_workaround(struct amdgpu_device *adev)
+static bool navi10_need_umc_cdr_12gbps_workaround(struct smu_context *smu)
 {
-       if (adev->asic_type != CHIP_NAVI10)
+       struct amdgpu_device *adev = smu->adev;
+
+       if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
                return false;
 
-       if (adev->pdev->device == 0x731f &&
-           (adev->pdev->revision == 0xc2 ||
-            adev->pdev->revision == 0xc3 ||
-            adev->pdev->revision == 0xca ||
-            adev->pdev->revision == 0xcb))
+       if (adev->asic_type == CHIP_NAVI10 ||
+           adev->asic_type == CHIP_NAVI14)
                return true;
-       else
-               return false;
+
+       return false;
 }
 
 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
@@ -2286,7 +2285,7 @@ static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
        uint32_t param;
        int ret = 0;
 
-       if (!navi10_need_umc_cdr_12gbps_workaround(adev))
+       if (!navi10_need_umc_cdr_12gbps_workaround(smu))
                return 0;
 
        ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);