jsr working

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index 8a6549c..b68bd23 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -84,6 +84,15 @@ end procedure;
         ----
     elsif sel = ALU_ADC then
         res := ('0' & d1) + ('0' & d2) + carry_in;
+        d_out <= res(dsize - 1 downto 0);
+        carry_out <= res(dsize);
+        if ((d1(dsize - 1) = d1(dsize - 1)) 
+                            and (d1(dsize - 1) /= res(dsize - 1))) then
+            overflow <= '1';
+        else
+            overflow <= '0';
+        end if;
+
     elsif sel = ALU_SBC then
         ----
     elsif sel = ALU_CMP then
@@ -102,6 +111,8 @@ end procedure;
         carry_out <= res(dsize);
     elsif sel = ALU_DEC then
         res := ('0' & d1) - "000000001";
+        d_out <= res(dsize - 1 downto 0);
+        carry_out <= res(dsize);
     end if;
     set_n(res(dsize - 1 downto 0));
     set_z(res(dsize - 1 downto 0));
@@ -125,6 +136,7 @@ entity alu is
             pcl_inc_n       : in std_logic;
             pch_inc_n       : in std_logic;
             sph_oe_n        : in std_logic;
+            sp_push_n       : in std_logic;
             abs_ea_n        : in std_logic;
             zp_ea_n         : in std_logic;
             arith_en_n      : in std_logic;
@@ -253,6 +265,12 @@ begin
         --stack operation...
         abl <= bal;
         abh <= "00000001";
+
+        if (sp_push_n = '0') then
+            sel <= ALU_DEC;
+            d1 <= bal;
+            pcl <= d_out;
+        end if;
     elsif (arith_en_n = '0') then
             --instruction is aaabbbcc format.
             if instruction (1 downto 0) = "01" then
@@ -284,10 +302,6 @@ begin
                     d_print("lsr");
                 elsif instruction (7 downto 5) = "011" then
                     d_print("ror");
-                elsif instruction (7 downto 5) = "100" then
-                    d_print("stx");
-                elsif instruction (7 downto 5) = "101" then
-                    d_print("ldx");
                 elsif instruction (7 downto 5) = "110" then
                     d_print("dec");
                 elsif instruction (7 downto 5) = "111" then
@@ -296,14 +310,6 @@ begin
             elsif instruction (1 downto 0) = "00" then
                 if instruction (7 downto 5) = "001" then
                     d_print("bit");
-                elsif instruction (7 downto 5) = "010" then
-                    d_print("jmp");
-                elsif instruction (7 downto 5) = "011" then
-                    d_print("jmp");
-                elsif instruction (7 downto 5) = "100" then
-                    d_print("sty");
-                elsif instruction (7 downto 5) = "101" then
-                    d_print("ldy");
                 elsif instruction (7 downto 5) = "110" then
                     d_print("cpy");
                 elsif instruction (7 downto 5) = "111" then

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 8dbfa1c..6011137 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -28,6 +28,7 @@ entity decoder is
             pch_cmd         : out std_logic_vector(3 downto 0);
             sp_cmd          : out std_logic_vector(3 downto 0);
             sph_oe_n        : out std_logic;
+            sp_push_n       : out std_logic;
             acc_cmd         : out std_logic_vector(3 downto 0);
             x_cmd           : out std_logic_vector(3 downto 0);
             y_cmd           : out std_logic_vector(3 downto 0);
@@ -177,6 +178,7 @@ begin
     pch_inc_n <= '1';
     sp_cmd <= "1111";
     sph_oe_n <= '1';
+    sp_push_n <= '1';
     acc_cmd <= "1111";
     x_cmd <= "1111";
     y_cmd <= "1111";
@@ -973,13 +975,14 @@ end  procedure;
                         dl_al_we_n <= '1';
 
                        --push return addr high into stack.
---                        sp_push_n <= '0';
+                        sp_push_n <= '0';
                         sph_oe_n <= '0';
                         front_oe(pch_cmd, '0');
                         back_oe(sp_cmd, '0');
+                        back_we(sp_cmd, '0');
                         r_nw <= '0';
---                        next_cycle <= T3;
---                    elsif exec_cycle = T3 then
+                        next_cycle <= T3;
+                    elsif exec_cycle = T3 then
 --                        d_print("jsr 4");
 --                        pch_d_oe_n <= '1';
 --
@@ -1141,6 +1144,7 @@ end  procedure;
                 pch_cmd <= "1111";
                 sp_cmd <= "1111";
                 sph_oe_n <= '1';
+                sp_push_n <= '1';
                 acc_cmd <= "1111";
                 x_cmd <= "1111";
                 y_cmd <= "1111";

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index 4c70245..146f928 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -49,6 +49,7 @@ component decoder
             pch_cmd         : out std_logic_vector(3 downto 0);
             sp_cmd          : out std_logic_vector(3 downto 0);
             sph_oe_n        : out std_logic;
+            sp_push_n       : out std_logic;
             acc_cmd         : out std_logic_vector(3 downto 0);
             x_cmd           : out std_logic_vector(3 downto 0);
             y_cmd           : out std_logic_vector(3 downto 0);
@@ -72,6 +73,7 @@ component alu
             pcl_inc_n       : in std_logic;
             pch_inc_n       : in std_logic;
             sph_oe_n        : in std_logic;
+            sp_push_n       : in std_logic;
             abs_ea_n        : in std_logic;
             zp_ea_n         : in std_logic;
             arith_en_n      : in std_logic;
@@ -232,6 +234,7 @@ end component;
     signal x_cmd : std_logic_vector(3 downto 0);
     signal y_cmd : std_logic_vector(3 downto 0);
     signal sph_oe_n : std_logic;
+    signal sp_push_n : std_logic;
 
     ---status register
     signal stat_dec_oe_n : std_logic;
@@ -319,6 +322,7 @@ begin
                     pch_cmd,
                     sp_cmd,
                     sph_oe_n,
+                    sp_push_n,
                     acc_cmd,
                     x_cmd,
                     y_cmd,
@@ -338,6 +342,7 @@ begin
                     pcl_inc_n,
                     pch_inc_n,
                     sph_oe_n,
+                    sp_push_n,
                     abs_ea_n,
                     zp_ea_n,
                     arith_en_n,