def : InstRW<[WriteI],
(instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
"AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
- "ADC?(W|X)r(i|r|s|x)", "ADCS?(W|X)r(i|r|s|x)",
+ "ADC(W|X)r",
"BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
"EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",
"ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)",
- "SUBS?(W|X)r(i|r|s|x)", "SBC?(W|X)r(i|r|s|x)",
- "SBCS?(W|X)r(i|r|s|x)", "CCMN?(W|X)r(i|r|s|x)",
- "CCMP?(W|X)r(i|r|s|x)", "CSEL?(W|X)r(i|r|s|x)",
- "CSINC?(W|X)r(i|r|s|x)", "CSINV?(W|X)r(i|r|s|x)",
- "CSNEG?(W|X)r(i|r|s|x)")>;
+ "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
+ "SBCS(W|X)r", "CCMN(W|X)(i|r)",
+ "CCMP(W|X)(i|r)", "CSEL(W|X)r",
+ "CSINC(W|X)r", "CSINV(W|X)r",
+ "CSNEG(W|X)r")>;
def : InstRW<[WriteI], (instrs COPY)>;
def : InstRW<[WriteISReg],
(instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
"AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
- "ADC?(W|X)r(i|r|s|x)", "ADCS?(W|X)r(i|r|s|x)",
+ "ADC(W|X)r",
"BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
"EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",
"ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)",
- "SUBS?(W|X)r(i|r|s|x)", "SBC?(W|X)r(i|r|s|x)",
- "SBCS?(W|X)r(i|r|s|x)", "CCMN?(W|X)r(i|r|s|x)",
- "CCMP?(W|X)r(i|r|s|x)", "CSEL?(W|X)r(i|r|s|x)",
- "CSINC?(W|X)r(i|r|s|x)", "CSINV?(W|X)r(i|r|s|x)",
- "CSNEG?(W|X)r(i|r|s|x)")>;
+ "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
+ "SBCS(W|X)r", "CCMN(W|X)(i|r)",
+ "CCMP(W|X)(i|r)", "CSEL(W|X)r",
+ "CSINC(W|X)r", "CSINV(W|X)r",
+ "CSNEG(W|X)r")>;
def : WriteRes<WriteIEReg, [THX2T99I012]> {
let Latency = 1;
def : InstRW<[WriteIEReg],
(instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",
"AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
- "ADC?(W|X)r(i|r|s|x)", "ADCS?(W|X)r(i|r|s|x)",
+ "ADC(W|X)r",
"BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",
"EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",
"ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)",
- "SUBS?(W|X)r(i|r|s|x)", "SBC?(W|X)r(i|r|s|x)",
- "SBCS?(W|X)r(i|r|s|x)", "CCMN?(W|X)r(i|r|s|x)",
- "CCMP?(W|X)r(i|r|s|x)", "CSEL?(W|X)r(i|r|s|x)",
- "CSINC?(W|X)r(i|r|s|x)", "CSINV?(W|X)r(i|r|s|x)",
- "CSNEG?(W|X)r(i|r|s|x)")>;
+ "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",
+ "SBCS(W|X)r", "CCMN(W|X)(i|r)",
+ "CCMP(W|X)(i|r)", "CSEL(W|X)r",
+ "CSINC(W|X)r", "CSINV(W|X)r",
+ "CSNEG(W|X)r")>;
// Move immed
def : WriteRes<WriteImm, [THX2T99I012]> {
def : InstRW<[THX2T99XWriteFSqrtSP], (instrs FSQRTSr)>;
def : InstRW<[THX2T99XWriteFDivSP], (instregex "^FDIVv.*32$")>;
def : InstRW<[THX2T99XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
-def : InstRW<[THX2T99Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSrr")>;
+def : InstRW<[THX2T99Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSr")>;
// FP divide, D-form
// FP square root, D-form
def : InstRW<[THX2T99XWriteFSqrtDP], (instrs FSQRTDr)>;
def : InstRW<[THX2T99XWriteFDivDP], (instregex "^FDIVv.*64$")>;
def : InstRW<[THX2T99XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
-def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDrr")>;
+def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
// FP multiply
// FP multiply accumulate
// ASIMD arith, reduce, 8B/8H
// ASIMD arith, reduce, 16B
-// ASIMD logical (MOV, MVN, ORN, ORR)
+// ASIMD logical (MVN (alias for NOT), ORN, ORR)
def : InstRW<[THX2T99Write_5Cyc_F01],
- (instregex "^ANDv", "^BICv", "^EORv", "^MOVv", "^MVNv",
- "^ORRv", "^ORNv", "^NOTv")>;
+ (instregex "^ANDv", "^BICv", "^EORv", "^ORRv", "^ORNv", "^NOTv")>;
+
// ASIMD arith, reduce
def : InstRW<[THX2T99Write_10Cyc_F01],
(instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>;
def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>;
// ASIMD move, integer immed
-def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv", "^MOVIDv")>;
+def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv")>;
// ASIMD move, FP immed
def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>;