v_sync_n : out std_logic;\r
r : out std_logic_vector(3 downto 0);\r
g : out std_logic_vector(3 downto 0);\r
- b : out std_logic_vector(3 downto 0);\r
-\r
- --SDRAM Signals\r
- dram_addr : out std_logic_vector (11 downto 0); --Address (12 bit)\r
- dram_bank : out std_logic_vector (1 downto 0); --Bank\r
- dram_cas_n : out std_logic; --Column Address is being transmitted\r
- dram_cke : out std_logic; --Clock Enable\r
- dram_clk : out std_logic; --Clock\r
- dram_cs_n : out std_logic; --Chip Select (Here - Mask commands)\r
- dram_dq : inout std_logic_vector (15 downto 0); --Data in / Data out\r
- dram_ldqm : out std_logic; --Byte masking\r
- dram_udqm : out std_logic; --Byte masking\r
- dram_ras_n : out std_logic; --Row Address is being transmitted\r
- dram_we_n : out std_logic --Write Enable\r
+ b : out std_logic_vector(3 downto 0)\r
\r
);\r
end qt_proj_test5;\r
\r
component vga_ctl\r
port ( ppu_clk : in std_logic;\r
- sdram_clk : in std_logic;\r
vga_clk : in std_logic;\r
rst_n : in std_logic;\r
pos_x : in std_logic_vector (8 downto 0);\r
v_sync_n : out std_logic;\r
r : out std_logic_vector(3 downto 0);\r
g : out std_logic_vector(3 downto 0);\r
- b : out std_logic_vector(3 downto 0);\r
- \r
- --SDRAM Signals\r
- wbs_adr_i : out std_logic_vector (21 downto 0); --Address (Bank, Row, Col)\r
- wbs_dat_i : out std_logic_vector (15 downto 0); --Data In (16 bits)\r
- wbs_we_i : out std_logic; --Write Enable\r
- wbs_tga_i : out std_logic_vector (7 downto 0); --Address Tag : Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
- wbs_cyc_i : out std_logic; --Cycle Command from interface\r
- wbs_stb_i : out std_logic; --Strobe Command from interface\r
- wbs_dat_o : in std_logic_vector (15 downto 0); --Data Out (16 bits)\r
- wbs_stall_o : in std_logic; --Slave is not ready to receive new data\r
- wbs_err_o : in std_logic; --Error flag: OOR Burst. Burst length is greater that 256-column address\r
- wbs_ack_o : in std_logic --When Read Burst: DATA bus must be valid in this cycle\r
+ b : out std_logic_vector(3 downto 0)\r
);\r
end component;\r
\r
-component sdram_controller\r
- generic\r
- (\r
- reset_polarity_g : std_logic := '0' --When rst = reset_polarity_g, system is in RESET mode\r
- );\r
- port (\r
- --Clocks and Reset \r
- clk_i : in std_logic; --Wishbone input clock\r
- rst : in std_logic; --Reset\r
- pll_locked : in std_logic; --PLL Locked indication, for CKE (Clock Enable) signal to SDRAM\r
- \r
- --SDRAM Signals\r
- dram_addr : out std_logic_vector (11 downto 0); --Address (12 bit)\r
- dram_bank : out std_logic_vector (1 downto 0); --Bank\r
- dram_cas_n : out std_logic; --Column Address is being transmitted\r
- dram_cke : out std_logic; --Clock Enable\r
- dram_cs_n : out std_logic; --Chip Select (Here - Mask commands)\r
- dram_dq : inout std_logic_vector (15 downto 0); --Data in / Data out\r
- dram_ldqm : out std_logic; --Byte masking\r
- dram_udqm : out std_logic; --Byte masking\r
- dram_ras_n : out std_logic; --Row Address is being transmitted\r
- dram_we_n : out std_logic; --Write Enable\r
- \r
- -- Wishbone Slave signals to Read/Write interface\r
- wbs_adr_i : in std_logic_vector (21 downto 0); --Address (Bank, Row, Col)\r
- wbs_dat_i : in std_logic_vector (15 downto 0); --Data In (16 bits)\r
- wbs_we_i : in std_logic; --Write Enable\r
- wbs_tga_i : in std_logic_vector (7 downto 0); --Address Tag : Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
- wbs_cyc_i : in std_logic; --Cycle Command from interface\r
- wbs_stb_i : in std_logic; --Strobe Command from interface\r
- wbs_dat_o : out std_logic_vector (15 downto 0); --Data Out (16 bits)\r
- wbs_stall_o : out std_logic; --Slave is not ready to receive new data\r
- wbs_err_o : out std_logic; --Error flag: OOR Burst. Burst length is greater that 256-column address\r
- wbs_ack_o : out std_logic; --When Read Burst: DATA bus must be valid in this cycle\r
- --When Write Burst: Data has been read from SDRAM and is valid\r
-\r
- --Debug signals\r
- cmd_ack : out std_logic; --Command has been acknowledged\r
- cmd_done : out std_logic; --Command has finished (read/write)\r
- init_st_o : out std_logic_vector (3 downto 0); --Current init state\r
- main_st_o : out std_logic_vector (3 downto 0) --Current main state\r
- ); \r
-end component;\r
-\r
constant data_size : integer := 8;\r
constant addr_size : integer := 16;\r
constant size14 : integer := 14;\r
signal vga_clk_pll, sdram_clk : std_logic;\r
signal pll_locked : std_logic;\r
\r
- -- Wishbone Slave signals to Read/Write interface\r
- signal wbs_adr_i : std_logic_vector (21 downto 0); --Address (Bank, Row, Col)\r
- signal wbs_dat_i : std_logic_vector (15 downto 0); --Data In (16 bits)\r
- signal wbs_we_i : std_logic; --Write Enable\r
- signal wbs_tga_i : std_logic_vector (7 downto 0); --Address Tag : Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
- signal wbs_cyc_i : std_logic; --Cycle Command from interface\r
- signal wbs_stb_i : std_logic; --Strobe Command from interface\r
- signal wbs_dat_o : std_logic_vector (15 downto 0); --Data Out (16 bits)\r
- signal wbs_stall_o : std_logic; --Slave is not ready to receive new data\r
- signal wbs_err_o : std_logic; --Error flag: OOR Burst. Burst length is greater that 256-column address\r
- signal wbs_ack_o : std_logic; --When Read Burst: DATA bus must be valid in this cycle\r
- --When Write Burst: Data has been read from SDRAM and is valid\r
-\r
- --Debug signals\r
- signal cmd_ack : std_logic; --Command has been acknowledged\r
- signal cmd_done : std_logic; --Command has finished (read/write)\r
- signal init_st_o : std_logic_vector (3 downto 0); --Current init state\r
- signal main_st_o : std_logic_vector (3 downto 0); --Current main state\r
-\r
begin\r
--ppu/cpu clock generator\r
clock_inst : clock_divider port map \r
\r
vga_ctl_inst : vga_ctl\r
port map ( ppu_clk ,\r
- sdram_clk,\r
--vga_clk_pll, \r
--ppu_clk ,\r
vga_clk ,\r
v_sync_n ,\r
r ,\r
g ,\r
- b ,\r
- \r
- --SDRAM Signals\r
- wbs_adr_i ,\r
- wbs_dat_i ,\r
- wbs_we_i ,\r
- wbs_tga_i ,\r
- wbs_cyc_i ,\r
- wbs_stb_i ,\r
- wbs_dat_o ,\r
- wbs_stall_o ,\r
- wbs_err_o ,\r
- wbs_ack_o \r
+ b \r
);\r
\r
- dram_clk <= sdram_clk;\r
-sdram_ctl_inst : sdram_controller\r
- port map (\r
- --Clocks and Reset \r
- sdram_clk, \r
- rst_n, \r
- pll_locked,\r
- \r
- --SDRAM Signals\r
- dram_addr ,\r
- dram_bank ,\r
- dram_cas_n ,\r
- dram_cke ,\r
- dram_cs_n ,\r
- dram_dq ,\r
- dram_ldqm ,\r
- dram_udqm ,\r
- dram_ras_n ,\r
- dram_we_n ,\r
\r
- -- Wishbone Slave signals to Read/Write interface\r
- wbs_adr_i ,\r
- wbs_dat_i ,\r
- wbs_we_i ,\r
- wbs_tga_i ,\r
- wbs_cyc_i ,\r
- wbs_stb_i ,\r
- wbs_dat_o ,\r
- wbs_stall_o ,\r
- wbs_err_o ,\r
- wbs_ack_o ,\r
-\r
- --Debug signals\r
- cmd_ack ,\r
- cmd_done ,\r
- init_st_o ,\r
- main_st_o \r
- ); \r
-\r
- \r
- -- signal addr : std_logic_vector( addr_size - 1 downto 0);\r
+-- signal addr : std_logic_vector( addr_size - 1 downto 0);\r
-- signal d_io : std_logic_vector( data_size - 1 downto 0);\r
--\r
--component counter_register\r
v_sync_n : out std_logic;
r : out std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0);
- b : out std_logic_vector(3 downto 0);
-
- --SDRAM Signals
- dram_addr : out std_logic_vector (11 downto 0); --Address (12 bit)
- dram_bank : out std_logic_vector (1 downto 0); --Bank
- dram_cas_n : out std_logic; --Column Address is being transmitted
- dram_cke : out std_logic; --Clock Enable
- dram_clk : out std_logic; --Clock
- dram_cs_n : out std_logic; --Chip Select (Here - Mask commands)
- dram_dq : inout std_logic_vector (15 downto 0); --Data in / Data out
- dram_ldqm : out std_logic; --Byte masking
- dram_udqm : out std_logic; --Byte masking
- dram_ras_n : out std_logic; --Row Address is being transmitted
- dram_we_n : out std_logic --Write Enable
+ b : out std_logic_vector(3 downto 0)
);
end component;
signal joypad1 : std_logic_vector(7 downto 0);
signal joypad2 : std_logic_vector(7 downto 0);
- signal dram_addr : std_logic_vector (11 downto 0); --Address (12 bit)
- signal dram_bank : std_logic_vector (1 downto 0); --Bank
- signal dram_cas_n : std_logic; --Column Address is being transmitted
- signal dram_cke : std_logic; --Clock Enable
- signal dram_clk : std_logic; --Clock
- signal dram_cs_n : std_logic; --Chip Select (Here - Mask commands)
- signal dram_dq : std_logic_vector (15 downto 0); --Data in / Data out
- signal dram_ldqm : std_logic; --Byte masking
- signal dram_udqm : std_logic; --Byte masking
- signal dram_ras_n : std_logic; --Row Address is being transmitted
- signal dram_we_n : std_logic; --Write Enable
-
constant powerup_time : time := 50 ns;
constant reset_time : time := 200 ns;
v_sync_n ,
r ,
g ,
- b ,
-
- dram_addr ,
- dram_bank ,
- dram_cas_n ,
- dram_cke ,
- dram_clk ,
- dram_cs_n ,
- dram_dq ,
- dram_ldqm ,
- dram_udqm ,
- dram_ras_n ,
- dram_we_n
+ b
);
-- dummy_vga_disp : vga_device
entity vga_ctl is
port ( ppu_clk : in std_logic;
- sdram_clk : in std_logic;\r
vga_clk : in std_logic;
rst_n : in std_logic;
pos_x : in std_logic_vector (8 downto 0);
v_sync_n : out std_logic;
r : out std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0);
- b : out std_logic_vector(3 downto 0);
-\r
- --SDRAM Signals\r
- wbs_adr_i : out std_logic_vector (21 downto 0); --Address (Bank, Row, Col)\r
- wbs_dat_i : out std_logic_vector (15 downto 0); --Data In (16 bits)\r
- wbs_we_i : out std_logic; --Write Enable\r
- wbs_tga_i : out std_logic_vector (7 downto 0); --Address Tag : Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
- wbs_cyc_i : out std_logic; --Cycle Command from interface\r
- wbs_stb_i : out std_logic; --Strobe Command from interface\r
- wbs_dat_o : in std_logic_vector (15 downto 0); --Data Out (16 bits)\r
- wbs_stall_o : in std_logic; --Slave is not ready to receive new data\r
- wbs_err_o : in std_logic; --Error flag: OOR Burst. Burst length is greater that 256-column address\r
- wbs_ack_o : in std_logic --When Read Burst: DATA bus must be valid in this cycle\r
+ b : out std_logic_vector(3 downto 0)
);
end vga_ctl;
signal nes_x_en_n : std_logic;\r
signal nes_x : std_logic_vector(7 downto 0);\r
\r
-signal dram_col_we_n : std_logic;\r
-signal dram_col : std_logic_vector(15 downto 0);\r
-\r
signal pos_x_we_n : std_logic;\r
signal pos_x_old : std_logic_vector(8 downto 0);\r
signal nes_x_we_n : std_logic;\r
signal nes_x_old : std_logic_vector(7 downto 0);\r
\r
-type sdram_write_status is (sw_idle, sw_write, sw_write_ack);\r
-type sdram_read_status is (sr_idle, sr_read_wait, sr_read, sr_read_ack);\r
-\r
-signal sw_state : sdram_write_status;\r
-signal sr_state : sdram_read_status;\r
-constant SDRAM_READ_WAIT_CNT : integer := 10;\r
-\r
-\r
---DE1 base clock 50 MHz\r
---motones sim project uses following clock.\r
--cpu clock = base clock / 24 = 2.08 MHz (480 ns / cycle)\r
port map (cnt_clk , x_res_n, '0', '1', (others => '0'), vga_x);
\r
pos_x_old_inst: d_flip_flop generic map (9)\r
- port map (sdram_clk, rst_n, '1', pos_x_we_n, pos_x, pos_x_old);\r
+ port map (vga_clk, rst_n, '1', pos_x_we_n, pos_x, pos_x_old);\r
\r
nes_x_old_inst: d_flip_flop generic map (8)\r
- port map (sdram_clk, rst_n, '1', nes_x_we_n, nes_x, nes_x_old);\r
+ port map (vga_clk, rst_n, '1', nes_x_we_n, nes_x, nes_x_old);\r
\r
y_inst : counter_register generic map (10, 1)
port map (cnt_clk , y_res_n, y_en_n, '1', (others => '0'), vga_y);
mem_cnt_inst : counter_register generic map (5, 1)\r
- port map (sdram_clk , x_res_n, '0', '1', (others => '0'), mem_cnt);\r
+ port map (vga_clk , x_res_n, '0', '1', (others => '0'), mem_cnt);\r
\r
count5_inst : counter_register generic map (3, 1)\r
port map (cnt_clk, count5_res_n, '0', '1', (others => '0'), count5);\r
nes_x_inst : counter_register generic map (8, 1)\r
port map (vga_clk, x_res_n, nes_x_en_n, '1', (others => '0'), nes_x);\r
\r
- col_inst : d_flip_flop generic map (16)\r
- port map (sdram_clk, rst_n, '1', dram_col_we_n, wbs_dat_o, dram_col);\r
+-- col_inst : d_flip_flop generic map (16)\r
+-- port map (vga_clk, rst_n, '1', dram_col_we_n, wbs_dat_o, dram_col);\r
\r
- dram_p : process (rst_n, sdram_clk)\r
-variable sr_read_ok : std_logic;\r
-variable wait_cnt : integer;\r
- begin\r
- if (rst_n = '0') then\r
- \r
- wbs_adr_i <= (others => '0');\r
- wbs_dat_i <= (others => '0');\r
- wbs_we_i <= '0';\r
- wbs_tga_i <= (others => '0');\r
- wbs_cyc_i <= '0';\r
- wbs_stb_i <= '0';\r
-\r
- sr_read_ok := '0';\r
- pos_x_we_n <= '1';\r
- nes_x_we_n <= '1';\r
- sw_state <= sw_idle;\r
- sr_state <= sr_idle;\r
- wait_cnt := SDRAM_READ_WAIT_CNT;\r
- \r
- elsif (rising_edge(sdram_clk)) then\r
- \r
- --write to sdram\r
- case sw_state is\r
- when sw_idle =>\r
- if (pos_x < conv_std_logic_vector(NES_W, 9) and \r
- pos_y < conv_std_logic_vector(NES_H, 9) and \r
- pos_x /= pos_x_old and sr_state = sr_idle) then\r
- --if (mem_cnt = conv_std_logic_vector(1, 5)) then\r
- sw_state <= sw_write;\r
- sr_read_ok := '0';\r
- pos_x_we_n <= '0';\r
-\r
- wbs_adr_i <= "000000" & pos_x(7 downto 0) & pos_y(7 downto 0);\r
- wbs_dat_i <= "0000" & nes_r & nes_g & nes_b;\r
- --wbs_dat_i <= (others => '1');\r
- end if;\r
-\r
- when sw_write =>\r
- pos_x_we_n <= '1';\r
- sw_state <= sw_write_ack;\r
-\r
- wbs_we_i <= '1';\r
- wbs_cyc_i <= '1';\r
- wbs_stb_i <= '1';\r
- wbs_tga_i <= conv_std_logic_vector(0, 8);\r
- when sw_write_ack =>\r
- sw_state <= sw_idle;\r
- sr_read_ok := '1';\r
- wait_cnt := SDRAM_READ_WAIT_CNT;\r
- end case;\r
- \r
--- --write to sdram\r
--- if (mem_cnt = conv_std_logic_vector(2, 4)) then\r
--- wbs_adr_i <= "000000" & pos_x(7 downto 0) & pos_y(7 downto 0);\r
--- wbs_dat_i <= "0000" & nes_r & nes_g & nes_b;\r
--- elsif (mem_cnt = conv_std_logic_vector(3, 4)) then\r
--- wbs_we_i <= '1';\r
--- wbs_cyc_i <= '1';\r
--- wbs_stb_i <= '1';\r
--- wbs_tga_i <= conv_std_logic_vector(0, 8);\r
---\r
--- elsif (mem_cnt = conv_std_logic_vector(4, 4)) then\r
--- --wbs_adr_i <= "0000" & pos_x & pos_y;\r
--- --wbs_dat_i <= "0000" & nes_r & nes_g & nes_b;\r
--- --wbs_dat_i <= "0000101000001111";\r
--- end if;\r
-\r
- --read from sdram\r
- if (vga_x <=conv_std_logic_vector(VGA_W , 10) \r
- and vga_y <=conv_std_logic_vector(VGA_H, 10)) then\r
-\r
- --read from sdram\r
- case sr_state is\r
- when sr_idle =>\r
- if (nes_x /= nes_x_old and sr_read_ok = '1') then\r
- --if (mem_cnt = conv_std_logic_vector(5, 5)) then\r
- if (wait_cnt = 0) then\r
- sr_state <= sr_read;\r
- else\r
- sr_state <= sr_read_wait;\r
- end if;\r
- wbs_adr_i <= "000000" & nes_x & vga_y(8 downto 1);\r
- wbs_cyc_i <= '0';\r
- wbs_stb_i <= '0';\r
- nes_x_we_n <= '0';\r
- end if;\r
- dram_col_we_n <= '1';\r
- when sr_read_wait =>\r
- wait_cnt := wait_cnt - 1;\r
- if (wait_cnt = 0) then\r
- sr_state <= sr_read;\r
- end if;\r
- when sr_read =>\r
- wbs_we_i <= '0';\r
- wbs_cyc_i <= '1';\r
- wbs_stb_i <= '1';\r
- wbs_tga_i <= conv_std_logic_vector(0, 8);\r
- nes_x_we_n <= '1';\r
- sr_state <= sr_read_ack;\r
- when sr_read_ack =>\r
- dram_col_we_n <= '0';\r
- sr_state <= sr_idle;\r
- end case;\r
- \r
--- if (mem_cnt > conv_std_logic_vector(4, 4) and \r
--- mem_cnt <= conv_std_logic_vector(15, 4)) then\r
--- --read wait cycle\r
--- wbs_adr_i <= "000000" & nes_x & vga_y(8 downto 1);\r
--- wbs_cyc_i <= '0';\r
--- wbs_stb_i <= '0';\r
--- elsif (mem_cnt <= conv_std_logic_vector(0, 4)) then\r
--- --read\r
--- wbs_we_i <= '0';\r
--- wbs_cyc_i <= '1';\r
--- wbs_stb_i <= '1';\r
--- wbs_tga_i <= conv_std_logic_vector(0, 8);\r
--- end if;\r
- else\r
- sr_state <= sr_idle;\r
- end if;\r
-\r
--- if (mem_cnt = conv_std_logic_vector(1, 4)) then\r
--- dram_col_we_n <= '0';\r
--- else\r
--- dram_col_we_n <= '1';\r
--- end if;\r
- \r
- end if;\r
- end process;\r
-\r
- dram_latch_p : process (rst_n, vga_clk)\r
- begin\r
- if (rst_n = '0') then\r
- nes_x_en_n <= '1';\r
- \r
- elsif (falling_edge(vga_clk)) then\r
-\r
- if (count5 = "001" or count5 = "011") then\r
- nes_x_en_n <= '0';\r
- else\r
- nes_x_en_n <= '1';\r
- end if;\r
- end if;\r
- end process;\r
-\r
vga_out_p : process (rst_n, vga_clk)
begin
if (rst_n = '0') then
if (vga_y <=conv_std_logic_vector((VGA_H) , 10)) then
if (vga_x < conv_std_logic_vector((VGA_W) , 10)) then
- r<= dram_col(11 downto 8);
- g<= dram_col(7 downto 4);
- b<= dram_col(3 downto 0);\r
+-- r<= dram_col(11 downto 8);
+-- g<= dram_col(7 downto 4);
+-- b<= dram_col(3 downto 0);\r
else
r<=(others => '0');
g<=(others => '0');
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