2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/sib.s: Add more eiz tests.
* gas/i386/x86-64-sib.s: Add more riz tests.
* gas/i386/sib-intel.d: Updated.
* gas/i386/sib.d: Likewise.
* gas/i386/x86-64-sib-intel.d: Likewise.
* gas/i386/x86-64-sib.d: Likewise.
opcodes/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_extended): Display eiz for [eiz*1 + offset].
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
+ * i386-dis.c (OP_E_extended): Display eiz for [eiz*1 + offset].
+
+2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
+
PR 658
* 386-dis.c (index64): New.
(index32): Likewise.
int havesib;
int havebase;
int haveindex;
+ int needindex;
int base;
int index = 0;
int scale = 0;
break;
}
- havedisp = havebase || (havesib && (haveindex || scale != 0));
+ /* In 32bit mode, we need index register to tell [offset] from
+ [eiz*1 + offset]. */
+ needindex = (havesib
+ && !havebase
+ && !haveindex
+ && address_mode == mode_32bit);
+ havedisp = (havebase
+ || needindex
+ || (havesib && (haveindex || scale != 0)));
if (!intel_syntax)
if (modrm.mod != 0 || (base & 7) == 5)
/* ESP/RSP won't allow index. If base isn't ESP/RSP,
print index to tell base + index from base. */
if (scale != 0
+ || needindex
|| haveindex
|| (havebase && base != ESP_REG_NUM))
{