drm/amdgpu: enable VCE clockgating in Polaris-10/11

VCE clocks are set to be disabled, when not in use.

Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 39f03f1..6b3293a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -134,7 +134,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
           accessible but the firmware will throttle the clocks on the
           fly as necessary.
        */
-       if (gated) {
+       if (!gated) {
                data = RREG32(mmVCE_CLOCK_GATING_B);
                data |= 0x1ff;
                data &= ~0xef0000;

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 243dcf7..9f771f4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -937,12 +937,14 @@ static int vi_common_early_init(void *handle)
                adev->external_rev_id = adev->rev_id + 0x14;
                break;
        case CHIP_POLARIS11:
-               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
+               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
+                       AMD_CG_SUPPORT_VCE_MGCG;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x5A;
                break;
        case CHIP_POLARIS10:
-               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
+               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
+                       AMD_CG_SUPPORT_VCE_MGCG;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x50;
                break;