drm/amd/display: Fix LB BPP and Cursor width

DCN2.0 LB BPP should be 48 or 16BPC and max cursor width should be 256.

Also use populate_dml_pipes as functions pointer instead of using it directly

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 0bd0b52..9243f27 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1720,10 +1720,10 @@ int dcn20_populate_dml_pipes_from_context(
                 * bw calculations due to cursor on/off
                 */
                pipes[pipe_cnt].pipe.src.num_cursors = 2;
-               pipes[pipe_cnt].pipe.src.cur0_src_width = 128;
-               pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_64bit;
-               pipes[pipe_cnt].pipe.src.cur1_src_width = 128;
-               pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_64bit;
+               pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
+               pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
+               pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
+               pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
 
                if (!res_ctx->pipe_ctx[i].plane_state) {
                        pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
@@ -1800,7 +1800,7 @@ int dcn20_populate_dml_pipes_from_context(
                                                res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
                        }
 
-                       pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_10;
+                       pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
                        pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
                        pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
                        pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
@@ -2022,7 +2022,12 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
                        resource_build_scaling_params(pipe);
        }
 
-       pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, &context->res_ctx, pipes);
+       if (dc->res_pool->funcs->populate_dml_pipes)
+               pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+                       &context->res_ctx, pipes);
+       else
+               pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+                       &context->res_ctx, pipes);
 
        if (!pipe_cnt) {
                BW_VAL_TRACE_SKIP(pass);
@@ -2223,8 +2228,14 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
                pipe_cnt++;
        }
 
-       if (pipe_cnt != pipe_idx)
-               pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, &context->res_ctx, pipes);
+       if (pipe_cnt != pipe_idx) {
+               if (dc->res_pool->funcs->populate_dml_pipes)
+                       pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+                               &context->res_ctx, pipes);
+               else
+                       pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+                               &context->res_ctx, pipes);
+       }
 
        pipes[0].clks_cfg.voltage = vlevel;
        pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index 2a65af3..0c2fab1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -86,7 +86,8 @@ enum dm_swizzle_mode {
        dm_sw_gfx7_2d_thin_gl
 };
 enum lb_depth {
-       dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16
+       dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
+       dm_lb_19 = 5
 };
 enum voltage_state {
        dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 7f3ea74..4df885d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -510,6 +510,9 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
                        case dm_lb_16:
                                lb_depth = 48;
                                break;
+                       case dm_lb_19:
+                               lb_depth = 57;
+                               break;
                        default:
                                lb_depth = 36;
                        }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 61c04bd..acb3104 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -103,6 +103,11 @@ struct resource_funcs {
                                        struct dc_state *context,
                                        bool fast_validate);
 
+       int (*populate_dml_pipes)(
+               struct dc *dc,
+               struct resource_context *res_ctx,
+               display_e2e_pipe_params_st *pipes);
+
        enum dc_status (*validate_global)(
                struct dc *dc,
                struct dc_state *context);