OSDN Git Service

dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle
authorEnric Balletbo i Serra <enric.balletbo@collabora.com>
Thu, 9 Jul 2020 09:05:29 +0000 (11:05 +0200)
committerChanwoo Choi <cw00.choi@samsung.com>
Thu, 30 Jul 2020 08:22:57 +0000 (17:22 +0900)
The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU
general register files to know the DRAM type, so add a phandle to the
syscon that manages these registers.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gaƫl PORTAY <gael.portay@collabora.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

index 0ec6814..a10d1f6 100644 (file)
@@ -18,6 +18,8 @@ Optional properties:
                         format depends on the interrupt controller.
                         It should be a DCF interrupt. When DDR DVFS finishes
                         a DCF interrupt is triggered.
+- rockchip,pmu:                 Phandle to the syscon managing the "PMU general register
+                        files".
 
 Following properties relate to DDR timing: