[ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D89939

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 0632e1b..817bc33 100644 (file)
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -626,13 +626,6 @@ bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,
   return (isSub && Offset.getReg() != 0);
 }
 
-bool ARMBaseInstrInfo::isLdstScaledReg(const MachineInstr &MI,
-                                       unsigned Op) const {
-  const MachineOperand &Opc = MI.getOperand(Op + 2);
-  unsigned OffImm = Opc.getImm();
-  return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
-}
-
 // Load, scaled register offset, not plus LSL2
 bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
                                                   unsigned Op) const {

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index f894a85..a03d57c 100644 (file)
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -180,8 +180,6 @@ public:
   static bool isCPSRDefined(const MachineInstr &MI);
   bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
 
-  // Load, scaled register offset
-  bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
   // Load, scaled register offset, not plus LSL2
   bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
   // Minus reg for ldstso addr mode

diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td
index 8cdf12a..23cbf6b 100644 (file)
--- a/llvm/lib/Target/ARM/ARMSchedule.td
+++ b/llvm/lib/Target/ARM/ARMSchedule.td
@@ -164,6 +164,10 @@ def IsCPSRDefined : CheckFunctionPredicateWithTII<
 
 def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>;
 
+let FunctionMapper = "ARM_AM::getAM2ShiftOpc" in {
+  def CheckExtNoShift : CheckImmOperand_s<4, "ARM_AM::no_shift">;
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //

diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index 1a9de1d..99a3105 100644 (file)
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -49,11 +49,7 @@ def IsLdstsoScaledNotOptimalPred :
 def IsLdstsoScaledNotOptimalPredX2 :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}]>;
 
-// Load, scaled register offset
-def IsLdstsoScaledPred :
-  SchedPredicate<[{TII->isLdstScaledReg(*MI, 1)}]>;
-def IsLdstsoScaledPredX2 :
-  SchedPredicate<[{TII->isLdstScaledReg(*MI, 2)}]>;
+def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>;
 
 def IsLdstsoMinusRegPredX0 :
   SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 0)}]>;

diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 293c2d6..774f250 100644 (file)
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARMMCTargetDesc.h"
+#include "ARMAddressingModes.h"
 #include "ARMBaseInfo.h"
 #include "ARMInstPrinter.h"
 #include "ARMMCAsmInfo.h"

diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
index 1def95e..d1e0880 100644 (file)
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
@@ -261,7 +261,7 @@
 # CHECK-NEXT:  1      1     1.00           *            str    r9, [r6, r3]
 # CHECK-NEXT:  1      1     1.00           *            str    r8, [r0, -r2]
 # CHECK-NEXT:  2      1     1.00           *            str    r7, [r1, r6]!
-# CHECK-NEXT:  2      1     1.00           *            str    r7, [r1, r6, lsl #2]!
+# CHECK-NEXT:  2      2     1.00           *            str    r7, [r1, r6, lsl #2]!
 # CHECK-NEXT:  2      1     1.00           *            str    r6, [sp, -r1]!
 # CHECK-NEXT:  2      2     1.00           *            str    r5, [r3], r9
 # CHECK-NEXT:  2      2     1.00           *            str    r4, [r2], -r5
@@ -321,7 +321,7 @@
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT:  -     44.50  44.50  284.00 8.00   55.00   -      -
+# CHECK-NEXT:  -     44.00  44.00  284.00 9.00   55.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
@@ -426,7 +426,7 @@
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str      r9, [r6, r3]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str      r8, [r0, -r2]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str      r7, [r1, r6]!
-# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str      r7, [r1, r6, lsl #2]!
+# CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     str      r7, [r1, r6, lsl #2]!
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str      r6, [sp, -r1]!
 # CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     str      r5, [r3], r9
 # CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     str      r4, [r2], -r5