Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom

part was always forced to be sextload, even when we needed an zextload.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30782 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index fc14b06..71f1c24 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4474,13 +4474,12 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     SDOperand Chain = Node->getOperand(0);
     SDOperand Ptr   = Node->getOperand(1);
     MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
-    unsigned LType = Node->getConstantOperandVal(4);
+    ISD::LoadExtType LType = (ISD::LoadExtType)Node->getConstantOperandVal(4);
     
     if (EVT == NVT)
       Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
     else
-      Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
-                          EVT);
+      Lo = DAG.getExtLoad(LType, NVT, Chain, Ptr, Node->getOperand(2), EVT);
     
     // Remember that we legalized the chain.
     AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));