static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size)
{
-#if HOST_BIG_ENDIAN != defined(TARGET_WORDS_BIGENDIAN)
+#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
/* The kernel expects ioeventfd values in HOST_BIG_ENDIAN
* endianness, but the memory core hands them in target endianness.
* For example, PPC is always treated as big-endian even if running
static inline uint64_t target_arg64(uint32_t word0, uint32_t word1)
{
#if TARGET_ABI_BITS == 32
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
return ((uint64_t)word0 << 32) | word1;
#else
return ((uint64_t)word1 << 32) | word0;
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
TARGET_HAS_BFLT=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
TARGET_ARCH=arm
TARGET_SYSTBL_ABI=common,oabi
TARGET_SYSTBL=syscall.tbl
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
TARGET_HAS_BFLT=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
TARGET_SYSTBL_ABI=common,32
TARGET_SYSTBL=syscall.tbl
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_ARCH=hppa
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
TARGET_ARCH=m68k
TARGET_SYSTBL_ABI=common
TARGET_SYSTBL=syscall.tbl
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_XML_FILES= gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-core.xml gdb-xml/m68k-fp.xml
TARGET_HAS_BFLT=y
TARGET_ARCH=m68k
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_XML_FILES= gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-core.xml gdb-xml/m68k-fp.xml
TARGET_ARCH=microblaze
TARGET_SYSTBL_ABI=common
TARGET_SYSTBL=syscall.tbl
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_HAS_BFLT=y
TARGET_ARCH=microblaze
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
TARGET_NEED_FDT=y
TARGET_SYSTBL_ABI=o32
TARGET_SYSTBL=syscall_o32.tbl
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_ARCH=mips
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
TARGET_SYSTBL_ABI=n64
TARGET_SYSTBL=syscall_n64.tbl
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_ARCH=mips64
TARGET_BASE_ARCH=mips
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SYSTBL_ABI=n32
TARGET_SYSTBL=syscall_n32.tbl
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_ARCH=openrisc
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_ARCH=openrisc
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_NEED_FDT=y
TARGET_ARCH=ppc
TARGET_SYSTBL_ABI=common,nospu,32
TARGET_SYSTBL=syscall.tbl
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_XML_FILES= gdb-xml/power-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml
TARGET_ARCH=ppc
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_XML_FILES= gdb-xml/power-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml
TARGET_NEED_FDT=y
TARGET_ABI_DIR=ppc
TARGET_SYSTBL_ABI=common,nospu,64
TARGET_SYSTBL=syscall.tbl
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml
TARGET_NEED_FDT=y
TARGET_ARCH=s390x
TARGET_SYSTBL_ABI=common,64
TARGET_SYSTBL=syscall.tbl
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-gs.xml
TARGET_ARCH=s390x
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-gs.xml
TARGET_SYSTBL_ABI=common
TARGET_SYSTBL=syscall.tbl
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_HAS_BFLT=y
TARGET_ARCH=sh4
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SYSTBL_ABI=common,32
TARGET_SYSTBL=syscall.tbl
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_ARCH=sparc
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SYSTBL_ABI=common,32
TARGET_SYSTBL=syscall.tbl
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SYSTBL_ABI=common,64
TARGET_SYSTBL=syscall.tbl
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_ARCH=sparc64
TARGET_BASE_ARCH=sparc
TARGET_ALIGNED_ONLY=y
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_ARCH=xtensa
TARGET_SYSTBL_ABI=common
TARGET_SYSTBL=syscall.tbl
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_HAS_BFLT=y
TARGET_ARCH=xtensa
-TARGET_WORDS_BIGENDIAN=y
+TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y
bool target_words_bigendian(void)
{
-#if defined(TARGET_WORDS_BIGENDIAN)
+#if TARGET_BIG_ENDIAN
return true;
#else
return false;
s->cpu = cpu;
s->info.read_memory_func = target_read_memory;
s->info.print_address_func = print_address;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->info.endian = BFD_ENDIAN_BIG;
#else
s->info.endian = BFD_ENDIAN_LITTLE;
There is a set of functions ending in ``_swap`` which, if the parameter
is true, returns the value in the endianness that is the reverse of
-the guest native endianness, as determined by ``TARGET_WORDS_BIGENDIAN``.
+the guest native endianness, as determined by ``TARGET_BIG_ENDIAN``.
Function names follow the pattern:
int asidx;
CPUState *cs = CPU(cpu);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
* into a device attribute set by the machine/platform to remove
* all target endian dependencies from this file.
*/
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->default_endian_fb = true;
#else
s->default_endian_fb = false;
uint32_t base32;
int big_endian = 0;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#endif
/* FIXME: Malta specific hw assumptions ahead */
/* CPU Configuration */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->regs[GT_CPU] = 0x00000000;
#else
s->regs[GT_CPU] = 0x00001000;
s->regs[GT_TC_CONTROL] = 0x00000000;
/* PCI Internal */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->regs[GT_PCI0_CMD] = 0x00000000;
#else
s->regs[GT_PCI0_CMD] = 0x00010001;
s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->regs[GT_PCI1_CMD] = 0x00000000;
#else
s->regs[GT_PCI1_CMD] = 0x00010001;
[JAZZ_PICA61] = {33333333, 4},
};
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
/* STATUS Register */
case 0x00208:
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
val = 0x00000012;
#else
val = 0x00000010;
stw_p(p++, 0xe040); stw_p(p++, 0x0681);
/* lui t1, %hi(0xb4000000) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
/* lui t0, %hi(0xdf000000) */
/* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */
#else
stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */
stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */
#else
stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
#endif
stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */
#else
stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */
#endif
stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */
#else
stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */
#endif
stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */
#else
stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */
#endif
stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */
#else
stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
#endif
stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */
#else
stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */
int prom_index = 0;
uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
ram_low_postio);
}
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
be = 1;
#else
be = 0;
* In little endian mode the 32bit words in the bios are swapped,
* a neat trick which allows bi-endian firmware.
*/
-#ifndef TARGET_WORDS_BIGENDIAN
+#if !TARGET_BIG_ENDIAN
{
uint32_t *end, *addr;
const size_t swapsize = MIN(bios_size, 0x3e0000);
ram_addr_t initrd_offset;
int big_endian;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
uint64_t entry, high;
int big_endian = 0;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#endif
void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine)
{
const char *kernel_filename = machine->kernel_filename;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
int big_endian = true;
#else
int big_endian = false;
static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
{
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
int be = 1;
#else
int be = 0;
}
if (entry_point != env->pc) {
uint8_t boot[] = {
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
0x60, 0x00, 0x08, /* j 1f */
0x00, /* .literal_position */
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
* HOST_BIG_ENDIAN : whether the host cpu is big endian and
* otherwise little endian.
*
- * TARGET_WORDS_BIGENDIAN : if defined, the host cpu is big endian and otherwise
- * little endian.
+ * TARGET_BIG_ENDIAN : same for the target cpu
*/
-#if HOST_BIG_ENDIAN != defined(TARGET_WORDS_BIGENDIAN)
+#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
#define BSWAP_NEEDED
#endif
/* Target-endianness CPU memory access functions. These fit into the
* {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
*/
-#if defined(TARGET_WORDS_BIGENDIAN)
+#if TARGET_BIG_ENDIAN
#define lduw_p(p) lduw_be_p(p)
#define ldsw_p(p) ldsw_be_p(p)
#define ldl_p(p) ldl_be_p(p)
#endif /* defined(CONFIG_USER_ONLY) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
# define cpu_lduw_data cpu_lduw_be_data
# define cpu_ldsw_data cpu_ldsw_be_data
# define cpu_ldl_data cpu_ldl_be_data
uint64_t val_lo)
{
uint64_t to_quad;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
to_quad = tswap64(val_hi);
g_byte_array_append(buf, (uint8_t *) &to_quad, 8);
to_quad = tswap64(val_lo);
MO_BE = MO_BSWAP,
#endif
#ifdef NEED_CPU_H
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
MO_TE = MO_BE,
#else
MO_TE = MO_LE,
QEMU_BUILD_BUG_ON(DEVICE_HOST_ENDIAN != DEVICE_LITTLE_ENDIAN &&
DEVICE_HOST_ENDIAN != DEVICE_BIG_ENDIAN);
-#if HOST_BIG_ENDIAN != defined(TARGET_WORDS_BIGENDIAN)
+#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
/* Swap if non-host endianness or native (target) endianness */
return (end == DEVICE_HOST_ENDIAN) ? 0 : MO_BSWAP;
#else
#pragma GCC poison TARGET_HAS_BFLT
#pragma GCC poison TARGET_NAME
#pragma GCC poison TARGET_SUPPORTS_MTTCG
-#pragma GCC poison TARGET_WORDS_BIGENDIAN
+#pragma GCC poison TARGET_BIG_ENDIAN
#pragma GCC poison BSWAP_NEEDED
#pragma GCC poison TARGET_LONG_BITS
* target_words_bigendian:
* Returns true if the (default) endianness of the target is big endian,
* false otherwise. Note that in target-specific code, you can use
- * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common
+ * TARGET_BIG_ENDIAN directly instead. On the other hand, common
* code should normally never need to know about the endianness of the
* target, so please do *not* use this function unless you know very well
* what you are doing!
#include "cpu.h"
#define BIOS_SIZE (4 * MiB)
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
#define BIOS_FILENAME "mips_bios.bin"
#else
#define BIOS_FILENAME "mipsel_bios.bin"
{
#if defined(LEGACY_VIRTIO_IS_BIENDIAN)
return virtio_is_big_endian(vdev);
-#elif defined(TARGET_WORDS_BIGENDIAN)
+#elif TARGET_BIG_ENDIAN
if (virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
/* Devices conforming to VIRTIO 1.0 or later are always LE. */
return false;
}
env->pc = regs->pc;
env->xregs[31] = regs->sp;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
env->cp15.sctlr_el[1] |= SCTLR_E0E;
for (i = 1; i < 4; ++i) {
env->cp15.sctlr_el[i] |= SCTLR_EE;
for (i = 0; i < 32; i++) {
uint64_t *q = aa64_vfp_qreg(env, i);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
__put_user(q[0], &fpsimd->vregs[i * 2 + 1]);
__put_user(q[1], &fpsimd->vregs[i * 2]);
#else
for (i = 0; i < 32; i++) {
uint64_t *q = aa64_vfp_qreg(env, i);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
__get_user(q[0], &fpsimd->vregs[i * 2 + 1]);
__get_user(q[1], &fpsimd->vregs[i * 2]);
#else
uint64_t pstate;
};
-#if defined(TARGET_WORDS_BIGENDIAN)
+#if TARGET_BIG_ENDIAN
#define UNAME_MACHINE "aarch64_be"
#else
#define UNAME_MACHINE "aarch64"
for(i = 0; i < 16; i++) {
env->regs[i] = regs->uregs[i];
}
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
/* Enable BE8. */
if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
&& (info->elf_flags & EF_ARM_BE8)) {
#define ARM_NR_set_tls (ARM_NR_BASE + 5)
#define ARM_NR_get_tls (ARM_NR_BASE + 6)
-#if defined(TARGET_WORDS_BIGENDIAN)
+#if TARGET_BIG_ENDIAN
#define UNAME_MACHINE "armv5teb"
#else
#define UNAME_MACHINE "armv5tel"
#define ELIBBAD 80
#endif
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
#define ELF_DATA ELFDATA2MSB
#else
#define ELF_DATA ELFDATA2LSB
{
CPUARMState *env = thread_cpu->env_ptr;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
# define END "b"
#else
# define END "l"
#define ELF_ARCH EM_AARCH64
#define ELF_CLASS ELFCLASS64
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
# define ELF_PLATFORM "aarch64_be"
#else
# define ELF_PLATFORM "aarch64"
return (oldsp - frame_size) & ~0xFUL;
}
-#if defined(TARGET_WORDS_BIGENDIAN) == HOST_BIG_ENDIAN
+#if TARGET_BIG_ENDIAN == HOST_BIG_ENDIAN
#define PPC_VEC_HI 0
#define PPC_VEC_LO 1
#else
env->nip = (target_ulong) ka->_sa_handler;
#endif
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
/* Signal handlers are entered in big-endian mode. */
ppc_store_msr(env, env->msr & ~(1ull << MSR_LE));
#else
*/
#if defined(TARGET_PPC64)
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
#define UNAME_MACHINE "ppc64"
#else
#define UNAME_MACHINE "ppc64le"
} while (0)
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
# define __put_user(x, hptr) __put_user_e(x, hptr, be)
# define __get_user(x, hptr) __get_user_e(x, hptr, be)
#else
return 0;
}
-#if HOST_BIG_ENDIAN != defined(TARGET_WORDS_BIGENDIAN) || \
+#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
static int is_proc(const char *filename, const char *entry)
{
}
#endif
-#if HOST_BIG_ENDIAN != defined(TARGET_WORDS_BIGENDIAN)
+#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
static int open_net_route(void *cpu_env, int fd)
{
FILE *fp;
{ "stat", open_self_stat, is_proc_myself },
{ "auxv", open_self_auxv, is_proc_myself },
{ "cmdline", open_self_cmdline, is_proc_myself },
-#if HOST_BIG_ENDIAN != defined(TARGET_WORDS_BIGENDIAN)
+#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
{ "/proc/net/route", open_net_route, is_proc },
#endif
#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
/* in theory, endianness is configurable on some ARM CPUs, but this isn't
* used in user mode emulation */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
#define utsname_suffix "b"
#else
#define utsname_suffix "l"
#if (TARGET_ABI_BITS == 32) && !defined(TARGET_ABI_MIPSN32)
static inline uint64_t target_offset64(uint32_t word0, uint32_t word1)
{
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
return ((uint64_t)word0 << 32) | word1;
#else
return ((uint64_t)word1 << 32) | word0;
static void install_sigtramp(uint8_t *tramp)
{
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
/* Generate instruction: MOVI a2, __NR_rt_sigreturn */
__put_user(0x22, &tramp[0]);
__put_user(0x0a, &tramp[1]);
struct target_semid64_ds {
struct target_ipc_perm sem_perm;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
abi_ulong __unused1;
abi_ulong sem_otime;
abi_ulong __unused2;
if 'TARGET_ABI_DIR' not in config_target
config_target += {'TARGET_ABI_DIR': config_target['TARGET_ARCH']}
endif
+ if 'TARGET_BIG_ENDIAN' not in config_target
+ config_target += {'TARGET_BIG_ENDIAN': 'n'}
+ endif
foreach k, v: disassemblers
if host_arch.startswith(k) or config_target['TARGET_BASE_ARCH'].startswith(k)
config_target_data.set_quoted(k, v)
elif v == 'y'
config_target_data.set(k, 1)
+ elif v == 'n'
+ config_target_data.set(k, 0)
else
config_target_data.set(k, v)
endif
static bool memory_region_big_endian(MemoryRegion *mr)
{
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
#else
return mr->ops->endianness == DEVICE_BIG_ENDIAN;
qtest_send(chr, "OK\n");
} else if (strcmp(words[0], "endianness") == 0) {
qtest_send_prefix(chr);
-#if defined(TARGET_WORDS_BIGENDIAN)
+#if TARGET_BIG_ENDIAN
qtest_sendf(chr, "OK big\n");
#else
qtest_sendf(chr, "OK little\n");
sctlr_b = arm_sctlr_b(env);
if (bswap_code(sctlr_b)) {
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
info->endian = BFD_ENDIAN_LITTLE;
#else
info->endian = BFD_ENDIAN_BIG;
static inline bool bswap_code(bool sctlr_b)
{
#ifdef CONFIG_USER_ONLY
- /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
- * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
+ /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.
+ * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0
* would also end up as a mixed-endian mode with BE code, LE data.
*/
return
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
1 ^
#endif
sctlr_b;
static inline bool arm_cpu_bswap_data(CPUARMState *env)
{
return
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
1 ^
#endif
arm_cpu_data_is_big_endian(env);
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
env->CP0_Config0 = env->cpu_model->CP0_Config0;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
env->CP0_Config0 |= (1 << CP0C0_BE);
#endif
env->CP0_Config1 = env->cpu_model->CP0_Config1;
CPUMIPSState *env = &cpu->env;
if (!(env->insn_flags & ISA_NANOMIPS32)) {
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
info->print_insn = print_insn_big_mips;
#else
info->print_insn = print_insn_little_mips;
#define MEMOP_IDX(DF)
#endif
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
static inline uint64_t bswap16x4(uint64_t x)
{
uint64_t m = 0x00ff00ff00ff00ffull;
*/
d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
d0 = bswap16x4(d0);
d1 = bswap16x4(d1);
#endif
*/
d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
d0 = bswap32x2(d0);
d1 = bswap32x2(d1);
#endif
/* Store 8 bytes at a time. See helper_msa_ld_h. */
d0 = pwd->d[0];
d1 = pwd->d[1];
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
d0 = bswap16x4(d0);
d1 = bswap16x4(d1);
#endif
/* Store 8 bytes at a time. See helper_msa_ld_w. */
d0 = pwd->d[0];
d1 = pwd->d[1];
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
d0 = bswap32x2(d0);
d1 = bswap32x2(d1);
#endif
#if defined(TARGET_PPC64)
msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
#endif
-#if !defined(TARGET_WORDS_BIGENDIAN)
+#if !TARGET_BIG_ENDIAN
msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
if (!((env->msr_mask >> MSR_LE) & 1)) {
fprintf(stderr, "Selected CPU does not support little-endian.\n");
/*
* We need to present the registers to gdb in the "current" memory
* ordering. For user-only mode we get this for free;
- * TARGET_WORDS_BIGENDIAN is set to the proper ordering for the
+ * TARGET_BIG_ENDIAN is set to the proper ordering for the
* binary, and cannot be changed. For system mode,
- * TARGET_WORDS_BIGENDIAN is always set, and we must check the current
+ * TARGET_BIG_ENDIAN is always set, and we must check the current
* mode of the chip to see if we're running in little-endian.
*/
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
static inline bool needs_byteswap(const CPUPPCState *env)
{
-#if defined(TARGET_WORDS_BIGENDIAN)
+#if TARGET_BIG_ENDIAN
return msr_le;
#else
return !msr_le;
/* Return true iff byteswap is needed in a scalar memop */
static inline bool need_byteswap(const DisasContext *ctx)
{
-#if defined(TARGET_WORDS_BIGENDIAN)
+#if TARGET_BIG_ENDIAN
return ctx->le_mode;
#else
return !ctx->le_mode;
#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
#else
#endif
-#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
+#if TARGET_BIG_ENDIAN == (XCHAL_HAVE_BE != 0)
#define REGISTER_CORE(core) \
static void __attribute__((constructor)) register_core(void) \
{ \
static void translate_bb(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
TCGv_i32 bit = tcg_const_i32(0x80000000u);
#else
TCGv_i32 bit = tcg_const_i32(0x00000001u);
#endif
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[1].in, 0x1f);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
tcg_gen_shr_i32(bit, bit, tmp);
#else
tcg_gen_shl_i32(bit, bit, tmp);
const uint32_t par[])
{
TCGv_i32 tmp = tcg_temp_new_i32();
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm);
#else
tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm);
# Xtensa softmmu tests
#
-ifneq ($(TARGET_WORDS_BIGENDIAN),y)
+ifneq ($(TARGET_BIG_ENDIAN),y)
XTENSA_SRC = $(SRC_PATH)/tests/tcg/xtensa
XTENSA_ALL = $(filter-out $(XTENSA_SRC)/linker.ld.S,$(wildcard $(XTENSA_SRC)/*.S))