net/mlx5: Introduce TLS RX offload hardware bits

Add TLS RX offload related IFC hardware fields and enumerations.

Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Reviewed-by: Maxim Mikityanskiy <maximmi@mellanox.com>
Reviewed-by: Boris Pismenny <borisp@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index de93f0b..1bc27ac 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -450,10 +450,12 @@ enum {
 
 enum {
        MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
+       MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2,
 };
 
 enum {
        MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
+       MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
 };
 
 enum {
@@ -764,7 +766,7 @@ struct mlx5_err_cqe {
 };
 
 struct mlx5_cqe64 {
-       u8              outer_l3_tunneled;
+       u8              tls_outer_l3_tunneled;
        u8              rsvd0;
        __be16          wqe_id;
        u8              lro_tcppsh_abort_dupack;
@@ -854,7 +856,12 @@ static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
 
 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
 {
-       return cqe->outer_l3_tunneled & 0x1;
+       return cqe->tls_outer_l3_tunneled & 0x1;
+}
+
+static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
+{
+       return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
 }
 
 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
@@ -942,6 +949,13 @@ enum {
        CQE_L4_OK       = 1 << 2,
 };
 
+enum {
+       CQE_TLS_OFFLOAD_NOT_DECRYPTED           = 0x0,
+       CQE_TLS_OFFLOAD_DECRYPTED               = 0x1,
+       CQE_TLS_OFFLOAD_RESYNC                  = 0x2,
+       CQE_TLS_OFFLOAD_ERROR                   = 0x3,
+};
+
 struct mlx5_sig_err_cqe {
        u8              rsvd0[16];
        __be32          expected_trans_sig;

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 058ded2..6a6bb5d 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1491,7 +1491,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 
        u8         reserved_at_480[0x1];
        u8         tls_tx[0x1];
-       u8         reserved_at_482[0x1];
+       u8         tls_rx[0x1];
        u8         log_max_l2_table[0x5];
        u8         reserved_at_488[0x8];
        u8         log_uar_page_sz[0x10];
@@ -3136,7 +3136,8 @@ struct mlx5_ifc_tirc_bits {
        u8         reserved_at_0[0x20];
 
        u8         disp_type[0x4];
-       u8         reserved_at_24[0x1c];
+       u8         tls_en[0x1];
+       u8         reserved_at_25[0x1b];
 
        u8         reserved_at_40[0x40];