[ARM] Mark select and selectcc of MVE vector operations as expand.

We already expand select and select_cc in codegenprepare, but they can
still be generated under some situations. Explicitly mark them as expand
to ensure they are not produced, leading to a failure to select the
nodes.

Differential Revision: https://reviews.llvm.org/D92373

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 0426a56..bc92221 100644 (file)
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -289,6 +289,8 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
     setOperationAction(ISD::UDIVREM, VT, Expand);
     setOperationAction(ISD::SDIVREM, VT, Expand);
     setOperationAction(ISD::CTPOP, VT, Expand);
+    setOperationAction(ISD::SELECT, VT, Expand);
+    setOperationAction(ISD::SELECT_CC, VT, Expand);
 
     // Vector reductions
     setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
@@ -335,6 +337,8 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
     setOperationAction(ISD::SETCC, VT, Custom);
     setOperationAction(ISD::MLOAD, VT, Custom);
     setOperationAction(ISD::MSTORE, VT, Legal);
+    setOperationAction(ISD::SELECT, VT, Expand);
+    setOperationAction(ISD::SELECT_CC, VT, Expand);
 
     // Pre and Post inc are supported on loads and stores
     for (unsigned im = (unsigned)ISD::PRE_INC;

diff --git a/llvm/test/CodeGen/Thumb2/mve-selectcc.ll b/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
index 2633d2a..b4f5d8d 100644 (file)
--- a/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
@@ -203,3 +203,53 @@ entry:
   %s = select i1 %c,  <2 x double> %s0, <2 x double> %s1
   ret <2 x double> %s
 }
+
+define i32 @e() {
+; CHECK-LABEL: e:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    adr r0, .LCPI14_0
+; CHECK-NEXT:    vmov.i32 q1, #0x4
+; CHECK-NEXT:    vldrw.u32 q0, [r0]
+; CHECK-NEXT:    movs r0, #0
+; CHECK-NEXT:    vmov q2, q0
+; CHECK-NEXT:  .LBB14_1: @ %vector.body
+; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    adds r0, #4
+; CHECK-NEXT:    vadd.i32 q2, q2, q1
+; CHECK-NEXT:    cmp r0, #8
+; CHECK-NEXT:    cset r1, eq
+; CHECK-NEXT:    tst.w r1, #1
+; CHECK-NEXT:    csetm r1, ne
+; CHECK-NEXT:    subs.w r2, r0, #8
+; CHECK-NEXT:    vdup.32 q3, r1
+; CHECK-NEXT:    csel r0, r0, r2, ne
+; CHECK-NEXT:    vbic q2, q2, q3
+; CHECK-NEXT:    vand q3, q3, q0
+; CHECK-NEXT:    vorr q2, q3, q2
+; CHECK-NEXT:    b .LBB14_1
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  @ %bb.2:
+; CHECK-NEXT:  .LCPI14_0:
+; CHECK-NEXT:    .long 0 @ 0x0
+; CHECK-NEXT:    .long 1 @ 0x1
+; CHECK-NEXT:    .long 2 @ 0x2
+; CHECK-NEXT:    .long 3 @ 0x3
+entry:
+  br label %vector.body
+
+vector.body:                                      ; preds = %pred.store.continue73, %entry
+  %index = phi i32 [ 0, %entry ], [ %spec.select, %pred.store.continue73 ]
+  %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %entry ], [ %spec.select74, %pred.store.continue73 ]
+  %l3 = icmp ult <4 x i32> %vec.ind, <i32 5, i32 5, i32 5, i32 5>
+  %l4 = extractelement <4 x i1> %l3, i32 0
+  br label %pred.store.continue73
+
+pred.store.continue73:                            ; preds = %pred.store.if72, %pred.store.continue71
+  %index.next = add i32 %index, 4
+  %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>
+  %l60 = icmp eq i32 %index.next, 8
+  %spec.select = select i1 %l60, i32 0, i32 %index.next
+  %spec.select74 = select i1 %l60, <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> %vec.ind.next
+  br label %vector.body
+}
+