/* Color format */
val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
- val = (val & ~MIPI_CSIS_ISPCFG_FMT_MASK) | state->csis_fmt->fmt_reg;
+ val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK);
+ val |= state->csis_fmt->fmt_reg;
mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
/* Pixel resolution */
mipi_csis_set_hsync_settle(state, state->hs_settle);
- val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
- if (state->csis_fmt->width == 32)
- val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT;
- else
- val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT;
- mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
-
val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
(0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
(0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);