[Hexagon] Make PS_fi and PS_fia extendable (they both expand to A2_addi)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315019 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonPseudo.td b/lib/Target/Hexagon/HexagonPseudo.td
index 094e0fb..199148f 100644 (file)
--- a/lib/Target/Hexagon/HexagonPseudo.td
+++ b/lib/Target/Hexagon/HexagonPseudo.td
@@ -247,11 +247,14 @@ def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
 // This simplifies the frame-index elimination code.
 //
 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
-    isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
+    isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0, isExtendable = 1,
+    isExtentSigned = 1, opExtentBits = 16, opExtentAlign = 0 in {
+  let opExtendable = 2 in
   def PS_fi  : Pseudo<(outs IntRegs:$Rd),
-                         (ins IntRegs:$fi, s32_0Imm:$off), "">;
+                      (ins IntRegs:$fi, s32_0Imm:$off), "">;
+  let opExtendable = 3 in
   def PS_fia : Pseudo<(outs IntRegs:$Rd),
-                         (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
+                      (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
 }
 
 class CondStr<string CReg, bit True, bit New> {