void riscv_cpu_update_mask(CPURISCVState *env)
{
target_ulong mask = 0, base = 0;
+ RISCVMXL xl = env->xl;
/*
* TODO: Current RVJ spec does not specify
* how the extension interacts with XLEN.
*/
#ifndef CONFIG_USER_ONLY
+ int mode = cpu_address_mode(env);
+ xl = cpu_get_xl(env, mode);
if (riscv_has_ext(env, RVJ)) {
- switch (env->priv) {
+ switch (mode) {
case PRV_M:
if (env->mmte & M_PM_ENABLE) {
mask = env->mpmmask;
}
}
#endif
- if (env->xl == MXL_RV32) {
+ if (xl == MXL_RV32) {
env->cur_pmmask = mask & UINT32_MAX;
env->cur_pmbase = base & UINT32_MAX;
} else {
*/
if (env->debugger) {
env->xl = cpu_recompute_xl(env);
- riscv_cpu_update_mask(env);
}
+
+ riscv_cpu_update_mask(env);
return RISCV_EXCP_NONE;
}
uint64_t mstatus;
env->mpmmask = val;
- if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmmask = val;
}
env->mmte |= EXT_STATUS_DIRTY;
return RISCV_EXCP_NONE;
}
env->spmmask = val;
- if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmmask = val;
+ if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
+ env->cur_pmmask &= UINT32_MAX;
+ }
}
env->mmte |= EXT_STATUS_DIRTY;
return RISCV_EXCP_NONE;
}
env->upmmask = val;
- if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmmask = val;
+ if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
+ env->cur_pmmask &= UINT32_MAX;
+ }
}
env->mmte |= EXT_STATUS_DIRTY;
uint64_t mstatus;
env->mpmbase = val;
- if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmbase = val;
}
env->mmte |= EXT_STATUS_DIRTY;
return RISCV_EXCP_NONE;
}
env->spmbase = val;
- if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmbase = val;
+ if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
+ env->cur_pmbase &= UINT32_MAX;
+ }
}
env->mmte |= EXT_STATUS_DIRTY;
return RISCV_EXCP_NONE;
}
env->upmbase = val;
- if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmbase = val;
+ if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
+ env->cur_pmbase &= UINT32_MAX;
+ }
}
env->mmte |= EXT_STATUS_DIRTY;