Subzero: Fix some legalization issues involving immediates.

Some lowering sequences were incorrectly allowing immediate operands in native instructions.  This includes 32-bit icmp, 64-bit icmp, select, switch, and 64-bit mul.

BUG= none
R=jvoung@chromium.org

Review URL: https://codereview.chromium.org/511543002

diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index 930836b..7ed8abf 100644 (file)
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -1214,6 +1214,8 @@ void TargetX8632::lowerArithmetic(const InstArithmetic *Inst) {
       //   t4.hi += t1
       //   t4.hi += t2
       //   a.hi = t4.hi
+      // The mul instruction cannot take an immediate operand.
+      Src1Lo = legalize(Src1Lo, Legal_Reg | Legal_Mem);
       _mov(T_1, Src0Hi);
       _imul(T_1, Src1Lo);
       _mov(T_2, Src1Hi);
@@ -2605,9 +2607,9 @@ void TargetX8632::lowerIcmp(const InstIcmp *Inst) {
   if (InstBr *NextBr = llvm::dyn_cast_or_null<InstBr>(Context.getNextInst())) {
     if (Src0->getType() != IceType_i64 && !NextBr->isUnconditional() &&
         Dest == NextBr->getSrc(0) && NextBr->isLastUse(Dest)) {
-      Operand *Src0New = legalize(
+      Operand *Src0RM = legalize(
           Src0, IsSrc1ImmOrReg ? (Legal_Reg | Legal_Mem) : Legal_Reg, true);
-      _cmp(Src0New, Src1);
+      _cmp(Src0RM, Src1);
       _br(getIcmp32Mapping(Inst->getCondition()), NextBr->getTargetTrue(),
           NextBr->getTargetFalse());
       // Skip over the following branch instruction.
@@ -2624,14 +2626,16 @@ void TargetX8632::lowerIcmp(const InstIcmp *Inst) {
     InstIcmp::ICond Condition = Inst->getCondition();
     size_t Index = static_cast<size_t>(Condition);
     assert(Index < TableIcmp64Size);
+    Operand *Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
+    Operand *Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
     Operand *Src1LoRI = legalize(loOperand(Src1), Legal_Reg | Legal_Imm);
     Operand *Src1HiRI = legalize(hiOperand(Src1), Legal_Reg | Legal_Imm);
     if (Condition == InstIcmp::Eq || Condition == InstIcmp::Ne) {
       InstX8632Label *Label = InstX8632Label::create(Func, this);
       _mov(Dest, (Condition == InstIcmp::Eq ? Zero : One));
-      _cmp(loOperand(Src0), Src1LoRI);
+      _cmp(Src0LoRM, Src1LoRI);
       _br(InstX8632Br::Br_ne, Label);
-      _cmp(hiOperand(Src0), Src1HiRI);
+      _cmp(Src0HiRM, Src1HiRI);
       _br(InstX8632Br::Br_ne, Label);
       Context.insert(InstFakeUse::create(Func, Dest));
       _mov(Dest, (Condition == InstIcmp::Eq ? One : Zero));
@@ -2640,10 +2644,10 @@ void TargetX8632::lowerIcmp(const InstIcmp *Inst) {
       InstX8632Label *LabelFalse = InstX8632Label::create(Func, this);
       InstX8632Label *LabelTrue = InstX8632Label::create(Func, this);
       _mov(Dest, One);
-      _cmp(hiOperand(Src0), Src1HiRI);
+      _cmp(Src0HiRM, Src1HiRI);
       _br(TableIcmp64[Index].C1, LabelTrue);
       _br(TableIcmp64[Index].C2, LabelFalse);
-      _cmp(loOperand(Src0), Src1LoRI);
+      _cmp(Src0LoRM, Src1LoRI);
       _br(TableIcmp64[Index].C3, LabelTrue);
       Context.insert(LabelFalse);
       Context.insert(InstFakeUse::create(Func, Dest));
@@ -2654,10 +2658,10 @@ void TargetX8632::lowerIcmp(const InstIcmp *Inst) {
   }
 
   // cmp b, c
-  Operand *Src0New =
-      legalize(Src0, IsSrc1ImmOrReg ? Legal_All : Legal_Reg, true);
+  Operand *Src0RM = legalize(
+      Src0, IsSrc1ImmOrReg ? (Legal_Reg | Legal_Mem) : Legal_Reg, true);
   InstX8632Label *Label = InstX8632Label::create(Func, this);
-  _cmp(Src0New, Src1);
+  _cmp(Src0RM, Src1);
   _mov(Dest, One);
   _br(getIcmp32Mapping(Inst->getCondition()), Label);
   Context.insert(InstFakeUse::create(Func, Dest));
@@ -3794,7 +3798,7 @@ void TargetX8632::lowerSelect(const InstSelect *Inst) {
   }
 
   // a=d?b:c ==> cmp d,0; a=b; jne L1; FakeUse(a); a=c; L1:
-  Operand *ConditionRMI = legalize(Condition);
+  Operand *ConditionRM = legalize(Condition, Legal_Reg | Legal_Mem);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   InstX8632Label *Label = InstX8632Label::create(Func, this);
 
@@ -3803,7 +3807,7 @@ void TargetX8632::lowerSelect(const InstSelect *Inst) {
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Operand *SrcLoRI = legalize(loOperand(SrcT), Legal_Reg | Legal_Imm, true);
     Operand *SrcHiRI = legalize(hiOperand(SrcT), Legal_Reg | Legal_Imm, true);
-    _cmp(ConditionRMI, Zero);
+    _cmp(ConditionRM, Zero);
     _mov(DestLo, SrcLoRI);
     _mov(DestHi, SrcHiRI);
     _br(InstX8632Br::Br_ne, Label);
@@ -3816,7 +3820,7 @@ void TargetX8632::lowerSelect(const InstSelect *Inst) {
     _mov(DestLo, SrcLoRI);
     _mov(DestHi, SrcHiRI);
   } else {
-    _cmp(ConditionRMI, Zero);
+    _cmp(ConditionRM, Zero);
     SrcT = legalize(SrcT, Legal_Reg | Legal_Imm, true);
     _mov(Dest, SrcT);
     _br(InstX8632Br::Br_ne, Label);
@@ -3882,7 +3886,7 @@ void TargetX8632::lowerSwitch(const InstSwitch *Inst) {
   if (NumCases >= 2)
     Src0 = legalizeToVar(Src0, true);
   else
-    Src0 = legalize(Src0, Legal_All, true);
+    Src0 = legalize(Src0, Legal_Reg | Legal_Mem, true);
   for (SizeT I = 0; I < NumCases; ++I) {
     Operand *Value = Ctx->getConstantInt(IceType_i32, Inst->getValue(I));
     _cmp(Src0, Value);

diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index 859d657..0989b96 100644 (file)
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -32,7 +32,7 @@ entry:
   %add3 = add i32 %add, %call2
   ret i32 %add3
 }
-; CHECK: pass64BitArg:
+; CHECK-LABEL: pass64BitArg
 ; CHECK:      sub     esp
 ; CHECK:      mov     dword ptr [esp+4]
 ; CHECK:      mov     dword ptr [esp]
@@ -55,7 +55,7 @@ entry:
 ; CHECK:      mov     dword ptr [esp+12]
 ; CHECK:      call    ignore64BitArgNoInline
 ;
-; OPTM1: pass64BitArg:
+; OPTM1-LABEL: pass64BitArg
 ; OPTM1:      sub     esp
 ; OPTM1:      mov     dword ptr [esp+4]
 ; OPTM1:      mov     dword ptr [esp]
@@ -85,7 +85,7 @@ entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 -2401053092306725256)
   ret i32 %call
 }
-; CHECK: pass64BitConstArg:
+; CHECK-LABEL: pass64BitConstArg
 ; CHECK:      sub     esp
 ; CHECK:      mov     dword ptr [esp+4]
 ; CHECK-NEXT: mov     dword ptr [esp]
@@ -94,7 +94,7 @@ entry:
 ; CHECK-NEXT: mov     dword ptr [esp+12], 305419896
 ; CHECK-NEXT: call    ignore64BitArgNoInline
 ;
-; OPTM1: pass64BitConstArg:
+; OPTM1-LABEL: pass64BitConstArg
 ; OPTM1:      sub     esp
 ; OPTM1:      mov     dword ptr [esp+4]
 ; OPTM1-NEXT: mov     dword ptr [esp]
@@ -107,12 +107,12 @@ define internal i64 @return64BitArg(i64 %a) {
 entry:
   ret i64 %a
 }
-; CHECK: return64BitArg:
+; CHECK-LABEL: return64BitArg
 ; CHECK: mov     {{.*}}, dword ptr [esp+4]
 ; CHECK: mov     {{.*}}, dword ptr [esp+8]
 ; CHECK: ret
 ;
-; OPTM1: return64BitArg:
+; OPTM1-LABEL: return64BitArg
 ; OPTM1: mov     {{.*}}, dword ptr [esp+4]
 ; OPTM1: mov     {{.*}}, dword ptr [esp+8]
 ; OPTM1: ret
@@ -121,12 +121,12 @@ define internal i64 @return64BitConst() {
 entry:
   ret i64 -2401053092306725256
 }
-; CHECK: return64BitConst:
+; CHECK-LABEL: return64BitConst
 ; CHECK: mov     eax, 305419896
 ; CHECK: mov     edx, 3735928559
 ; CHECK: ret
 ;
-; OPTM1: return64BitConst:
+; OPTM1-LABEL: return64BitConst
 ; OPTM1: mov     eax, 305419896
 ; OPTM1: mov     edx, 3735928559
 ; OPTM1: ret
@@ -136,12 +136,12 @@ entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
-; CHECK: add64BitSigned:
+; CHECK-LABEL: add64BitSigned
 ; CHECK: add
 ; CHECK: adc
 ; CHECK: ret
 ;
-; OPTM1: add64BitSigned:
+; OPTM1-LABEL: add64BitSigned
 ; OPTM1: add
 ; OPTM1: adc
 ; OPTM1: ret
@@ -151,12 +151,12 @@ entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
-; CHECK: add64BitUnsigned:
+; CHECK-LABEL: add64BitUnsigned
 ; CHECK: add
 ; CHECK: adc
 ; CHECK: ret
 ;
-; OPTM1: add64BitUnsigned:
+; OPTM1-LABEL: add64BitUnsigned
 ; OPTM1: add
 ; OPTM1: adc
 ; OPTM1: ret
@@ -166,12 +166,12 @@ entry:
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
-; CHECK: sub64BitSigned:
+; CHECK-LABEL: sub64BitSigned
 ; CHECK: sub
 ; CHECK: sbb
 ; CHECK: ret
 ;
-; OPTM1: sub64BitSigned:
+; OPTM1-LABEL: sub64BitSigned
 ; OPTM1: sub
 ; OPTM1: sbb
 ; OPTM1: ret
@@ -181,12 +181,12 @@ entry:
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
-; CHECK: sub64BitUnsigned:
+; CHECK-LABEL: sub64BitUnsigned
 ; CHECK: sub
 ; CHECK: sbb
 ; CHECK: ret
 ;
-; OPTM1: sub64BitUnsigned:
+; OPTM1-LABEL: sub64BitUnsigned
 ; OPTM1: sub
 ; OPTM1: sbb
 ; OPTM1: ret
@@ -196,7 +196,7 @@ entry:
   %mul = mul i64 %b, %a
   ret i64 %mul
 }
-; CHECK: mul64BitSigned:
+; CHECK-LABEL: mul64BitSigned
 ; CHECK: imul
 ; CHECK: imul
 ; CHECK: mul
@@ -204,7 +204,7 @@ entry:
 ; CHECK: add
 ; CHECK: ret
 ;
-; OPTM1: mul64BitSigned:
+; OPTM1-LABEL: mul64BitSigned
 ; OPTM1: imul
 ; OPTM1: imul
 ; OPTM1: mul
@@ -217,7 +217,7 @@ entry:
   %mul = mul i64 %b, %a
   ret i64 %mul
 }
-; CHECK: mul64BitUnsigned:
+; CHECK-LABEL: mul64BitUnsigned
 ; CHECK: imul
 ; CHECK: imul
 ; CHECK: mul
@@ -225,7 +225,7 @@ entry:
 ; CHECK: add
 ; CHECK: ret
 ;
-; OPTM1: mul64BitUnsigned:
+; OPTM1-LABEL: mul64BitUnsigned
 ; OPTM1: imul
 ; OPTM1: imul
 ; OPTM1: mul
@@ -238,11 +238,11 @@ entry:
   %div = sdiv i64 %a, %b
   ret i64 %div
 }
-; CHECK: div64BitSigned:
+; CHECK-LABEL: div64BitSigned
 ; CHECK: call    __divdi3
 ; CHECK: ret
 ;
-; OPTM1: div64BitSigned:
+; OPTM1-LABEL: div64BitSigned
 ; OPTM1: call    __divdi3
 ; OPTM1: ret
 
@@ -251,13 +251,13 @@ entry:
   %div = sdiv i64 %a, 12345678901234
   ret i64 %div
 }
-; CHECK-LABEL: div64BitSignedConst:
+; CHECK-LABEL: div64BitSignedConst
 ; CHECK: mov     dword ptr [esp+12], 2874
 ; CHECK: mov     dword ptr [esp+8],  1942892530
 ; CHECK: call    __divdi3
 ; CHECK: ret
 ;
-; OPTM1-LABEL: div64BitSignedConst:
+; OPTM1-LABEL: div64BitSignedConst
 ; OPTM1: mov     dword ptr [esp+12], 2874
 ; OPTM1: mov     dword ptr [esp+8],  1942892530
 ; OPTM1: call    __divdi3
@@ -268,11 +268,11 @@ entry:
   %div = udiv i64 %a, %b
   ret i64 %div
 }
-; CHECK: div64BitUnsigned:
+; CHECK-LABEL: div64BitUnsigned
 ; CHECK: call    __udivdi3
 ; CHECK: ret
 ;
-; OPTM1: div64BitUnsigned:
+; OPTM1-LABEL: div64BitUnsigned
 ; OPTM1: call    __udivdi3
 ; OPTM1: ret
 
@@ -281,11 +281,11 @@ entry:
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
-; CHECK: rem64BitSigned:
+; CHECK-LABEL: rem64BitSigned
 ; CHECK: call    __moddi3
 ; CHECK: ret
 ;
-; OPTM1: rem64BitSigned:
+; OPTM1-LABEL: rem64BitSigned
 ; OPTM1: call    __moddi3
 ; OPTM1: ret
 
@@ -294,11 +294,11 @@ entry:
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
-; CHECK: rem64BitUnsigned:
+; CHECK-LABEL: rem64BitUnsigned
 ; CHECK: call    __umoddi3
 ; CHECK: ret
 ;
-; OPTM1: rem64BitUnsigned:
+; OPTM1-LABEL: rem64BitUnsigned
 ; OPTM1: call    __umoddi3
 ; OPTM1: ret
 
@@ -307,13 +307,13 @@ entry:
   %shl = shl i64 %a, %b
   ret i64 %shl
 }
-; CHECK: shl64BitSigned:
+; CHECK-LABEL: shl64BitSigned
 ; CHECK: shld
 ; CHECK: shl e
 ; CHECK: test {{.*}}, 32
 ; CHECK: je
 ;
-; OPTM1: shl64BitSigned:
+; OPTM1-LABEL: shl64BitSigned
 ; OPTM1: shld
 ; OPTM1: shl e
 ; OPTM1: test {{.*}}, 32
@@ -324,13 +324,13 @@ entry:
   %shl = shl i64 %a, %b
   ret i64 %shl
 }
-; CHECK: shl64BitUnsigned:
+; CHECK-LABEL: shl64BitUnsigned
 ; CHECK: shld
 ; CHECK: shl e
 ; CHECK: test {{.*}}, 32
 ; CHECK: je
 ;
-; OPTM1: shl64BitUnsigned:
+; OPTM1-LABEL: shl64BitUnsigned
 ; OPTM1: shld
 ; OPTM1: shl e
 ; OPTM1: test {{.*}}, 32
@@ -341,14 +341,14 @@ entry:
   %shr = ashr i64 %a, %b
   ret i64 %shr
 }
-; CHECK: shr64BitSigned:
+; CHECK-LABEL: shr64BitSigned
 ; CHECK: shrd
 ; CHECK: sar
 ; CHECK: test {{.*}}, 32
 ; CHECK: je
 ; CHECK: sar {{.*}}, 31
 ;
-; OPTM1: shr64BitSigned:
+; OPTM1-LABEL: shr64BitSigned
 ; OPTM1: shrd
 ; OPTM1: sar
 ; OPTM1: test {{.*}}, 32
@@ -360,13 +360,13 @@ entry:
   %shr = lshr i64 %a, %b
   ret i64 %shr
 }
-; CHECK: shr64BitUnsigned:
+; CHECK-LABEL: shr64BitUnsigned
 ; CHECK: shrd
 ; CHECK: shr
 ; CHECK: test {{.*}}, 32
 ; CHECK: je
 ;
-; OPTM1: shr64BitUnsigned:
+; OPTM1-LABEL: shr64BitUnsigned
 ; OPTM1: shrd
 ; OPTM1: shr
 ; OPTM1: test {{.*}}, 32
@@ -377,11 +377,11 @@ entry:
   %and = and i64 %b, %a
   ret i64 %and
 }
-; CHECK: and64BitSigned:
+; CHECK-LABEL: and64BitSigned
 ; CHECK: and
 ; CHECK: and
 ;
-; OPTM1: and64BitSigned:
+; OPTM1-LABEL: and64BitSigned
 ; OPTM1: and
 ; OPTM1: and
 
@@ -390,11 +390,11 @@ entry:
   %and = and i64 %b, %a
   ret i64 %and
 }
-; CHECK: and64BitUnsigned:
+; CHECK-LABEL: and64BitUnsigned
 ; CHECK: and
 ; CHECK: and
 ;
-; OPTM1: and64BitUnsigned:
+; OPTM1-LABEL: and64BitUnsigned
 ; OPTM1: and
 ; OPTM1: and
 
@@ -403,11 +403,11 @@ entry:
   %or = or i64 %b, %a
   ret i64 %or
 }
-; CHECK: or64BitSigned:
+; CHECK-LABEL: or64BitSigned
 ; CHECK: or
 ; CHECK: or
 ;
-; OPTM1: or64BitSigned:
+; OPTM1-LABEL: or64BitSigned
 ; OPTM1: or
 ; OPTM1: or
 
@@ -416,11 +416,11 @@ entry:
   %or = or i64 %b, %a
   ret i64 %or
 }
-; CHECK: or64BitUnsigned:
+; CHECK-LABEL: or64BitUnsigned
 ; CHECK: or
 ; CHECK: or
 ;
-; OPTM1: or64BitUnsigned:
+; OPTM1-LABEL: or64BitUnsigned
 ; OPTM1: or
 ; OPTM1: or
 
@@ -429,11 +429,11 @@ entry:
   %xor = xor i64 %b, %a
   ret i64 %xor
 }
-; CHECK: xor64BitSigned:
+; CHECK-LABEL: xor64BitSigned
 ; CHECK: xor
 ; CHECK: xor
 ;
-; OPTM1: xor64BitSigned:
+; OPTM1-LABEL: xor64BitSigned
 ; OPTM1: xor
 ; OPTM1: xor
 
@@ -442,11 +442,11 @@ entry:
   %xor = xor i64 %b, %a
   ret i64 %xor
 }
-; CHECK: xor64BitUnsigned:
+; CHECK-LABEL: xor64BitUnsigned
 ; CHECK: xor
 ; CHECK: xor
 ;
-; OPTM1: xor64BitUnsigned:
+; OPTM1-LABEL: xor64BitUnsigned
 ; OPTM1: xor
 ; OPTM1: xor
 
@@ -455,11 +455,11 @@ entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
-; CHECK: trunc64To32Signed:
+; CHECK-LABEL: trunc64To32Signed
 ; CHECK: mov     eax, dword ptr [esp+4]
 ; CHECK-NEXT: ret
 ;
-; OPTM1: trunc64To32Signed:
+; OPTM1-LABEL: trunc64To32Signed
 ; OPTM1: mov     eax, dword ptr [esp+
 ; OPTM1: ret
 
@@ -469,12 +469,12 @@ entry:
   %conv.ret_ext = sext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
-; CHECK: trunc64To16Signed:
+; CHECK-LABEL: trunc64To16Signed
 ; CHECK:      mov     eax, dword ptr [esp+4]
 ; CHECK-NEXT: movsx  eax, ax
 ; CHECK-NEXT: ret
 ;
-; OPTM1: trunc64To16Signed:
+; OPTM1-LABEL: trunc64To16Signed
 ; OPTM1:      mov     eax, dword ptr [esp+
 ; OPTM1: movsx  eax,
 ; OPTM1: ret
@@ -485,12 +485,12 @@ entry:
   %conv.ret_ext = sext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
-; CHECK: trunc64To8Signed:
+; CHECK-LABEL: trunc64To8Signed
 ; CHECK:      mov     eax, dword ptr [esp+4]
 ; CHECK-NEXT: movsx  eax, al
 ; CHECK-NEXT: ret
 ;
-; OPTM1: trunc64To8Signed:
+; OPTM1-LABEL: trunc64To8Signed
 ; OPTM1:      mov     eax, dword ptr [esp+
 ; OPTM1: movsx  eax,
 ; OPTM1: ret
@@ -525,11 +525,11 @@ entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
-; CHECK: trunc64To32Unsigned:
+; CHECK-LABEL: trunc64To32Unsigned
 ; CHECK: mov     eax, dword ptr [esp+4]
 ; CHECK-NEXT: ret
 ;
-; OPTM1: trunc64To32Unsigned:
+; OPTM1-LABEL: trunc64To32Unsigned
 ; OPTM1: mov     eax, dword ptr [esp+
 ; OPTM1: ret
 
@@ -539,12 +539,12 @@ entry:
   %conv.ret_ext = zext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
-; CHECK: trunc64To16Unsigned:
+; CHECK-LABEL: trunc64To16Unsigned
 ; CHECK:      mov     eax, dword ptr [esp+4]
 ; CHECK-NEXT: movzx  eax, ax
 ; CHECK-NEXT: ret
 ;
-; OPTM1: trunc64To16Unsigned:
+; OPTM1-LABEL: trunc64To16Unsigned
 ; OPTM1:      mov     eax, dword ptr [esp+
 ; OPTM1: movzx  eax,
 ; OPTM1: ret
@@ -555,12 +555,12 @@ entry:
   %conv.ret_ext = zext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
-; CHECK: trunc64To8Unsigned:
+; CHECK-LABEL: trunc64To8Unsigned
 ; CHECK:      mov     eax, dword ptr [esp+4]
 ; CHECK-NEXT: movzx  eax, al
 ; CHECK-NEXT: ret
 ;
-; OPTM1: trunc64To8Unsigned:
+; OPTM1-LABEL: trunc64To8Unsigned
 ; OPTM1:      mov     eax, dword ptr [esp+
 ; OPTM1: movzx  eax,
 ; OPTM1: ret
@@ -572,12 +572,12 @@ entry:
   %tobool.ret_ext = zext i1 %tobool to i32
   ret i32 %tobool.ret_ext
 }
-; CHECK: trunc64To1:
+; CHECK-LABEL: trunc64To1
 ; CHECK:      mov     eax, dword ptr [esp+4]
 ; CHECK:      and     eax, 1
 ; CHECK-NEXT: ret
 ;
-; OPTM1: trunc64To1:
+; OPTM1-LABEL: trunc64To1
 ; OPTM1:      mov     eax, dword ptr [esp+
 ; OPTM1:      and     eax, 1
 ; OPTM1: ret
@@ -587,11 +587,11 @@ entry:
   %conv = sext i32 %a to i64
   ret i64 %conv
 }
-; CHECK: sext32To64:
+; CHECK-LABEL: sext32To64
 ; CHECK: mov
 ; CHECK: sar {{.*}}, 31
 ;
-; OPTM1: sext32To64:
+; OPTM1-LABEL: sext32To64
 ; OPTM1: mov
 ; OPTM1: sar {{.*}}, 31
 
@@ -601,11 +601,11 @@ entry:
   %conv = sext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
-; CHECK: sext16To64:
+; CHECK-LABEL: sext16To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}}, 31
 ;
-; OPTM1: sext16To64:
+; OPTM1-LABEL: sext16To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}}, 31
 
@@ -615,11 +615,11 @@ entry:
   %conv = sext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
-; CHECK: sext8To64:
+; CHECK-LABEL: sext8To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}}, 31
 ;
-; OPTM1: sext8To64:
+; OPTM1-LABEL: sext8To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}}, 31
 
@@ -628,11 +628,11 @@ entry:
   %conv = zext i32 %a to i64
   ret i64 %conv
 }
-; CHECK: zext32To64:
+; CHECK-LABEL: zext32To64
 ; CHECK: mov
 ; CHECK: mov {{.*}}, 0
 ;
-; OPTM1: zext32To64:
+; OPTM1-LABEL: zext32To64
 ; OPTM1: mov
 ; OPTM1: mov {{.*}}, 0
 
@@ -642,11 +642,11 @@ entry:
   %conv = zext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
-; CHECK: zext16To64:
+; CHECK-LABEL: zext16To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}}, 0
 ;
-; OPTM1: zext16To64:
+; OPTM1-LABEL: zext16To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}}, 0
 
@@ -656,11 +656,11 @@ entry:
   %conv = zext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
-; CHECK: zext8To64:
+; CHECK-LABEL: zext8To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}}, 0
 ;
-; OPTM1: zext8To64:
+; OPTM1-LABEL: zext8To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}}, 0
 
@@ -670,11 +670,11 @@ entry:
   %conv = zext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
-; CHECK: zext1To64:
+; CHECK-LABEL: zext1To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}}, 0
 ;
-; OPTM1: zext1To64:
+; OPTM1-LABEL: zext1To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}}, 0
 
@@ -698,7 +698,7 @@ if.then2:                                         ; preds = %if.end
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
-; CHECK: icmpEq64:
+; CHECK-LABEL: icmpEq64
 ; CHECK: jne
 ; CHECK: jne
 ; CHECK: call
@@ -706,7 +706,7 @@ if.end3:                                          ; preds = %if.then2, %if.end
 ; CHECK: jne
 ; CHECK: call
 ;
-; OPTM1: icmpEq64:
+; OPTM1-LABEL: icmpEq64
 ; OPTM1: jne
 ; OPTM1: jne
 ; OPTM1: call
@@ -736,7 +736,7 @@ if.then2:                                         ; preds = %if.end
 if.end3:                                          ; preds = %if.end, %if.then2
   ret void
 }
-; CHECK: icmpNe64:
+; CHECK-LABEL: icmpNe64
 ; CHECK: jne
 ; CHECK: jne
 ; CHECK: call
@@ -744,7 +744,7 @@ if.end3:                                          ; preds = %if.end, %if.then2
 ; CHECK: jne
 ; CHECK: call
 ;
-; OPTM1: icmpNe64:
+; OPTM1-LABEL: icmpNe64
 ; OPTM1: jne
 ; OPTM1: jne
 ; OPTM1: call
@@ -772,7 +772,7 @@ if.then2:                                         ; preds = %if.end
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
-; CHECK: icmpGt64:
+; CHECK-LABEL: icmpGt64
 ; CHECK: ja
 ; CHECK: jb
 ; CHECK: ja
@@ -782,7 +782,7 @@ if.end3:                                          ; preds = %if.then2, %if.end
 ; CHECK: ja
 ; CHECK: call
 ;
-; OPTM1: icmpGt64:
+; OPTM1-LABEL: icmpGt64
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: ja
@@ -812,7 +812,7 @@ if.then2:                                         ; preds = %if.end
 if.end3:                                          ; preds = %if.end, %if.then2
   ret void
 }
-; CHECK: icmpGe64:
+; CHECK-LABEL: icmpGe64
 ; CHECK: ja
 ; CHECK: jb
 ; CHECK: jae
@@ -822,7 +822,7 @@ if.end3:                                          ; preds = %if.end, %if.then2
 ; CHECK: jae
 ; CHECK: call
 ;
-; OPTM1: icmpGe64:
+; OPTM1-LABEL: icmpGe64
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: jae
@@ -852,7 +852,7 @@ if.then2:                                         ; preds = %if.end
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
-; CHECK: icmpLt64:
+; CHECK-LABEL: icmpLt64
 ; CHECK: jb
 ; CHECK: ja
 ; CHECK: jb
@@ -862,7 +862,7 @@ if.end3:                                          ; preds = %if.then2, %if.end
 ; CHECK: jb
 ; CHECK: call
 ;
-; OPTM1: icmpLt64:
+; OPTM1-LABEL: icmpLt64
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: jb
@@ -892,7 +892,7 @@ if.then2:                                         ; preds = %if.end
 if.end3:                                          ; preds = %if.end, %if.then2
   ret void
 }
-; CHECK: icmpLe64:
+; CHECK-LABEL: icmpLe64
 ; CHECK: jb
 ; CHECK: ja
 ; CHECK: jbe
@@ -902,7 +902,7 @@ if.end3:                                          ; preds = %if.end, %if.then2
 ; CHECK: jbe
 ; CHECK: call
 ;
-; OPTM1: icmpLe64:
+; OPTM1-LABEL: icmpLe64
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: jbe
@@ -918,11 +918,11 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpEq64Bool:
+; CHECK-LABEL: icmpEq64Bool
 ; CHECK: jne
 ; CHECK: jne
 ;
-; OPTM1: icmpEq64Bool:
+; OPTM1-LABEL: icmpEq64Bool
 ; OPTM1: jne
 ; OPTM1: jne
 
@@ -932,11 +932,11 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpNe64Bool:
+; CHECK-LABEL: icmpNe64Bool
 ; CHECK: jne
 ; CHECK: jne
 ;
-; OPTM1: icmpNe64Bool:
+; OPTM1-LABEL: icmpNe64Bool
 ; OPTM1: jne
 ; OPTM1: jne
 
@@ -946,14 +946,14 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpSgt64Bool:
+; CHECK-LABEL: icmpSgt64Bool
 ; CHECK: cmp
 ; CHECK: jg
 ; CHECK: jl
 ; CHECK: cmp
 ; CHECK: ja
 ;
-; OPTM1: icmpSgt64Bool:
+; OPTM1-LABEL: icmpSgt64Bool
 ; OPTM1: cmp
 ; OPTM1: jg
 ; OPTM1: jl
@@ -966,14 +966,14 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpUgt64Bool:
+; CHECK-LABEL: icmpUgt64Bool
 ; CHECK: cmp
 ; CHECK: ja
 ; CHECK: jb
 ; CHECK: cmp
 ; CHECK: ja
 ;
-; OPTM1: icmpUgt64Bool:
+; OPTM1-LABEL: icmpUgt64Bool
 ; OPTM1: cmp
 ; OPTM1: ja
 ; OPTM1: jb
@@ -986,14 +986,14 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpSge64Bool:
+; CHECK-LABEL: icmpSge64Bool
 ; CHECK: cmp
 ; CHECK: jg
 ; CHECK: jl
 ; CHECK: cmp
 ; CHECK: jae
 ;
-; OPTM1: icmpSge64Bool:
+; OPTM1-LABEL: icmpSge64Bool
 ; OPTM1: cmp
 ; OPTM1: jg
 ; OPTM1: jl
@@ -1006,14 +1006,14 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpUge64Bool:
+; CHECK-LABEL: icmpUge64Bool
 ; CHECK: cmp
 ; CHECK: ja
 ; CHECK: jb
 ; CHECK: cmp
 ; CHECK: jae
 ;
-; OPTM1: icmpUge64Bool:
+; OPTM1-LABEL: icmpUge64Bool
 ; OPTM1: cmp
 ; OPTM1: ja
 ; OPTM1: jb
@@ -1026,14 +1026,14 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpSlt64Bool:
+; CHECK-LABEL: icmpSlt64Bool
 ; CHECK: cmp
 ; CHECK: jl
 ; CHECK: jg
 ; CHECK: cmp
 ; CHECK: jb
 ;
-; OPTM1: icmpSlt64Bool:
+; OPTM1-LABEL: icmpSlt64Bool
 ; OPTM1: cmp
 ; OPTM1: jl
 ; OPTM1: jg
@@ -1046,14 +1046,14 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpUlt64Bool:
+; CHECK-LABEL: icmpUlt64Bool
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
 ; CHECK: cmp
 ; CHECK: jb
 ;
-; OPTM1: icmpUlt64Bool:
+; OPTM1-LABEL: icmpUlt64Bool
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
@@ -1066,14 +1066,14 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpSle64Bool:
+; CHECK-LABEL: icmpSle64Bool
 ; CHECK: cmp
 ; CHECK: jl
 ; CHECK: jg
 ; CHECK: cmp
 ; CHECK: jbe
 ;
-; OPTM1: icmpSle64Bool:
+; OPTM1-LABEL: icmpSle64Bool
 ; OPTM1: cmp
 ; OPTM1: jl
 ; OPTM1: jg
@@ -1086,14 +1086,14 @@ entry:
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
-; CHECK: icmpUle64Bool:
+; CHECK-LABEL: icmpUle64Bool
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
 ; CHECK: cmp
 ; CHECK: jbe
 ;
-; OPTM1: icmpUle64Bool:
+; OPTM1-LABEL: icmpUle64Bool
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
@@ -1106,12 +1106,12 @@ entry:
   %v0 = load i64* %__1, align 1
   ret i64 %v0
 }
-; CHECK: load64:
+; CHECK-LABEL: load64
 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]]
 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]+4]
 ;
-; OPTM1: load64:
+; OPTM1-LABEL: load64
 ; OPTM1: mov e{{..}}, dword ptr [e{{..}}]
 ; OPTM1: mov e{{..}}, dword ptr [e{{..}}+4]
 
@@ -1121,12 +1121,12 @@ entry:
   store i64 %value, i64* %__2, align 1
   ret void
 }
-; CHECK: store64:
+; CHECK-LABEL: store64
 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
 ; CHECK: mov dword ptr [e[[REGISTER]]+4],
 ; CHECK: mov dword ptr [e[[REGISTER]]],
 ;
-; OPTM1: store64:
+; OPTM1-LABEL: store64
 ; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4],
 ; OPTM1: mov dword ptr [e[[REGISTER]]],
 
@@ -1136,12 +1136,12 @@ entry:
   store i64 -2401053092306725256, i64* %a.asptr, align 1
   ret void
 }
-; CHECK: store64Const:
+; CHECK-LABEL: store64Const
 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
 ; CHECK: mov dword ptr [e[[REGISTER]]+4], 3735928559
 ; CHECK: mov dword ptr [e[[REGISTER]]], 305419896
 ;
-; OPTM1: store64Const:
+; OPTM1-LABEL: store64Const
 ; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4], 3735928559
 ; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896
 
@@ -1151,7 +1151,7 @@ entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 }
-; CHECK: select64VarVar:
+; CHECK-LABEL: select64VarVar
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
@@ -1160,7 +1160,7 @@ entry:
 ; CHECK: cmp
 ; CHECK: jne
 ;
-; OPTM1: select64VarVar:
+; OPTM1-LABEL: select64VarVar
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
@@ -1175,7 +1175,7 @@ entry:
   %cond = select i1 %cmp, i64 %a, i64 -2401053092306725256
   ret i64 %cond
 }
-; CHECK: select64VarConst:
+; CHECK-LABEL: select64VarConst
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
@@ -1184,7 +1184,7 @@ entry:
 ; CHECK: cmp
 ; CHECK: jne
 ;
-; OPTM1: select64VarConst:
+; OPTM1-LABEL: select64VarConst
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
@@ -1199,7 +1199,7 @@ entry:
   %cond = select i1 %cmp, i64 -2401053092306725256, i64 %b
   ret i64 %cond
 }
-; CHECK: select64ConstVar:
+; CHECK-LABEL: select64ConstVar
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
@@ -1208,7 +1208,7 @@ entry:
 ; CHECK: cmp
 ; CHECK: jne
 ;
-; OPTM1: select64ConstVar:
+; OPTM1-LABEL: select64ConstVar
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
@@ -1217,5 +1217,59 @@ entry:
 ; OPTM1: cmp
 ; OPTM1: jne
 
+define internal void @icmpEq64Imm() {
+entry:
+  %cmp = icmp eq i64 123, 234
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  call void @func()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  %cmp1 = icmp eq i64 345, 456
+  br i1 %cmp1, label %if.then2, label %if.end3
+
+if.then2:                                         ; preds = %if.end
+  call void @func()
+  br label %if.end3
+
+if.end3:                                          ; preds = %if.then2, %if.end
+  ret void
+}
+; The following checks are not strictly necessary since one of the RUN
+; lines actually runs the output through the assembler.
+; CHECK-LABEL: icmpEq64Imm
+; CHECK-NOT: cmp {{[0-9]+}},
+; OPTM1-LABEL: icmpEq64Imm
+; OPTM1-LABEL-NOT: cmp {{[0-9]+}},
+
+define internal void @icmpLt64Imm() {
+entry:
+  %cmp = icmp ult i64 123, 234
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  call void @func()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  %cmp1 = icmp slt i64 345, 456
+  br i1 %cmp1, label %if.then2, label %if.end3
+
+if.then2:                                         ; preds = %if.end
+  call void @func()
+  br label %if.end3
+
+if.end3:                                          ; preds = %if.then2, %if.end
+  ret void
+}
+; The following checks are not strictly necessary since one of the RUN
+; lines actually runs the output through the assembler.
+; CHECK-LABEL: icmpLt64Imm
+; CHECK-NOT: cmp {{[0-9]+}},
+; OPTM1-LABEL: icmpLt64Imm
+; OPTM1-NOT: cmp {{[0-9]+}},
+
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ

diff --git a/tests_lit/llvm2ice_tests/arith-opt.ll b/tests_lit/llvm2ice_tests/arith-opt.ll
index fff8e3f..bc1a6a3 100644 (file)
--- a/tests_lit/llvm2ice_tests/arith-opt.ll
+++ b/tests_lit/llvm2ice_tests/arith-opt.ll
@@ -111,5 +111,15 @@ entry:
   ret i32 %rem
 }
 
+; Check for a valid addressing mode in the x86-32 mul instruction when
+; the second source operand is an immediate.
+define i64 @MulImm() {
+entry:
+  %mul = mul i64 3, 4
+  ret i64 %mul
+}
+; CHECK-LABEL: MulImm
+; CHECK-NOT: mul {{[0-9]+}}
+
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ

diff --git a/tests_lit/llvm2ice_tests/bool-opt.ll b/tests_lit/llvm2ice_tests/bool-opt.ll
index 40cc44b..2484327 100644 (file)
--- a/tests_lit/llvm2ice_tests/bool-opt.ll
+++ b/tests_lit/llvm2ice_tests/bool-opt.ll
@@ -14,6 +14,18 @@ entry:
   ret void
 }
 
+; Check that correct addressing modes are used for comparing two
+; immediates.
+define void @testIcmpImm() {
+entry:
+  %cmp = icmp eq i32 1, 2
+  %cmp_ext = zext i1 %cmp to i32
+  tail call void @use(i32 %cmp_ext)
+  ret void
+}
+; CHECK-LABEL: testIcmpImm
+; CHECK-NOT: cmp {{[0-9]+}},
+
 declare void @use(i32)
 
 ; CHECK-NOT: ICE translation error

diff --git a/tests_lit/llvm2ice_tests/select-opt.ll b/tests_lit/llvm2ice_tests/select-opt.ll
index 1d2e2e0..83a3d42 100644 (file)
--- a/tests_lit/llvm2ice_tests/select-opt.ll
+++ b/tests_lit/llvm2ice_tests/select-opt.ll
@@ -36,5 +36,26 @@ declare void @useInt(i32)
 ; CHECK:      call useInt
 ; CHECK:      ret
 
+; Check for valid addressing mode in the cmp instruction when the
+; operand is an immediate.
+define i32 @testSelectImm32(i32 %a, i32 %b) {
+entry:
+  %cond = select i1 0, i32 %a, i32 %b
+  ret i32 %cond
+}
+; CHECK-LABEL: testSelectImm32
+; CHECK-NOT: cmp {{[0-9]+}},
+
+; Check for valid addressing mode in the cmp instruction when the
+; operand is an immediate.  There is a different x86-32 lowering
+; sequence for 64-bit operands.
+define i64 @testSelectImm64(i64 %a, i64 %b) {
+entry:
+  %cond = select i1 1, i64 %a, i64 %b
+  ret i64 %cond
+}
+; CHECK-LABEL: testSelectImm64
+; CHECK-NOT: cmp {{[0-9]+}},
+
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ

diff --git a/tests_lit/llvm2ice_tests/switch-opt.ll b/tests_lit/llvm2ice_tests/switch-opt.ll
index 19187e4..710879c 100644 (file)
--- a/tests_lit/llvm2ice_tests/switch-opt.ll
+++ b/tests_lit/llvm2ice_tests/switch-opt.ll
@@ -37,6 +37,22 @@ sw.epilog:                                        ; preds = %sw.bb2, %sw.default
   ret i32 %result.1
 }
 
+; Check for a valid addressing mode when the switch operand is an
+; immediate.  It's important that there is exactly one case, because
+; for two or more cases the source operand is legalized into a
+; register.
+define i32 @testSwitchImm() {
+entry:
+  switch i32 10, label %sw.default [
+    i32 1, label %sw.default
+  ]
+
+sw.default:
+  ret i32 20
+}
+; CHECK-LABEL: testSwitchImm
+; CHECK-NOT: cmp {{[0-9]*}},
+
 ; CHECK-NOT: ICE translation error
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ