Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300905
91177308-0d34-0410-b5e6-
96231b3b80d8
AArch64::XZR, NextMBBI);
case AArch64::CMP_SWAP_128:
return expandCMP_SWAP_128(MBB, MBBI, NextMBBI);
+
}
return false;
}
//===----------------------------------
// Atomic fences
//===----------------------------------
+let AddedComplexity = 15, Size = 0 in
+def CompilerBarrier : Pseudo<(outs), (ins i32imm:$ordering),
+ [(atomic_fence imm:$ordering, 0)]>, Sched<[]>;
def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
}
}
+ if (Opcode == AArch64::CompilerBarrier) {
+ O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
+ printAnnotation(O, Annot);
+ return;
+ }
+
if (!printAliasInstr(MI, STI, O))
printInstruction(MI, STI, O);
MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
return;
+ } else if (MI.getOpcode() == AArch64::CompilerBarrier) {
+ // This just prevents the compiler from reordering accesses, no actual code.
+ return;
}
uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);