drm/i915/xehpsdv: factor out function to read RP_STATE_CAP

Instead of maintaining the same if ladder in 3 different places, add a
function to read RP_STATE_CAP.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210805163647.801064-6-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index d6f5836..f6733f2 100644 (file)
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -309,13 +309,11 @@ static int frequency_show(struct seq_file *m, void *unused)
                int max_freq;
 
                rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
-               if (IS_GEN9_LP(i915)) {
-                       rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
+               rp_state_cap = intel_rps_read_state_cap(rps);
+               if (IS_GEN9_LP(i915))
                        gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
-               } else {
-                       rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
+               else
                        gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
-               }
 
                /* RPSTAT1 is in the GT power well */
                intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index d812b27..a3e69eb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -996,20 +996,16 @@ int intel_rps_set(struct intel_rps *rps, u8 val)
 static void gen6_rps_init(struct intel_rps *rps)
 {
        struct drm_i915_private *i915 = rps_to_i915(rps);
-       struct intel_uncore *uncore = rps_to_uncore(rps);
+       u32 rp_state_cap = intel_rps_read_state_cap(rps);
 
        /* All of these values are in units of 50MHz */
 
        /* static values from HW: RP0 > RP1 > RPn (min_freq) */
        if (IS_GEN9_LP(i915)) {
-               u32 rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
-
                rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
                rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
                rps->min_freq = (rp_state_cap >>  0) & 0xff;
        } else {
-               u32 rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
-
                rps->rp0_freq = (rp_state_cap >>  0) & 0xff;
                rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
                rps->min_freq = (rp_state_cap >> 16) & 0xff;
@@ -2140,6 +2136,17 @@ int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val)
                return set_min_freq(rps, val);
 }
 
+u32 intel_rps_read_state_cap(struct intel_rps *rps)
+{
+       struct drm_i915_private *i915 = rps_to_i915(rps);
+       struct intel_uncore *uncore = rps_to_uncore(rps);
+
+       if (IS_GEN9_LP(i915))
+               return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
+       else
+               return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
+}
+
 /* External interface for intel_ips.ko */
 
 static struct drm_i915_private __rcu *ips_mchdev;

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 4213bcc..11960d6 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -41,6 +41,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
 u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
 u32 intel_rps_read_punit_req(struct intel_rps *rps);
 u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_state_cap(struct intel_rps *rps);
 
 void gen5_rps_irq_handler(struct intel_rps *rps);
 void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index cc74575..6c83da3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -420,13 +420,11 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                int max_freq;
 
                rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS);
-               if (IS_GEN9_LP(dev_priv)) {
-                       rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP);
+               rp_state_cap = intel_rps_read_state_cap(rps);
+               if (IS_GEN9_LP(dev_priv))
                        gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS);
-               } else {
-                       rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP);
+               else
                        gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS);
-               }
 
                /* RPSTAT1 is in the GT power well */
                intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);