+++ /dev/null
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:40 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
-*/\r
-\r
-module FIFO ( p_reset , m_clock );\r
- input p_reset, m_clock;\r
-\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:40 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Jul 23 20:50:38 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 25 23:44:36 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
*/\r
\r
-module vga_gen ( m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , outled );\r
+module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_we1 , i_wrdata1 , i_we2 , i_wrdata2 , i_fifo1_rst , i_fifo2_rst , outled );\r
+ input i_clk50M;\r
input m_clock;\r
input p_reset;\r
output o_vsync;\r
output [3:0] o_vga_r;\r
output [3:0] o_vga_g;\r
output [3:0] o_vga_b;\r
+ input i_we1;\r
+ input [7:0] i_wrdata1;\r
+ input i_we2;\r
+ input [7:0] i_wrdata2;\r
+ input i_fifo1_rst;\r
+ input i_fifo2_rst;\r
output outled;\r
+ wire fi_fifo1_read;\r
+ wire fi_fifo2_read;\r
reg r_vsync;\r
reg r_hsync;\r
reg [9:0] r_vcnt;\r
reg testled;\r
reg [2:0] r_outcnt;\r
reg [6:0] r_outclr;\r
+ wire _u_FIFO_p_reset;\r
+ wire _u_FIFO_m_clock;\r
+ wire _u_FIFO_i_we1;\r
+ wire [7:0] _u_FIFO_i_wdata1;\r
+ wire _u_FIFO_i_we2;\r
+ wire [7:0] _u_FIFO_i_wdata2;\r
+ wire [7:0] _u_FIFO_o_rddata1;\r
+ wire [7:0] _u_FIFO_o_rddata2;\r
+ wire _u_FIFO_i_clock;\r
+ wire _u_FIFO_i_re1;\r
+ wire _u_FIFO_i_re2;\r
+ wire _u_FIFO_i_fifo1_rst;\r
+ wire _u_FIFO_i_fifo2_rst;\r
+ wire _u_FIFO_o_rdack1;\r
+ wire _u_FIFO_o_rdack2;\r
wire _net_0;\r
wire _net_1;\r
wire _net_2;\r
wire _net_35;\r
wire _net_36;\r
wire _net_37;\r
+vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_fifo2_rst(_u_FIFO_i_fifo2_rst), .i_fifo1_rst(_u_FIFO_i_fifo1_rst), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wdata2(_u_FIFO_i_wdata2), .i_we2(_u_FIFO_i_we2), .i_wdata1(_u_FIFO_i_wdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));\r
\r
+ assign fi_fifo1_read = 1'b0;\r
+ assign fi_fifo2_read = 1'b0;\r
+ assign _u_FIFO_m_clock = i_clk50M;\r
+ assign _u_FIFO_i_we1 = i_we1;\r
+ assign _u_FIFO_i_wdata1 = i_wrdata1;\r
+ assign _u_FIFO_i_we2 = i_we2;\r
+ assign _u_FIFO_i_wdata2 = i_wrdata2;\r
+ assign _u_FIFO_i_clock = m_clock;\r
+ assign _u_FIFO_i_re1 = fi_fifo1_read;\r
+ assign _u_FIFO_i_re2 = fi_fifo2_read;\r
+ assign _u_FIFO_i_fifo1_rst = i_fifo1_rst;\r
+ assign _u_FIFO_i_fifo2_rst = i_fifo2_rst;\r
assign _net_0 = (cnt)==(26'b01011111010111100001000000);\r
assign _net_1 = ~_net_0;\r
assign _net_2 = (r_hcnt) < (10'b1100100000);\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Jul 23 20:50:40 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 25 23:44:38 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
* @version 1.2
*/
-#include "vga_ram.nsh"
+#include "vga_ram.nsh" // vga ram module
#define H_ACT_MAX 10'd640
#define H_FRONTP_MAX 10'd656
#define V_SYNC_MAX 10'd492
#define V_BACKP_MAX 10'd521
-
-
#define VCNT_1SEC 26'd25000000
declare vga_gen interface {
-// input i_clk50M ; // 50MHz main clock
+ input i_clk50M ; // 50MHz main clock
input m_clock ;
input p_reset ;
output o_vsync ;
output o_vga_r[4] ;
output o_vga_g[4] ;
output o_vga_b[4] ;
+
+ input i_we1 ;
+ input i_wrdata1[8] ;
+ input i_we2 ;
+ input i_wrdata2[8] ;
-// input i_color_mode[2] ;
+ input i_fifo1_rst ;
+ input i_fifo2_rst ;
-// input i_wrdata1[8] ;
-// input i_wrdata2[8] ;
-// func_in fi_fifo1_write( i_wrdata1 ) ;
-// func_in fi_fifo2_write( i_wrdata2 ) ;
output outled ;
}
module vga_gen {
-// func_self fs_fifo1_rst ;
-// func_self fs_fifo2_rst ;
+ func_self fi_fifo1_read() ;
+ func_self fi_fifo2_read() ;
reg r_vsync = 0 ;
reg r_hsync = 0 ;
reg testled = 0 ;
reg r_outcnt[3] = 0 ;
reg r_outclr[7] = 0 ;
+
+ vga_ram u_FIFO ;
{
+ /* FIFO assign */
+ u_FIFO.m_clock = i_clk50M ;
+ u_FIFO.i_we1 = i_we1 ;
+ u_FIFO.i_wdata1 = i_wrdata1 ;
+ u_FIFO.i_we2 = i_we2 ;
+ u_FIFO.i_wdata2 = i_wrdata2 ;
+ u_FIFO.i_fifo1_rst = i_fifo1_rst ;
+ u_FIFO.i_fifo2_rst = i_fifo2_rst ;
+ u_FIFO.i_clock = m_clock ;
+
/* LED test */
outled = testled ;
o_vsync = r_vsync ;
}
if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) {
+
+ /* \83J\83\89\81[\83o\81[\8dì\90¬ */
if( r_outcnt < 3'd4 ) {
r_outcnt++ ;
} else {
r_outcnt := 0 ;
r_outclr++ ;
}
-
- /* \83J\83\89\81[\83o\81[\8dì\90¬ */
+
if( ~r_outclr[4]) o_vga_b = ~r_outclr[3:0] ;
else o_vga_b = 0 ;
} else {
any {
r_hcnt == H_ACT_MAX : {
+ /* VGA\81@null\81@ */
o_vga_r = 0 ;
o_vga_g = 0 ;
o_vga_b = 0 ;
}
}
+ func fi_fifo1_read {
+ u_FIFO.i_re1 = 1 ;
+ }
+
+ func fi_fifo2_read {
+ u_FIFO.i_re2 = 1 ;
+ }
+
} //module end
\ No newline at end of file
input m_clock ;
input i_we1 ;
- input i_wdata1[32] ;
+ input i_wdata1[8] ;
input i_we2 ;
- input i_wdata2[32] ;
+ input i_wdata2[8] ;
- output o_rddata1[32] ;
- output o_rddata2[32] ;
+ output o_rddata1[8] ;
+ output o_rddata2[8] ;
input i_clock ;
\r
input p_reset ;\r
input m_clock ;\r
-\r
input i_clock ;\r
\r
input i_we1 ;\r
- input [31:0] i_wdata1 ;\r
-\r
+ input [7:0] i_wdata1 ;\r
input i_we2 ;\r
- input [31:0] i_wdata2 ;\r
+ input [7:0] i_wdata2 ;\r
\r
- output [31:0] o_rddata1 ;\r
-\r
- output [31:0] o_rddata2 ;\r
+ output [23:0] o_rddata1 ;\r
+ output [23:0] o_rddata2 ;\r
\r
input i_re1 ;\r
input i_re2 ;\r
reg r_hld_re1 = 0 ;\r
reg r_hld_re2 = 0 ;\r
\r
- reg [4:0] r_wradrs1 = 0 ;\r
- reg [4:0] r_wradrs2 = 0 ;\r
-\r
- reg [4:0] r_rdadrs1 = 0 ;\r
- reg [4:0] r_rdadrs2 = 0 ;\r
+ reg [7:0] r_wradrs1 = 0 ;\r
+ reg [7:0] r_wradrs2 = 0 ;\r
+ reg [7:0] r_rdadrs1 = 0 ;\r
+ reg [7:0] r_rdadrs2 = 0 ;\r
\r
- (* remstyle = "no_rw_check" *) reg [31:0] mem1[31:0] ;\r
- (* remstyle = "no_rw_check" *) reg [31:0] mem2[31:0] ;\r
+ (* remstyle = "no_rw_check" *) reg [7:0] mem1[255:0] ;\r
+ (* remstyle = "no_rw_check" *) reg [7:0] mem2[255:0] ;\r
\r
assign o_rdack1 = r_hld_re1 ;\r
assign o_rdack2 = r_hld_re2 ;\r
\r
// memory write command\r
always @ ( posedge i_clock ) begin\r
- if( we1 ) begin\r
+ if( i_we1 ) begin\r
mem1[r_wradrs1] <= i_wdata1 ;\r
- r_wradrs1++ ;\r
+ r_wradrs1 = r_wradrs1 + 1 ;\r
end\r
end\r
\r
always @ ( posedge i_clock ) begin\r
- if( we2 ) begin\r
- mem1[r_wradrs2] <= i_wdata2 ;\r
- r_wradrs2++ ;\r
+ if( i_we2 ) begin\r
+ mem2[r_wradrs2] <= i_wdata2 ;\r
+ r_wradrs2 = r_wradrs2 + 1 ;\r
end\r
end\r
\r
always @ ( posedge m_clock ) begin\r
- if( i_re1 ) r_rdadrs1++ ;\r
+ if( i_re1 ) r_rdadrs1 = r_rdadrs1 + 3'd3 ;\r
end\r
\r
always @ ( posedge m_clock ) begin\r
- if( i_re2 ) r_rdadrs2++ ;\r
+ if( i_re2 ) r_rdadrs2 = r_rdadrs2 + 3'd3 ;\r
end\r
\r
always @ ( posedge m_clock ) begin\r
r_hld_re2 = i_re2 ;\r
end\r
\r
- assign q = mem1[r_rdadrs1] ;\r
- assign q = mem2[r_rdadrs2] ;\r
+ assign o_rddata1 = {\r
+ mem1[r_rdadrs1+8'd2],\r
+ mem1[r_rdadrs1+8'd1],\r
+ mem1[r_rdadrs1]\r
+ } ;\r
+ assign o_rddata2 = {\r
+ mem2[r_rdadrs2+8'd2],\r
+ mem2[r_rdadrs2+8'd1],\r
+ mem2[r_rdadrs2]\r
+ } ;\r
\r
always @ ( posedge i_clock ) begin\r
if( i_fifo1_rst ) begin\r
- r_wradrs1 = 5'd0 ;\r
- r_wradrs2 = 5'd0 ;\r
+ r_wradrs1 = 8'd0 ;\r
+ r_rdadrs1 = 8'd0 ;\r
end\r
\r
if( i_fifo2_rst ) begin\r
- r_rdadrs1 = 5'd0 ;\r
- r_rdadrs2 = 5'd0 ;\r
+ r_wradrs2 = 8'd0 ;\r
+ r_rdadrs2 = 8'd0 ;\r
end\r
- end\r
- \r
+ end \r
endmodule
\ No newline at end of file
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