drm/i915/mtl: C20 port clock calculation

Calculate port clock with C20 phy.

BSpec: 64568

Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-5-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 8a014f4..aa8fc7b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2283,6 +2283,51 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
        return tmpclk;
 }
 
+int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+                                const struct intel_c20pll_state *pll_state)
+{
+       unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
+       unsigned int multiplier, refclk = 38400;
+       unsigned int tx_clk_div;
+       unsigned int ref_clk_mpllb_div;
+       unsigned int fb_clk_div4_en;
+       unsigned int ref, vco;
+       unsigned int tx_rate_mult;
+       unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
+
+       if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
+               tx_rate_mult = 1;
+               frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
+               frac_quot = pll_state->mpllb[8];
+               frac_rem =  pll_state->mpllb[9];
+               frac_den =  pll_state->mpllb[7];
+               multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
+               tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
+               ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
+               fb_clk_div4_en = 0;
+       } else {
+               tx_rate_mult = 2;
+               frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
+               frac_quot = pll_state->mplla[8];
+               frac_rem =  pll_state->mplla[9];
+               frac_den =  pll_state->mplla[7];
+               multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
+               tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
+               ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
+               fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
+       }
+
+       if (frac_en)
+               frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
+       else
+               frac = 0;
+
+       ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
+       vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
+
+       return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
+}
+
 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
                                         const struct intel_crtc_state *crtc_state,
                                         bool lane_reversal)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c643aae..83bd350 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -34,6 +34,8 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
                                   struct intel_c20pll_state *pll_state);
 void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
                                const struct intel_c20pll_state *hw_state);
+int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+                                const struct intel_c20pll_state *pll_state);
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
                                     const struct intel_crtc_state *crtc_state);
 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index bfb39bc..d3de4df 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -196,16 +196,19 @@
 #define   PHY_C20_CUSTOM_WIDTH(val)    REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
 #define PHY_C20_A_TX_CNTX_CFG(idx)     (0xCF2E - (idx))
 #define PHY_C20_B_TX_CNTX_CFG(idx)     (0xCF2A - (idx))
+#define   C20_PHY_TX_RATE              REG_GENMASK(2, 0)
 #define PHY_C20_A_CMN_CNTX_CFG(idx)    (0xCDAA - (idx))
 #define PHY_C20_B_CMN_CNTX_CFG(idx)    (0xCDA5 - (idx))
 #define PHY_C20_A_MPLLA_CNTX_CFG(idx)  (0xCCF0 - (idx))
 #define PHY_C20_B_MPLLA_CNTX_CFG(idx)  (0xCCE5 - (idx))
 #define   C20_MPLLA_FRACEN             REG_BIT(14)
+#define   C20_FB_CLK_DIV4_EN           REG_BIT(13)
 #define   C20_MPLLA_TX_CLK_DIV_MASK    REG_GENMASK(10, 8)
 #define PHY_C20_A_MPLLB_CNTX_CFG(idx)  (0xCB5A - (idx))
 #define PHY_C20_B_MPLLB_CNTX_CFG(idx)  (0xCB4E - (idx))
 #define   C20_MPLLB_TX_CLK_DIV_MASK    REG_GENMASK(15, 13)
 #define   C20_MPLLB_FRACEN             REG_BIT(13)
+#define   C20_REF_CLK_MPLLB_DIV_MASK   REG_GENMASK(12, 10)
 #define   C20_MULTIPLIER_MASK          REG_GENMASK(11, 0)
 #define   C20_PHY_USE_MPLLB            REG_BIT(7)
 

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2a0aa42..ff4d8d6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3856,13 +3856,13 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
        if (intel_is_c10phy(i915, phy)) {
                intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
                intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
+               crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
        } else {
                intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
                intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
+               crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
        }
 
-       crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
-
        intel_ddi_get_config(encoder, crtc_state);
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index a9fbef0..ca0f362 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1014,6 +1014,8 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
        /* TODO: Do the readback via intel_compute_shared_dplls() */
        if (intel_is_c10phy(i915, phy))
                crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
+       else
+               crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
 
        crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);