[Hexagon] Avoid predicate copies to integer registers from store-locked

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332260 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td
index 91e03b5..3615633 100644 (file)
--- a/lib/Target/Hexagon/HexagonPatterns.td
+++ b/lib/Target/Hexagon/HexagonPatterns.td
@@ -2910,3 +2910,18 @@ def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf,
   [SDNPHasChain]>;
 
 def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>;
+
+// The declared return value of the store-locked intrinsics is i32, but
+// the instructions actually define i1. To avoid register copies from
+// IntRegs to PredRegs and back, fold the entire pattern checking the
+// result against true/false.
+let AddedComplexity = 100 in {
+  def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
+           (S2_storew_locked I32:$Rs, I32:$Rt)>;
+  def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
+           (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>;
+  def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
+           (S4_stored_locked I32:$Rs, I64:$Rt)>;
+  def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
+           (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>;
+}

diff --git a/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll b/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
index 23baa2d..87f832e 100644 (file)
--- a/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
+++ b/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
@@ -39,7 +39,7 @@ BINARY_OP_entry:
 ; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
 ; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
 
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
 ; CHECK-DAG: memw(gp+#i32Result) = [[LOCKED_READ_REG]]
 ; CHECK-DAG: jumpr r31
 
@@ -60,7 +60,7 @@ entry:
 ; CHECK: [[RESULT_REG:r[0-9]+:[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
 ; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
 
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
 ; CHECK-DAG: memd(gp+#i64Result) = [[LOCKED_READ_REG]]
 ; CHECK-DAG: jumpr r31
 
@@ -81,7 +81,7 @@ entry:
 ; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
 ; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
 
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
 ; CHECK-DAG: memw(gp+#ptrResult) = [[LOCKED_READ_REG]]
 ; CHECK-DAG: jumpr r31
 

diff --git a/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll b/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
index 5beecc7..df5198b 100644 (file)
--- a/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
+++ b/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
@@ -32,7 +32,7 @@
 ; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
 ; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
 
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
 ; CHECK-DAG: memw(gp+#g2) = [[LOCKED_READ_REG]]
 ; CHECK-DAG: jumpr r31
 define void @f0() {
@@ -53,7 +53,7 @@ BINARY_OP_entry:
 ; CHECK: [[RESULT_REG:r[:0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
 ; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
 
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
 ; CHECK-DAG: memd(gp+#g5) = [[LOCKED_READ_REG]]
 ; CHECK-DAG: jumpr r31
 define void @f1() {

diff --git a/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll b/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
index 5a97de1..15c94d6 100644 (file)
--- a/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
+++ b/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
@@ -22,7 +22,7 @@
 ; CHECK: [[RESULT_REG:r[0-9]+]] = sub(#-1,[[AND_RESULT_REG]])
 ; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
 
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
 ; CHECK-DAG: memw(gp+#g2) = [[LOCKED_READ_REG]]
 ; CHECK-DAG: jumpr r31
 define void @f0() {
@@ -44,7 +44,7 @@ b0:
 ; CHECK: [[RESULT_REG:r[:0-9]+]] = not([[AND_RESULT_REG]])
 ; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
 
-; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
+; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
 ; CHECK-DAG: memd(gp+#g5) = [[LOCKED_READ_REG]]
 ; CHECK-DAG: jumpr r31
 define void @f1() {