cpu i/f r_nw > oe_n and we_n.

diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd
index f9653a7..cab1b44 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.vhd
+++ b/de0_cv_nes/de0_cv_nes.vhd
@@ -38,7 +38,8 @@ architecture rtl of de0_cv_nes is
                 pi_rdy         : in std_logic;\r
                 pi_irq_n       : in std_logic;\r
                 pi_nmi_n       : in std_logic;\r
-                po_r_nw        : out std_logic;\r
+                po_oe_n        : out std_logic;\r
+                po_we_n        : out std_logic;\r
                 po_addr        : out std_logic_vector ( 15 downto 0);\r
                 pio_d_io       : inout std_logic_vector ( 7 downto 0)\r
         );
@@ -68,6 +69,7 @@ architecture rtl of de0_cv_nes is
     component prg_rom port (\r
                 pi_base_clk    : in std_logic;\r
                 pi_ce_n         : in std_logic;\r
+                pi_oe_n         : in std_logic;\r
                 pi_addr         : in std_logic_vector (14 downto 0);\r
                 po_data         : out std_logic_vector (7 downto 0)\r
             );\r
@@ -78,7 +80,8 @@ architecture rtl of de0_cv_nes is
                 pi_base_clk    : in std_logic;
                 pi_cpu_en      : in std_logic_vector (7 downto 0);\r
                 pi_ce_n        : in std_logic;
-                pi_r_nw        : in std_logic;
+                pi_oe_n        : in std_logic;\r
+                pi_we_n        : in std_logic;\r
                 pi_cpu_addr    : in std_logic_vector (2 downto 0);
                 pio_cpu_d      : inout std_logic_vector (7 downto 0);
 
@@ -135,6 +138,7 @@ architecture rtl of de0_cv_nes is
         port (  \r
                 pi_base_clk     : in std_logic;\r
                 pi_ce_n         : in std_logic;\r
+                pi_oe_n         : in std_logic;\r
                 pi_addr         : in std_logic_vector (12 downto 0);\r
                 po_data         : out std_logic_vector (7 downto 0)\r
             );\r
@@ -206,9 +210,8 @@ signal wr_rnd_en       : std_logic_vector (3 downto 0);
 signal wr_rdy       : std_logic;\r
 signal wr_irq_n     : std_logic;\r
 signal wr_nmi_n     : std_logic;\r
-signal wr_r_nw      : std_logic;\r
---r_n is negative logic of wr_r_nw.\r
-signal lg_r_n       : std_logic;\r
+signal wr_oe_n      : std_logic;\r
+signal wr_we_n      : std_logic;\r
 \r
 signal wr_addr      : std_logic_vector ( 15 downto 0);\r
 signal wr_d_io      : std_logic_vector ( 7 downto 0);\r
@@ -268,7 +271,8 @@ begin
             wr_rdy,\r
             wr_irq_n, \r
             wr_nmi_n, \r
-            wr_r_nw, \r
+            wr_oe_n, \r
+            wr_we_n, \r
             wr_addr, \r
             wr_d_io\r
             );\r
@@ -288,18 +292,18 @@ begin
     prom_inst : prg_rom port map (\r
             pi_base_clk, \r
             wr_rom_ce_n,\r
+            wr_oe_n,\r
             wr_addr(14 downto 0), \r
             wr_d_io\r
             );\r
 \r
-    lg_r_n <= not wr_r_nw;\r
     --cpu ram inst.\r
     cpu_ram_inst : ram generic map\r
         (ram_2k, 8) port map (\r
             pi_base_clk,\r
             wr_ram_ce_n,\r
-            lg_r_n, \r
-            wr_r_nw, \r
+            wr_oe_n,\r
+            wr_we_n,\r
             wr_addr(10 downto 0), \r
             wr_d_io\r
             );\r
@@ -310,7 +314,8 @@ begin
             pi_base_clk, \r
             wr_cpu_en,\r
             wr_ppu_ce_n,\r
-            wr_r_nw, \r
+            wr_oe_n,\r
+            wr_we_n,\r
             wr_addr(2 downto 0), \r
             wr_d_io,\r
 \r
@@ -388,6 +393,7 @@ begin
     chr_rom_inst : chr_rom port map (\r
             pi_base_clk,\r
             wr_pt_ce_n,\r
+            wr_v_rd_n,\r
             wr_v_addr(12 downto 0),\r
             wr_v_data\r
             );\r

diff --git a/de0_cv_nes/dummy-ppu.vhd b/de0_cv_nes/dummy-ppu.vhd
index e867270..0f0993a 100644 (file)
--- a/de0_cv_nes/dummy-ppu.vhd
+++ b/de0_cv_nes/dummy-ppu.vhd
@@ -8,7 +8,8 @@ entity ppu is
                 pi_base_clk    : in std_logic;\r
                 pi_cpu_en      : in std_logic_vector (7 downto 0);\r
                 pi_ce_n        : in std_logic;\r
-                pi_r_nw        : in std_logic;\r
+                pi_oe_n        : in std_logic;\r
+                pi_we_n        : in std_logic;\r
                 pi_cpu_addr    : in std_logic_vector (2 downto 0);\r
                 pio_cpu_d      : inout std_logic_vector (7 downto 0);\r
 \r
@@ -162,6 +163,7 @@ entity chr_rom is
     port (  \r
             pi_base_clk     : in std_logic;\r
             pi_ce_n         : in std_logic;\r
+            pi_oe_n         : in std_logic;\r
             pi_addr         : in std_logic_vector (12 downto 0);\r
             po_data         : out std_logic_vector (7 downto 0)\r
         );\r

diff --git a/de0_cv_nes/mem/chr_rom.vhd b/de0_cv_nes/mem/chr_rom.vhd
index d35334d..679b12a 100644 (file)
--- a/de0_cv_nes/mem/chr_rom.vhd
+++ b/de0_cv_nes/mem/chr_rom.vhd
@@ -8,6 +8,7 @@ entity chr_rom is
     port (  
             pi_base_clk     : in std_logic;
             pi_ce_n         : in std_logic;
+            pi_oe_n         : in std_logic;
             pi_addr         : in std_logic_vector (12 downto 0);
             po_data         : out std_logic_vector (7 downto 0)
         );
@@ -58,7 +59,7 @@ begin
     p : process (pi_base_clk)
     begin
     if (rising_edge(pi_base_clk)) then
-        if (pi_ce_n = '0') then
+        if (pi_ce_n = '0' and pi_oe_n = '0') then
             po_data <= p_rom(conv_integer(pi_addr));
         else
             po_data <= (others => 'Z');

diff --git a/de0_cv_nes/mem/prg_rom.vhd b/de0_cv_nes/mem/prg_rom.vhd
index c56ad43..a37cea1 100644 (file)
--- a/de0_cv_nes/mem/prg_rom.vhd
+++ b/de0_cv_nes/mem/prg_rom.vhd
@@ -8,6 +8,7 @@ entity prg_rom is
     port (  
             pi_base_clk     : in std_logic;
             pi_ce_n         : in std_logic;
+            pi_oe_n         : in std_logic;
             pi_addr         : in std_logic_vector (14 downto 0);
             po_data         : out std_logic_vector (7 downto 0)
         );
@@ -53,7 +54,7 @@ begin
     p : process (pi_base_clk)
     begin
     if (rising_edge(pi_base_clk)) then
-        if (pi_ce_n = '0') then
+        if (pi_ce_n = '0' and pi_oe_n = '0') then
             po_data <= p_rom(conv_integer(pi_addr));
         else
             po_data <= (others => 'Z');

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index 3ac5cde..4b3b070 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -11,7 +11,8 @@ entity mos6502 is
             pi_rdy         : in std_logic;\r
             pi_irq_n       : in std_logic;\r
             pi_nmi_n       : in std_logic;\r
-            po_r_nw        : out std_logic;\r
+            po_oe_n        : out std_logic;\r
+            po_we_n        : out std_logic;\r
             po_addr        : out std_logic_vector ( 15 downto 0);\r
             pio_d_io       : inout std_logic_vector ( 7 downto 0)\r
     );\r
@@ -221,7 +222,8 @@ signal reg_tmp_h    : std_logic_vector (7 downto 0);
 signal reg_tmp_data : std_logic_vector (7 downto 0);\r
 \r
 --bus i/o reg.\r
-signal reg_r_nw     : std_logic;\r
+signal reg_oe_n     : std_logic;\r
+signal reg_we_n     : std_logic;\r
 signal reg_addr     : std_logic_vector (15 downto 0);\r
 signal reg_d_in     : std_logic_vector (7 downto 0);\r
 signal reg_d_out    : std_logic_vector (7 downto 0);\r
@@ -1001,7 +1003,8 @@ begin
     end process;\r
 \r
 \r
-    po_r_nw     <= reg_r_nw;\r
+    po_oe_n     <= reg_oe_n;\r
+    po_we_n     <= reg_we_n;\r
     po_addr     <= reg_addr;\r
     pio_d_io    <= reg_d_out;\r
 \r
@@ -1031,7 +1034,8 @@ end;
             reg_addr    <= (others => 'Z');\r
             reg_d_out   <= (others => 'Z');\r
             reg_d_in    <= (others => '0');\r
-            reg_r_nw    <= 'Z';\r
+            reg_oe_n    <= 'Z';\r
+            reg_we_n    <= 'Z';\r
             reg_tmp_pg_crossed  <= '0';\r
             calc_adl    := (others => '0');\r
         elsif (rising_edge(pi_base_clk)) then\r
@@ -1046,44 +1050,45 @@ end;
                 reg_inst    <= (others => '0');\r
                 reg_addr    <= (others => '0');\r
                 reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
+                reg_oe_n    <= '1';\r
+                reg_we_n    <= '1';\r
             elsif (reg_main_state = ST_RS_T3) then\r
                 --dummy sp out 1.\r
                 reg_addr    <= "11111111" & reg_sp;\r
                 reg_d_out   <= (others => '0');\r
-                reg_r_nw    <= '0';\r
+                reg_we_n    <= '0';\r
             elsif (reg_main_state = ST_RS_T4) then\r
                 --dummy sp out 2.\r
                 reg_addr    <= "11111111" & (reg_sp - 1);\r
                 reg_d_out   <= (others => '0');\r
-                reg_r_nw    <= '0';\r
+                reg_we_n    <= '0';\r
             elsif (reg_main_state = ST_RS_T5) then\r
                 --dummy sp out 3.\r
                 reg_addr    <= "11111111" & (reg_sp - 2);\r
                 reg_d_out   <= (others => '0');\r
-                reg_r_nw    <= '0';\r
+                reg_we_n    <= '0';\r
             elsif (reg_main_state = ST_RS_T6) then\r
                 --reset vector low...\r
                 reg_addr    <= "1111111111111100";\r
                 reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
+                reg_oe_n    <= '0';\r
+                reg_we_n    <= '1';\r
                 reg_pc_l    <= reg_d_in;\r
             elsif (reg_main_state = ST_RS_T7) then\r
                 --reset vector high...\r
                 reg_addr    <= "1111111111111101";\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
                 reg_pc_h    <= reg_d_in;\r
             elsif (reg_main_state = ST_CM_T0) then\r
                 --init pg crossing flag.\r
                 reg_tmp_pg_crossed <= '0';\r
                 calc_adl    := (others => '0');\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_oe_n    <= '0';\r
+                reg_we_n    <= '1';\r
 \r
                 if (reg_sub_state = ST_SUB00) then\r
                     --fetch next.\r
                     reg_addr    <= reg_pc_h & reg_pc_l;\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 elsif (reg_sub_state = ST_SUB30) then\r
                     --update instruction register.\r
                     reg_inst    <= reg_d_in;\r
@@ -1124,8 +1129,6 @@ end;
                 if (reg_sub_state = ST_SUB00) then\r
                     --fetch next.\r
                     reg_addr    <= reg_pc_h & reg_pc_l;\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 elsif (reg_sub_state = ST_SUB70) then\r
                     --pc move next.\r
                     pc_inc;\r
@@ -1146,23 +1149,17 @@ end;
                 --ind, y\r
                 --ial cycle.\r
                 reg_addr    <= "00000000" & reg_idl_l;\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
             elsif (reg_main_state = ST_A24_T3 or\r
                 reg_main_state = ST_A33_T3\r
                 ) then\r
                 --ind, x\r
                 --bal + x cycle.\r
                 reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
             elsif (reg_main_state = ST_A24_T4 or\r
                 reg_main_state = ST_A33_T4) then\r
                 --ind, x\r
                 --bal + x + 1 cycle.\r
                 reg_addr    <= "00000000" & (reg_idl_l + reg_x + 1);\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
             elsif (reg_main_state = ST_A25_T3 or\r
                 reg_main_state = ST_A34_T3 or\r
                 reg_main_state = ST_A44_T3\r
@@ -1206,8 +1203,6 @@ end;
                         calc_adl    := ("0" & reg_idl_l) + ("0" & reg_x);\r
                     end if; \r
                 end if;\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
 \r
                 reg_tmp_pg_crossed <= calc_adl(8);\r
             elsif (reg_main_state = ST_A27_T3 or\r
@@ -1215,15 +1210,11 @@ end;
                 --ind, y\r
                 --ial + 1 cycle.\r
                 reg_addr    <= "00000000" & (reg_idl_l + 1);\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
             elsif (reg_main_state = ST_A27_T4 or\r
                 reg_main_state = ST_A36_T4) then\r
                 --ind, y\r
                 --bal + y cycle.\r
                 reg_addr    <= reg_tmp_h & (reg_tmp_l + reg_y);\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
                 calc_adl    := ("0" & reg_tmp_l) + ("0" & reg_y);\r
                 reg_tmp_pg_crossed <= calc_adl(8);\r
             elsif (reg_main_state = ST_A51_T1 or\r
@@ -1231,17 +1222,12 @@ end;
                 --push/pull\r
                 --discard pc cycle.\r
                 reg_addr    <= reg_pc_h & (reg_pc_l + 1);\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
             elsif (reg_main_state = ST_A52_T2 or\r
                 reg_main_state = ST_A53_T2\r
                 ) then\r
                 --pull, jsr\r
                 --discard sp cycle.\r
                 reg_addr    <= "00000001" & reg_sp;\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
-\r
 \r
 \r
            --a2 instructions.\r
@@ -1253,8 +1239,6 @@ end;
                 reg_main_state = ST_A27_T5\r
             ) then\r
                 --execute cycle.\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
 \r
                 --address bus out.\r
                 if (reg_main_state = ST_A22_T2) then\r
@@ -1334,14 +1318,15 @@ end;
                 end if;\r
 \r
                 --rw ctrl\r
+                reg_oe_n    <= '1';\r
                 if (reg_sub_state = ST_SUB32 or\r
                     reg_sub_state = ST_SUB33 or\r
                     reg_sub_state = ST_SUB40 or\r
                     reg_sub_state = ST_SUB41\r
                     ) then\r
-                    reg_r_nw    <= '0';\r
+                    reg_we_n    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_we_n    <= '1';\r
                 end if;\r
 \r
                 --address bus out.\r
@@ -1395,8 +1380,6 @@ end;
                 reg_main_state = ST_A44_T4\r
             ) then\r
                 --data fetch cycle.\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
 \r
                 --address bus out.\r
                 if (reg_main_state = ST_A41_T2) then\r
@@ -1428,6 +1411,7 @@ end;
                 --data store cycle.\r
                 --data out\r
                 reg_d_out   <= reg_tmp_data;\r
+                reg_oe_n    <= '1';\r
 \r
                 --rw ctrl\r
                 if (reg_sub_state = ST_SUB32 or\r
@@ -1435,9 +1419,9 @@ end;
                     reg_sub_state = ST_SUB40 or\r
                     reg_sub_state = ST_SUB41\r
                     ) then\r
-                    reg_r_nw    <= '0';\r
+                    reg_we_n    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_we_n    <= '1';\r
                 end if;\r
 \r
                 --address bus out.\r
@@ -1470,43 +1454,42 @@ end;
             --push\r
             elsif (reg_main_state = ST_A51_T2) then\r
                 reg_addr    <= "00000001" & reg_sp;\r
+                reg_oe_n    <= '1';\r
+                if (reg_inst = conv_std_logic_vector(16#48#, 8)) then\r
+                    --pha\r
+                    reg_d_out   <= reg_acc;\r
+                elsif (reg_inst = conv_std_logic_vector(16#08#, 8)) then\r
+                    --php\r
+                    reg_d_out   <= reg_status;\r
+                end if;\r
                 if (reg_sub_state = ST_SUB32 or\r
                     reg_sub_state = ST_SUB33 or\r
                     reg_sub_state = ST_SUB40 or\r
                     reg_sub_state = ST_SUB41\r
                     ) then\r
-                    if (reg_inst = conv_std_logic_vector(16#48#, 8)) then\r
-                        --pha\r
-                        reg_d_out   <= reg_acc;\r
-                    elsif (reg_inst = conv_std_logic_vector(16#08#, 8)) then\r
-                        --php\r
-                        reg_d_out   <= reg_status;\r
-                    end if;\r
-                    reg_r_nw    <= '0';\r
+                    reg_we_n    <= '0';\r
                 else\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
+                    reg_we_n    <= '1';\r
                 end if;\r
 \r
             --pull\r
             elsif (reg_main_state = ST_A52_T3) then\r
                 reg_addr    <= "00000001" & reg_sp;\r
-                reg_r_nw    <= '1';\r
-                reg_d_out   <= (others => 'Z');\r
 \r
             --jsr.\r
             elsif (reg_main_state = ST_A53_T3) then\r
                 --push pch\r
                 reg_addr    <= "00000001" & reg_sp;\r
                 reg_d_out   <= reg_pc_h;\r
+                reg_oe_n    <= '1';\r
                 if (reg_sub_state = ST_SUB32 or\r
                     reg_sub_state = ST_SUB33 or\r
                     reg_sub_state = ST_SUB40 or\r
                     reg_sub_state = ST_SUB41\r
                     ) then\r
-                    reg_r_nw    <= '0';\r
+                    reg_we_n    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_we_n    <= '1';\r
                 end if;\r
             elsif (reg_main_state = ST_A53_T4) then\r
                 --push pcl\r
@@ -1517,16 +1500,16 @@ end;
                     reg_sub_state = ST_SUB40 or\r
                     reg_sub_state = ST_SUB41\r
                     ) then\r
-                    reg_r_nw    <= '0';\r
+                    reg_we_n    <= '0';\r
                 else\r
-                    reg_r_nw    <= 'Z';\r
+                    reg_we_n    <= '1';\r
                 end if;\r
             elsif (reg_main_state = ST_A53_T5) then\r
                 if (reg_sub_state = ST_SUB00) then\r
                     --fetch next.\r
                     reg_addr    <= reg_pc_h & reg_pc_l;\r
                     reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
+                    reg_oe_n    <= '0';\r
                 elsif (reg_sub_state = ST_SUB70) then\r
                     --go to sub-routine addr.\r
                     reg_pc_l    <= reg_idl_l;\r
@@ -1538,8 +1521,6 @@ end;
                 if (reg_sub_state = ST_SUB00) then\r
                     --fetch next.\r
                     reg_addr    <= reg_pc_h & reg_pc_l;\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 elsif (reg_sub_state = ST_SUB70) then\r
                     reg_pc_l    <= reg_idl_l;\r
                     reg_pc_h    <= reg_idl_h;\r
@@ -1549,16 +1530,12 @@ end;
             elsif (reg_main_state = ST_A562_T3) then\r
                 if (reg_sub_state = ST_SUB00) then\r
                     reg_addr    <= (reg_idl_h & reg_idl_l);\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 elsif (reg_sub_state = ST_SUB70) then\r
                     reg_pc_l    <= reg_d_in;\r
                 end if;\r
             elsif (reg_main_state = ST_A562_T4) then\r
                 if (reg_sub_state = ST_SUB00) then\r
                     reg_addr    <= (reg_idl_h & reg_idl_l) + 1;\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 elsif (reg_sub_state = ST_SUB70) then\r
                     reg_pc_h    <= reg_d_in;\r
                 end if;\r
@@ -1567,14 +1544,10 @@ end;
             elsif (reg_main_state = ST_A57_T2) then\r
                 --sp out (discarded.)\r
                 reg_addr    <= "00000001" & reg_sp;\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
             elsif (reg_main_state = ST_A57_T3) then\r
                 --pull pcl\r
                 if (reg_sub_state = ST_SUB00) then\r
                     reg_addr    <= "00000001" & reg_sp;\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 elsif (reg_sub_state = ST_SUB70) then\r
                     reg_pc_l    <= reg_d_in;\r
                 end if;\r
@@ -1582,8 +1555,6 @@ end;
                 --pull pch\r
                 if (reg_sub_state = ST_SUB00) then\r
                     reg_addr    <= "00000001" & reg_sp;\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 elsif (reg_sub_state = ST_SUB70) then\r
                     reg_pc_h    <= reg_d_in;\r
                 end if;\r
@@ -1591,8 +1562,6 @@ end;
                 --pc out (discarded.)\r
                 if (reg_sub_state = ST_SUB00) then\r
                     reg_addr    <= reg_pc_h & reg_pc_l;\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 elsif (reg_sub_state = ST_SUB70) then\r
                     reg_pc_l    <= reg_pc_l + 1;\r
                 end if;\r
@@ -1610,8 +1579,6 @@ end;
 \r
                     reg_pc_l    <= calc_adl(7 downto 0);\r
                     reg_addr    <= reg_pc_h & calc_adl(7 downto 0);\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 end if;\r
 \r
             --page crossed.\r
@@ -1626,8 +1593,6 @@ end;
                         reg_pc_h    <= reg_pc_h - "1";\r
                         reg_addr    <= (reg_pc_h - "1") & reg_pc_l;\r
                     end if;\r
-                    reg_d_out   <= (others => 'Z');\r
-                    reg_r_nw    <= '1';\r
                 end if;\r
             end if;--if (reg_main_state = ST_RS_T0) then\r
         end if;--if (pi_rst_n = '0') then\r

diff --git a/de0_cv_nes/ppu/ppu.vhd b/de0_cv_nes/ppu/ppu.vhd
index bf50b0c..4c0ed7f 100644 (file)
--- a/de0_cv_nes/ppu/ppu.vhd
+++ b/de0_cv_nes/ppu/ppu.vhd
@@ -8,7 +8,8 @@ entity ppu is
                 pi_base_clk    : in std_logic;
                 pi_cpu_en      : in std_logic_vector (7 downto 0);
                 pi_ce_n        : in std_logic;
-                pi_r_nw        : in std_logic;
+                pi_oe_n        : in std_logic;\r
+                pi_we_n        : in std_logic;\r
                 pi_cpu_addr    : in std_logic_vector (2 downto 0);
                 pio_cpu_d      : inout std_logic_vector (7 downto 0);
 
@@ -48,6 +49,13 @@ constant OAMDATA   : std_logic_vector(2 downto 0) := "100";
 constant PPUSCROLL : std_logic_vector(2 downto 0) := "101";
 constant PPUADDR   : std_logic_vector(2 downto 0) := "110";
 constant PPUDATA   : std_logic_vector(2 downto 0) := "111";
+\r
+---cpu timing synchronization.\r
+constant CP_ST0   : integer := 4;\r
+constant CP_ST1   : integer := (CP_ST0 + 1) mod 8;\r
+constant CP_ST2   : integer := (CP_ST0 + 2) mod 8;\r
+constant CP_ST3   : integer := (CP_ST0 + 3) mod 8;\r
+constant CP_ST4   : integer := (CP_ST0 + 4) mod 8;\r
 
 signal reg_ppu_ctrl         : std_logic_vector (7 downto 0);
 signal reg_ppu_mask         : std_logic_vector (7 downto 0);
@@ -113,7 +121,7 @@ begin
             scr_set := 0;
             oam_addr_inc := 0;
         elsif (rising_edge(pi_base_clk)) then
-            if (pi_cpu_en(1) = '1' and pi_ce_n = '0' and pi_r_nw = '0') then
+            if (pi_cpu_en(CP_ST0) = '1' and pi_ce_n = '0' and pi_we_n = '0') then
                 if (pi_cpu_addr = PPUCTRL) then
                     reg_ppu_ctrl <= pio_cpu_d;
                 elsif (pi_cpu_addr = PPUMASK) then
@@ -161,7 +169,7 @@ begin
                     reg_oam_addr <= reg_oam_addr + 1;
                     oam_addr_inc := 0;
                 end if;
-            end if;--if (pi_cpu_en(0) = '1' and pi_ce_n = '0') then
+            end if;--if (pi_cpu_en(CP_ST0) = '1' and pi_ce_n = '0') then
         end if;--if (pi_rst_n = '0') then
     end process;
 
@@ -171,13 +179,13 @@ begin
         if (pi_rst_n = '0') then
             pio_cpu_d <= (others => 'Z');
         elsif (rising_edge(pi_base_clk)) then
-            if (pi_cpu_en(1) = '1' and pi_ce_n = '0' and pi_r_nw = '1') then
+            if (pi_cpu_en(CP_ST0) = '1' and pi_ce_n = '0' and pi_oe_n = '0') then
                 if (pi_cpu_addr = PPUSTATUS) then
                     pio_cpu_d <= pi_ppu_status;
                 end if;
             elsif (pi_ce_n = '1') then
                 pio_cpu_d <= (others => 'Z');
-            end if;--if (pi_cpu_en(0) = '1' and pi_ce_n = '0') then
+            end if;--if (pi_cpu_en(CP_ST0) = '1' and pi_ce_n = '0') then
         end if;--if (pi_rst_n = '0') then
     end process;
 
@@ -207,35 +215,35 @@ begin
     end process;
 
     --state change to next.
-    vac_next_stat_p : process (reg_v_cur_state, pi_cpu_en, pi_ce_n, pi_r_nw, pi_cpu_addr)
+    vac_next_stat_p : process (reg_v_cur_state, pi_cpu_en, pi_ce_n, pi_we_n, pi_cpu_addr)
     begin
         case reg_v_cur_state is
             when idle =>
-                if (pi_cpu_en(1) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = PPUDATA) then
+                if (pi_cpu_en(CP_ST0) = '1' and pi_ce_n = '0' and pi_we_n = '0' and pi_cpu_addr = PPUDATA) then
                     reg_v_next_state <= reg_set;
                 else
                     reg_v_next_state <= reg_v_cur_state;
                 end if;
             when reg_set =>
-                if (pi_cpu_en(2) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = PPUDATA) then
+                if (pi_cpu_en(CP_ST1) = '1') then
                     reg_v_next_state <= reg_out;
                 else
                     reg_v_next_state <= reg_v_cur_state;
                 end if;
             when reg_out =>
-                if (pi_cpu_en(3) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = PPUDATA) then
+                if (pi_cpu_en(CP_ST2) = '1') then
                     reg_v_next_state <= mem_write;
                 else
                     reg_v_next_state <= reg_v_cur_state;
                 end if;
             when mem_write =>
-                if (pi_cpu_en(4) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = PPUDATA) then
+                if (pi_cpu_en(CP_ST3) = '1') then
                     reg_v_next_state <= write_end;
                 else
                     reg_v_next_state <= reg_v_cur_state;
                 end if;
             when write_end =>
-                if (pi_cpu_en(5) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = PPUDATA) then
+                if (pi_cpu_en(CP_ST4) = '1') then
                     reg_v_next_state <= complete;
                 else
                     reg_v_next_state <= reg_v_cur_state;
@@ -318,35 +326,35 @@ begin
     po_spr_data     <= reg_spr_data;\r
 \r
     --sprite state change to next.\r
-    sac_next_stat_p : process (reg_spr_cur_state, pi_cpu_en, pi_ce_n, pi_r_nw, pi_cpu_addr)\r
+    sac_next_stat_p : process (reg_spr_cur_state, pi_cpu_en, pi_ce_n, pi_we_n, pi_cpu_addr)\r
     begin\r
         case reg_spr_cur_state is\r
             when idle =>\r
-                if (pi_cpu_en(1) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = OAMDATA) then\r
+                if (pi_cpu_en(CP_ST0) = '1' and pi_ce_n = '0' and pi_we_n = '0' and pi_cpu_addr = OAMDATA) then\r
                     reg_spr_next_state <= reg_set;\r
                 else\r
                     reg_spr_next_state <= reg_spr_cur_state;\r
                 end if;\r
             when reg_set =>\r
-                if (pi_cpu_en(2) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = OAMDATA) then\r
+                if (pi_cpu_en(CP_ST1) = '1') then\r
                     reg_spr_next_state <= reg_out;\r
                 else\r
                     reg_spr_next_state <= reg_spr_cur_state;\r
                 end if;\r
             when reg_out =>\r
-                if (pi_cpu_en(3) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = OAMDATA) then\r
+                if (pi_cpu_en(CP_ST2) = '1') then\r
                     reg_spr_next_state <= mem_write;\r
                 else\r
                     reg_spr_next_state <= reg_spr_cur_state;\r
                 end if;\r
             when mem_write =>\r
-                if (pi_cpu_en(4) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = OAMDATA) then\r
+                if (pi_cpu_en(CP_ST3) = '1') then\r
                     reg_spr_next_state <= write_end;\r
                 else\r
                     reg_spr_next_state <= reg_spr_cur_state;\r
                 end if;\r
             when write_end =>\r
-                if (pi_cpu_en(5) = '1' and pi_ce_n = '0' and pi_r_nw = '0' and pi_cpu_addr = OAMDATA) then\r
+                if (pi_cpu_en(CP_ST4) = '1') then\r
                     reg_spr_next_state <= complete;\r
                 else\r
                     reg_spr_next_state <= reg_spr_cur_state;\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index afce3ee..3705fd4 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -7,10 +7,10 @@ vmap work rtl_work
 \r
 vcom -93 -work work {../../chip_selector.vhd}\r
 vcom -93 -work work {../../mem/ram.vhd}\r
-#vcom -93 -work work {../../mem/chr_rom.vhd}\r
-#vcom -93 -work work {../../ppu/ppu.vhd}\r
-#vcom -93 -work work {../../ppu/render.vhd}\r
-vcom -93 -work work {../../dummy-ppu.vhd}\r
+vcom -93 -work work {../../mem/chr_rom.vhd}\r
+vcom -93 -work work {../../ppu/ppu.vhd}\r
+vcom -93 -work work {../../ppu/render.vhd}\r
+#vcom -93 -work work {../../dummy-ppu.vhd}\r
 \r
 #vcom -93 -work work {../../dummy-mos6502.vhd}\r
 vcom -93 -work work {../../mem/prg_rom.vhd}\r
@@ -28,9 +28,10 @@ vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -
 add wave -label dbg_cnt -radix hex  sim:/testbench_motones_sim/sim_board/po_dbg_cnt;\r
 add wave -label rst_n               sim:/testbench_motones_sim/sim_board/pi_rst_n;\r
 #add wave -label base_clk            sim:/testbench_motones_sim/sim_board/pi_base_clk;\r
-#add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en;\r
+add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en;\r
 add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en(0);\r
-add wave -label r_nw                sim:/testbench_motones_sim/sim_board/wr_r_nw;\r
+add wave -label wr_oe_n             sim:/testbench_motones_sim/sim_board/wr_oe_n;\r
+add wave -label wr_we_n             sim:/testbench_motones_sim/sim_board/wr_we_n;\r
 add wave -label addr -radix hex     sim:/testbench_motones_sim/sim_board/wr_addr;\r
 add wave -label d_io -radix hex     sim:/testbench_motones_sim/sim_board/wr_d_io;\r
 \r
@@ -56,91 +57,91 @@ add wave -label reg_idl_h -radix hex sim:/testbench_motones_sim/sim_board/cpu_in
 add wave -label reg_tmp_pg_crossed  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_tmp_pg_crossed;\r
 \r
 \r
+#view structure\r
+#view signals\r
+#\r
+#run 25 us\r
+#wave zoom full\r
+#\r
+#run 4923 us\r
+\r
+\r
+#################################### PPU part.... ###########################################\r
+add wave -divider ppu\r
+add wave -label pi_ce_n         -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ce_n;\r
+add wave -label ppu_ctrl        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_ctrl;\r
+add wave -label ppu_mask        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_mask;\r
+add wave -label ppu_status      -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ppu_status;\r
+add wave -label oam_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_addr;\r
+add wave -label oam_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_data;\r
+add wave -label ppu_scroll_x    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_x;\r
+add wave -label ppu_scroll_y    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_y;\r
+add wave -label ppu_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_addr;\r
+add wave -label ppu_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_data;\r
+\r
+add wave -divider vram\r
+add wave -label v_rd_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_rd_n;\r
+add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_wr_n;\r
+add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
+add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
+\r
+add wave -divider render\r
+#add wave -label vga_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_x;\r
+#add wave -label vga_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_y;\r
+add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
+add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
+\r
+\r
+add wave -divider bg\r
+#add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
+add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
+#add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
+#add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
+\r
+add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
+add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
+add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
+add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
+\r
+add wave -divider sprite\r
+add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
+add wave -label reg_s_oam_ce_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
+add wave -label reg_s_oam_rd_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
+add wave -label reg_s_oam_wr_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
+add wave -label reg_s_oam_addr -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
+add wave -label reg_s_oam_data -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
+\r
+add wave -label wr_spr_ce_n  sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
+add wave -label wr_spr_rd_n  sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
+add wave -label wr_spr_wr_n  sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
+add wave -label wr_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
+add wave -label wr_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
+\r
+add wave -label reg_spr_y_tmp -radix hex    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
+add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
+add wave -label reg_spr_attr -radix hex     sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
+add wave -label reg_spr_x -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
+add wave -label reg_spr_ptn_sft_start -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
+add wave -label reg_spr_ptn_l -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
+add wave -label reg_spr_ptn_h -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
+\r
+add wave -divider palette\r
+add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
+add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
+\r
+\r
+add wave -divider vga\r
+add wave -label h_sync_n       sim:/testbench_motones_sim/sim_board/po_h_sync_n;\r
+add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/po_v_sync_n;\r
+add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/po_r;\r
+add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/po_g;\r
+add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/po_b;\r
+\r
 view structure\r
 view signals\r
 \r
-run 25 us\r
+run 4 us\r
 wave zoom full\r
 \r
-run 4923 us\r
+run 210 us\r
 \r
-\r
-#################################### PPU part.... ###########################################\r
-#add wave -divider ppu\r
-#add wave -label pi_ce_n         -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ce_n;\r
-#add wave -label ppu_ctrl        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_ctrl;\r
-#add wave -label ppu_mask        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_mask;\r
-#add wave -label ppu_status      -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ppu_status;\r
-#add wave -label oam_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_addr;\r
-#add wave -label oam_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_data;\r
-#add wave -label ppu_scroll_x    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_x;\r
-#add wave -label ppu_scroll_y    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_y;\r
-#add wave -label ppu_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_addr;\r
-#add wave -label ppu_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_data;\r
-\r
-#add wave -divider vram\r
-#add wave -label v_rd_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_rd_n;\r
-#add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_wr_n;\r
-#add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
-#add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
-#\r
-#add wave -divider render\r
-##add wave -label vga_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_x;\r
-##add wave -label vga_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_y;\r
-#add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
-#add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
-#\r
-#\r
-#add wave -divider bg\r
-##add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
-#add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
-##add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
-##add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
-#\r
-#add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
-#add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
-#add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
-#add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
-#\r
-#add wave -divider sprite\r
-#add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
-#add wave -label reg_s_oam_ce_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
-#add wave -label reg_s_oam_rd_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
-#add wave -label reg_s_oam_wr_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
-#add wave -label reg_s_oam_addr -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
-#add wave -label reg_s_oam_data -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
-#\r
-#add wave -label wr_spr_ce_n  sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
-#add wave -label wr_spr_rd_n  sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
-#add wave -label wr_spr_wr_n  sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
-#add wave -label wr_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
-#add wave -label wr_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
-#\r
-#add wave -label reg_spr_y_tmp -radix hex    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
-#add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
-#add wave -label reg_spr_attr -radix hex     sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
-#add wave -label reg_spr_x -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
-#add wave -label reg_spr_ptn_sft_start -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
-#add wave -label reg_spr_ptn_l -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
-#add wave -label reg_spr_ptn_h -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
-#\r
-#add wave -divider palette\r
-#add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
-#add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
-#\r
-#\r
-#add wave -divider vga\r
-#add wave -label h_sync_n       sim:/testbench_motones_sim/sim_board/po_h_sync_n;\r
-#add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/po_v_sync_n;\r
-#add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/po_r;\r
-#add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/po_g;\r
-#add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/po_b;\r
-#\r
-#view structure\r
-#view signals\r
-#\r
-#run 4 us\r
-#wave zoom full\r
-#\r
-#run 210 us\r
-#\r